Equipment power-on control method and device, storage medium and electronic equipment

Abstract

The invention discloses an equipment power-on control method and device, a storage medium and electronic equipment, and relates to the technical field of computer hardware, and the method comprises the steps: receiving a reference clock signal transmitted by a host end through a clock buffer group under the condition that the clock buffer group is powered on, the receiving unit receives a reference clock signal and converts the received reference clock signal into an output clock signal of the clock buffer group, and the output clock signal of the clock buffer group is distributed to the control unit; the signal state of the output clock signal of the clock buffer group is detected through the control component, the hardware equipment is subjected to power-on control through the control component on the basis of the detected signal state, the reference clock signal is converted and then distributed to the control component, and the control component carries out equipment power-on control on the basis of the signal state. The technical problem of low stability caused by limited power-on time sequence control in an equipment power-on control method in the related technology is solved.

Description

Technical Field

[0001] This application relates to the technical field of computer hardware, and in particular, to a device power-on control method, device, storage medium, and electronic device. Background Art

[0002] In order to meet the high demand for server performance, an architecture of multiple modules cooperating with a common substrate can be adopted. The host provides a reference clock signal for initialization and data transmission to the substrate. However, in this case, the hardware devices on the common substrate need to rely on the reference clock signal for power-on timing control, and the host needs to adjust the firmware according to the power-on and power-off timing of the UBB board (Universal Baseboard), or readjust and test the firmware on the UBB board when the power-on policy of the host changes. Such adjustment not only increases the workload of firmware development and verification, but also may cause compatibility problems when facing diverse server hardware configurations, increasing the risk of device initialization errors and system instability.

[0003] It can be seen that the device power-on control method in the related art has the technical problem of low stability caused by limited power-on timing control. Summary of the Invention

[0004] This application provides a device power-on control method, device, storage medium, and electronic device to at least solve the technical problem of low stability in the device power-on control method in the related art caused by limited power-on timing control.

[0005] This application provides a device power-on control method applied to an electronic device. The electronic device includes a clock buffer group, a control component, and a hardware device. The clock buffer group is connected to the control component. The method includes: when the clock buffer group is powered on, receiving a reference clock signal transmitted from the host through the clock buffer group, and converting the received reference clock signal into an output clock signal of the clock buffer group, where the output clock signal of the clock buffer group is distributed to the control component; detecting, by the control component, a signal state of the output clock signal of the clock buffer group, and based on the detected signal state, controlling the power-on of the hardware device by the control component.

[0006] The present application also provides a device power-on control device, which is applied to an electronic device. The electronic device includes a clock buffer group, a control component, and a hardware device. Among them, the clock buffer group is connected to the control component. The device includes: a first execution unit, configured to receive a reference clock signal transmitted from a host side through the clock buffer group when the clock buffer group is powered on, and convert the received reference clock signal into an output clock signal of the clock buffer group, where the output clock signal of the clock buffer group is distributed to the control component; a second execution unit, configured to detect a signal state of the output clock signal of the clock buffer group through the control component, and perform power-on control on the hardware device through the control component based on the detected signal state.

[0007] The present application also provides an electronic device, including: a memory, configured to store a computer program; a processor, configured to implement the steps of any of the above device power-on control methods when executing the computer program.

[0008] The present application also provides a computer-readable storage medium, in which a computer program is stored. When the computer program is executed by a processor, the steps of any of the above device power-on control methods are implemented.

[0009] The present application also provides a computer program product, including a computer program. When the computer program is executed by a processor, the steps of any of the above device power-on control methods are implemented.

[0010] Through the present application, since when the clock buffer group is powered on, a reference clock signal transmitted from the host side is received through the clock buffer group, and the received reference clock signal is converted into an output clock signal of the clock buffer group, where the output clock signal of the clock buffer group is distributed to the control component; the signal state of the output clock signal of the clock buffer group is detected through the control component, and based on the detected signal state, power-on control on the hardware device is performed through the control component. By directly distributing the reference clock signal received by the clock buffer from the host side to the control component, the control component monitors and detects the reference clock signal in real time, and dynamically adjusts the power-on control of the hardware device based on the detected signal state of the reference clock signal. Therefore, the technical problem of low stability caused by limited power-on timing control in the device power-on control method in the related art can be solved, and the technical effect of improving the accuracy and reliability of device power-on control can be achieved. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] To more clearly illustrate the embodiments of the present application, the accompanying drawings required for use in the embodiments will be briefly introduced below. Obviously, the accompanying drawings in the following description are only some embodiments of the present application. For those of ordinary skill in the art, without creative efforts, other accompanying drawings can be obtained based on these drawings.

[0012] Figure 1 FIG. is a schematic diagram of an application scenario of a device power-on control method provided by an embodiment of the present application.

[0013] Figure 2 FIG. is a schematic flowchart of an optional device power-on control method according to an embodiment of the present application.

[0014] Figure 3 FIG. is a schematic diagram of an optional device power-on control method according to an embodiment of the present application.

[0015] Figure 4 FIG. is a schematic diagram of another optional device power-on control method according to an embodiment of the present application.

[0016] Figure 5 FIG. is a schematic flowchart of another optional device power-on control method according to an embodiment of the present application.

[0017] Figure 6 FIG. is a schematic diagram of yet another optional device power-on control method according to an embodiment of the present application.

[0018] Figure 7 FIG. is a schematic circuit diagram of an optional device power-on control method according to an embodiment of the present application.

[0019] Figure 8 FIG. is a structural block diagram of an optional device power-on control device according to an embodiment of the present application. Detailed implementation manners

[0020] Next, the technical solutions in the embodiments of the present application will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only some embodiments of the present application, rather than all embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative efforts belong to the protection scope of the present application.

[0021] It should be noted that in the description of this application, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements not only includes those elements, but also includes other elements not explicitly listed, or elements inherent to such a process, method, article or device. The terms "first", "second", etc. in this application are used to distinguish similar objects and are not used to describe a specific order or sequence.

[0022] To enable those skilled in the art of this technology to better understand the solution of this application, the following further detailed description of this application will be given in conjunction with the accompanying drawings and specific embodiments.

[0023] According to one aspect of the embodiments of this application, a device power-on control method is provided. Optionally, in this embodiment, the above device power-on control method can be applied to a hardware environment constituted by an electronic device 101 as Figure 1 shown. As Figure 1 shown, the electronic device 101 may include a clock buffer group 1011, a control component 1012, and a hardware device 1013. Among them, the clock buffer group 1011 is connected to the control component 1012, Figure 2 is a schematic flowchart of an optional device power-on control method according to the embodiments of this application. As Figure 2 shown, the process of this method includes the following steps:

[0024] Step S202, when the clock buffer group is powered on, receive the reference clock signal transmitted from the host through the clock buffer group, and convert the received reference clock signal into the output clock signal of the clock buffer group, where the output clock signal of the clock buffer group is distributed to the control component;

[0025] Step S204, detect the signal state of the output clock signal of the clock buffer group through the control component, and based on the detected signal state, perform power-on control on the hardware device through the control component.

[0026] The device power-on control method in this embodiment can be applied to the field of computer hardware technology and can be applied to the scenario of power-on control of hardware devices on a general substrate.

[0027] With the advancement of the information technology wave, servers, as the infrastructure of data centers and cloud computing platforms, play a crucial role. In recent years, the breakthrough progress in the field of Artificial Intelligence (AI) has further led to an increased demand for high-performance AI servers, especially those used to process large-scale Machine Learning (ML), Deep Learning (DL) models, and High Performance Computing (HPC) tasks. AI applications often involve the rapid processing of massive amounts of data, real-time feedback in model training, and complex parallel computing capabilities. However, these are difficult to meet with traditional PCIe CEM (PCI Express Card Electromechanical Specification) size cards. Although CEM cards dominated early server designs, due to their physical size limitations and signal integrity considerations, they lack sufficient support for high-bandwidth AI loads, especially in scenarios that require fast and reliable data transmission and flexible interconnection. The design of CEM cards lacks targeted optimization.

[0028] For this reason, new UBB architectures and hardware designs have emerged. For example, the OAM (Open Accelerator Module) module, which is designed specifically for accelerating AI and HPC computing, can provide higher bandwidth and interconnection flexibility than traditional PCIe CEM cards. Generally, an AI server can integrate multiple OAM modules and use the UBB board for unified management and signal distribution to build an efficient and scalable computing platform that can enhance the multi-module parallel processing ability without sacrificing signal integrity and system stability.

[0029] To meet the high-performance requirements of this architecture, a new interface specification has been proposed, aiming to optimize the signal transmission efficiency and timing control ability between the UBB and the host side (i.e., the Host side). Under this specification framework, the host side is required to provide a set of reference clock signals for initialization and data transmission to the UBB board. It can affect the startup, configuration, and data transmission rate of hardware devices on the general substrate. It is not only crucial for the normal startup of devices but also an important foundation for achieving high-bandwidth data exchange and optimizing system performance.

[0030] It should be noted that the hardware devices on the substrate are usually extremely sensitive to timing control during the power-on and power-off processes. The orderly arrival of the power supply and reset signals, as well as the stability and availability of the reference clock signal, are all indispensable factors for ensuring the correct startup and operation of the hardware devices on the substrate. Once the timing control is improper, it may lead to problems such as the inability of the device to be normally initialized, data transmission errors, system suspension, or even hardware damage during operation, seriously affecting the overall performance and stability of the server.

[0031] Optionally, taking the hardware device as a PCIe (Peripheral Component Interconnect Express) device as an example, the host side can provide 3 stable and reliable 100 MHz (megahertz) clock signals to the general substrate to support the normal operation of each PCIe device on the UBB board. The transmission of this reference clock signal can be input into the Clock Buffer, and the clock buffer is used for strengthening and distribution. That is, the clock buffer can be used to copy and amplify the single 100 MHz clock signal from the host side to generate multiple identical clock signals, and then evenly distribute them to all PCIe devices on the UBB board.

[0032] For example, as Figure 3 shown, the 3-way PCIe 100 MHz reference clock signals input from the Host side (which can be transmitted through the connector) can be respectively connected to 3 clock buffers, and the generated clock signals (including the main reference clock signal and the auxiliary reference clock signal) are respectively provided to 8 PCIe retimers and 8 OAMs.

[0033] Optionally, only two of the three reference clock signals can also be used. For example, as Figure 4 shown, 2 of the 3-way PCIe 100 MHz reference clocks input from the Host side, namely CLK_REFCLK_0_DP / DN (i.e., reference clock signal_0) and CLK_REFCLK_1_DP / DN (i.e., reference clock signal_1), can be respectively connected to 2 clock buffers, and these signals are subdivided into modular outputs and respectively provided to the retimer, OAM, and expansion slot.

[0034] However, the power-on of the hardware devices on the general substrate in this case is controlled according to a preset timing strategy. When designing the power-on timing firmware on the host side, it is necessary to pre-consider the dependence of the UBB board on the clock signal, and adjust the firmware adaptation according to the power-on and power-off timing of the UBB board to ensure that the stable supply of the clock signal is coordinated with the power-on sequence of the devices. Correspondingly, once the power-on strategy of the host side changes, it is necessary to re-adjust and test the firmware on the UBB board to ensure that all PCIe devices can be initialized under the correct clock signal state, avoiding the situation of power-on failure or abnormal device operation. That is, in some cases, when the timing of the host side is fixed and the UBB board needs to adapt to different server environments, it may be necessary to modify the firmware on the UBB board to adjust the power-on and power-off timing of the devices to achieve synchronization with the clock signal state of the host side. This adjustment not only increases the workload of firmware development and verification, but also may cause compatibility problems when facing diverse server hardware configurations, increasing the risk of device initialization errors and system instability.

[0035] It can be seen that in the power-on and power-off logic control of the server system, the control component is in a passive state and relies on the preset firmware strategy to make power-on control decisions. This limitation not only affects the accuracy and reliability of device initialization and cannot adjust the device power-on in a timely manner when the clock signal changes, but also restricts the adaptability and compatibility of the server system in different hardware environments. That is, the device power-on control method in the related technology has the technical problem of low stability caused by limited power-on timing control.

[0036] To at least partially solve the above technical problems, an apparatus power-on control method is provided in this embodiment. When the clock buffer group is powered on, a reference clock signal transmitted from the host side is received through the clock buffer group, and the received reference clock signal is converted into an output clock signal of the clock buffer group, wherein the output clock signal of the clock buffer group is distributed to the control component; the control component detects the signal state of the output clock signal of the clock buffer group, and based on the detected signal state, the control component performs power-on control on the hardware device. By directly distributing the reference clock signal received by the clock buffer from the host side to the control component, the control component performs real-time monitoring and detection on the reference clock signal, and dynamically adjusts the power-on control of the hardware device based on the detected signal state of the reference clock signal, which can solve the technical problem of low stability caused by limited power-on timing control in the related device power-on control method, and achieve the technical effect of improving the accuracy and reliability of device power-on control.

[0037] Optionally, the above device power-on control method can be applied to an electronic device, which includes a clock buffer group, a control component, and a hardware device. Among them, the clock buffer group is connected to the control component. Thus, the clock buffer can directly send the clock signal it outputs to the control component.

[0038] Optionally, when the clock buffer group is powered on, it can receive a reference clock signal transmitted by the host side according to a pre-defined signal standard and interface protocol through the clock buffer group, and the received reference clock signal.

[0039] Optionally, after receiving the reference clock signal, the clock buffer group can optimize and convert the reference clock signal level, impedance, and frequency characteristics through its internal signal processing circuit, and convert it into the output clock signal of the clock buffer group. Its processing method for the reference clock signal can be pre-set, and can include but is not limited to: amplifying the reference clock signal, duplicating the reference clock signal.

[0040] Optionally, the output clock signal of the clock buffer group can be distributed to multiple targets. For example, it can be distributed to the control component. Thus, the control component can perform real-time detection on the output clock signal distributed by the clock buffer group through the signal detection hardware integrated inside it.

[0041] The above control component can be a CPLD (Complex Programmable Logic Device), or other control components such as FPGA (Field Programmable Gate Array), MCU (Microcontroller Unit), or BMC (Baseboard Management Controller). This is not limited in this embodiment.

[0042] Optionally, the control component can perform power-on control on the hardware device according to a preset algorithm based on the detected signal state. For example, if the signal frequency is lower than expected, the control component can delay or suspend the power-on of the device until the signal returns to stability; conversely, when the signal state is good, the device is allowed to continue power-on until the initialization process is completed.

[0043] Optionally, the control component may have built-in signal detection hardware, such as a Phase-Locked Loop (PLL) module, to perform real-time evaluation of aspects such as the frequency, phase, amplitude, and jitter of the signal. Here, the phase-locked loop is an electronic circuit based on the principle of negative feedback control, which can be used to capture and lock the frequency and phase of the input signal by mechanisms such as phase detection, loop filtering, and frequency adjustment. In this embodiment, the PLL module can be used to quickly capture the clock signal and perform comparison and adjustment of the phase and frequency to ensure the stability and quality of the signal. Once the signal reaches a stable locked state, a feedback signal can be sent to the control component.

[0044] The process of powering on the hardware device as described above may include the process of controlling the hardware device to receive power supply and the process of controlling the hardware device to complete initialization. Controlling the hardware device to complete initialization can be achieved by sending a control signal to the hardware device. That is, the above-mentioned hardware device first receives the current input from the power supply, and then performs device initialization after the control component sends the control signal, thus completing the complete power-on process of the hardware device.

[0045] The implementation of the above device power-on control method can make the power-on timing design of the entire server more flexible. Specifically, in the server system, there used to be a relatively tight timing coupling relationship between the UBB board and other boards, such as the motherboard or the switching board. This coupling relationship limited the degree of freedom of the server power-on timing design to a certain extent. By effectively monitoring the reference clock signal, the timing coupling degree between the UBB and other boards can be reduced, thus providing a broader adjustment space for the server power-on timing design.

[0046] In addition, when the UBB is applied to servers with different platforms and architectures, complex design adjustments usually need to be made for different platforms and architectures, which is a cumbersome process and inefficient. However, based on the embodiments of this application, when the UBB adapts to servers with different platforms and architectures, the operation is simpler and more convenient, and the flexibility is greatly enhanced. This not only improves the versatility of the UBB, enabling it to operate efficiently in various server environments, but also reduces the development cost and time cost.

[0047] Through the embodiments provided in this application, when the clock buffer group is powered on, the reference clock signal transmitted by the host is received through the clock buffer group, and the received reference clock signal is converted into the output clock signal of the clock buffer group. Among them, the output clock signal of the clock buffer group is distributed to the control component; the control component detects the signal state of the output clock signal of the clock buffer group, and based on the detected signal state, the control component performs power-on control on the hardware device, which can solve the technical problem of low stability in the device power-on control method in the related art due to limited power-on timing control, and achieve the technical effect of improving the accuracy and reliability of device power-on control.

[0048] In an exemplary embodiment, the clock buffer group is also connected to the hardware device. Based on the detected signal state, the control component performs power-on control on the hardware device, including: when it is detected that the output clock signal of the clock buffer group is connected, the control component controls the hardware device to power on. Among them, after the hardware device is powered on, the output clock signal of the clock buffer group is also distributed to the hardware device; when it is detected that the signal frequency of the output clock signal of the clock buffer group reaches the signal frequency threshold, the control component releases a reset signal to the hardware device to reset the hardware device.

[0049] In this embodiment, the clock buffer group can also be connected to the hardware device, so that the clock buffer group can distribute its processed output clock signal to the hardware device.

[0050] Optionally, when the control component detects that the output clock signal of the clock buffer group has been connected, it can start the power-on process of the hardware device.

[0051] First, the control component can control the hardware device to power on, that is, control the hardware device to obtain the current input from the power supply. After the hardware device is powered on, the hardware device can receive the output clock signal from the clock buffer group.

[0052] After that, the control component can continuously monitor the signal frequency of the output clock signal of the clock buffer group. Here, a signal frequency threshold can be preset in advance. After the output clock signal of the clock buffer group reaches the signal frequency threshold, it can be considered that the clock signal has stabilized. For example, for a PCIe device, this clock signal threshold can be 100 MHz.

[0053] Optionally, in order to adapt to the differences in different environments and devices, the control component can allow modification of this signal frequency threshold. The signal frequency threshold can be preset with a modification range. For example, the custom range of the signal frequency threshold can be set to cover from 99.9 MHz to 100.1 MHz.

[0054] Optionally, when it is detected that the signal frequency of the output clock signal of the clock buffer group reaches the signal frequency threshold, the control component can release a reset signal to the hardware device, thereby completing the initialization process of the hardware device and ensuring that the device can enter the normal working state under the drive of a stable clock signal.

[0055] Optionally, a time window for stable determination of the signal frequency threshold can also be set. This time window is used to measure the minimum time requirement for the clock signal to continuously remain within the threshold range after reaching the preset frequency threshold. Only when the signal continuously and stably remains within the specified frequency range within this time window will the control component determine that the clock signal is stable and perform subsequent hardware device control operations accordingly, such as releasing the reset signal.

[0056] For example, a signal frequency threshold stable time window can be defined and set to 500 milliseconds (ms). The control component can consider the signal stable after detecting that the clock signal frequency reaches the preset threshold and continuously monitoring the signal to remain within this frequency range for at least 500 ms.

[0057] Optionally, the PLL module or other signal detection components inside the control component can have the ability of continuous monitoring. For example, when the signal is first detected to reach the threshold, the control component can start an internal timer to record the duration for which the signal remains within the threshold range. Only when the reading of the timer reaches the preset time window length will the control component consider the signal stable.

[0058] Optionally, the time window length for signal stability determination can be dynamically adjusted according to changes in environmental conditions (such as temperature fluctuations, power supply stability). It can be automatically adjusted or manually adjusted, and this is not limited in this embodiment.

[0059] Through this embodiment, by powering on the hardware device when detecting the output clock signal of the clock buffer and resetting the hardware device when detecting that the output clock signal of the clock buffer is stable, the stability and reliability of device power-on control can be improved.

[0060] In an exemplary embodiment, the clock buffer group, the control component, and the hardware device are located on the same substrate and are connected through a Peripheral Component Interconnect (PCI) bus. The hardware device is a PCI device, and the number of hardware devices is at least two; when it is detected that the signal frequency of the output clock signal of the clock buffer group reaches the signal frequency threshold, releasing a reset signal to the hardware device through the control component includes: when it is detected that the signal frequency of the output clock signal of the clock buffer group reaches the signal frequency threshold, releasing a reset signal on the PCI bus through the control component to reset at least two hardware devices.

[0061] In this embodiment, the clock buffer group, the control component, and the hardware device are located on the same substrate and are connected via a Peripheral Component Interconnect (PCIe) bus. The hardware device is a PCIe device. When the control component detects that the frequency of the output clock signal of the clock buffer group reaches a preset signal frequency threshold, it can release a reset signal to at least two hardware devices via the PCIe bus. This reset signal is designed to be recognizable and responsive by all hardware devices connected to the bus. That is, the control component can broadcast the reset signal to all relevant hardware devices via the shared communication path of the PCIe bus, ensuring that all devices can be reset and initialized synchronously, thereby achieving coordinated and stable operation at the system level.

[0062] Optionally, the number of hardware devices is at least two. That is, multiple hardware devices can exist on the same substrate. These multiple hardware devices can be of the same type or different types. For example, the hardware devices on the same substrate can include PCIe retimers, OAM, or expansion slots. This embodiment does not limit this.

[0063] In this embodiment, the clock buffer group on the substrate can receive a reference clock signal (i.e., the main clock signal) from the host side. It can enhance the signal strength of this main clock signal to compensate for the attenuation and distortion during signal transmission on the substrate. At the same time, the clock buffer also has the functions of signal bifurcation and replication, and can copy and convert a single main clock signal into multiple identical clock signals. Each signal has the same or appropriately adjusted frequency and phase as the main clock. During this process, the clock buffer can use its internal clock replication and distribution network to ensure that the quality of the clock signal is not affected by the number of replications. Thus, the multiple output clock signals can be distributed to the clock input ports of each hardware device through the wiring on the substrate.

[0064] Through this embodiment, by generating and distributing multiple clock signals to multiple hardware devices on the same substrate through the clock buffer group and uniformly resetting the multiple hardware devices, the power-on process of the hardware devices can be optimized, and the stability of device power-on control can be improved.

[0065] In an exemplary embodiment, the above method further includes: in response to the power-on indication signal from the host side, controlling the power-on of the clock buffer group through the control component and opening the output channel of the clock buffer group, where the output clock signal of the clock buffer group is transmitted through the output channel of the clock buffer group.

[0066] In this embodiment, when powering on the hardware devices on the substrate is required, the host can send a power-on indication signal to the control component on the substrate to indicate the control component on the substrate to start the power-on process, which can be sent through the peripheral interconnect bus; in response to the power-on indication signal from the host, the control component can control the power-on of the clock buffer group and turn on its output channels.

[0067] Optionally, after receiving the power-on command, the clock buffer powers on to make the internal circuit components start working and activates the output channel, which can allow the main clock signal to be transmitted through the channel to downstream hardware devices, such as PCIe retimers, OAM modules, etc.

[0068] For example, as Figure 5 shown, the control component (such as CPLD) on the UBB board receives the power-on signal from the host, can control the power-on of the clock buffer and turn on its channel to prepare for receiving the reference clock from the host later. After the clock signal is connected, the CPLD immediately controls the power-on of devices such as PCIe and continuously monitors the clock status. When the CPLD monitors that the frequency of the PCIe 100MHz reference clock reaches 100MHz and remains stable, it releases the reset signal of PCIe, thereby realizing the normal power-on of all PCIe devices on the UBB board.

[0069] Through this embodiment, by controlling the power-on of the clock buffer group and turning on its output channels when the host sends a power-on indication, the accuracy of controlling the power-on timing of multiple devices can be improved.

[0070] In an exemplary embodiment, the clock buffer group includes a first clock buffer and a second clock buffer; receiving the reference clock signal transmitted by the host through the clock buffer group and converting the received reference clock signal into the output clock signal of the clock buffer group includes: receiving the first path of reference clock signal transmitted by the host through the first clock buffer and converting the first path of reference clock signal into the output clock signal of the first clock buffer; receiving the second path of reference clock signal transmitted by the host through the second clock buffer and converting the second path of reference clock signal into the output clock signal of the second clock buffer; wherein, the paths of reference clock signals transmitted by the host include the first path of reference clock signal and the second path of reference clock signal.

[0071] In this embodiment, the host side can be configured with two central processing units, thereby improving its parallel processing ability and system redundancy. Correspondingly, each reference clock signal on the host side can be provided by an independent clock source (for example, a clock generator inside the processor). To support the input and processing of such multiple clock signals, the clock buffer group can include a first clock buffer and a second clock buffer, and each buffer is specifically responsible for processing and forwarding the reference clock signal from one CPU.

[0072] Optionally, the first clock buffer can be associated with the first reference clock signal corresponding to the first processor, perform gain, shaping, and frequency locking on the received clock signal. The processed signal can be used as the output clock signal of the first clock buffer, which will be directionally allocated to the hardware devices connected under the first processor. The control component can also determine when to release the power-on control of this part of the hardware devices connected to the first processor according to the state of the output clock signal of the first clock buffer, ensuring that the devices can be started under the best conditions.

[0073] Similarly, the second clock buffer can also receive the second reference clock signal corresponding to the second processor, convert it into the output clock signal of the second clock buffer, and then directionally transmit it to the hardware devices connected to the second processor. The control component controls the power-on process of this part of the devices connected to the second processor according to the state of the output clock signal of the second clock buffer.

[0074] Optionally, when setting the hardware devices on the substrate, they can be set in different modules according to the correspondence with the processors. For example, as Figure 6 shown, two of the three 100 MHz PCIe reference clocks input at the Host end, CLK_REFCLK_0_DP / DN and CLK_REFCLK_1_DP / DN, are respectively connected to two clock buffers, and are respectively provided to the corresponding retimers, open acceleration modules, and expansion slots. The output clocks of the clock buffers are synchronously connected to the differential signal input pins of the control component (such as CPLD) used to control the power-on and power-off timing inside the board. The control component realizes the status monitoring of the 100 MHz PCIe reference clock, ensuring that the CPLD on the UBB can achieve more precise power-on control of the PCIe devices through the status monitoring of the clock.

[0075] Through this embodiment, the corresponding reference clock signals are converted into corresponding output clock signals through multiple clock buffers. This modular signal processing and distribution can enhance the stability and performance of the server, and improve the overall operation efficiency and reliability of the server.

[0076] In an exemplary embodiment, a level conversion circuit is connected between the output end of the clock buffer group and the input end of the control component; after receiving the reference clock signal transmitted from the host side through the clock buffer group and converting the received reference clock signal into the output clock signal of the clock buffer group, the method further includes: adjusting the level state of the output clock signal of the clock buffer group to a target level state through the level conversion circuit, and inputting the adjusted output clock signal of the clock buffer group into the signal input end of the control component.

[0077] The output clock signal of the clock buffer group usually adopts a high-speed and low-power standard level, such as LP-HCSL (Low Power High Speed Low Swing) level, while the input level of the control component may be different. For example, a CPLD may require an LP-PECL (Low Voltage Positive Emitter Coupled Logic) level, etc. That is to say, there may be a situation of level mismatch between the output level of the clock buffer group and the input level of the control component. If the level conversion is not performed and the clock signal is directly input into the control component, the signal may be misread due to the level mismatch, and even the control component may be damaged, affecting the stability of the entire system.

[0078] In this embodiment, a level conversion circuit can be connected between the output end of the clock buffer group and the input end of the control component, which is used to adjust the level state of the output clock signal of the clock buffer group to a level state that can be correctly recognized by the control component, that is, the target level state.

[0079] For example, as Figure 7 shown, the PCIe 100MHz reference clock signal output by the clock buffer can be sent to the CPLD of the control component for controlling power on and off on the substrate through the level conversion circuit between the clock buffer and the control component (such as a CPLD).

[0080] Through this embodiment, by distributing the output signal of the clock buffer to the control component after level conversion, the risk of level mismatch can be avoided, and the stability of the device power-on control is improved.

[0081] In an exemplary embodiment, the frequency of the output clock signal of the clock buffer group is greater than the signal frequency of the clock signal of the control component itself; the method further includes: inputting the output clock signal of the clock buffer group into a first phase-locked loop for clock frequency division to obtain the output clock signal of the clock buffer group after frequency division, wherein the signal frequency of the output clock signal of the clock buffer group after frequency division is less than the signal frequency of the clock signal of the control component itself; sampling the output clock signal of the clock buffer group after frequency division within the signal period of the clock signal of the control component itself by the control component to detect the signal state of the output clock signal of the clock buffer group; or,

[0082] inputting the clock signal of the control component itself into a second phase-locked loop for clock multiplication to obtain the clock signal of the control component itself after multiplication, wherein the signal frequency of the output clock signal of the clock buffer group is less than the signal frequency of the clock signal of the control component itself after multiplication; sampling the output clock signal of the clock buffer group within the signal period of the clock signal of the control component itself after multiplication by the control component to detect the signal state of the output clock signal of the clock buffer group; or,

[0083] inputting the output clock signal of the clock buffer group into a third phase-locked loop for clock frequency division to obtain the output clock signal of the clock buffer group after frequency division, and inputting the clock signal of the control component itself into a fourth phase-locked loop for clock multiplication to obtain the clock signal of the control component itself after multiplication, wherein the signal frequency of the output clock signal of the clock buffer group after frequency division is less than the signal frequency of the clock signal of the control component itself after multiplication; sampling the output clock signal of the clock buffer group after frequency division within the signal period of the clock signal of the control component itself after multiplication by the control component to detect the signal state of the output clock signal of the clock buffer group.

[0084] In this embodiment, it is possible that the frequency of the output clock signal of the clock buffer group is greater than the signal frequency of the clock signal of the control component itself. For example, taking the control component as a CPLD, the CPLD's own clock generally uses an external 25 MHz crystal oscillator clock input, and the PCIE reference clock monitored by the CPLD is 100 MHz. This frequency inequality means that directly using the CPLD's own clock for monitoring may not be able to capture enough clock edges, resulting in inaccurate monitoring results. If it is necessary to monitor the PCIE reference clock, the CPLD's own clock needs to be much higher than the monitored clock to ensure accurate determination of the frequency of the PCIe reference clock.

[0085] Optionally, the output clock signal of the clock buffer group can be input into the first phase-locked loop for clock frequency division to obtain the output clock signal of the clock buffer group after frequency division, where the signal frequency of the output clock signal of the clock buffer group after frequency division is less than the signal frequency of the clock signal of the control component itself; the control component samples the output clock signal of the clock buffer group after frequency division within the signal period of the clock signal of the control component itself to detect the signal state of the output clock signal of the clock buffer group. For example, a 100 MHz PCIe reference clock signal can be frequency-divided through a PLL phase-locked loop and converted into a 5 MHz low-frequency signal, enabling the CPLD to sample the 5 MHz signal multiple times within its own 25 MHz clock period. Five samples can be taken in each CPLD clock period, thereby realizing the frequency judgment of the monitored clock and improving the monitoring accuracy.

[0086] Optionally, the clock signal of the control component itself can also be input into the second phase-locked loop for clock multiplication to obtain the clock signal of the control component itself after multiplication, where the signal frequency of the output clock signal of the clock buffer group is less than the signal frequency of the clock signal of the control component itself after multiplication; the control component samples the output clock signal of the clock buffer group within the signal period of the clock signal of the control component itself after multiplication to detect the signal state of the output clock signal of the clock buffer group. For example, the CPLD's own clock (25 MHz) can be multiplied to 400 MHz through a PLL phase-locked loop, increasing the CPLD's clock frequency. In this way, the CPLD can sample the 100 MHz PCIe reference clock at least four times within each 400 MHz high-speed clock period, also realizing the accurate judgment of the frequency of the monitored clock.

[0087] Optionally, when the number of PLL phase-locked loops inside the CPLD is equal to or greater than two, two methods can be used simultaneously, namely, multiplying the own clock and dividing the monitored clock. The output clock signal of the clock buffer group is input into the third phase-locked loop for clock frequency division to obtain the output clock signal of the clock buffer group after frequency division, and the clock signal of the control component itself is input into the fourth phase-locked loop for clock multiplication to obtain the clock signal of the control component itself after multiplication, where the signal frequency of the output clock signal of the clock buffer group after frequency division is less than the signal frequency of the clock signal of the control component itself after multiplication; the control component samples the output clock signal of the clock buffer group after frequency division within the signal period of the clock signal of the control component itself after multiplication to detect the signal state of the output clock signal of the clock buffer group, so that the advantages of frequency increase and decrease can be combined, enabling the CPLD to capture signal changes with higher resolution and achieve more accurate frequency judgment when monitoring the PCIe reference clock.

[0088] In this embodiment, by using a phase-locked loop to divide or multiply the clock signal, the control component can efficiently sample within its own clock cycle, which can improve the accuracy of monitoring the clock state and further improve the accuracy of power-on control of the device.

[0089] Through the description of the above embodiments, those skilled in the art can clearly understand that the method according to the above embodiments can be implemented by means of software plus a necessary general hardware platform. Of course, it can also be implemented by hardware, but in many cases, the former is a better implementation method.

[0090] According to another aspect of the embodiments of the present application, there is also provided a device power-on control device, which can be used to implement the device power-on control method provided in the above embodiments, and those that have been described will not be repeated. As used below, the term "module" can be a combination of software and / or hardware that can implement a predetermined function. Although the devices described in the following embodiments are preferably implemented in software, implementation in hardware, or a combination of software and hardware is also possible and contemplated.

[0091] Figure 8 is a structural block diagram of an optional device power-on control device according to the embodiments of the present application. As shown in Figure 8 , the device power-on control device includes:

[0092] A first execution unit 802, configured to receive a reference clock signal transmitted by a host end through a clock buffer group when the clock buffer group is powered on, and convert the received reference clock signal into an output clock signal of the clock buffer group, where the output clock signal of the clock buffer group is distributed to a control component;

[0093] A second execution unit 804, configured to detect a signal state of the output clock signal of the clock buffer group through the control component, and perform power-on control on the hardware device through the control component based on the detected signal state.

[0094] It should be noted that the first execution unit 802 in this embodiment can be used to execute the above step S202, and the second execution unit 804 in this embodiment can be used to execute the above step S204.

[0095] Through the embodiments provided in this application, when the clock buffer group is powered on, the reference clock signal transmitted by the host is received through the clock buffer group, and the received reference clock signal is converted into the output clock signal of the clock buffer group. Among them, the output clock signal of the clock buffer group is distributed to the control component; the control component detects the signal state of the output clock signal of the clock buffer group, and based on the detected signal state, the control component controls the power-on of the hardware device, which can solve the technical problem of low stability caused by limited power-on timing control in the device power-on control device in the related art, and achieve the technical effect of improving the accuracy and reliability of the device power-on control.

[0096] In an exemplary embodiment, the clock buffer group is also connected to the hardware device. The second execution unit includes: a power-on module, configured to control the hardware device to be powered on through the control component when it is detected that the output clock signal of the clock buffer group is accessed. Among them, after the hardware device is powered on, the output clock signal of the clock buffer group is also distributed to the hardware device; a reset module, configured to release a reset signal to the hardware device through the control component when it is detected that the signal frequency of the output clock signal of the clock buffer group reaches the signal frequency threshold, so as to reset the hardware device.

[0097] In an exemplary embodiment, the clock buffer group, the control component and the hardware device are located on the same substrate and are connected through a peripheral component interconnect bus. The hardware device is a peripheral component interconnect device, and the number of hardware devices is at least two; the reset module includes: a reset sub-module, configured to release a reset signal on the peripheral component interconnect bus through the control component when it is detected that the signal frequency of the output clock signal of the clock buffer group reaches the signal frequency threshold, so as to reset at least two hardware devices.

[0098] In an exemplary embodiment, the above device further includes: a third execution unit, configured to control the clock buffer group to be powered on through the control component in response to the power-on instruction signal of the host, and open the output channel of the clock buffer group, where the output clock signal of the clock buffer group is transmitted through the output channel of the clock buffer group.

[0099] In an exemplary embodiment, the clock buffer group includes a first clock buffer and a second clock buffer; the first execution unit includes: a first execution module, configured to receive a first reference clock signal transmitted from the host through the first clock buffer, and convert the first reference clock signal into an output clock signal of the first clock buffer; a second execution module, configured to receive a second reference clock signal transmitted from the host through the second clock buffer, and convert the second reference clock signal into an output clock signal of the second clock buffer; wherein, the reference clock signals transmitted from the host include a first reference clock signal and a second reference clock signal.

[0100] In an exemplary embodiment, a level conversion circuit is connected between the output end of the clock buffer group and the input end of the control component; the above device further includes: a fourth execution unit, configured to, after receiving the reference clock signal transmitted from the host through the clock buffer group and converting the received reference clock signal into an output clock signal of the clock buffer group, adjust the level state of the output clock signal of the clock buffer group to a target level state through the level conversion circuit, and input the adjusted output clock signal of the clock buffer group into the signal input end of the control component.

[0101] In an exemplary embodiment, the frequency of the output clock signal of the clock buffer group is greater than the signal frequency of the clock signal of the control component itself; the apparatus further includes: a frequency division unit, configured to input the output clock signal of the clock buffer group into a first phase-locked loop for clock frequency division to obtain a frequency-divided output clock signal of the clock buffer group, wherein the signal frequency of the frequency-divided output clock signal of the clock buffer group is less than the signal frequency of the clock signal of the control component itself; the control component samples the frequency-divided output clock signal of the clock buffer group within the signal period of the clock signal of the control component itself to detect the signal state of the output clock signal of the clock buffer group; or, a frequency multiplication unit, configured to input the clock signal of the control component itself into a second phase-locked loop for clock frequency multiplication to obtain a frequency-multiplied clock signal of the control component itself, wherein the signal frequency of the output clock signal of the clock buffer group is less than the signal frequency of the frequency-multiplied clock signal of the control component itself; the control component samples the output clock signal of the clock buffer group within the signal period of the frequency-multiplied clock signal of the control component itself to detect the signal state of the output clock signal of the clock buffer group; or, a fifth execution unit, configured to input the output clock signal of the clock buffer group into a third phase-locked loop for clock frequency division to obtain a frequency-divided output clock signal of the clock buffer group, and input the clock signal of the control component itself into a fourth phase-locked loop for clock frequency multiplication to obtain a frequency-multiplied clock signal of the control component itself, wherein the signal frequency of the frequency-divided output clock signal of the clock buffer group is less than the signal frequency of the frequency-multiplied clock signal of the control component itself; the control component samples the frequency-divided output clock signal of the clock buffer group within the signal period of the frequency-multiplied clock signal of the control component itself to detect the signal state of the output clock signal of the clock buffer group.

[0102] For the description of the features corresponding to the above device power-on control device in the corresponding embodiment, reference may be made to the relevant description in the corresponding embodiment of the device power-on control method, which will not be elaborated here one by one.

[0103] An embodiment of the present application further provides an electronic device, including a memory and a processor, wherein a computer program is stored in the memory, and the processor is configured to run the computer program to execute the steps in any of the above embodiments of the device power-on control method.

[0104] An embodiment of the present application further provides a computer-readable storage medium, wherein a computer program is stored in the computer-readable storage medium, and the computer program is configured to execute the steps in any of the above embodiments of the device power-on control method when running.

[0105] In an exemplary embodiment, the above computer-readable storage medium may include, but is not limited to: various media capable of storing computer programs, such as USB flash drives, read-only memory (ROM), random access memory (RAM), mobile hard disks, magnetic disks, or optical discs.

[0106] An embodiment of the present application also provides a computer program product. The above computer program product includes a computer program, and when the computer program is executed by a processor, the steps in any of the above embodiments of the device power-on control method are implemented.

[0107] An embodiment of the present application also provides another computer program product, including a non-volatile computer-readable storage medium. The non-volatile computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the steps in any of the above embodiments of the device power-on control method are implemented.

[0108] Those skilled in the art can further realize that the units and algorithm steps of each example described in combination with the embodiments disclosed herein can be implemented by electronic hardware, computer software, or a combination of the two. To clearly illustrate the interchangeability of hardware and software, the composition and steps of each example have been generally described according to functions in the above description. Whether these functions are executed in a hardware or software manner depends on the specific application and design constraints of the technical solution. Skilled professionals can use different methods to implement the described functions for each specific application, but such implementation should not be considered to exceed the scope of this application.

[0109] The above has introduced in detail a device power-on control method and device, a storage medium, and an electronic device provided by the present application. Specific examples are used in this article to elaborate on the principles and implementation manners of the present application. The description of the above embodiments is only used to help understand the method and its core idea of the present application. It should be noted that for those of ordinary skill in the art in the technical field, without departing from the principle of the present application, several improvements and modifications can be made to the present application, and these improvements and modifications also fall within the protection scope of the claims of the present application.

Claims

1. A method for controlling power-on of a device, characterized in that, Applied to an electronic device, the electronic device includes a clock buffer group, a control component, and a hardware device, wherein the clock buffer group is connected to the control component; the method includes: When the clock buffer group is powered on, receive a reference clock signal transmitted from a host through the clock buffer group, and convert the received reference clock signal into an output clock signal of the clock buffer group, wherein the output clock signal of the clock buffer group is distributed to the control component; Detect a signal state of the output clock signal of the clock buffer group through the control component, and based on the detected signal state, perform power-on control on the hardware device through the control component.

2. The method according to claim 1, wherein The clock buffer group is also connected to the hardware device, and the performing power-on control on the hardware device through the control component based on the detected signal state includes: When it is detected that the output clock signal of the clock buffer group is accessed, control the hardware device to power on through the control component, wherein after the hardware device is powered on, the output clock signal of the clock buffer group is also distributed to the hardware device; When it is detected that the signal frequency of the output clock signal of the clock buffer group reaches a signal frequency threshold, release a reset signal to the hardware device through the control component to reset the hardware device.

3. The method according to claim 2, wherein The clock buffer group, the control component, and the hardware device are located on the same substrate and are connected through a peripheral component interconnect bus, the hardware device is a peripheral component interconnect device, and the number of the hardware devices is at least two; The releasing a reset signal to the hardware device through the control component when it is detected that the signal frequency of the output clock signal of the clock buffer group reaches a signal frequency threshold includes: When it is detected that the signal frequency of the output clock signal of the clock buffer group reaches a signal frequency threshold, release a reset signal on the peripheral component interconnect bus through the control component to reset at least two of the hardware devices.

4. The method according to claim 1, wherein The method further includes: In response to a power-on indication signal from the host, control the clock buffer group to power on through the control component and open an output channel of the clock buffer group, wherein the output clock signal of the clock buffer group is transmitted through the output channel of the clock buffer group.

5. The method according to claim 1, wherein The clock buffer group includes a first clock buffer and a second clock buffer; The receiving a reference clock signal transmitted from a host through the clock buffer group and converting the received reference clock signal into an output clock signal of the clock buffer group includes: Receive a first path of reference clock signal transmitted from the host through the first clock buffer, and convert the first path of reference clock signal into an output clock signal of the first clock buffer; Receive a second path of reference clock signal transmitted from the host through the second clock buffer, and convert the second path of reference clock signal into an output clock signal of the second clock buffer; Among them, the path reference clock signals transmitted by the host include the first path reference clock signal and the second path reference clock signal.

6. The method according to claim 1, wherein A level conversion circuit is connected between the output end of the clock buffer group and the input end of the control component; After receiving the reference clock signal transmitted by the host through the clock buffer group and converting the received reference clock signal into the output clock signal of the clock buffer group, the method further includes: Adjusting the level state of the output clock signal of the clock buffer group to a target level state through the level conversion circuit, and inputting the adjusted output clock signal of the clock buffer group into the signal input end of the control component.

7. The method according to any one of claims 1 to 6, characterized in that The signal frequency of the output clock signal of the clock buffer group is greater than the signal frequency of the clock signal of the control component itself; The method further includes: Inputting the output clock signal of the clock buffer group into a first phase-locked loop for clock frequency division to obtain the output clock signal of the clock buffer group after frequency division, where the signal frequency of the output clock signal of the clock buffer group after frequency division is less than the signal frequency of the clock signal of the control component itself; sampling the output clock signal of the clock buffer group after frequency division within the signal period of the clock signal of the control component itself through the control component to detect the signal state of the output clock signal of the clock buffer group; or, Inputting the clock signal of the control component itself into a second phase-locked loop for clock multiplication to obtain the clock signal of the control component itself after multiplication, where the signal frequency of the output clock signal of the clock buffer group is less than the signal frequency of the clock signal of the control component itself after multiplication; sampling the output clock signal of the clock buffer group within the signal period of the clock signal of the control component itself after multiplication through the control component to detect the signal state of the output clock signal of the clock buffer group; or, Inputting the output clock signal of the clock buffer group into a third phase-locked loop for clock frequency division to obtain the output clock signal of the clock buffer group after frequency division, and inputting the clock signal of the control component itself into a fourth phase-locked loop for clock multiplication to obtain the clock signal of the control component itself after multiplication, where the signal frequency of the output clock signal of the clock buffer group after frequency division is less than the signal frequency of the clock signal of the control component itself after multiplication; sampling the output clock signal of the clock buffer group after frequency division within the signal period of the clock signal of the control component itself after multiplication through the control component to detect the signal state of the output clock signal of the clock buffer group.

8. An apparatus power-on control device, characterized in that, Applied to an electronic device, the electronic device includes a clock buffer group, a control component, and a hardware device, where the clock buffer group is connected to the control component; the device includes: A first execution unit, configured to receive a reference clock signal transmitted from a host side through the clock buffer group when the clock buffer group is powered on, and convert the received reference clock signal into an output clock signal of the clock buffer group, wherein the output clock signal of the clock buffer group is distributed to the control component; A second execution unit, configured to detect a signal state of the output clock signal of the clock buffer group through the control component, and perform power-on control on the hardware device through the control component based on the detected signal state.

9. An electronic device, characterized in that, Comprising: A memory, configured to store a computer program; A processor, configured to implement the steps of the device power-on control method according to any one of claims 1 to 7 when executing the computer program.

10. A computer-readable storage medium, characterized in that, A computer program is stored in the computer-readable storage medium, wherein the computer program implements the steps of the device power-on control method according to any one of claims 1 to 7 when being executed by a processor.

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