Server serial port information transmission method and server

Abstract

The embodiment of the invention provides a server serial port information transmission method and a server. In the application, the BMC receives an externally input instruction through management, and then performs write operation on a register indicated by the instruction, and when the CPLD detects that data is written into the register, if the register is an input / output enabled register, the communication state of a corresponding target I / O port is adjusted according to newly written data, so that the communication state of the target I / O port is adjusted. According to the control instruction, the target I / O port is controlled to be in the communication state required by the instruction (the communication state comprises port enabling or port enabling forbidding). Therefore, when the newly written data represents the port enabling forbidding state, the target IO is in the port enabling forbidding state, at the moment, even if the target IO is communicated with the BIOS serial port, the interior of the server cannot be accessed through the BIOS serial port and the target IO, the data in the server can be effectively prevented from being stolen or tampered, and the data potential safety hazard of the server is avoided.

Description

Technical Field

[0001] This application relates to the field of computer technologies, and in particular, to a method for transmitting serial port information of a server and a server. Background Art

[0002] In the management and maintenance of a server, it is necessary to connect the serial ports of the Baseboard Management Controller (BMC) inside the server, the serial ports of the Central Processing Unit (CPU), and the serial ports of core processing components such as the Platform Controller Hub (PCH) to the serial port of the Basic Input / Output System (BIOS) for debugging.

[0003] However, during the debugging process, when any of the above serial ports is connected to the BIOS serial port, it is very easy to steal or tamper with the internal data of the server through this serial port and the BIOS serial port, which poses a security risk to the server data. Summary of the Invention

[0004] In view of this, embodiments of this application provide a method for transmitting serial port information of a server and a server to avoid the security risks of data during server debugging.

[0005] Embodiments of this application provide a method for transmitting serial port information of a server. The method is applied to a server. At least one serial port of the BMC in the server, at least one serial port of the core processing components in the server, and the debugging serial port on the server are respectively connected to the input / output (I / O) ports of the Complex Programmable Logic Device (CPLD) in the server; different serial ports are connected to different I / O ports; the I / O port connected to the debugging serial port on the CPLD is configured with a corresponding input / output enable register and a serial port switching register; the method includes:

[0006] Receiving an externally input instruction through the management network port of the BMC; and, performing a write operation on the register indicated by the instruction through the BMC; the register indicated by the instruction is an input / output enable register or a serial port switching register;

[0007] Detecting each register by the CPLD according to a specified priority order; the input / output enable register has a higher priority than the serial port switching register at least;

[0008] After the CPLD detects that a register has been written with data, if the register is an input / output enable register, adjusting the connection state of the corresponding target I / O port according to the newly written data; the connection state includes: port enabling or port disabling.

[0009] An embodiment of the present application further provides a server, including: a Baseboard Management Controller (BMC), a core processing component, a Complex Programmable Logic Device (CPLD), and a debug serial port;

[0010] At least one serial port of the BMC in the server, at least one serial port of the core processing component in the server, and the debug serial port on the server are respectively connected to the input / output (I / O) ports of the CPLD; different serial ports are connected to different I / O ports; the I / O port on the CPLD connected to the debug serial port is configured with a corresponding input / output enable register and a serial port switching register;

[0011] The BMC is used for: receiving an externally input instruction through the management network port and performing a write operation on the register indicated by the instruction; the register indicated by the instruction is an input / output enable register or a serial port switching register;

[0012] The CPLD is used for: detecting each register according to a specified priority order; the input / output enable register has a higher priority than the serial port switching register at least;

[0013] After detecting that a register has been written with data, if the register is an input / output enable register, the connection state of the corresponding target I / O port is adjusted according to the newly written data; the connection state includes: port enable or port disable enable.

[0014] An embodiment of the present application further provides a machine-readable storage medium, which stores computer program instructions that can implement the steps of the above method when the computer program instructions are executed.

[0015] It can be seen from the above technical solutions that in this embodiment, the BMC receives an externally input instruction through management and then performs a write operation on the register indicated by the instruction. When the CPLD detects that a register has been written with data, if the register is an input / output enable register, the connection state of the corresponding target I / O port is adjusted according to the newly written data to implement controlling the target I / O port to be in the connection state required by the instruction (the connection state includes: port enable or port disable enable) according to the control instruction. In this way, when the newly written data represents the port disable enable state, the target I / O is in the port disable enable state. At this time, even if the target I / O is connected to the BIOS serial port, it is impossible to access the server internal through the BIOS serial port and the target I / O, which can effectively prevent the server internal data from being stolen or tampered with and avoid potential server data security risks. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 It is an architecture diagram of the server provided by an embodiment of the present application;

[0017] Figure 2 Schematic flowchart of the method provided by the embodiment of the present application;

[0018] Figure 3A Schematic diagram of serial port connection provided by the embodiment of the present application;

[0019] Figure 3B Schematic diagram of serial port connection provided by the embodiment of the present application;

[0020] Figure 4 Schematic diagram of the structure of the server provided by the embodiment of the present application. Detailed implementation manners

[0021] In order to enable those skilled in the art to better understand the technical solutions provided by the embodiments of the present application, and to make the above-mentioned objects, features, and advantages of the embodiments of the present application more obvious and understandable, the technical solutions in the embodiments of the present application will be further described in detail below with reference to the accompanying drawings.

[0022] Before introducing the method provided by the embodiment of the present application, the architecture diagram of the server provided by the embodiment of the present application will be described first:

[0023] Please refer to Figure 1 , Figure 1 , which is the architecture diagram of the server provided by the embodiment of the present application. This architecture is the implementation environment of the method provided by the embodiment of the present application. As Figure 1 shown, at least one serial port of the baseboard management controller (BMC) in the server, at least one serial port of the core processing component in the server, and the debug serial port on the server are respectively connected to the input / output (I / O) ports of the complex programmable logic device (CPLD) in the server. Different serial ports are connected to different I / O ports. The I / O port on the CPLD of the server connected to the debug serial port is configured with a corresponding input / output enable register and a serial port switching register.

[0024] Here, the core processing component includes at least a central processing unit (CPU) and a platform controller hub (PCH). The debug serial port includes an internal debug serial port and an external debug serial port. The internal debug serial port refers to the debug serial port located inside the server and can only be seen by opening the server. The external debug serial port refers to the serial port of the basic input / output system (BIOS) of the server.

[0025] Combined with the above network architecture, the method provided by the embodiment of the present application will be described below:

[0026] Please refer toFigure 2 , Figure 2 is the flowchart of the method provided by the embodiment of this application.

[0027] S201, receiving an externally input instruction through the management network port of the BMC; and, performing a write operation on the register indicated by the instruction through the BMC; the register indicated by the instruction is an input / output enable register or a serial port switching register.

[0028] In this embodiment, the serial peripheral interface (SPI) bus is adopted between the BMC and the CPLD for transmitting the externally input instruction. The above instruction carries the indicated register and the data to be written into the register. Optionally, a corresponding register address is configured for each register. After receiving the instruction, the BMC can distinguish the register indicated by the instruction through the address of the register, and write the data carried by the instruction into the indicated register.

[0029] For example, if the address of the input / output enable register is 0x01, and the address carried in the instruction is 0x01, then the BMC writes data into the input / output enable register through the SPI bus.

[0030] In this embodiment, the data to be written for performing the write operation on the register indicated by the instruction needs to be written according to the user's intention. The specific writing rule of the data to be written for the above write operation is related to the type of the indicated register, the number of registers of this type configured in the CPLD, and the number of I / O ports connected to the debug serial port.

[0031] Optionally, as an embodiment, when the indicated register is an input / output enable register, if there are multiple debug serial ports on the server (that is, the number of I / O connected to the debug serial port on the CPLD is multiple), only one input / output enable register is configured on the CPLD, and there is a one-to-one correspondence between each I / O port connected to the debug serial port and the bit on the input / output enable register. At this time, the data to be written for the above write operation is the value on each bit of the output enable register. If it is desired that the target I / O port is in the port enable state, the first value (such as 0) needs to be written on the bit corresponding to the target I / O port. If it is desired that the target I / O port is in the port disable state, the second value (such as 1) needs to be written on the bit corresponding to the target I / O port.

[0032] Optionally, as another embodiment, when the indicated register is the input / output enable register, if the number of debug serial ports of the server is multiple (that is, the number of I / Os connected to the debug serial ports on the CPLD is multiple), an input / output enable register is configured for each I / O connected to the debug serial port on the CPLD of the server, and there is a one-to-one correspondence between each I / O port connected to the debug serial port and each input / output enable register. At this time, the data to be written for the above write operation is the value on the indicated output enable register. If it is desired that the target I / O port is in the port enable state, the first value (such as 0) needs to be written to the output enable register corresponding to the target I / O port. If it is desired that the target I / O port is in the port disable state, the first value (such as 1) needs to be written to the output enable register corresponding to the target I / O port.

[0033] Optionally, as yet another embodiment, when the indicated register is the serial port switching register, if the number of debug serial ports of the server is multiple (that is, the number of I / Os connected to the debug serial ports on the CPLD is multiple), a serial port switching register is configured for each I / O connected to the debug serial port on the CPLD of the server, and there is a one-to-one correspondence between each I / O port connected to the debug serial port and each serial port switching register. At this time, the data to be written for the above write operation is the value on the indicated serial port switching register. The specific value to be written is used to indicate the source port, and the value when each I / O port connected to the BMC serial port or the core processing component serial port on the CPLD is used as the source port needs to be set in advance.

[0034] S202, detect each register through the CPLD according to the specified priority order; the input / output enable register has at least a higher priority than the serial port switching register.

[0035] Optionally, the server further includes a DIP switch connected to the CPLD, and a DIP switch register is configured for the I / O port on the CPLD connected to the DIP switch. The input / output enable register has at least a higher priority than the serial port switching register. The serial port switching register has at least a higher priority than the DIP switch register. That is to say, the inspection is sequentially performed in the order of the input / output enable register, the serial port switching register, and the DIP switch register.

[0036] S203, after the CPLD detects that data is written to the existing / occurred register, if the register is the input / output enable register, adjust the connection state of the corresponding target I / O port according to the newly written data; the connection state includes: port enable or port disable.

[0037] In this embodiment, if the target I / O port is in the port enabled state, it indicates that the target I / O port is in a normal connection state and can perform data interaction with other serial ports. If the target I / O port is in the port disabled state, it indicates that the target I / O port is in an abnormal connection state and cannot perform data interaction with other serial ports.

[0038] The specific implementation of adjusting the connection state of the corresponding target I / O port according to the newly written data in step S203 above can be as follows: when the newly written data is the first value (such as 0), control the corresponding target I / O port to be in the port enabled state; when the newly written data is the second value (such as 1), control the corresponding target I / O port to be in the port disabled state.

[0039] For example, there is only one input / output enable register in the server, and the address of this input / output enable register is 0x01. There are 7 BMC serial ports and 1 PCH serial port on the server. These 7 BMC serial ports and 1 PCH serial port are respectively connected to 8 IO ports on the GPLD. The 8 IO ports on the GPLD are respectively connected to 7 internal debug serial ports and an external debug serial port (i.e., the BIOS serial port) inside the server.

[0040] The correspondence between the bits on the input / output enable register and the I / O ports connecting to the debug serial ports is shown in the following table.

[0041]

[0042] BIT[0] of the 0x01 input / output enable register is connected to the I / O port of the BIOS serial port, and the default is 0 (port enabled state, that is, normal input / output). If the instruction received by the BMC is 0x01 10000000, after the user issues a command to the BMC through the BMC network port, the BMC sets BIT[0] of the input / output enable register 0x01 of the CPLD to 1 through the SPI bus. After the CPLD detects that BIT[0] in its own input / output enable register is 1, it adjusts the I / O port connected to the BIOS serial port to the port disabled state, that is, prohibits this I / O port from performing data exchange with the BIOS serial port.

[0043] Thus, the Figure 1 shown process is completed.

[0044] Through Figure 1As can be seen from the process shown, the BMC receives an externally input instruction through management, and then performs a write operation on the register indicated by the instruction. When the CPLD detects that data has been written to the register, if the register is an input / output enable register, the connection state of the corresponding target I / O port is adjusted according to the newly written data, so as to control the target I / O port to be in the connection state required by the control instruction (the connection state includes: port enable or port disable). In this way, when the state represented by the newly written data is the port disable state, the target IO is in the port disable state. At this time, even if the target IO is connected to the BIOS serial port, the internal data of the server cannot be accessed through the BIOS serial port and the target IO, which can effectively prevent the internal data of the server from being stolen or tampered with, and avoid potential data security risks of the server.

[0045] Based on Figure 2 the embodiment shown, the steps after the serial port switching register is detected to have data written to it are described below:

[0046] After the CPLD detects that data has been written to the register, if the register is a serial port switching register, the connection state between the I / O port corresponding to the serial port switching register and the source port indicated by the data is adjusted according to the newly written data. The adjusted connection state includes: connected or disconnected.

[0047] In specific implementation, the initial state of each serial port switching register is a set value. When any serial port switching register is in the set value, it indicates that there is no data source for the I / O port corresponding to the serial port switching register, that is, it is not connected to any other I / O port in the CPLD.

[0048] The CPLD stores the data that needs to be written to the corresponding serial port switching register when each IO connected to the BMC serial port or the core processing component serial port on the CPLD is used as the source port. That is, the CPLD stores the corresponding relationship between the set data (the data that needs to be written to the above-mentioned serial port switching register) and the I / O port (the I / O used as the data source port mentioned above).

[0049] After the CPLD detects that data has been written to the register, if the register is a serial port switching register, the I / O port that matches the data written to the serial port switching register is found from the corresponding relationship between the obtained set data and the I / O port. The found I / O port is the source port.

[0050] If the I / O port corresponding to the serial port switching register was not previously connected to any I / O, to connect the I / O port corresponding to the serial port switching register to the I / O port found as the data source, optionally, components such as diodes and gate circuits on the link between the two I / O ports are configured to conduct through the logical control of the CPLD.

[0051] If the I / O port corresponding to the serial port switching register was previously connected to other I / O except the I / O port found as the data source, then switch from the originally connected I / O to the I / O found as the data source. Optionally, components such as diodes and gate circuits on the link between the I / O port corresponding to the serial port switching register and the originally connected I / O port are configured not to conduct, and components such as diodes and gate circuits on the link between the I / O port corresponding to the serial port switching register and the I / O found as the data source are configured to conduct.

[0052] For example, continuing with the previous example, the correspondence between the newly written data in the serial port switching register and the I / O of the data source is represented by the following table:

[0053]

[0054] Among them, the serial port switching register 0x02 corresponds to the I / O port 1 on the GPIO connected to the BIOS serial port;

[0055] The serial port switching register 0x03 corresponds to the I / O port 2 on the GPIO connected to the internal debug serial port 1;

[0056] The serial port switching register 0x04 corresponds to the I / O port 3 on the GPIO connected to the internal debug serial port 2;

[0057] The serial port switching register 0x05 corresponds to the I / O port 4 on the GPIO connected to the internal debug serial port 3;

[0058] The serial port switching register 0x06 corresponds to the I / O port 5 on the GPIO connected to the internal debug serial port 4;

[0059] The serial port switching register 0x07 corresponds to the I / O port 6 on the GPIO connected to the internal debug serial port 5;

[0060] The serial port switching register 0x08 corresponds to the I / O port 7 on the GPIO connected to the internal debug serial port 6;

[0061] The serial port switching register 0x09 corresponds to the I / O port 8 on the GPIO connected to the internal debug serial port 7;

[0062] The BMC serial port 1 inside the server is connected to the I / O port 11 on the GPIO;

[0063] The BMC serial port 2 inside the server is connected to the I / O port 12 on the GPIO;

[0064] The BMC serial port 3 inside the server is connected to the I / O port 13 on the GPIO;

[0065] The BMC serial port 4 inside the server is connected to the I / O port 14 on the GPIO;

[0066] The BMC serial port 5 inside the server is connected to the I / O port 15 on the GPIO;

[0067] The BMC serial port 6 inside the server is connected to the I / O port 16 on the GPIO;

[0068] The BMC serial port 7 inside the server is connected to the I / O port 17 on the GPIO;

[0069] The PCH serial port 1 inside the server is connected to the I / O port 18 on the GPIO.

[0070] For example, if the BMC sets the register value of the serial port switching register 0x02 on the CPLD to the binary number 010 through the SPI bus, this indicates that the data source port of the I / O port 1 corresponding to the serial port switching register 0x02 is the I / O port 18 connected to the PCH serial port. At this time, all components on the link between the I / O port 1 and the I / O port 18 are in the conducting state, thus realizing the conduction between the BMC serial port 1 and the BIOS serial port 1. For details, see the appendix Figure 3A .

[0071] Through the above method, by the instruction input by the BMC, any serial port switching register can be controlled to be written with any set data, so that any I / O connected to the debug serial port can be specified as the source port for any I / O connected to the BMC serial port or the serial port of the core processing component, thus realizing the connection of any BMC serial port and the serial port of the core processing component to any debug serial port.

[0072] In the current related technologies, generally only one external debugging serial port, i.e., the serial port of the BIOS, is set on a server. Generally, a PCH serial port or a CPU serial port is selected to be connected to the BIOS serial port to achieve accessing the PCH serial port or the CPU serial port through the BIOS serial port. However, the BMC serial port still remains inside the server. When BMC serial port debugging is required, at this time, it is necessary to manually open the server to access the internal BMC serial port. However, this way of manually opening the server has problems such as cutting off the server service, low efficiency, and poor operation flexibility. And through the method provided by the above embodiments, in the case where only one external debugging serial port is set on this server, it is also possible to connect any BMC serial port to the external debugging serial port, which can achieve accessing the internal BMC serial port without manually opening the server, thereby avoiding the problems of cutting off the server service, low efficiency, and poor operation flexibility existing in manually opening the server to access the internal serial port of the server.

[0073] As an embodiment, if the above instructions allow writing operations on at least two serial port switching registers, and it is detected by the CPLD that there are / occur at least two serial port switching registers being written with data based on the instructions, then according to the data written to each serial port switching register, the connection state between the I / O port corresponding to the serial port switching register and the source port indicated by the data is adjusted. The adjusted connection states include: connecting or disconnecting.

[0074] For example, the BMC sets the register values of the serial port switching register 0x02 and the serial port switching register 0x03 on the CPLD to the binary number 010 through the SPI bus. In this way, it means that the data source of the I / O port 1 corresponding to the serial port switching register 0x02 is the I / O port 11 connected to the BMC serial port 1, and the data source of the I / O port 2 corresponding to the serial port switching register 0x03 is the I / O port 11 connected to the BMC serial port 1. At this time, all components on the link between the I / O port 1 and the I / O port 11 are set to the conducting state, and all components on the link between the I / O port 2 and the external I / O port 11 are set to the conducting state, then the conduction between the BMC serial port 1 and the BIOS serial port 1 is achieved, and the conduction between the BMC serial port 1 and the internal debugging serial port 1 is achieved. For details, see the appendix Figure 3B 。

[0075] It can be seen from the above description that the I / O ports corresponding to at least two serial port switching registers are connected to different debugging serial ports. Through the above method, it is possible to specify the same source port for at least two debugging serial ports, that is, to achieve the function of one-to-many or many-to-one.

[0076] It should be noted that adjusting the connection state between the I / O port corresponding to each serial port switching register and the source port indicated by the data according to the data written into the serial port switching register is executed on the premise that it is determined according to the input / output enable register that the I / O port is in the port enable state.

[0077] In specific implementation, the CPLD sequentially checks whether data is written into each register in the order of the input / output enable register, the serial port switching register, and the DIP switch switching register at each set check time point. After detecting that data is written into the serial port switching register, it is necessary to first determine whether the I / O port corresponding to the serial port switching register is in the port enable state or the port disable state according to the newly written data of the input / output enable register obtained at the previous check time point of the current check time point. Only when the I / O port is in the port enable state can the connection state between the I / O port corresponding to the serial port switching register and the source port indicated by the data be adjusted according to the newly written data in the serial port switching register.

[0078] The above has elaborated in detail the steps after the serial port switching register is detected to have data written into it.

[0079] The following elaborates in detail the steps after the DIP switch switching register is detected to have data written into it.

[0080] The DIP switch switching register writes data when the DIP switch is triggered. By switching the DIP switch between high and low level signals, the values corresponding to the high and low level signals are written into the DIP switch switching register. For example, the high level signal corresponds to a first value (such as 0), and the low level signal corresponds to a second value (such as 1).

[0081] After the CPLD detects that data is written into the register, if the register is the DIP switch switching register, then according to the newly written data, the connection mode of the corresponding at least two target I / O ports is switched; the connection mode includes: the first connection mode or the second connection mode; the source port specified to be connected among the at least two target I / O ports in the first connection mode is different from the source port specified to be connected among the at least two target I / O ports in the first connection mode.

[0082] For example, the number of target I / O ports is 3. It is preset that in the first connection mode (corresponding to the DIP switch being in the high level signal), the source port situations corresponding to each target I / O port are as follows:

[0083] The source port of I / O port 1 connected to the BIOS serial port is I / O port 18 connected to the PCH serial port 1;

[0084] The source port of I / O port 2 connected to the internal test serial port 1 is I / O port 11 connected to the BMC serial port 1;

[0085] The source port of I / O port 3 connected to the internal test serial port 2 is I / O port 12 connected to the BMC serial port 1.

[0086] The second connection mode is preset (corresponding to the dip switch being at a low level signal), and the source port conditions of the respective target I / O ports are as follows:

[0087] The source port of I / O port 1 connected to the BIOS serial port is I / O port 11 connected to the BMC serial port 1;

[0088] The source port of I / O port 2 connected to the internal test serial port 1 is I / O port 18 connected to the BIOS serial port;

[0089] The source port of I / O port 3 connected to the internal test serial port 2 is I / O port 12 connected to the BMC serial port 1.

[0090] When the data written to the dip switch register is 0, it switches to the first connection mode. At this time, the connection conditions of the respective target I / O ports are:

[0091] I / O port 18 is conducted with I / O port 1, and PCH serial port 1 is conducted with the BIOS serial port;

[0092] I / O port 11 is conducted with I / O port 2, and BMC serial port 1 is conducted with the internal test serial port 1;

[0093] I / O port 12 is conducted with I / O port 3, and BMC serial port 2 is conducted with the internal test serial port 2.

[0094] When the data written to the dip switch register is 1, it switches to the second connection mode. At this time, the connection conditions of the respective target I / O ports are:

[0095] I / O port 11 is conducted with I / O port 1, and PCH serial port 1 is conducted with the internal test serial port 1;

[0096] I / O port 18 is conducted with I / O port 2, and BMC serial port 1 is conducted with the BIOS serial port;

[0097] I / O port 12 is conducted with I / O port 3, and the internal test serial port 2 is conducted with the BMC serial port 2.

[0098] It should be noted that according to the newly written data, switching the connection mode of the corresponding at least two target I / O ports is executed on the premise that the serial port switching registers corresponding to the respective at least two target I / O ports are all determined to have not been written with data.

[0099] In specific implementation, the CPLD checks whether data has been written to each register in sequence at each set check time point for the input / output enable register, serial port switching register, and DIP switch switching register. After detecting the data written to the DIP switch switching register, it is necessary to first determine whether each target I / O port is in the port enable state or the port disable state based on the newly written data of the input / output enable register obtained at the previous check time point of the current check time point. When it is determined that each target I / O port is in the port enable state, then based on the values of the serial port switching registers corresponding to each target I / O port obtained at the previous check time point of the current check time point, it is determined whether each serial port switching register is in the initial state. If so, according to the newly written data in the DIP switch switching register, the connection modes of at least two corresponding target I / O ports are switched between the first connection mode and the second connection mode.

[0100] In the above manner, the signal sources of each target IO port can be switched according to the manual operation of the DIP switch. This method that supports two working modes of automatic signal source switching and manual signal source switching can improve the applicability of this method.

[0101] The above has elaborated in detail on the steps after the DIP switch switching register is detected to have data written to it.

[0102] The above has described the method provided by the embodiments of this application. Next, the server provided by the embodiments of this application will be described:

[0103] See Figure 4 , Figure 4 which is the structural diagram of the server provided by the embodiments of this application. As Figure 4 shown, the server includes: a management controller BMC401, a core processing component 402, a complex programmable logic device CPLD403, and a debug serial port (not shown in the figure).

[0104] At least one serial port of the management controller BMC401 in the server, at least one serial port of the core processing component 402 in the server, and the debug serial port on the server are respectively connected to the input / output I / O ports of the CPLD403; different serial ports are connected to different I / O ports; the I / O port on the CPLD403 connected to the debug serial port is configured with a corresponding input / output enable register and serial port switching register;

[0105] The BMC401 is used for: receiving an externally input instruction through the management network port and performing a write operation on the register indicated by the instruction; the register indicated by the instruction is the input / output enable register or the serial port switching register;

[0106] CPLD403 is used for: detecting each register according to the specified priority order; the input / output enable register has at least a higher priority than the serial port switching register;

[0107] After detecting that the existence / occurrence register is written with data, if the register is the input / output enable register, then according to the newly written data, adjust the connection state of the corresponding target I / O port; the connection state includes: port enable or port disable enable.

[0108] As an embodiment, the server further includes a DIP switch connected to the CPLD403, and the I / O port on the CPLD403 connected to the DIP switch is configured with a DIP switch register;

[0109] The input / output enable register has at least a higher priority than the serial port switching register;

[0110] The serial port switching register has at least a higher priority than the DIP switch register.

[0111] As an embodiment, the instruction allows writing operations on at least two serial port switching registers; the CPLD403 is further used for:

[0112] Detect that at least two serial port switching registers are written with data based on the instruction, then according to the data written to each serial port switching register, adjust the connection state between the I / O port corresponding to the serial port switching register and the source port indicated by the data, and the adjusted connection state includes: connection or disconnection.

[0113] As an embodiment, adjusting the connection state between the I / O port corresponding to each serial port switching register and the source port indicated by the data is performed on the premise that it is determined according to the input / output enable register that the I / O port is in the port enable state.

[0114] As an embodiment, the source port indicated by the data is determined through the following steps:

[0115] From the obtained correspondence between the set data and the I / O ports, find the I / O port that matches the data written to the serial port switching register, and the found I / O port is the source port.

[0116] As an embodiment, the CPLD403 is further used for:

[0117] After detecting that data is written to the presence / occurrence register, if the register is a DIP switch register, the connection modes of the corresponding at least two target I / O ports are switched according to the newly written data; the connection modes include: a first connection mode or a second connection mode; the source ports designated to be connected among the at least two target I / O ports in the first connection mode are different from the source ports designated to be connected among the at least two target I / O ports in the first connection mode.

[0118] As an embodiment, switching the connection modes of the corresponding at least two target I / O ports according to the newly written data is performed on the premise that the serial port switching registers corresponding to the at least two target I / O ports are all determined to have not been written with data.

[0119] As an embodiment, instructions are transmitted between BMC401 and CPLD403 using a Serial Peripheral Interface (SPI) bus.

[0120] As an embodiment, the core processing component 402 includes a central processing unit (CPU) and / or a platform controller hub (PCH).

[0121] As an embodiment, the debug serial port includes an external debug serial port (BIOS serial port) and / or an internal debug serial port.

[0122] Thus far, the Figure 4 structural description of the shown server is completed.

[0123] The above are only embodiments of the present application and are not used to limit the present application. For those skilled in the art, various changes and modifications can be made to the present application. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included within the scope of the claims of the present application.

Claims

1. A server serial port information transmission method, characterized in that: The method is applied to a server; at least one serial port of a management controller BMC in the server, at least one serial port of a core processing component in the server, and a debugging serial port on the server are respectively connected to an input / output I / O port of a complex programmable logic device CPLD in the server; Different serial ports connect to different I / O ports; The I / O port on the CPLD connected to the debug serial port is configured with a corresponding input / output enable register and a serial port switching register; the method comprises: An external input instruction is received through the management network port of the BMC; and a write operation is performed on the register indicated by the instruction through the BMC; the register indicated by the instruction is an input / output enable register or a serial port switching register; The CPLD detects each register according to a specified priority order; the input and output enable register at least takes precedence over the serial port switch register; After the CPLD detects that data is written into the existence / occurrence register, if the register is an input / output enable register, the connectivity state of the corresponding target I / O port is adjusted according to the newly written data; the connectivity state includes: port enable or port disable.

2. The method according to claim 1, characterized in that The server further comprises a dip switch connected to the CPLD, and an I / O port on the CPLD connected to the dip switch is configured with a dip switch register; The input / output enable register at least takes precedence over the serial port switch register; The serial port switch register at least takes precedence over the DIP switch register.

3. The method according to claim 1, characterized in that The instruction allows writing operations to be performed on at least two serial port switching registers; the method further comprises: When the CPLD detects that there are / occurs at least two serial port switching registers to which data is written based on the instruction, the connection status between the I / O port corresponding to the serial port switching register and the source port indicated by the data is adjusted according to the data written into each serial port switching register, and the adjusted connection status includes: connection or cancellation.

4. The method according to claim 3, characterized in that The adjusting of the connection status between the I / O port corresponding to each serial port switching register and the source port indicated by the data according to the data written into the serial port switching register is performed on the premise that the I / O port is in the port enable state according to the input / output enable register.

5. The method according to claim 3, characterized in that: The source of the data indication is determined by the following steps: From the obtained correspondence between the set data and the I / O port, an I / O port matching the data written into the serial port switch register is found, and the found I / O port is the source port.

6. The method according to claim 1, characterized in that The method further comprises: After the CPLD detects that data is written to the existence / occurrence register, if the register is a DIP switch register, the connection mode of the corresponding at least two target I / O ports is switched according to the newly written data; the connection mode includes: a first connection mode or a second connection mode; the source port designated to be connected among the at least two target I / O ports in the first connection mode is different from the source port designated to be connected among the at least two target I / O ports in the first connection mode.

7. The method according to claim 5, characterized in that The switching of the connection modes of the corresponding at least two target I / O ports according to the newly written data is performed on the premise that the serial port switching registers corresponding to the at least two target I / O ports are determined to have no data written thereto.

8. A server, characterized in that: include: Management controller BMC, core processing components, complex programmable logic device CPLD, and debug serial port; At least one serial port of a management controller BMC in the server, at least one serial port of a core processing component in the server, and a debugging serial port on the server are respectively connected to an input and output I / O port of the CPLD; Different serial ports are connected to different I / O ports; the I / O port connected to the debug serial port on the CPLD is configured with corresponding input and output enable registers and serial port switching registers; The BMC is used to: receive an external input instruction through a management network port, and perform a write operation on a register indicated by the instruction; the register indicated by the instruction is an input / output enable register or a serial port switching register; The CPLD is used to: detect each register according to a specified priority order; the input and output enable register at least takes precedence over the serial port switch register; After detecting that data is written into the existence / occurrence register, if the register is an input / output enable register, the connectivity state of the corresponding target I / O port is adjusted according to the newly written data; the connectivity state includes: port enable or port disable.

9. The server according to claim 8, characterized in that: The server further comprises a dip switch connected to the CPLD, and an I / O port on the CPLD connected to the dip switch is configured with a dip switch register; The input / output enable register at least takes precedence over the serial port switch register; The serial port switching register at least takes precedence over the DIP switch register; and / or, The instruction allows writing operations to be performed on at least two serial port switching registers; and the CPLD is further used for: When it is detected that at least two serial port switch registers are written with data based on the instruction, the connection state between the I / O port corresponding to each serial port switch register and the source port indicated by the data is adjusted according to the data written to the serial port switch register, and the adjusted connection state includes: connection or cancellation; and / or, The step of adjusting the connection state between the I / O port corresponding to each serial port switch register and the source port indicated by the data according to the data written into the serial port switch register is performed on the premise that the I / O port is in the port enable state according to the input / output enable register; and / or, The source of the data indication is determined by the following steps: From the obtained correspondence between the set data and the I / O port, an I / O port matching the data written into the serial port switch register is found, and the found I / O port is the source port.

10. The server according to claim 8, characterized in that: The CPLD is further used for: After detecting that data is written into the existence / occurrence register, if the register is a DIP switch register, the connection mode of the corresponding at least two target I / O ports is switched according to the newly written data; the connection mode includes: a first connection mode or a second connection mode; the source port designated to be connected among the at least two target I / O ports in the first connection mode is different from the source port designated to be connected among the at least two target I / O ports in the first connection mode; and / or, The switching of the connection modes of the corresponding at least two target I / O ports according to the newly written data is performed under the premise that the serial port switching registers corresponding to the at least two target I / O ports are determined to have no data written thereto; and / or, The BMC and the CPLD use a serial peripheral interface (SPI) bus to transmit the instructions. and / or, The core processing component includes a core processor CPU and / or a platform controller PCH.

Images