Instruction merging system based on cost model

Abstract

The invention relates to the technical field of integrated circuits, in particular to an instruction merging system based on a cost model, which is characterized in that a plurality of reference merging schemes are determined through 2 * N instructions to be merged, and the number of copy instructions corresponding to each reference merging scheme is determined; performing cost evaluation on the reference merging schemes according to the number of the copy instructions, and selecting the reference merging schemes corresponding to the number of the copy instructions meeting the first preset condition as target merging schemes, so as to select the reference merging schemes with the smaller number of the copy instructions as far as possible as the target merging schemes; according to the instruction merging method and device, when all the to-be-merged instructions are merged according to the target merging scheme, the number of additionally-added copy instructions is small, then the instruction execution efficiency of the instruction merging operation is improved, and therefore the instruction execution efficiency is improved.

Description

Technical Field

[0001] The present invention relates to the field of integrated circuit technology, and particularly to an instruction merging system based on a cost model. Background Art

[0002] During the execution of traditional GPU instructions, there is a large amount of instruction overhead. For example, stages such as instruction fetching, decoding, and issuing all consume a certain amount of time and hardware resources. Instruction merging operations can merge multiple instructions with similar functions or correlations into a composite instruction, reducing the total number of instructions, thereby shortening the total instruction execution time and improving the running speed and efficiency of the GPU.

[0003] Generally, an instruction includes a destination operand and source operands. The destination operand and source operands included in the instructions to be merged can be regarded as respectively occupying one sub-register, while the destination operand and source operands included in the composite instruction can be regarded as respectively occupying multiple consecutively addressed sub-registers. Therefore, when performing an instruction merging operation, if the sub-register addresses corresponding to a group of operands of two instructions to be merged are not consecutive, additional copy instructions need to be added. Obviously, if multiple copy instructions need to be added for the merging of two instructions to be merged, the number of instructions will instead increase, making it difficult to achieve the expected improvement in instruction execution efficiency, and even possibly resulting in a decrease in instruction execution efficiency.

[0004] Therefore, how to determine a reasonable merging scheme to improve the instruction execution efficiency as much as possible has become an urgent problem to be solved. Summary of the Invention

[0005] In view of the above technical problems, the technical solution adopted by the present invention is as follows: An instruction merging system based on a cost model, the system comprising: a processor and a memory storing a computer program, when the computer program is executed by the processor, the following steps are implemented: S101, obtain 2×N instructions to be merged, where N is a positive integer, and the instructions to be merged include a destination operand and source operands.

[0006] S102, determine a plurality of reference merging schemes and the number of copy instructions respectively corresponding to each reference merging scheme according to each instruction to be merged.

[0007] S103, select the reference merging scheme corresponding to the number of copy instructions that meets the first preset condition as the target merging scheme.

[0008] S104, merge each instruction to be merged according to the target merging scheme to obtain a plurality of target merged instructions and a plurality of copy instructions.

[0009] The present invention has obvious beneficial effects compared with the prior art. By means of the above technical solution, an instruction merging system based on a cost model provided by the present invention can achieve quite remarkable technological progressiveness and practicality, and has extensive utilization value in the industry. It has at least the following beneficial effects: The present invention provides an instruction merging system based on a cost model. The system includes: a processor and a memory storing a computer program. When the computer program is executed by the processor, the following steps are implemented: S101, obtaining 2×N instructions to be merged, where N is a positive integer, and the instructions to be merged include destination operands and source operands; S102, determining a plurality of reference merging schemes and the number of copy instructions corresponding to each reference merging scheme according to each instruction to be merged; S103, selecting the reference merging scheme corresponding to the number of copy instructions that meets the first preset condition as the target merging scheme; S104, merging each instruction to be merged according to the target merging scheme to obtain a plurality of target merged instructions and a plurality of copy instructions.

[0010] It can be seen that a plurality of reference merging schemes are determined through 2×N instructions to be merged, and the number of copy instructions corresponding to each reference merging scheme is determined. The cost of each reference merging scheme is evaluated according to the number of copy instructions, and the reference merging scheme corresponding to the number of copy instructions that meets the first preset condition is selected as the target merging scheme. Thus, a reference merging scheme with a relatively small number of copy instructions is preferably selected as the target merging scheme, so that when each instruction to be merged is merged according to the target merging scheme, the number of additional copy instructions is small, and further, the improvement of the instruction execution efficiency caused by the instruction merging operation is increased, thereby improving the instruction execution efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following will briefly introduce the drawings required for the description of the embodiments. Obviously, the following drawings are only some embodiments of the present invention. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0012] Figure 1 It is a first flowchart diagram when the computer program in an instruction merging system based on a cost model provided in Embodiment 1 of the present invention is executed by a processor; Figure 2 It is a first schematic diagram of instruction merging in an instruction merging system based on a cost model provided in Embodiment 1 of the present invention; Figure 3 It is a second schematic diagram of instruction merging in an instruction merging system based on a cost model provided in Embodiment 1 of the present invention; Figure 4The third schematic diagram of instruction merging in an instruction merging system based on a cost model provided in Embodiment 1 of the present invention; Figure 5 The fourth schematic diagram of instruction merging in an instruction merging system based on a cost model provided in Embodiment 1 of the present invention; Figure 6 The second flowchart of a computer program when executed by a processor in an instruction merging system based on a cost model provided in Embodiment 2 of the present invention; Figure 7 The third flowchart of a computer program when executed by a processor in an instruction merging system based on a cost model provided in Embodiment 3 of the present invention; Figure 8 The schematic diagram of constructing an instruction dependency chain in an instruction merging system based on a cost model provided in Embodiment 3 of the present invention; Figure 9 The fourth flowchart of a computer program when executed by a processor in an instruction merging system based on a cost model provided in Embodiment 4 of the present invention. Detailed implementation manners

[0013] Next, the technical solutions in the embodiments of the present invention will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative efforts belong to the scope of protection of the present invention.

[0014] Embodiment 1 of the present invention provides an instruction merging system based on a cost model. Refer to Figure 1 , which is the first flowchart of a computer program when executed by a processor in an instruction merging system based on a cost model provided in Embodiment 1 of the present invention. The system includes: S101. Obtain 2×N instructions to be merged, where N is a positive integer, and the instructions to be merged include destination operands and source operands; S102. Determine a number of reference merging schemes and the number of copy instructions corresponding to each reference merging scheme according to each instruction to be merged; S103. Select the reference merging scheme corresponding to the number of copy instructions that meets the first preset condition as the target merging scheme; S104. Merge each instruction to be merged according to the target merging scheme to obtain a number of target merged instructions and a number of copy instructions.

[0015] Among them, the instructions to be merged may include a destination operand and several source operands. The reference merging scheme may include the merging combinations of all the instructions to be merged. The number of copy instructions corresponding to the reference merging scheme may refer to the number of copy instructions increased after merging all the instructions to be merged according to the reference merging scheme.

[0016] The first preset condition can be used to measure the impact of the reference merging scheme on the instruction execution efficiency, which is characterized in that the fewer the number of copy instructions, the higher the instruction execution efficiency.

[0017] Specifically, refer to Figure 2 , which is the first schematic diagram of instruction merging in an instruction merging system based on a cost model provided in Embodiment 1 of the present invention. Among them, this first schematic diagram takes the merging of multiply-add instructions as an example. Each multiply-add instruction to be merged includes a destination operand DST and three source operands SRC0, SRC1, and SRC2. SRC0_lo may represent the low-order part of the first source operand after merging, SRC0_hi may represent the high-order part of the first source operand after merging, SRC1_lo may represent the low-order part of the second source operand after merging, SRC1_hi may represent the high-order part of the second source operand after merging, SRC2_lo may represent the low-order part of the third source operand after merging, SRC2_hi may represent the high-order part of the third source operand after merging, DST_lo may represent the low-order part of the destination operand calculated by the merged source operands, and DST_hi may represent the high-order part of the destination operand calculated by the merged source operands. It can be seen that when merging instructions, the source operand SRC0 in two multiply-add instructions to be merged is merged into a single source operand according to the high-order part and the low-order part, the source operand SRC1 in two multiply-add instructions to be merged is merged into a single source operand according to the high-order part and the low-order part, the source operand SRC2 in two multiply-add instructions to be merged is merged into a single source operand according to the high-order part and the low-order part, and the destination operand calculated by the merged source operands is split according to the high-order part and the low-order part to obtain the destination operands corresponding to the two multiply-add instructions to be merged respectively.

[0018] Refer to Figure 3 , which is the second schematic diagram of instruction merging in an instruction merging system based on a cost model provided in Embodiment 1 of the present invention. Among them, this third schematic diagram takes the merging of multiply-add instructions as an example. When the 32-bit operation bits %218_lo and %25_lo corresponding to two multiply-add instructions to be merged are not adjacent in address, it is necessary to splice %218_lo and %25_lo into a 64-bit register, thereby generating a copy operation.

[0019] Refer to Figure 4, which is the third schematic diagram of instruction merging in an instruction merging system based on a cost model provided by Embodiment 1 of the present invention. Among them, this third schematic diagram takes the merging of multiply-add instructions as an example. There are address constraints on registers %119 and %120. If the first two multiply-add instructions are merged, when the subsequent fourth and fifth multiply-add instructions are merged, %220 and %221 will both generate copy operations due to address constraints. And due to data dependency issues, that is, the source operand %221 of the fourth and fifth multiply-add instructions merged is the target operand of the third multiply-add instruction, resulting in the third multiply-add instruction not being able to be merged. However, if the second and third multiply-add instructions are merged, no copy operation will be generated due to address constraints, effectively reducing the number of copy instructions.

[0020] See Figure 5 , which is the fourth schematic diagram of instruction merging in an instruction merging system based on a cost model provided by Embodiment 1 of the present invention. Among them, this fourth schematic diagram takes the merging of multiply-add instructions as an example. Registers %218_lo and %25_lo are reused in multiple instruction mergings. Although copy operations are generated at this time, there is still a performance gain.

[0021] If there is no reference merging scheme corresponding to the number of copy instructions that meets the first preset condition, it means that the instruction merging operation at this time is a negative gain for the instruction execution efficiency. Then the target merging scheme is not to merge the 2×N instructions to be merged. Correspondingly, the number of target merged instructions and copy instructions is both 0.

[0022] In Embodiment 1, several reference merging schemes are determined from the 2×N instructions to be merged, and the number of copy instructions corresponding to each reference merging scheme is determined. The reference merging schemes are evaluated based on the number of copy instructions, and the reference merging scheme corresponding to the number of copy instructions that meets the first preset condition is selected as the target merging scheme. Thus, a reference merging scheme with a relatively small number of copy instructions is preferably selected as the target merging scheme, so that when the instructions to be merged are merged according to the target merging scheme, the number of additional copy instructions is relatively small, and further the improvement of the instruction merging operation on the instruction execution efficiency is increased, thereby improving the instruction execution efficiency.

[0023] Embodiment 2 of the present invention provides an instruction merging system based on a cost model. See Figure 6 , which is the second flowchart of the computer program executed by the processor in an instruction merging system based on a cost model provided by Embodiment 2 of the present invention. The step of determining several reference merging schemes and the number of copy instructions corresponding to each reference merging scheme according to each instruction to be merged includes: S201. Randomly combine every two of the 2×N instructions to be merged to form P temporary merging schemes, where each temporary merging scheme contains N temporary instruction combinations, and P = (2N - 1)!!. S202. Take each temporary merging scheme as a reference merging scheme. S203. Determine the number of copy instructions corresponding to each reference merging scheme respectively.

[0024] Among them, when randomly combining every two of the 2×N instructions to be merged, each instruction to be merged can only belong to one temporary instruction combination, and there are P combination methods, that is, P temporary merging schemes. P = (2N - 1)!! = (2N - 1)×(2N - 3)×(2N - 5)×…×3×1, and (2N - 1)!! represents double factorial calculation.

[0025] It should be noted that for the convenience of description in this embodiment, it is described by taking two instructions to be merged into one instruction as an example. In the actual application scenario, the implementer can make adaptive modifications to this embodiment to apply it to the scenario where multiple instructions to be merged are merged into one instruction. Randomly combine Z of the Z×N instructions to be merged to form P temporary merging schemes. At this time, the general calculation method is P = ((Z×N)!) / ((Z!) N ×N!), and Z can be an integer greater than 1.

[0026] In a specific implementation manner, the determining the number of copy instructions corresponding to each reference merging scheme respectively includes: S2031. For the p-th reference merging scheme, determine the initial number of copy instructions a1 = (L + 1)×N of this reference merging scheme, where L is the number of source operands in the instructions to be merged, and p is an integer within the range of [1, P]. S2032. Traverse each group of operands in each temporary instruction combination in this reference merging scheme. When the two sub-data corresponding to a group of operands belong to the same register, update the address constraint count value a2 to a2 = a2 + 1 to obtain the corresponding address constraint count value a2 at the end of the traversal. Among them, the operands include destination operands and source operands. A single operand in a single instruction to be merged corresponds to a sub-data, and a single register contains two sub-data, and the initial value of a2 is 0. S2033. Traverse each group of destination operands in each temporary instruction combination in this reference merging scheme. When a group of destination operands are the same as b groups of source operands, update the instruction dependence count value a3 to a3 = a3 + b - 1, where the initial value of a3 is 0. S2034. Traverse each group of source operands in each temporary instruction combination in the reference merging scheme. When a group of source operands is the same as each of the c groups of source operands, update the instruction repetition count value a4 to a4 = a4 + c - 1, where the initial value of a4 is 0; S2035. Determine the number of copy instructions A corresponding to the p-th reference merging scheme p = a1 - a2 - a3 - a4.

[0027] Among them, since copy operations may be generated for each group of source operands and destination operands, in this embodiment, it is default that a copy operation is to copy a sub-data to an adjacent position in the register where another sub-data is located. Therefore, it is default that only one copy instruction is generated for one copy operation. The implementer can adjust the calculation method of the initial number of copy instructions according to the actual situation. For example, when the copy operation is to copy two sub-data to adjacent positions in a new register, then a1 = 2×(L + 1)×N.

[0028] When the two sub-data corresponding to a group of operands belong to the same register, it means that at this time, this group of operands does not need a copy operation and can directly obtain the operands required for the merging instruction from a single register. The address constraint count value can be increased by 1, and in the subsequent process, the address constraint count value is subtracted from the initial number of copy instructions.

[0029] When a group of destination operands is the same as each of the b groups of source operands, it means that the destination operands of one merging instruction can be reused in other b merging instructions. At this time, this group of destination operands only needs one copy operation to belong to the same register. Therefore, increase the instruction dependence count value by b - 1. Similarly, in the subsequent process, subtract the instruction dependence count value from the initial number of copy instructions.

[0030] When a group of source operands is the same as each of the c groups of source operands, at this time, this group of source operands only needs one copy operation to belong to the same register. Therefore, increase the instruction repetition count value by c - 1. Similarly, in the subsequent process, subtract the instruction repetition count value from the initial number of copy instructions.

[0031] The number of copy instructions A corresponding to the p-th reference merging scheme p = a1 - a2 - a3 - a4, which can accurately represent the number of additional copy instructions required for the p-th reference merging scheme.

[0032] In a specific implementation manner, the step of selecting the reference merging scheme corresponding to the number of copy instructions that meets the first preset condition as the target merging scheme includes: Determine the smallest number of copy instructions from the numbers of copy instructions corresponding to the P reference merging schemes as the number of copy instructions that meets the first preset condition; Select the reference merging scheme corresponding to the number of copy instructions that meets the first preset condition as the target merging scheme.

[0033] Among them, the number of copy instructions that meets the first preset condition can be expressed as min p∈(1,P) (A p ).

[0034] In one embodiment, determine the minimum number of copy instructions from the number of copy instructions corresponding to P reference merging schemes. If the minimum number of copy instructions meets the condition of being less than N, determine the minimum number of copy instructions as the number of copy instructions that meets the first preset condition, so as to avoid the situation where the number of instructions remains unchanged or increases after instruction merging.

[0035] In the second embodiment, all merging schemes are evaluated by an enumeration method, which can fully evaluate the optimization benefits and overheads, minimize the generated copy instructions, obtain the optimal target merging scheme, and thus improve the efficiency of instruction execution.

[0036] The third embodiment provides an instruction merging system based on a cost model. Refer to Figure 7 , which is the third process schematic diagram when the computer program in an instruction merging system based on a cost model provided by the third embodiment of the present invention is executed by a processor. Determining a plurality of reference merging schemes and the number of copy instructions respectively corresponding to each reference merging scheme according to each instruction to be merged includes: S301, form M instruction dependency chains according to the destination operands and source operands of each instruction to be merged, where M is an integer less than or equal to N. The instruction dependency chain includes at least two instructions to be merged with a dependency relationship. The two instructions to be merged with a dependency relationship meet the condition that the target operand of one instruction to be merged is the source operand of another instruction to be merged; S302, randomly combine the M instruction dependency chains in pairs to form Q first dependency chain combination schemes. A single first dependency chain combination scheme contains D first dependency chain combinations. When M is odd, D = (M - 1) / 2; when M is even, D = M / 2; S303, for the q-th first dependency chain combination scheme, retain the first dependency chain combinations without a dependency relationship in the D first dependency chain combinations in the first dependency chain combination scheme to obtain E first dependency chain combinations. The two first dependency chain combinations with a dependency relationship meet the condition that among the several combinations to be merged determined according to the two first dependency chain combinations, there is a combination to be merged in which the target operand of one instruction to be merged is the source operand of another instruction to be merged. q is an integer within the range of [1, Q]; S304. Determine f1 first combinations to be merged according to E first dependency chain combinations, and form a dependency instruction combination scheme from the f1 first combinations to be merged; S305. Randomly combine every two of all the instructions to be merged that do not belong to the f1 first combinations to be merged to form R(q) remaining instruction combination schemes; S306. According to the dependency instruction combination scheme and the R(q) remaining instruction combination schemes, form R(q) intermediate merging schemes as reference merging schemes; S307. Traverse Q first dependency chain combination schemes to obtain S reference merging schemes, where ; S308. Determine the number of copy instructions corresponding to each reference merging scheme.

[0037] Among them, the first dependency chain combination scheme only involves the combination method of instruction dependency chains. That is, a single first dependency chain combination scheme contains D first dependency chain combinations. When there is a dependency relationship in the first dependency chain combination, the situation where the sub-data required by the instruction cannot be obtained will occur. That is, among the several combinations to be merged determined by the first dependency chain combination, there is a target operand of a to-be-merged instruction in a combination to be merged that is the source operand of another to-be-merged instruction, resulting in the instruction being unable to execute normally. Therefore, retain the first dependency chain combinations without dependency relationships among the D first dependency chain combinations in the first dependency chain combination scheme to obtain E first dependency chain combinations.

[0038] And due to the fact that the number of instructions to be merged included in the first dependency chain combination may be different, resulting in instructions to be merged that do not form the first combinations to be merged, instructions to be merged in the first dependency chain combination with a dependency relationship, and instructions to be merged that exist independently and do not belong to the instruction dependency chain, these are the instructions to be merged that do not belong to the f1 first combinations to be merged.

[0039] Specifically, refer to Figure 8 , which is a schematic diagram of the construction of an instruction dependency chain in an instruction merging system based on a cost model provided in Embodiment 3 of the present invention. Among them, this schematic diagram takes the multiplication-addition instruction merging as an example. The destination operand of the first multiplication-addition instruction is the source operand of the second multiplication-addition instruction, the destination operand of the second multiplication-addition instruction is the source operand of the third multiplication-addition instruction, and the destination operand of the third multiplication-addition instruction is the source operand of the fourth multiplication-addition instruction, thus forming an instruction dependency chain of four multiplication-addition instructions.

[0040] In a specific implementation manner, the determining f1 first combinations to be merged according to E first dependency chain combinations and forming a dependency instruction combination scheme from the f1 first combinations to be merged includes: S3041. For any first dependency chain combination, match the to-be-merged instructions in the two instruction dependency chains in the first dependency chain combination in sequence to obtain f1 first to-be-merged combinations; S3042. Form a dependency instruction combination scheme from the f1 first to-be-merged combinations.

[0041] Among them, in the instruction dependency chain, the to-be-merged instructions are sorted according to the dependency order. If the destination operand of a to-be-merged instruction is the source operand of another to-be-merged instruction, then this to-be-merged instruction is before the other to-be-merged instruction to ensure that the other to-be-merged instruction can obtain its source operand when executed.

[0042] In the third embodiment, by constructing the dependency chain, the number of generated schemes is effectively reduced, the schemes with a greater possibility of improving the efficiency are preferentially generated, the computational burden is reduced, and the efficiency of generating the instruction merging scheme is improved.

[0043] The fourth embodiment provides an instruction merging system based on a cost model. Refer to Figure 9 , which is the fourth process schematic diagram when the computer program in the instruction merging system based on the cost model provided by the fourth embodiment of the present invention is executed by the processor. Determining a plurality of reference merging schemes and the number of copy instructions corresponding to each reference merging scheme according to each to-be-merged instruction includes: S401. According to the destination operands and source operands of each to-be-merged instruction, form M instruction dependency chains, where M is an integer less than or equal to N. The instruction dependency chain includes at least two to-be-merged instructions with a dependency relationship. The two to-be-merged instructions with a dependency relationship meet the condition: the destination operand of one to-be-merged instruction is the source operand of the other to-be-merged instruction; S402. Determine the merging priorities corresponding to the M instruction dependency chains respectively according to the number of to-be-merged instructions included in the M instruction dependency chains; S403. According to the merging priorities corresponding to the M instruction dependency chains respectively, form a dependency chain matching pair sequence in the order from largest to smallest of the sum of the merging priorities. The dependency chain matching pair sequence includes M(M - 1) / 2 dependency chain matching pairs; S404. Initialize the selection flag I = 1; S405. Use the I-th dependency chain matching pair in the dependency chain matching pair sequence as a second dependency chain combination, and randomly combine the remaining M - 2 instruction dependency chains in pairs to form J dependency chain combination schemes; S406. For the j-th dependency chain combination scheme, determine T(j) basic merging schemes as reference merging schemes, where the initial value of j is 1, and j is an integer within the range of [1, J]; S407. Determine the number of copy instructions corresponding to each reference merging scheme.

[0044] Among them, when forming a sequence of dependency chain matching pairs, if the sum of the merging priorities of the dependency chain matching pairs is the same, they can be randomly sorted.

[0045] According to the remaining M - 2 instruction dependency chains, randomly combining them in pairs can form J dependency chain combination schemes. In the j-th dependency chain combination scheme, several second combinations to be merged can be formed according to each second dependency chain included in the j-th dependency chain combination scheme, and T(j) basic merging schemes can be formed according to the instructions to be merged not in the second combinations to be merged, and then T(j) reference merging schemes can be determined.

[0046] In a specific implementation manner, the step of selecting the reference merging scheme corresponding to the number of copy instructions that meets the first preset condition as the target merging scheme includes: S408, determine the smallest number of copy instructions from the number of copy instructions corresponding to each reference merging scheme. If the smallest number of copy instructions is less than the preset threshold, it is determined that the smallest number of copy instructions meets the first preset condition, and the reference merging scheme corresponding to the smallest number of copy instructions is used as the target merging scheme; S409, otherwise, update j = j + 1, and return to execute step S406 until the target merging scheme is determined or j = J + 1. When j = J + 1, execute step S410; S410, update I = I + 1, and return to execute step S405 until the target merging scheme is determined or I = (M(M - 1) / 2)+1. When I = (M(M - 1) / 2)+1, it is determined that the target merging scheme is not to perform merging.

[0047] Among them, in order to improve the efficiency of scheme determination, the implementer can set a preset threshold. When the smallest number of copy instructions determined from the number of copy instructions corresponding to each reference merging scheme is less than the preset threshold, it can be considered that the expected optimization effect of instruction execution efficiency can be achieved.

[0048] Specifically, when determining the smallest number of copy instructions from the number of copy instructions corresponding to each reference merging scheme, if the smallest number of copy instructions is greater than or equal to the preset threshold, j can be updated to determine a new batch of reference merging schemes with another dependency chain combination scheme. When j = J + 1, it means that the J dependency chain combination schemes formed by the I-th dependency chain matching pair cannot meet the expectation. At this time, I can be updated.

[0049] In the fourth embodiment, a set of dependency chain matching pairs is determined as fixed pairs through the merging priority, and then the generation of the dependency chain combination scheme and the generation of the basic merging scheme under each dependency chain combination scheme are carried out, effectively reducing the number of generated schemes. At the same time, the schemes with a greater possibility of improving efficiency are preferentially generated through the merging priority. When the expected effect cannot be achieved, the scheme generation is carried out in an iterative manner, thereby further reducing the number of generated schemes, reducing the computational burden, and improving the efficiency of the instruction merging scheme generation.

[0050] Although some specific embodiments of the present invention have been described in detail by way of examples, those skilled in the art should understand that the above examples are for illustrative purposes only and not for limiting the scope of the present invention. Those skilled in the art should also understand that various modifications can be made to the embodiments without departing from the scope and spirit of the present invention. The scope of the present invention disclosed is defined by the appended claims.

Claims

1. An instruction merging system based on a cost model, characterized in that, The system includes: a processor and a memory storing a computer program, and when the computer program is executed by the processor, the following steps are implemented: S101. Obtain 2×N instructions to be merged, where N is a positive integer, and the instructions to be merged include destination operands and source operands; S102. Determine a number of reference merging schemes and the number of copy instructions corresponding to each reference merging scheme according to each instruction to be merged; S103. Select the reference merging scheme corresponding to the number of copy instructions that meets the first preset condition as the target merging scheme; S104. Merge each instruction to be merged according to the target merging scheme to obtain a number of target merged instructions and a number of copy instructions.

2. The instruction merging system based on a cost model according to claim 1, wherein The determining a number of reference merging schemes and the number of copy instructions corresponding to each reference merging scheme according to each instruction to be merged includes: S201. Randomly combine every two of the 2×N instructions to be merged to form P temporary merging schemes, where each temporary merging scheme contains N temporary instruction combinations, and P = (2N - 1)!!; S202. Take each temporary merging scheme as a reference merging scheme; S203. Determine the number of copy instructions corresponding to each reference merging scheme.

3. The instruction merging system based on a cost model according to claim 2, wherein The determining the number of copy instructions corresponding to each reference merging scheme includes: S2031. For the p-th reference merging scheme, determine the initial number of copy instructions a1 = (L + 1)×N of this reference merging scheme, where L is the number of source operands in the instructions to be merged, and p is an integer within the range of [1, P]; S2032. Traverse each group of operands in each temporary instruction combination in this reference merging scheme. When the two sub-data corresponding to a group of operands belong to the same register, update the address constraint count value a2 to a2 = a2 + 1 to obtain the address constraint count value a2 corresponding to the end of the traversal. Here, the operands include destination operands and source operands, a single operand in a single instruction to be merged corresponds to a sub-data, a single register contains two sub-data, and the initial value of a2 is 0; S2033. Traverse each group of destination operands in each temporary instruction combination in this reference merging scheme. When a group of destination operands are the same as b groups of source operands, update the instruction dependency count value a3 to a3 = a3 + b - 1, where the initial value of a3 is 0; S2034. Traverse each group of source operands in each temporary instruction combination in this reference merging scheme. When a group of source operands are the same as c groups of source operands, update the instruction repetition count value a4 to a4 = a4 + c - 1, where the initial value of a4 is 0; S2035, determine the number of copy instructions A corresponding to the p-th reference merge scheme p = a1 - a2 - a3 - a4.

4. The instruction merging system based on a cost model according to claim 3, wherein The selecting the reference merging scheme corresponding to the number of copy instructions that meets the first preset condition as the target merging scheme includes: Determine the smallest number of copy instructions among the numbers of copy instructions corresponding to the P reference merging schemes as the number of copy instructions that meets the first preset condition; Select the reference merging scheme corresponding to the number of copy instructions that meets the first preset condition as the target merging scheme.

5. The instruction merging system based on a cost model according to claim 1, wherein Determining a plurality of reference merging schemes and the number of copy instructions corresponding to each reference merging scheme according to each instruction to be merged, including: S301. Forming M instruction dependency chains according to the destination operands and source operands of each instruction to be merged, where M is an integer less than or equal to N, and each instruction dependency chain includes at least two instructions to be merged with a dependency relationship. Two instructions to be merged with a dependency relationship meet the condition that the destination operand of one instruction to be merged is the source operand of the other instruction to be merged; S302. Randomly combining the M instruction dependency chains in pairs to form Q first dependency chain combination schemes. A single first dependency chain combination scheme contains D first dependency chain combinations, where when M is odd, D = (M - 1) / 2, and when M is even, D = M / 2; S303. For the q-th first dependency chain combination scheme, retaining the first dependency chain combinations without a dependency relationship in the D first dependency chain combinations in this first dependency chain combination scheme to obtain E first dependency chain combinations. The first dependency chain combinations with a dependency relationship meet the condition that among the several instructions to be merged determined according to the first dependency chain combination, there is an instruction to be merged in one instruction combination to be merged whose destination operand is the source operand of another instruction to be merged, and q is an integer within the range of [1, Q]; S304. Determining f1 first combinations to be merged according to the E first dependency chain combinations, and forming a dependency instruction combination scheme from the f1 first combinations to be merged; S305. Randomly combining in pairs all the instructions to be merged that do not belong to the f1 first combinations to be merged to form R(q) remaining instruction combination schemes; S306. Forming R(q) intermediate merging schemes as reference merging schemes according to this dependency instruction combination scheme and the R(q) remaining instruction combination schemes; S307, traverse Q first dependency chain combination solutions to obtain S reference merging solutions, where, ; S308. Determining the number of copy instructions corresponding to each reference merging scheme.

6. The instruction merging system based on a cost model according to claim 5, wherein Determining f1 first combinations to be merged according to the E first dependency chain combinations, and forming a dependency instruction combination scheme from the f1 first combinations to be merged, including: S3041. For any one first dependency chain combination, matching the instructions to be merged in the two instruction dependency chains in this first dependency chain combination in sequence to obtain f1 first combinations to be merged; S3042. Forming a dependency instruction combination scheme from the f1 first combinations to be merged.

7. The instruction merging system based on a cost model according to claim 1, wherein Determining a plurality of reference merging schemes and the number of copy instructions corresponding to each reference merging scheme according to each instruction to be merged, including: S401. Forming M instruction dependency chains according to the destination operands and source operands of each instruction to be merged, where M is an integer less than or equal to N, and each instruction dependency chain includes at least two instructions to be merged with a dependency relationship. Two instructions to be merged with a dependency relationship meet the condition that the destination operand of one instruction to be merged is the source operand of the other instruction to be merged; S402. Determining the merging priorities corresponding to the M instruction dependency chains respectively according to the number of instructions to be merged included in the M instruction dependency chains; S403. According to the merging priorities corresponding to the M instruction dependency chains respectively, form a sequence of dependency chain matching pairs in the order from largest to smallest of the sum of the merging priorities. The sequence of dependency chain matching pairs includes M(M - 1) / 2 dependency chain matching pairs; S404. Initialize the selection flag I = 1; S405. Take the I-th dependency chain matching pair in the sequence of dependency chain matching pairs as a second dependency chain combination, and randomly combine two by two according to the remaining M - 2 instruction dependency chains to form J dependency chain combination schemes; S406. For the j-th dependency chain combination scheme, determine T(j) basic merging schemes as reference merging schemes, where the initial value of j is 1 and j is an integer within the range of [1, J]; S407. Determine the number of copy instructions corresponding to each reference merging scheme.

8. The instruction merging system based on a cost model according to claim 7, wherein Selecting the reference merging scheme corresponding to the number of copy instructions that meets the first preset condition as the target merging scheme includes: S408. Determine the smallest number of copy instructions from the numbers of copy instructions corresponding to each reference merging scheme. If the smallest number of copy instructions is less than the preset threshold, determine that the smallest number of copy instructions meets the first preset condition, and take the reference merging scheme corresponding to the smallest number of copy instructions as the target merging scheme; S409. Otherwise, update j = j + 1, and return to execute step S406 until the target merging scheme is determined or j = J + 1. When j = J + 1, execute step S410; S410. Update I = I + 1, and return to execute step S405 until the target merging scheme is determined or I = (M(M - 1) / 2)+1. When I = (M(M - 1) / 2)+1, determine that the target merging scheme is not to perform merging.

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