Chip test case construction method, electronic device and medium

Abstract

The present invention relates to the field of chip technology, and in particular to a method, electronic device, and medium for constructing a chip test case. The method comprises steps S1, constructing a target test case reconstruction structure {C0, (C1, B1), (C2, B2), ..., (C n ,B n ),...,(C N ,B N )}; Step S2, parse the target test case reconstruction structure, obtain C0, and then obtain each C in parallel n and B n ; Step S3, parallel analysis of each B n , get each F i n ; Step S4, based on each F i n 、F i n Corresponding C n , C0 generates all chip test cases of the chip to be tested. The present invention improves the efficiency and accuracy of building chip test cases.

Description

Technical Field

[0001] The present invention relates to the field of chip technology, and in particular to a method for constructing a chip test case, electronic equipment, and a medium. Background Art

[0002] To ensure that chips function properly under various conditions and meet design specifications and industry standards, the chip verification process requires the construction of numerous chip test cases. These test cases can be used to verify chip functionality, performance, reliability, and compatibility. Conventional verification engineers must configure parameters for each test case based on specific verification requirements, leading to low efficiency and error-prone construction. Therefore, improving the efficiency and accuracy of chip test case construction has become a pressing technical challenge. Summary of the Invention

[0003] The present invention aims to provide a chip test case construction method, electronic equipment and medium, which improve the chip test case construction efficiency and accuracy.

[0004] According to a first aspect of the present invention, a method for constructing a chip test case is provided, comprising:

[0005] Step S1, construct the target test case reconstruction structure {C0, (C1, B1), (C2, B2), ..., (C n ,B n ),...,(C N ,B N )}, C0 is the shared test case configuration information corresponding to the chip design under test, C n The shared test case configuration information corresponding to the nth sub-design of the chip under test, B n The nth group of test case reconstruction information list for the chip under test design, n ranges from 1 to N, N is the total number of sub-designs of the chip under test design, B n ={F1 n ,F2 n ,...,F i n ,...,F a(n) n}, F i n Reconstruct the information of the i-th test case in the n-th test case reconstruction information list. The value of i ranges from 1 to a(n), and a(n) is B n The total number of corresponding test case reconstruction information;

[0006] Step S2: parse the target test case and reconstruct the structure to obtain C0, and then obtain each C in parallel. n and Bn ;

[0007] Step S3, parallel analysis of each B n , get each F i n ;

[0008] Step S4: Based on each F i n 、F i n Corresponding C n , C0 generates all chip test cases for the chip design to be tested.

[0009] According to a second aspect of the present invention, an electronic device is provided, comprising: at least one processor; and a memory communicatively connected to the at least one processor; wherein the memory stores instructions executable by the at least one processor, the instructions being configured to execute the method described in the first aspect of the present invention.

[0010] According to a third aspect of the present invention, a computer-readable storage medium is provided, storing computer-executable instructions, wherein the computer instructions are used to execute the method according to the first aspect of the present invention.

[0011] The present invention has significant advantages and beneficial effects compared to the prior art. By utilizing the above technical solution, the present invention provides a chip test case construction method, electronic device, and medium that can achieve considerable technological advancement and practicality, and has wide industrial application value, with at least the following beneficial effects:

[0012] The present invention generates a target test case reconstruction structure by setting a unique test case reconstruction information data structure, layers the necessary information for generating test cases in the test case reconstruction information data structure, extracts multi-level shared configuration information, divides test cases into test case groups, and generates all chip test cases for the chip design to be tested by parsing the target test case reconstruction structure, thereby improving the construction efficiency and accuracy of chip test cases. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0014] Figure 1 A flowchart of a method for constructing a chip test case provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0015] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without making any creative efforts shall fall within the scope of protection of the present invention.

[0016] The embodiment of the present invention provides a method for constructing a chip test case, such as Figure 1 Shown, including:

[0017] Step S1, construct the target test case reconstruction structure {C0, (C1, B1), (C2, B2), ..., (C n ,B n ),...,(C N ,B N )}, C0 is the shared test case configuration information corresponding to the chip design under test, C n The shared test case configuration information corresponding to the nth sub-design of the chip under test, B n The nth group of test case reconstruction information list for the chip under test design, n ranges from 1 to N, N is the total number of sub-designs of the chip under test design, B n ={F1 n ,F2 n ,...,F i n ,...,F a(n) n}, F i n Reconstruct the information of the i-th test case in the n-th test case reconstruction information list. The value of i ranges from 1 to a(n), and a(n) is B n The total number of corresponding test case reconstruction information.

[0018] It should be noted that multi-level shared test case configuration information is set in the target test case reconstruction structure, which reduces the maintenance amount of test case configuration information and facilitates global changes of the same test case configuration information, thereby reducing the error rate.

[0019] Step S2: parse the target test case and reconstruct the structure to obtain C0, and then obtain each C in parallel. n and B n .

[0020] It should be noted that, by reconstructing the structure based on the target test case, the shared test case configuration information only needs to be parsed once and can maintain consistency, which improves the efficiency of test case construction and avoids errors.

[0021] Step S3, parallel analysis of each B n , get each F i n .

[0022] Step S4: Based on each F i n 、F i n Corresponding C n , C0 generates all chip test cases for the chip design to be tested.

[0023] As an example, each F i n Including one or more of user identification, configuration information of the design to be tested, operating parameters, number of cycles, test case group and running time; C0, C n Including one or more of the design configuration information to be tested, operating parameters, number of cycles and running time. It should be noted that the user identifier and test case group are maintained separately for each test case reconstruction information. The design configuration information to be tested, operating parameters, number of cycles and running time can be used as shared test case configuration information, that is, the design configuration information to be tested, operating parameters, number of cycles and running time of the test cases can be set in batches through the test case configuration information. Among them, the number of cycles is set according to the specific test regression requirements, for example, it is set to 10 times or 20 times. The running time can be specifically set to execute within a preset time interval or once every preset time period. The preset time interval can specifically be daytime period, nighttime period, morning period, afternoon period, etc. The preset time period can specifically be one day, one week, etc.

[0024] As an embodiment, the configuration information of the design to be tested is used to set the composition form of each component of the chip design to be tested, and the composition form includes a first form and a second form, the first form is a form including component ports and internal logic, and the second form is a form including only component ports. Taking the design to be tested as an example including the first component, the second component, the third component and the fourth component, assuming that the object to be verified is the first component, then the corresponding configuration information of the design to be tested is to set the first component to the first form, and the second component, the third component and the fourth component to the second form. Assuming that the verification object is the interaction between the first component and the second component, then the first component and the second component are set to the first form, and the third component and the fourth component are set to the second form.

[0025] As an embodiment, the design configuration information to be tested includes master configuration information and multiple slave configuration information. The master configuration information is the configuration information with the highest frequency of use. When no information is specified in the design configuration information to be tested, the master configuration information is set by default. When slave configuration information needs to be set, the corresponding slave configuration information needs to be specified in the design configuration information to be tested. By setting the master configuration information and multiple slave configuration information, the default configuration can be directly used in most scenarios, further improving the efficiency of constructing the target test case reconstruction structure, thereby improving the efficiency of test case generation.

[0026] As an embodiment, the operating parameters include environment variables, variables required by the preset script, and options that need to be passed to the electronic design automation (EDA) tool during the chip test case running process, wherein the environment variables can specifically be Linux environment variables, the preset script is a script for executing the chip test case, and the script type can specifically be Python, Perl, Ruby, Rust, Ymal, etc.

[0027] As an embodiment, the test case group includes at least one test case, and the test case group is divided based on chip functional characteristics or based on running time period. Based on chip functional characteristics, test cases that verify the same chip functional characteristics under the same design configuration information to be tested can be divided into one test case group. In order to improve resource utilization, it is also possible to divide the test cases with the same or similar running time into one test case group based on running time period.

[0028] As an embodiment, the test case group further includes a first identifier and a second identifier. If the first identifier is set, the current regression test process needs to generate test cases in the test case group. If the second identifier is set, the current regression test process does not need to generate test cases in the test case group. By setting the test case group identifier, flexible configuration of regression testing can be achieved. When a test case group does not need to participate in the current regression, the test case group can be set to the second identifier without deleting the test case group. When the test case group is needed in a subsequent regression test process, the test case group only needs to be set to the first identifier.

[0029] As an embodiment, step S4 includes:

[0030] Step S41: Get F i n Corresponding user ID and test case group {T1 in ,T2 in ,...,T j in ,,...,Tb(in) in}, T j in F i n The corresponding j-th test case information, j value range is 1 to b(in), b(in) is F i n The number of test cases in the corresponding test case group.

[0031] It is understandable that when i and n take different values, the corresponding value of b(in) may also be different.

[0032] Step S42: If F i n If there are preset parameters in the i n The preset parameters in are determined as T j in Corresponding target parameters, otherwise, execute step S43, the preset parameters are the design configuration information to be tested, operating parameters, number of cycles, test case group or running time.

[0033] It should be noted that each F i n The user ID and test case group must be set in the test. The design configuration information to be tested, running parameters, number of cycles, test case group or running time can be set or not. If not set, they will be generated based on the shared test case configuration information.

[0034] Step S43: If C n If there are preset parameters in the n The preset parameters in are determined as T j in Corresponding target parameters, otherwise, execute step S44.

[0035] Step S44: If a preset parameter is set in C0, the preset parameter of C0 is determined as T j in If the target parameter is correct, execute step S45; otherwise, generate a prompt message and end the process.

[0036] Through steps S42 to S44, when F i n When preset parameters are set in F i n Set the preset parameters as target parameters. The preset parameters can be one or more of the following: the configuration information of the design to be tested, the operating parameters, the number of cycles, the test case group, and the operating time. i n If there is no preset parameter in then Find the corresponding preset parameters in C, if they exist, n The preset parameters in are determined as the corresponding target parameters. n If it does not exist in C0, the preset parameters corresponding to the settings in C0 are determined as the target parameters. It can be seen that the preset parameters that work on the global design under test are set in C0, and the preset parameters that work on the sub-design of the design under test are set in C n In the test case reconstruction information of each group of personalized i n In , multi-level configuration of test case reconstruction information is implemented.

[0037] Step S45: Based on each T j in , each T j in The corresponding user ID and each T j in All target parameters corresponding to each T j in Corresponding test cases.

[0038] It should be noted that chip regression testing can be performed after all test cases are generated, and the step S4 further includes:

[0039] Step S5: compile the chip design code to generate an executable file of the chip design to be tested.

[0040] Step S6: Based on the executable file of the chip to be tested, the test cases required for the chip regression test are run in parallel to generate a test case run record. The test case run record includes a run log and a run result. The run result is generated based on the run log, and the run result includes success, failure and uncertainty.

[0041] Step S7: Generate a chip regression test database based on the test case running record, and display the chip regression test results based on the chip regression test database.

[0042] As an embodiment, step S6 includes:

[0043] Step S61: Test cases required for chip regression testing x Assign the corresponding number of CPUs P x And memory storage space Q x , the value of x ranges from 1 to X, where X is the total number of test cases required for chip regression testing.

[0044] Step S62: Design an executable file based on the chip to be tested and run all t in parallel. x , generating each run t xThe corresponding test case running record, the running log includes the actual number of CPUs required for running P1 x And the actual memory storage space required Q1 x .

[0045] Step S63: When t x When the corresponding test case running records reach R, get the R records closest to the current one. x P1 in the corresponding test case run record x The data P2 after rounding the mean x and Q1 x The mean of the rounded data Q2 x , P x Updated to P x =P2 x +P0 x , Q x Updated to Q x =Q2 x +Q0 x , P0 x Q0 is the preset CPU quantity adjustment value. x is the preset memory storage space adjustment value, and R is the preset test case running record accumulation threshold.

[0046] Through steps S61 to S63, the resources allocated to the test case can be dynamically adjusted based on the actual running status of the test case, thereby avoiding resource waste and improving resource utilization.

[0047] The step S6 further includes:

[0048] Step C61: Get test case t x In the corresponding run log text information, the value of x ranges from 1 to X, where X is the total number of test cases.

[0049] Step C62: In the order from front to back, x Read the G1 line text information from the corresponding running log text information, parse the currently read G1 line text information to obtain t x Corresponding test information, G1 is the preset first read row number.

[0050] It should be noted that the test information is usually located at the head of the log text information, and the number of G1 lines can cover t x Corresponding test information, so first follow the order from front to back from t xRead G1 lines of text information from the corresponding operation log text information. The information containing the operation results is usually located at the back of the operation log text, so the text is read from the back to the front for subsequent analysis. However, if the number of log text lines is less than or equal to G1, all the operation log text information has been read out in step C62. It can be understood that when the number of log text lines is less than or equal to G1, step C62 will read t x All lines of the corresponding run log text information are read out.

[0051] As an example, t x The corresponding test information includes t x The corresponding chip design name to be tested, t x The corresponding chip design configuration and t x The corresponding test case name.

[0052] Step C6: Determine the current t x Check whether there is any unread text line in the corresponding operation log text information. If so, execute step C64. Otherwise, take the currently read G1 line of text information as the current text to be analyzed and execute step C65.

[0053] It should be noted that when the number of log text information lines is less than or equal to G1, the G1 line text information currently read refers to all text line information corresponding to the running log text information.

[0054] Step C64: In order from back to front, x Read G2 lines of text information from the unread text lines in the corresponding operation log text information, take the currently read G2 lines of text information as the current text to be analyzed, and execute step C65, where G2 is a preset second number of read lines.

[0055] It should be noted that if the number of unread text lines in the running log text information is greater than or equal to G2, the text information of line G2 currently read is t x The corresponding running log text information is read from the back to front in the unread text line G2 line text information. If the number of unread text lines in the running log text information is less than G2, the currently read G2 line text information is t x All remaining text lines in the corresponding run log text information. G2 and G1 may be equal or unequal. The specific data is set according to the specific application scenario.

[0056] Step C65: Scan the current text to be analyzed line by line in the order from back to front. If a preset failed text mark appears, determine t x If the result of the operation is not passed, then execute step C66.

[0057] Step C66, determine the current t x Whether there is an unread text line in the corresponding running log text information. If so, return to execute Step C64. Otherwise, determine that the x running result of t is passed.

[0058] In the embodiments of the present invention, Steps C61 - C66 do not need to obtain the file size of the running log text information, and obtain test information by reading the running log text information from front to back, and obtain the preset failure text identifier by reading the running log text information from back to front. For most running log text information files, it is not necessary to obtain the entire running log text information file to accurately and quickly determine the situation where the running result is not passed.

[0059] As an embodiment, Step C65 includes:

[0060] Step C651, set the line number g to be processed as 1, and the total number of lines of the current text to be analyzed is G3.

[0061] It can be understood that in different situations, the total number of lines of the current text to be analyzed may be different, may be G1, may be G2, may be less than G1, or may be less than G2.

[0062] Step C652, obtain the g-th line text in the current text to be analyzed in the order from back to front, perform word segmentation on the g-th line text to obtain the word segmentation corresponding to the g-th line text. If there is a word segmentation of the preset failure text identifier, determine that the x running result of t is not passed. Otherwise, execute Step C653.

[0063] Among them, the word segmentation of the preset failure text identifier can be specifically set to "error". It should be noted that in the application scenarios of the embodiments of the present invention, as long as the word segmentation of the preset failure text identifier appears in the running log text information, it can be determined that the running result is not passed.

[0064] Step C653, compare g and G3. If g = G3, execute Step C66. If g < G3, set g = g + 1 and return to Step C652.

[0065] In some cases, the word segmentation of the preset failure text identifier may be distributed in two lines. In this case, it is impossible to identify the word segmentation of the preset failure text identifier only through Steps C651 - C653, which may lead to misjudgment. To avoid the above situation, as an embodiment, Step C65 includes:

[0066] Step D651, based on the preset failure text identifier, set the candidate word segmentation combination {(A1, D1), (A2, D2),...,(A z,D z ),...,(A Z ,D Z )},(A z ,D z ) is the zth group of candidate word combinations, the value range of z is 1 to Z, Z is the total number of candidate word combinations, and the total number of characters of the preset failed text mark is Z+1, A z and D z The preset failed text mark is formed by splicing, and the line number to be processed is set to g=1. The total number of lines of text to be analyzed is G3.

[0067] Among them, taking the preset failure text mark word setting as "error" as an example, {(A1,D1),(A2,D2),...,(A z ,D z ),...,(A Z ,D Z )} is {(e,rror),(er,ror),(err,or),(erro,r)}.

[0068] Step D652: Obtain the g-th line of text in the current text to be analyzed in order from back to front, perform word segmentation on the g-th line of text, and obtain the word segmentation corresponding to the g-th line of text. If there is a word segmentation with a preset failed text mark, determine t x The result of the operation is failure, otherwise, execute step D653.

[0069] Step D653: Determine whether the first word is {(A1, D1), (A2, D2), ..., (A z ,D z ),...,(A Z ,D Z )} one of the D z If so, then D z Set as target D z , the target D z Corresponding A z Set as target A z , set g=g+1, execute step D654, otherwise, execute step D655.

[0070] Step D654: If g≤G3, then obtain the gth line of text in the current text to be analyzed in the order from back to front. If g=G3+1, then obtain the current t x The first unread text line in the corresponding running log text information is taken as the g-th line of text. The g-th line of text is segmented to obtain the segmentation corresponding to the g-th line of text. If the last segmentation corresponding to the g-th line of text is the target A zIf there is a word segmentation with a preset failure text identifier in the g-th line of text, then determine t x The operation result of is failed. Otherwise, execute step D655.

[0071] Step D655: Compare g and G3. If g = G3, then execute step C66. If g < G3, then set g = g + 1 and return to step D652.

[0072] It should be noted that through steps D651 - D655, all the word segmentations with the preset failure text identifier of the current text to be analyzed can be accurately analyzed, improving the accuracy of the operation result recognition.

[0073] As an embodiment, the step S7 includes:

[0074] Step S71: Generate a corresponding first chip regression test database based on the test case running records of each chip regression test, and display the regression test results of each chip regression test in real time based on the first chip regression test database corresponding to each chip regression test. [[ID=ID=16]]

[0075] It should be noted that through step S71, the regression test results of each chip regression test can be displayed in real time, which is convenient for timely discovering the abnormalities of each chip regression test.

[0076] Step S72: When all the chip regression tests corresponding to the IP in the to-be-tested chip design y are completed, generate a second chip regression test database corresponding to the IP based on the test case running records of all the chip regression tests corresponding to the IP in the to-be-tested chip design y and display the regression test results corresponding to the IP based on the second chip regression test database corresponding to the IP. The value range of y is from 1 to Y, where Y is the total number of IPs (Intellectual Property) in the to-be-tested chip design. y y y y y It should be noted that each IP corresponds to a sub-design in the to-be-tested chip design. Through step S72, the abnormalities of the regression tests of each IP in the to-be-tested chip design can be discovered in time.

[0077]

[0078] Step S73: When all the chip regression tests corresponding to all the IPs in the to-be-tested chip design y are completed, generate a third chip regression test database corresponding to the to-be-tested chip design based on the test case running records of all the chip regression tests corresponding to all the IPs in the to-be-tested chip design y and display the regression test results corresponding to the to-be-tested chip design based on the third chip regression test database corresponding to the to-be-tested chip design.​

[0079] It should be noted that, through step S73, anomalies in the regression test can be discovered in a timely manner from the perspective of the overall design of the chip to be tested.

[0080] As an embodiment, step S71 includes:

[0081] Step S711: Obtain the pass rate of each chip regression test based on the test case running record of each chip regression test.

[0082] Step S712: Store the test case running records of each chip regression test with a failed running result and the pass rate of each chip regression test in the first chip regression test database.

[0083] Step S713: Displaying the test cases with failed running results of each chip regression test and the pass rate of each chip regression test based on the first chip regression test database.

[0084] Step S714 : Debug the corresponding function point of each chip regression test based on the displayed running result of each chip regression test, the failed test case running record and the pass rate of each chip regression test.

[0085] It should be noted that through steps S711 to S714, the pass rate of each chip regression test and the test case operation records with failed results can be presented in real time. Based on the pass rate of each chip regression test and the test case operation records with failed results, the chip regression test can be analyzed in real time.

[0086] As an embodiment, step S72 includes:

[0087] Step S721: When the IP y After all corresponding chip regression tests are completed, based on the IP in the chip design to be tested y Get the IP from the corresponding test case running records of all chip regression tests y The corresponding pass rate.

[0088] It should be noted that each test case has corresponding configuration information of the design to be tested, and the IP corresponding to the test case can be determined based on the configuration information of the design to be tested.

[0089] Step S722: Design the IP in the chip to be tested y The corresponding running result is the failed test case running record and IP y The corresponding pass rate is stored in the second chip regression test database.

[0090] Step S723: Display each IP based on the second chip regression test database. y The corresponding running results are the failed test cases and IP y The corresponding pass rate.

[0091] Step S724: Based on each displayed IP y The corresponding running results are the failed test cases and IP y The corresponding pass rate debugging each IP y .

[0092] It should be noted that each IP address can be presented through steps S721 to S724. y The corresponding pass rate and the test case running record with failed results, based on each IP y The corresponding pass rate and the test case running records with failed results can be used to analyze the chip regression test.

[0093] As an embodiment, step S73 includes:

[0094] Step S731: When all IP y After all corresponding chip regression tests are completed, all IP y The corresponding test case running records of all chip regression tests are used to obtain the corresponding pass rate of the chip design to be tested.

[0095] Step S732: Design all IPs in the chip to be tested y The corresponding running results are the failed test case running records and the corresponding pass rates of the chip design to be tested, which are stored in the third chip regression test database.

[0096] Step S733: Display all IP addresses in the chip under test design based on the third chip regression test database. y The corresponding running results are the failed test case running records and the corresponding pass rate of the chip design under test.

[0097] Step S734: Based on the displayed chip design, all IP y The corresponding running results are the failed test case running records and the corresponding pass rate of the chip design to be tested to debug the chip design to be tested.

[0098] It should be noted that through steps S731 to S734, the pass rate corresponding to each chip design to be tested and the test case operation records with failed operation results can be presented. Based on the pass rate corresponding to each chip design to be tested and the test case operation records with failed operation results, the chip regression test can be analyzed.

[0099] It should be noted that some exemplary embodiments are described as processes or methods depicted as flowcharts. Although the flowcharts describe the steps as sequential processes, many of the steps can be performed in parallel, concurrently, or simultaneously. In addition, the order of the steps can be rearranged. A process can be terminated when its operation is completed, but can also have additional steps not included in the accompanying drawings. A process can correspond to a method, function, procedure, subroutine, subprogram, etc.

[0100] An embodiment of the present invention also provides an electronic device, comprising: at least one processor; and a memory communicatively connected to the at least one processor; wherein the memory stores instructions executable by the at least one processor, and the instructions are configured to execute the method described in the embodiment of the present invention.

[0101] An embodiment of the present invention further provides a computer-readable storage medium storing computer-executable instructions, wherein the computer instructions are used to execute the method described in the embodiment of the present invention.

[0102] The embodiment of the present invention generates a target test case reconstruction structure by setting a unique test case reconstruction information data structure, layers the necessary information for generating test cases in the test case reconstruction information data structure, extracts multi-level shared configuration information, divides test cases into test case groups, and generates all chip test cases for the chip design to be tested by parsing the target test case reconstruction structure, thereby improving the construction efficiency and accuracy of chip test cases.

[0103] The above description is merely a preferred embodiment of the present invention and does not constitute any form of limitation to the present invention. Although the present invention has been disclosed as a preferred embodiment, it is not intended to limit the present invention. Any technician familiar with the present profession can make slight changes or modifications to equivalent embodiments using the technical contents disclosed above without departing from the scope of the technical solution of the present invention. However, any simple modifications, equivalent changes and modifications made to the above embodiments based on the technical essence of the present invention without departing from the content of the technical solution of the present invention are still within the scope of the technical solution of the present invention.

Claims

1. A method for constructing a chip test case, characterized in that: include: Step S1, construct the target test case reconstruction structure {C0, (C1, B1), (C2, B2), ..., (C n ,B n ),...,(C N ,B N )}, C0 is the shared test case configuration information corresponding to the chip design under test, C n The shared test case configuration information corresponding to the nth sub-design of the chip under test, B n The nth group of test case reconstruction information list for the chip under test design, n ranges from 1 to N, N is the total number of sub-designs of the chip under test design, B n ={F1 n ,F2 n ,...,F i n ,...,F a(n) n }, F i n Reconstruct the information of the i-th test case in the n-th test case reconstruction information list. The value of i ranges from 1 to a(n), and a(n) is B n The total number of corresponding test case reconstruction information; Step S2: parse the target test case and reconstruct the structure to obtain C0, and then obtain each C in parallel. n and B n ; Step S3, parallel analysis of each B n , get each F i n ; Step S4: Based on each F i n 、F i n Corresponding C n ,C0 generates all chip test cases for the chip design to be tested; Each F i n Including one or more of user identification, configuration information of the design to be tested, operating parameters, number of cycles, test case group and running time; C0, C n including one or more of the design configuration information to be tested, operating parameters, number of cycles, and operating time; The step S4 comprises: Step S41: Get F i n Corresponding user ID and test case group {T1 in ,T2 in ,...,T j in ,...,T b(in) in }, T j in F i n The corresponding j-th test case information, j value range is 1 to b(in), b(in) is F i n The number of test cases in the corresponding test case group; Step S42: If F i n If there are preset parameters in the i n The preset parameters in are determined as T j in If the corresponding target parameter is not met, step S43 is executed, where the preset parameter is the design configuration information to be tested, the operating parameter, the number of cycles, the test case group or the operating time; Step S43: If C n If there are preset parameters in the n The preset parameters in are determined as T j in Corresponding target parameters, otherwise, execute step S44; Step S44: If a preset parameter is set in C0, the preset parameter of C0 is determined as T j in If the target parameter is the same as the target parameter, execute step S45; otherwise, generate a prompt message and end the process; Step S45: Based on each T j in , each T j in The corresponding user ID and each T j in All target parameters corresponding to each T j in Corresponding test cases.

2. The method according to claim 1, characterized in that The test design configuration information is used to set the composition form of each component of the test chip design, and the composition form includes a first form and a second form. The first form is a form including component ports and internal logic, and the second form is a form including only component ports.

3. The method according to claim 1, characterized in that The design configuration information to be tested includes main configuration information and multiple slave configuration information. The main configuration information is the configuration information with the highest frequency of use. When no information is specified in the design configuration information to be tested, the main configuration information is set by default. When slave configuration information needs to be set, the corresponding slave configuration information needs to be specified in the design configuration information to be tested.

4. The method according to claim 1, wherein The operating parameters include environment variables, variables required by preset scripts, and options that need to be passed to the EDA tool during the chip test case running process.

5. The method according to claim 1, wherein The test case group includes at least one test case, and the test case group is divided based on chip functional characteristics or based on operating time periods.

6. The method according to claim 1, characterized in that The test case group also includes a first identifier and a second identifier. If it is set to the first identifier, the current regression test process needs to generate test cases in the test case group. If it is set to the second identifier, the current regression test process does not need to generate test cases in the test case group.

7. An electronic device, characterized in that: include: at least one processor; and, a memory communicatively coupled to the at least one processor; The memory stores instructions that can be executed by the at least one processor, and the instructions are configured to execute the method according to any one of claims 1 to 6.

8. A computer-readable storage medium, characterized in that The computer-executable instructions are stored, and the computer-executable instructions are used to execute the method according to any one of the preceding claims 1 to 6.

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