Netlist segmentation method and device and storage medium
During the netlist slicing process, the slicing points are determined based on the number of fan-out or fan-in connection lines of the target interface, the inter-module interface is reduced, and the integrated circuit design is optimized, which solves the problem of excessive number of inter-module interfaces in the existing technology, and improves design efficiency and power network connectivity.
Patent Information
- Application Number
- CN202311870872.9
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2023-12-29
- Publication Date
- 2025-07-01
AI Technical Summary
The existing netlist splitting method fails to effectively optimize the integrated circuit design structure, especially the number of interfaces between modules, resulting in high design complexity and increased timing convergence difficulty.
By extracting the target interface in the target netlist, tracking the drive unit or load unit associated with it, determining the netlist slitting point based on the number of fan-out or fan-in connection lines, reducing the number of interfaces between modules, and optimizing the integrated circuit design.
It realizes reducing the number of interfaces between modules, optimizing the integrated circuit design structure, reducing design complexity, accelerating the timing convergence process, and improving the connectivity of the power network.
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Figure CN120235089A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of integrated circuit technology, and particularly to a netlist splitting method, device, and storage medium. Background Art
[0002] In circuit design, a netlist is used to describe the connection relationships between circuit components. Generally, it is a text file that follows a relatively simple markup syntax. Gate-level refers to the circuit synthesis level described by the netlist, and a gate-level netlist describes circuit components that are basically gates or components at the same level.
[0003] In the prior art, when splitting a gate-level netlist, it is mainly split according to the functions of each module in the gate-level netlist. However, this splitting method only considers the module functions and fails to implement it from the module interfaces. Therefore, the existing splitting methods cannot further optimize the integrated circuit design structure from the aspect of module interfaces. Summary of the Invention
[0004] The purpose of this application is to provide a netlist splitting method, device, and storage medium for the deficiencies in the above-mentioned prior art, which can reduce the number of interfaces between modules, optimize the design structure of integrated circuits, and contribute to the rapid realization of the design.
[0005] To achieve the above purpose, the technical solutions adopted in the embodiments of this application are as follows:
[0006] In a first aspect, the present invention provides a netlist splitting method, including:
[0007] Extract at least one target interface from the target netlist, where the target netlist is the netlist after initial splitting, and at least one target interface in the target netlist belongs to one area after initial splitting;
[0008] Based on the logical structure of the target netlist, for each of the target interfaces, trace the target units associated with each of the target interfaces, where the target units include: driving units or load units;
[0009] Determine the netlist splitting points corresponding to each of the target interfaces according to the number of fan-out or fan-in connection lines corresponding to each of the target units;
[0010] Split the target netlist according to each of the netlist splitting points to obtain the split netlist.
[0011] In an optional implementation, if the target interface is an input interface, the target unit is a driving unit, and trace the number of fan-out connection lines corresponding to the driving unit; if the target interface is an output interface, the target unit is a load unit, and trace the number of fan-in connection lines corresponding to the load unit.
[0012] In an alternative embodiment, determining the netlist splitting points corresponding to the target interfaces according to the number of fan-out or fan-in connection lines corresponding to each target unit includes:
[0013] Comparing the number of fan-out or fan-in connection lines corresponding to each target unit. If the target interface is an input interface, determining the driving unit corresponding to the minimum number as the netlist splitting point corresponding to the input interface; if the target interface is an output interface, determining the load unit corresponding to the maximum number as the netlist splitting point corresponding to the output interface.
[0014] In an alternative embodiment, if the target interface is an input interface and there are multiple minimum numbers, determining the driving unit far from the input interface among the driving units corresponding to the multiple minimum numbers as the netlist splitting point corresponding to the input interface;
[0015] If the target interface is an output interface and there are multiple maximum numbers, determining the load unit far from the output interface among the load units corresponding to the multiple maximum numbers as the netlist splitting point corresponding to the output interface.
[0016] In an alternative embodiment, based on the logical structure of the target netlist, for each target interface, tracing the target units associated with each target interface includes:
[0017] Based on the logical structure of the target netlist, if the target interface is an input interface, for the input interface, tracing the first N levels of connection lines of the input interface until the starting timing unit is traced, and determining the driving units corresponding to each level of connection lines, where N is an integer greater than 0;
[0018] If the target interface is an output interface, for the output interface, tracing the last M levels of connection lines of the output interface until the terminating timing unit is traced, and determining the load units corresponding to each level of connection lines, where M is an integer greater than 0.
[0019] In an alternative embodiment, there are multiple target units corresponding to the same target interface in the target netlist.
[0020] In an alternative embodiment, if multiple target interfaces include multiple input interfaces, there is the same starting timing unit corresponding to the multiple input interfaces in the target netlist; if multiple target interfaces include multiple output interfaces, there is the same terminating timing unit corresponding to the multiple output interfaces in the target netlist.
[0021] In an alternative embodiment, splitting the target netlist according to each netlist splitting point to obtain the split netlist includes:
[0022] Determine the boundaries between modules corresponding to the target netlist according to each of the netlist segmentation points;
[0023] Segment the target netlist according to the boundaries between modules to obtain the segmented netlist.
[0024] In an alternative embodiment, the extraction of at least one target interface from the target netlist includes:
[0025] Obtain an initial hierarchical gate-level netlist;
[0026] Determine an initial segmentation line according to the functional regions of the chip;
[0027] Divide the initial hierarchical gate-level netlist according to the initial segmentation line to obtain the target netlist;
[0028] Perform a flattening operation on the target netlist based on the logical structure of the target netlist to extract at least one target interface from the target netlist.
[0029] In an alternative embodiment, the dividing the initial hierarchical gate-level netlist according to the initial segmentation line to obtain the target netlist includes:
[0030] Divide the initial hierarchical gate-level netlist according to the initial segmentation line to generate hierarchical interface points and another part of interface points connected to the hierarchical interface points;
[0031] Connect the hierarchical interface points and connect the other part of interface points respectively to form the target netlist.
[0032] In a second aspect, the present invention provides an electronic device, including: a processor, a storage medium, and a bus. The storage medium stores machine-readable instructions executable by the processor. When the electronic device runs, the processor communicates with the storage medium through the bus. The processor executes the machine-readable instructions to perform the steps of the netlist segmentation method according to any one of the foregoing embodiments.
[0033] In a third aspect, the present invention provides a computer-readable storage medium, on which a computer program is stored. When the computer program is run by a processor, it performs the steps of the netlist segmentation method according to any one of the foregoing embodiments.
[0034] The beneficial effects of the present application are:
[0035] In the netlist splitting method, device, and storage medium provided by the embodiments of the present application, at least one target interface is extracted from a target netlist. The target netlist is the netlist after initial splitting, and at least one target interface in the target netlist belongs to one area after initial splitting. Based on the logical structure of the target netlist, for each target interface, target units associated with each target interface are traced, where the target units include: driving units or load units. According to the number of fan-out or fan-in connection lines corresponding to each target unit, the netlist splitting points corresponding to each target interface are determined. The target netlist is split according to each netlist splitting point to obtain the split netlist. Applying the embodiments of the present application can regard the logical divergence points or logical convergence points corresponding to each target interface as the netlist splitting points corresponding to each target interface. Furthermore, when splitting based on the netlist splitting points, the number of interfaces between modules can be reduced, and the design structure of the integrated circuit can be optimized. BRIEF DESCRIPTION OF THE DRAWINGS
[0036] To more clearly illustrate the technical solutions in the embodiments of the present application, the following briefly introduces the accompanying drawings required for the embodiments. It should be understood that the following drawings only show some embodiments of the present application and should not be regarded as limiting the scope. For those of ordinary skill in the art, other related drawings can be obtained based on these drawings without creative efforts.
[0037] Figure 1 It is a flowchart of a netlist splitting method provided by an embodiment of the present application;
[0038] Figure 2 It is an interface distribution model provided by an embodiment of the present application;
[0039] Figure 3 It is another interface distribution model provided by an embodiment of the present application;
[0040] Figure 4 It is a flowchart of another netlist splitting method provided by an embodiment of the present application;
[0041] Figure 5 It is a flowchart of yet another netlist splitting method provided by an embodiment of the present application;
[0042] Figure 6 It is a flattened diagram of a hierarchical gate-level netlist provided by an embodiment of the present application;
[0043] Figure 7 It is a functional module diagram of a netlist splitting device provided by an embodiment of the present application;
[0044] Figure 8 It is a schematic diagram of the structure of an electronic device provided by an embodiment of the present application. DETAILED DESCRIPTION OF THE EMBODIMENTS
[0045] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the following will clearly and completely describe the technical solutions in the embodiments of this application with reference to the accompanying drawings in the embodiments of this application. Apparently, the described embodiments are some, but not all, of the embodiments of this application. Usually, the components of the embodiments of this application described and illustrated in the accompanying drawings here can be arranged and designed in various different configurations.
[0046] Therefore, the following detailed description of the embodiments of this application provided in the accompanying drawings is not intended to limit the scope of this application that is claimed, but merely represents selected embodiments of this application. All other embodiments obtained by those of ordinary skill in the art based on the embodiments in this application without creative efforts fall within the scope of protection of this application.
[0047] It should be noted that: Similar reference numerals and letters denote similar items in the following drawings. Therefore, once an item is defined in one drawing, it does not need to be further defined and explained in subsequent drawings.
[0048] In current integrated circuit design, based on the EDA tools developed by Cadence Design Systems, the netlist splitting process is as follows: Using a hierarchical physical design method, the entire chip is divided into multiple first-level modules according to logical functions, all standard cells are pre-placed, the timing between modules is simulated through the internal algorithm of the tool, and the total wire length of the chip is calculated, and the splitting, recombination, and partitioning between the bottom-level modules are performed. This netlist splitting method is considered from the functional aspect of the modules and pays little attention to the number of interfaces between the modules.
[0049] In integrated circuit design, the interface design between modules is usually the key to restricting the design. Therefore, the existing splitting methods cannot further optimize the integrated circuit design structure from the aspect of module interfaces.
[0050] In view of this, the embodiments of this application provide a netlist splitting method. Applying this method can reduce the number of interfaces between modules, optimize the design structure of the integrated circuit, and contribute to the rapid realization of the design.
[0051] Figure 1 FIG. is a schematic flowchart of a netlist splitting method provided by an embodiment of this application. The execution subject of this method can be an electronic device with computing and processing capabilities, such as a server, a computer, a desktop computer, etc. As Figure 1 shown, this method can include:
[0052] S101. Extract at least one target interface from the target netlist.
[0053] Among them, the target netlist is the netlist after initial partitioning, and at least one target interface in the target netlist belongs to one area after initial partitioning.
[0054] Optionally, the target netlist can be obtained by initially partitioning the initial hierarchical gate-level netlist, which can be understood as the netlist area corresponding to the initial partitioning area. In some embodiments, the initial partitioning area can be obtained according to the chip functional areas, and the initial hierarchical gate-level netlist can be obtained by simulating the target integrated circuit corresponding to the target chip with the help of EDA tools.
[0055] In some embodiments, at least one target interface in the extracted target netlist may include: input interfaces and / or output interfaces, and at least one target interface should belong to the initial partitioning area.
[0056] Of course, the present application does not limit the number of each type of interface here, and it can vary according to the actual application scenario.
[0057] S102. Based on the logical structure of the target netlist, for each target interface, trace the target units associated with each target interface, where the target units include: driving units or load units.
[0058] Among them, the logical structure of the target netlist can describe the mutual connection relationship between the circuit elements in the corresponding integrated circuit. For each of the above-mentioned extracted target interfaces, the target units associated with each target interface can be located in sequence according to this logical structure.
[0059] Optionally, the target interface may include input interfaces and output interfaces. According to the interface type of the target interface, the target interface can be associated with different types of target units. Among them, the target unit associated with the input interface can be called a driving unit, and the target unit associated with the output interface can be called a load unit.
[0060] In some embodiments, the driving unit and the load unit can specifically be AND gates, OR gates, NOT gates, NAND gates, NOR gates, AND-OR-NOT gates, XOR gates, etc., which are not limited herein.
[0061] S103. Determine the netlist cut points corresponding to each target interface according to the number of fan-out or fan-in connection lines corresponding to each target unit.
[0062] Among them, the number of fan-out or fan-in connection lines corresponding to the target unit is also the number of circuit units that the target unit can drive or the number of circuit units that drive the target unit. The number of fan-out or fan-in connection lines corresponding to different target units can be the same or different.
[0063] Optionally, by counting the number of fan-out or fan-in connection lines corresponding to each target unit, the logical divergence points or logical convergence points corresponding to each target interface can be located. Furthermore, the logical divergence points or logical convergence points corresponding to each target interface can be regarded as the netlist splitting points corresponding to each target interface. Among them, the logical divergence points or logical convergence points can characterize the data flow direction of the paths where each target interface is located. It can be understood that there will be a situation where multiple target interfaces correspond to the same logical divergence point or logical convergence point. Therefore, the number of obtained netlist splitting points will be less than the number of target interfaces.
[0064] S104. Split the target netlist according to each netlist splitting point to obtain the split netlist.
[0065] Based on the above description, after determining each netlist splitting point, the target netlist can be split accordingly. It can be understood that since the number of obtained netlist splitting points will be less than the number of target interfaces at this time, when splitting the target netlist according to each netlist splitting point, for the split netlist, the number of interfaces between modules can be reduced, the design structure can be optimized, which is helpful for the rapid implementation of the design.
[0066] In summary, the embodiment of the present application provides a netlist splitting method, which includes: extracting at least one target interface from the target netlist, where the target netlist is the initially split netlist, and at least one target interface in the target netlist belongs to one area after the initial split; based on the logical structure of the target netlist, for each target interface, trace the target units associated with each target interface, where the target units include: driving units or load units; determine the netlist splitting points corresponding to each target interface according to the number of fan-out or fan-in connection lines corresponding to each target unit; split the target netlist according to each netlist splitting point to obtain the split netlist. Applying the embodiment of the present application, it is realized that the logical divergence points or logical convergence points corresponding to each target interface can be regarded as the netlist splitting points corresponding to each target interface. Furthermore, when splitting based on this netlist splitting point, the number of interfaces between modules can be reduced, the design structure of the integrated circuit can be optimized, which is helpful for the rapid implementation of the design.
[0067] Among them, when applying the method of the present application to two-dimensional integrated circuit design, by re-finely splitting the netlist, the number of internal interfaces between each module can be optimized, which is helpful for reducing the design complexity, accelerating the timing convergence process, and optimizing the design; when applied to three-dimensional integrated circuit design, the number of interfaces between the same-layer modules (internal) can be optimized and the number of interfaces between different-layer chips (micro bump or hybrid bonding) can be optimized, which can effectively reduce the number of communication interfaces between different-layer chips. In this way, more chip-to-chip communication interfaces can be introduced for power network construction, which is beneficial to improving the overall power network connectivity of the integrated circuit design.
[0068] In an alternative embodiment, if the target interface is an input interface, the target unit is a driving unit, and the number of fan-out connection lines corresponding to the driving unit is traced; if the target interface is an output interface, the target unit is a load unit, and the number of fan-in connection lines corresponding to the load unit is traced.
[0069] Among them, for different types of target interfaces, different tracing logics will be corresponding. If the target interface is an input interface, the associated target unit is a driving unit. When specifically tracing, the number of fan-out connection lines corresponding to the driving unit needs to be traced. Among them, the number of fan-out connection lines can represent the number of circuit units that the driving unit can drive; if the target interface is an output interface, the associated target unit is a load unit. When specifically tracing, the number of fan-in connection lines corresponding to the load unit needs to be traced. Among them, the number of fan-in connection lines can represent the number of circuit units that drive the load unit.
[0070] Optionally, determining the netlist splitting points corresponding to each target interface according to the number of fan-out or fan-in connection lines corresponding to each target unit includes:
[0071] Compare the number of fan-out or fan-in connection lines corresponding to each target unit. If the target interface is an input interface, determine the driving unit corresponding to the minimum number as the netlist splitting point corresponding to the input interface; if the target interface is an output interface, determine the load unit corresponding to the maximum number as the netlist splitting point corresponding to the output interface.
[0072] Among them, the target interface can be divided into an input interface and an output interface. Different methods can be used to determine the netlist splitting point for different types of interfaces.
[0073] When specifically determining, for each input interface, the driving unit corresponding to the minimum number can be selected to replace the input interface, so as to obtain a new interface for each input interface in the target netlist. At this time, the new interface for each input interface in the target netlist can be regarded as the netlist splitting point at the input end; for each output interface, the load unit corresponding to the maximum number can be selected to replace the output interface, so as to obtain a new interface for each output interface in the target netlist. At this time, the new interface for each output interface in the target netlist can be regarded as the netlist splitting point at the output end.
[0074] Based on the above description, it can also be understood that for each input interface, the driving unit corresponding to the minimum number associated with it can be regarded as the logical divergence point corresponding to the input interface; for each output interface, the load unit corresponding to the maximum number associated with it can be regarded as the logical convergence point corresponding to the output interface.
[0075] Optionally, if the target interface is an input interface and there are multiple minimum quantities, determine the drive unit among the drive units corresponding to the multiple minimum quantities that is farthest from the input interface as the netlist splitting point corresponding to the input interface; if the target interface is an output interface and there are multiple maximum quantities, determine the load unit among the load units corresponding to the multiple maximum quantities that is farthest from the output interface as the netlist splitting point corresponding to the output interface.
[0076] Based on the above description, of course, for an input interface, there may also be multiple cases of the same minimum quantity. In this case, the netlist splitting point can be determined according to the positional relationship between the drive unit corresponding to each minimum quantity and the input interface. When specifically determining, the drive unit that is farthest from the input interface can be used as the netlist splitting point corresponding to the input interface; for an output interface, there may also be multiple cases of the same maximum quantity. In this case, the netlist splitting point can be determined according to the positional relationship between the load unit corresponding to each maximum quantity and the output interface. When specifically determining, the load unit that is farthest from the output interface can be used as the netlist splitting point corresponding to the input interface. Applying the embodiments of the present application enables the number of interfaces between modules to be reduced as much as possible for both the input interface and the output interface through the determined netlist splitting point.
[0077] Optionally, for each target interface based on the logical structure of the target netlist, trace the target units associated with each target interface, including:
[0078] Based on the logical structure of the target netlist, if the target interface is an input interface, then for the input interface, trace the first N levels of connections of the input interface until the starting timing unit is traced, and determine the drive unit corresponding to each level of connection, where N is an integer greater than 0; if the target interface is an output interface, then for the output interface, trace the last M levels of connections of the output interface until the terminating timing unit is traced, and determine the load unit corresponding to each level of connection, where M is an integer greater than 0.
[0079] Among them, the tracing logics of the input interface and the output interface are different. To better understand the embodiments of the present application, specific examples are given below for illustration.
[0080] Figure 2 This is an interface distribution model provided by the embodiments of the present application; Figure 3 This is another interface distribution model provided by the embodiments of the present application. Among them, taking the second design S2 as the target netlist as an example, the method of splitting the netlist is specifically described. For the first-level interface pin1, it can be divided into two major categories: input interface and output interface.
[0081] Among them, referring to Figure 2As shown, along the transmission direction of the data stream, the data stream flows through the first interface register 101 and the first interface combination unit 102 in the first design S1 in sequence, and then flows to multiple input interfaces in the second design S2. The multiple input interfaces are arranged in a divergent layout. For example, it may include a first input interface input_pin_a, a second input interface input_pin_b, a third input interface input_pin_c, and a fourth input interface input_pin_d.
[0082] To better understand this application, taking the first input interface input_pin a in FIG. 2 as an example, according to the logical structure of the target netlist corresponding to the second design S2, the previous-level connection of the first input interface input_pin a can be traced, and then the number Ca1 of the first fanout connection lines (fanout1) of the first driver unit Ra1 corresponding to the previous-level connection line can be traced; then the second-level previous connection line is traced, and then the number Ca2 of the second fanout connection lines (fanout2) of the second driver unit Ra2 corresponding to the second-level previous connection line is traced; and so on until the starting timing unit is traced, and the number Cai of the fanout connection lines (fanouti) of each driver unit Rai is obtained. Wherein, i is an integer less than N, and the value of N can be determined according to the logical level of the path where the first input interface input_pin a is located.
[0083] Next, the number of fanout connection lines of its previous i-level driver units Rai can be compared in sequence to obtain the minimum value Camin and the driver unit Ramin corresponding to the minimum value Camin. The driver unit Ramin is used to replace input_pin a as the netlist splitting point corresponding to the first input interface, thereby forming a new inter-module boundary. Similar operations can be performed for other input interfaces with reference to this process, which will not be elaborated here. Further, the target netlist can be split according to this inter-module boundary to obtain the split netlist. It can be seen that through this splitting method, each input interface can be traced according to the preset tracing direction to find the logical divergence point, and then the divergence point is used as a new splitting basis, which can effectively reduce the number of input interfaces in the second design S2, thereby reducing the number of inter-module interfaces and optimizing the design structure.
[0084] Or, referring to Figure 3 As shown, according to the transmission direction of the data stream, the data stream passes through multiple output interfaces in the second design S2 and flows through the second interface combination unit 201 and the second interface register 202 in the first design S1 in sequence. Among them, the multiple output interfaces are arranged in a converging layout. For example, it may include a first output interface output_pin_A, a second output interface output_pin_B, a third output interface output_pin_C, and a fourth output interface input_pin_D.
[0085] Continuing with the first output interface output_pin_A in FIG. 3 as an example, according to the logical structure of the target netlist corresponding to the second design S2, the subsequent i-level connections of the first output interface output_pin_A (where i is an integer less than M), the load units RAi corresponding to each connection can be traced in sequence, and the number CAi of the fan-in connections of each load unit RAi can be obtained until the termination timing unit is traced. Then, the numbers CAi of the fan-in connections corresponding to each output interface are compared to obtain the maximum value CAmax and the load unit RAmax corresponding to the maximum value CAmax. The load unit RAmax is used to replace output_pinA as the netlist splitting point corresponding to the first output interface, thereby forming a new inter-module boundary. Similar operations can be performed for other output interfaces by referring to this process, which will not be elaborated here. Further, the target netlist can be split according to this inter-module boundary to obtain the split netlist. It can be seen that through this splitting method, each output interface can be traced according to the preset tracing direction to find the logical convergence point, and then the convergence point is used as the new splitting basis, which can effectively reduce the number of output interfaces in the second design S2, thereby reducing the number of inter-module interfaces and optimizing the design structure.
[0086] Optionally, there is the same target unit corresponding to multiple target interfaces in the target netlist.
[0087] Among them, taking the above example, that is, for multiple input interfaces or output interfaces, there will be cases where the driving units corresponding to the minimum number they trace are the same or the load units corresponding to the maximum number are the same. In this case, there will be a situation where these multiple input interfaces or output interfaces correspond to the same netlist splitting point. Therefore, the newly obtained netlist splitting point will be less than the total number of input interfaces or output interfaces, that is, less than the total number of input interfaces or output interfaces in the original hierarchical splitting.
[0088] Optionally, if the multiple target interfaces include multiple input interfaces, there is the same starting timing unit corresponding to multiple input interfaces in the target netlist; if the multiple target interfaces include multiple output interfaces, there is the same termination timing unit corresponding to multiple output interfaces in the target netlist.
[0089] For input interfaces, in some embodiments, although the driving units corresponding to the maximum number traced for multiple input interfaces are not the same, these multiple input interfaces all originate from the same starting timing unit. In this case, along the reverse direction of the data flow transmission, the first common logic unit on the timing common path of these input interfaces can be found first, and then for this common logic unit, the steps of S101 to S104 described above are followed for tracing to determine the final netlist splitting point.
[0090] For the output interface, in some embodiments, although the driving units corresponding to the maximum number tracked for multiple output interfaces are not the same, these multiple output interfaces all pass through the same termination timing unit. In this case, along the data flow direction, the first common logic unit on the timing common path of these output interfaces can be found first, and then for this common logic unit, the steps of S101 to S104 described above are followed for tracking to determine the final netlist splitting point.
[0091] Of course, in some embodiments, considering factors such as the difficulty of timing convergence of the interface for the determined netlist splitting point, it can also be adjusted. For example, other common logic units on the timing common path can be used as the new netlist splitting point.
[0092] In summary, it can be seen that in the netlist splitting method provided by the embodiments of the present application, during the splitting process, for each input interface or output interface, by tracking the front and rear stage logics, finding the logic divergence point or convergence point, and using this as the netlist splitting point to obtain a new interface of the netlist, the number of interfaces between modules can be effectively reduced, the design structure can be optimized, and it is helpful for the rapid implementation of the design.
[0093] Figure 4 It is a schematic flowchart of another netlist splitting method provided by the embodiments of the present application. Optionally, as Figure 4 shown, the above-mentioned splitting of the target netlist according to each netlist splitting point to obtain the split netlist includes:
[0094] S301. Determine the boundaries between modules corresponding to the target netlist according to each netlist splitting point.
[0095] S302. Split the target netlist according to the boundaries between modules to obtain the split netlist.
[0096] Among them, the boundaries between modules can indicate the division method of the internal interfaces between modules in the target netlist. After obtaining each netlist splitting point, the number of internal interfaces between modules in the target netlist can be optimized and reduced, so that the obtained split netlist can have fewer interfaces between modules compared with before splitting.
[0097] Figure 5 It is a schematic flowchart of yet another netlist splitting method provided by the embodiments of the present application. Figure 6 It is a flattening schematic diagram of a hierarchical gate-level netlist provided by the embodiments of the present application. Optionally, as Figure 5 shown, the above-mentioned extraction of at least one target interface from the target netlist includes:
[0098] S401. Obtain the initial hierarchical gate-level netlist.
[0099] Optionally, the initial hierarchical gate-level netlist can be obtained by simulating the target integrated circuit corresponding to the target chip with the help of EDA tools.
[0100] S402. Determine the initial cut line according to the functional regions of the chip.
[0101] Optionally, the functional regions of the chip may include: input region, output region, clock region, counter region, register region, arithmetic operation unit region, CPU region, etc., which are not limited herein. According to the actual application scenario, the initial cut line can be determined based on at least one functional region. Referring to Figure 6 as shown, the curve L is the initial cut line.
[0102] S403. Divide the initial hierarchical gate-level netlist according to the initial cut line to obtain the target netlist.
[0103] S404. Based on the logical structure of the target netlist, perform a flattening operation on the target netlist to extract at least one target interface in the target netlist.
[0104] Among them, different target netlists will be obtained according to different initial cut lines; the flattening operation of the target netlist can be implemented with the help of EDA design tools. Specifically, when implemented, if based on the logical structure of the target netlist, the target netlist can be flattened and expanded, so as to obtain at least one target interface in the target netlist.
[0105] Optionally, the flattening operation of the target netlist can be implemented through EDA design tools. Referring to Figure 6 (b) as shown, the flattened first netlist can correspond to the first design S1 and the flattened second netlist can correspond to the second design S2. Taking the second design S2 as an example, for the flattened second design S2, at least one target interface in the second design can be extracted according to the logical structure of the second netlist and a splitting operation can be performed based on this. Among them, the target interface may include an input interface and / or an output interface, which are not limited herein and may vary according to the actual application scenario. The specific splitting principle can be seen in the relevant parts described above and will not be elaborated herein.
[0106] Optionally, the above-mentioned dividing the initial hierarchical gate-level netlist according to the initial cut line to obtain the target netlist includes:
[0107] Dividing the initial hierarchical gate-level netlist according to the initial cut line to generate hierarchical interface points and another part of interface points connected to the hierarchical interface points; connecting the hierarchical interface points and connecting the other part of interface points respectively to form the target netlist.
[0108] For a better understanding of this application, refer to the above Figure 6, the initial hierarchical gate-level netlist may include multiple modules, such as Figure 6 As shown in (a), it may include a first-level module 10, a second-level module 20, and a third-level module 30. If the preset splitting function corresponds to the splitting line L, the initial hierarchical gate-level netlist can be split according to the splitting line L, and two target netlists with the splitting line L as the boundary can be obtained.
[0109] Optionally, the generation process of the target netlist can be referred to the following content: With the help of an EDA design tool, extract the interface points at the splitting positions in the initial hierarchical gate-level netlist, such as Figure 6 As shown in (b), after splitting based on the splitting line L, a first design S1 and a second design S2 can be formed. Among them, the first design S1 may include at least one first hierarchical interface pin1, and the second design S2 may include at least one second hierarchical interface pin2. The first hierarchical interface pin1 and the second hierarchical interface pin2 are a pair of matching interfaces.
[0110] Figure 7 It is a schematic diagram of the functional modules of a netlist splitting device provided by an embodiment of the present application. This embodiment provides a netlist splitting device. The basic principle and the technical effects generated by this device are the same as those of the corresponding method embodiment described above. For a brief description, for the parts not mentioned in this embodiment, reference can be made to the corresponding content in the method embodiment. As Figure 7 shown, the netlist splitting device 100 includes:
[0111] An extraction module 110, configured to extract at least one target interface in the target netlist, where the target netlist is the netlist after initial splitting, and at least one target interface in the target netlist belongs to one area after initial splitting;
[0112] A tracking module 120, configured to, based on the logical structure of the target netlist, for each of the target interfaces, track the target units associated with each of the target interfaces, where the target units include: driving units or load units;
[0113] A determination module 130, configured to determine the netlist splitting points corresponding to each of the target interfaces according to the number of fan-out or fan-in connection lines corresponding to each target unit;
[0114] A splitting module 140, configured to split the target netlist according to each of the netlist splitting points to obtain the split netlist.
[0115] In an alternative embodiment, if the target interface is an input interface, the target unit is a driving unit, and the number of fan-out connection lines corresponding to the driving unit is tracked; if the target interface is an output interface, the target unit is a load unit, and the number of fan-in connection lines corresponding to the load unit is tracked.
[0116] In an alternative embodiment, the determining module 130 is specifically configured to compare the number of fan - out or fan - in connection lines corresponding to each target unit. If the target interface is an input interface, the driving unit corresponding to the minimum number is determined as the netlist splitting point corresponding to the input interface; if the target interface is an output interface, the load unit corresponding to the maximum number is determined as the netlist splitting point corresponding to the output interface.
[0117] In an alternative embodiment, if the target interface is an input interface and there are multiple minimum numbers, the driving unit among the driving units corresponding to the multiple minimum numbers that is farthest from the input interface is determined as the netlist splitting point corresponding to the input interface; if the target interface is an output interface and there are multiple maximum numbers, the load unit among the load units corresponding to the multiple maximum numbers that is farthest from the output interface is determined as the netlist splitting point corresponding to the output interface.
[0118] In an alternative embodiment, the tracing module 120 is specifically configured to, based on the logical structure of the target netlist, if the target interface is an input interface, for the input interface, trace the first N - level connections of the input interface until the starting timing unit is traced, and determine the driving units corresponding to each level of connections, where N is an integer greater than 0;
[0119] If the target interface is an output interface, for the output interface, trace the last M - level connections of the output interface until the terminating timing unit is traced, and determine the load units corresponding to each level of connections, where M is an integer greater than 0.
[0120] In an alternative embodiment, there are multiple target units corresponding to the same target interface in the target netlist.
[0121] In an alternative embodiment, if multiple target interfaces include multiple input interfaces, there is the same starting timing unit corresponding to multiple input interfaces in the target netlist; if multiple target interfaces include multiple output interfaces, there is the same terminating timing unit corresponding to multiple output interfaces in the target netlist.
[0122] In an alternative embodiment, the splitting module 140 is specifically configured to determine the inter - module boundary corresponding to the target netlist according to each netlist splitting point;
[0123] The target netlist is split according to the inter - module boundary to obtain the split netlist.
[0124] In an alternative embodiment, the extraction module is specifically configured to obtain an initial hierarchical gate - level netlist;
[0125] Determine an initial splitting line according to the functional area of the chip;
[0126] Partition the initial hierarchical gate-level netlist according to the initial segmentation line to obtain the target netlist;
[0127] Based on the logical structure of the target netlist, perform a flattening operation on the target netlist to extract at least one target interface in the target netlist.
[0128] In an alternative embodiment, the extraction module is specifically configured to partition the initial hierarchical gate-level netlist according to the initial segmentation line to generate hierarchical interface points and another part of interface points connected to the hierarchical interface points;
[0129] Connect the hierarchical interface points and the other part of interface points respectively to form the target netlist.
[0130] The above device is used to execute the method provided in the foregoing embodiment, and its implementation principle and technical effects are similar, which will not be elaborated here.
[0131] The above modules may be one or more integrated circuits configured to implement the above method, for example: one or more application specific integrated circuits (ASICs), or, one or more microprocessors, or, one or more field programmable gate arrays (FPGAs), etc. Again, when a certain above module is implemented in the form of a processing element scheduling program code, the processing element may be a general-purpose processor, such as a central processing unit (CPU) or other processors that can call program code. Again, these modules may be integrated together and implemented in the form of a system-on-a-chip (SOC).
[0132] Figure 8 It is a schematic structural diagram of an electronic device provided in an embodiment of the present application, and this electronic device may be integrated into a netlist segmentation device. As Figure 8 shown, this electronic device may include: a processor 210, a storage medium 220, and a bus 230. The storage medium 220 stores machine-readable instructions executable by the processor 210. When the electronic device runs, the processor 210 communicates with the storage medium 220 through the bus 230, and the processor 210 executes the machine-readable instructions to execute the steps of the above method embodiment. The specific implementation manner and technical effects are similar and will not be elaborated here.
[0133] Optionally, the present application also provides a storage medium, on which a computer program is stored. When the computer program is run by a processor, the steps of the above method embodiment are executed. The specific implementation manners and technical effects are similar and will not be elaborated here.
[0134] In several embodiments provided by the present application, it should be understood that the disclosed apparatus and method can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative. For example, the division of units is only a logical function division. In actual implementation, there may be other division methods. For example, multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the displayed or discussed couplings or direct couplings or communication connections to each other can be through some interfaces. The indirect couplings or communication connections of the apparatus or units can be in electrical, mechanical or other forms.
[0135] The units described as separate components may or may not be physically separated. The components displayed as units may or may not be physical units, that is, they may be located in one place, or may be distributed to multiple network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of this embodiment.
[0136] In addition, in each embodiment of the present application, the functional units can be integrated in a processing unit, or each unit can exist physically alone, or two or more units can be integrated in one unit. The above integrated units can be implemented in the form of hardware, or in the form of hardware plus software functional units.
[0137] The above integrated units implemented in the form of software functional units can be stored in a computer-readable storage medium. The above software functional units are stored in a storage medium, including several instructions for causing a computer device (which can be a personal computer, a server, or a network device, etc.) or a processor (English: processor) to execute some steps of the methods of each embodiment of the present application. The foregoing storage medium includes: various media that can store program codes such as USB flash drives, mobile hard disks, read-only memories (English: Read-Only Memory, abbreviated as: ROM), random access memories (English: Random Access Memory, abbreviated as: RAM), magnetic disks, or optical discs.
[0138] It should be noted that in this text, relational terms such as "first" and "second" are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the terms "comprising", "including" or any other variant thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device comprising a series of elements not only includes those elements but also includes other elements not expressly listed, or elements inherent to such process, method, article or device. Without further limitation, an element defined by the statement "comprising an..." does not exclude the presence of additional identical elements in the process, method, article or device comprising the element.
[0139] The above are only the preferred embodiments of the present application and are not intended to limit the present application. For those skilled in the art, various changes and modifications can be made to the present application. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principle of the present application shall be included within the protection scope of the present application. It should be noted that similar reference numerals and letters denote similar items in the following drawings. Therefore, once an item is defined in one drawing, it does not need to be further defined and explained in subsequent drawings. The above are only the preferred embodiments of the present application and are not intended to limit the present application. For those skilled in the art, various changes and modifications can be made to the present application. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principle of the present application shall be included within the protection scope of the present application.
Claims
1. A netlist splitting method, characterized in that, Including: Extracting at least one target interface from the target netlist, where the target netlist is the netlist after initial partitioning, and at least one target interface in the target netlist belongs to one area after initial partitioning; Based on the logical structure of the target netlist, for each of the target interfaces, tracing the target units associated with each of the target interfaces, where the target units include: driving units or load units; Determining the netlist splitting points corresponding to each of the target interfaces according to the number of fan-out or fan-in connection lines corresponding to each of the target units; Splitting the target netlist according to each of the netlist splitting points to obtain the split netlist.
2. The method according to claim 1, wherein If the target interface is an input interface, the target unit is a driving unit, and trace the number of fan-out connection lines corresponding to the driving unit; If the target interface is an output interface, the target unit is a load unit, and trace the number of fan-in connection lines corresponding to the load unit.
3. The method according to claim 2, wherein The determining the netlist splitting points corresponding to each of the target interfaces according to the number of fan-out or fan-in connection lines corresponding to each of the target units includes: Comparing the number of fan-out or fan-in connection lines corresponding to each target unit. If the target interface is an input interface, determine the driving unit corresponding to the minimum number as the netlist splitting point corresponding to the input interface; if the target interface is an output interface, determine the load unit corresponding to the maximum number as the netlist splitting point corresponding to the output interface.
4. The method according to claim 3, characterized in that, If the target interface is an input interface and there are multiple minimum numbers, determine the driving unit far from the input interface among the driving units corresponding to the multiple minimum numbers as the netlist splitting point corresponding to the input interface; If the target interface is an output interface and there are multiple maximum numbers, determine the load unit far from the output interface among the load units corresponding to the multiple maximum numbers as the netlist splitting point corresponding to the output interface.
5. The method according to claim 1, characterized in that The tracing the target units associated with each of the target interfaces based on the logical structure of the target netlist includes: Based on the logical structure of the target netlist, if the target interface is an input interface, for the input interface, trace the first N levels of connection lines of the input interface until tracing to the starting timing unit, and determine the driving units corresponding to each level of connection lines, where N is an integer greater than 0; If the target interface is an output interface, for the output interface, trace the last M levels of connection lines of the output interface until tracing to the terminating timing unit, and determine the load units corresponding to each level of connection lines, where M is an integer greater than 0.
6. The method according to claim 1, wherein There are multiple target units corresponding to the same target interface in the target netlist.
7. The method according to claim 5, wherein If multiple target interfaces include multiple input interfaces, there are multiple starting timing units corresponding to the multiple input interfaces in the target netlist; if multiple target interfaces include multiple output interfaces, there are multiple terminating timing units corresponding to the multiple output interfaces in the target netlist.
8. The method according to claim 1, wherein The splitting the target netlist according to each of the netlist splitting points to obtain the split netlist includes: Determining the module - level boundaries corresponding to the target netlist according to each of the netlist splitting points; Partition the target netlist according to the boundaries between the modules to obtain the partitioned netlist.
9. The method according to any one of claims 1-8, characterized in that The extraction of at least one target interface from the target netlist includes: Obtain an initial hierarchical gate-level netlist; Determine an initial partitioning line according to the functional regions of the chip; Partition the initial hierarchical gate-level netlist according to the initial partitioning line to obtain the target netlist; Based on the logical structure of the target netlist, perform a flattening operation on the target netlist to extract at least one target interface from the target netlist.
10. The method according to claim 9, wherein The partitioning of the initial hierarchical gate-level netlist according to the initial partitioning line to obtain the target netlist includes: Partition the initial hierarchical gate-level netlist according to the initial partitioning line to generate hierarchical interface points and another part of interface points connected to the hierarchical interface points; Connect the hierarchical interface points and connect the other part of interface points respectively to form the target netlist.
11. An electronic device, characterized in that, Including: A processor, a storage medium, and a bus. The storage medium stores machine-readable instructions executable by the processor. When the electronic device runs, the processor communicates with the storage medium through the bus, and the processor executes the machine-readable instructions to perform the steps of the netlist partitioning method according to any one of claims 1-10.
12. A computer-readable storage medium, characterized in that, A computer program is stored on the computer-readable storage medium, and when the computer program is run by the processor, it performs the steps of the netlist partitioning method according to any one of claims 1-10.