A GPU shader tracking and recording system

Abstract

The present application relates to the field of integrated circuit design technology, and in particular to a GPU shader tracking and recording system. The system obtains shader tracking data of each sub-module through a shader tracking module in the shader, and splices the shader tracking data of each sub-module into a token, and then sends the token to a cache module to provide it to the software side, so as to facilitate the software side to parse the token and perform performance analysis of the GPU chip, making the obtained shader tracking data more comprehensive, detailed and correlated, thereby improving the efficiency and accuracy of the software side in analyzing the GPU chip performance according to the token to find performance bottlenecks.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuit design, and in particular to a GPU shader tracking and recording system. Background Art

[0002] Currently, GPU performance analysis on the software side is usually based on directly obtained performance indicators of the GPU chip. Performance indicators can include CPU runtime, GPU runtime, storage utilization, etc. However, these performance indicators usually do not involve the underlying information of GPU operation, resulting in incomplete information used by the software side for GPU performance analysis, resulting in low accuracy of GPU performance analysis on the software side.

[0003] To address the above issues, existing technologies have proposed GPU shader tracing. GPU shader tracing is a technical means for recording and analyzing shader-related events and operations in GPU chips. It can obtain detailed information during the shader execution process, such as the execution status of instructions, the execution time of instructions, the number of instruction types, etc., thereby helping the software side to have an in-depth understanding of the operation of the shader, and thus perform debugging, performance optimization, and research on the graphics rendering process.

[0004] However, since the shader contains multiple sub-modules, each sub-module can provide corresponding shader tracking data, the shader tracking module will obtain a large amount of shader tracking data, which requires the software side to perform GPU performance analysis based on the numerous and messy shader tracking data, reducing the efficiency of GPU performance analysis. Therefore, how to improve the efficiency of GPU performance analysis has become an urgent problem to be solved. Summary of the Invention

[0005] In view of the above technical problems, the technical solution adopted by the present invention is:

[0006] A GPU shader tracking and recording system includes: a software side, a GPU chip, and a device memory, wherein the GPU chip includes a shader, the shader includes A submodules and a shader tracking module, A is an integer greater than zero, and the device memory includes a cache module.

[0007] The shader tracing module is used to obtain corresponding shader tracing data from the A sub-modules respectively.

[0008] The shader tracing module is further configured to splice the acquired shader tracing data into tokens in a preset manner.

[0009] The shader tracking module is further configured to send a token to the cache module.

[0010] The cache module is used to receive access from the software side to provide a token to support the software side in performing performance analysis of the GPU chip.

[0011] Compared with the prior art, the present invention has significant advantages. By utilizing the above technical solution, the GPU shader tracking and recording system provided by the present invention can achieve considerable technological advancement and practicality, and has wide industrial application value. It has at least the following advantages:

[0012] The present invention provides a GPU shader tracing and recording system, which includes: a software side, a GPU chip and a device memory, wherein the GPU chip includes a shader, the shader includes A sub-modules and a shader tracing module, A is an integer greater than zero, the device memory includes a cache module, the shader tracing module is used to obtain corresponding shader tracing data from the A sub-modules respectively, the shader tracing module is also used to splice the obtained shader tracing data into tokens in a preset manner, the shader tracing module is also used to send the tokens to the cache module, and the cache module is used to receive access from the software side to provide tokens to support the software side in performing performance analysis of the GPU chip.

[0013] It can be seen that the shader tracing data of each sub-module is obtained by the shader tracing module in the shader, and the shader tracing data of each sub-module is spliced ​​into tokens, and then the tokens are sent to the cache module to be provided to the software side, so that the software side can parse the tokens and perform performance analysis of the GPU chip, making the obtained shader tracing data more comprehensive, detailed and correlated, thereby improving the efficiency and accuracy of the software side in analyzing the GPU chip performance according to the tokens to find out the performance bottlenecks. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0015] Figure 1 A schematic diagram of the architecture of a GPU shader tracking and recording system provided in Example 1 of the present invention;

[0016] Figure 2 A schematic diagram of the architecture of a token generation system based on GPU shader tracing data provided in the second embodiment of the present invention;

[0017] Figure 3A schematic diagram of a flow chart of a computer program being processed and executed in a timestamp token generation system provided in a third embodiment of the present invention;

[0018] Figure 4 A schematic diagram of the architecture of a cache system based on shader tracking data provided by the fourth embodiment of the present invention;

[0019] Figure 5 This is a schematic diagram of the architecture of an address translation system based on shader tracing data provided in Example 5 of the present invention. DETAILED DESCRIPTION

[0020] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without making any creative efforts shall fall within the scope of protection of the present invention.

[0021] This embodiment provides a GPU shader tracking and recording system. Figure 1 , is a schematic diagram of the architecture of a GPU shader tracking and recording system provided in a first embodiment of the present invention, the system comprising: a software side, a GPU chip, and a device memory, wherein the GPU chip comprises a shader, the shader comprises A submodules and a shader tracking module, where A is an integer greater than zero, and the device memory comprises a cache module;

[0022] The shader tracing module is used to obtain corresponding shader tracing data from the A sub-modules respectively;

[0023] The shader tracing module is further configured to splice the acquired shader tracing data into tokens in a preset manner;

[0024] The shader tracking module is further configured to send a token to the cache module;

[0025] The cache module is used to receive access from the software side to provide a token to support the software side in performing performance analysis of the GPU chip.

[0026] Among them, shaders are an important part of the graphics rendering pipeline. Shaders can be used to implement various operations and effects on graphics. Shaders can include multi-level shaders, such as vertex shaders, pixel shaders, geometry shaders, etc.

[0027] A submodule may refer to a module in a shader that performs a specific function. A shader typically contains multiple submodules with different specific functions.

[0028] The device memory may adopt Double Data Rate SDRAM (DDR), High Bandwidth Memory (HBM), etc.

[0029] Shader tracing data can be used to record shader-related events and operations in GPU chips to obtain detailed information about the shader execution process, such as the execution status of instructions, the execution time of instructions, and the number of instruction types.

[0030] Tokens can be used to integrate related shader tracking data to obtain more integrated data, so that subsequent software can quickly analyze based on tokens and gain an in-depth understanding of the operation of the shader, thereby performing debugging, performance optimization, and research on the graphics rendering process.

[0031] The cache module can be used to temporarily store tokens. Since the cache module is in the device memory, the cache module can support reading on the software side, that is, receive access from the software side to provide tokens to support the software side to perform performance analysis of the GPU chip.

[0032] In a specific embodiment, for any submodule, the submodule includes a plurality of target interfaces, each target interface corresponding to shader tracing data of a different tracing data type, and all target interfaces are connected to the shader tracing module;

[0033] The obtaining corresponding shader tracking data from the A sub-modules respectively includes:

[0034] For any sub-module, shader tracing data of corresponding tracing data type is obtained from each target interface included in the sub-module.

[0035] Among them, different sub-modules correspond to different functions, and the same sub-module can include multiple target interfaces. The shader tracking data provided by different target interfaces are also different for domestic tracking data types. The tracking data type may include instruction status, instruction execution time, instruction type, etc.

[0036] Specifically, shader tracing data is provided to the shader tracing module through each target interface of each sub-module, which improves the comprehensiveness and richness of the shader tracing data. The provided shader tracing data is also more detailed and low-level, making it easier for the software to parse the token after the token is formed, analyze the GPU performance and find performance bottlenecks.

[0037] In a specific embodiment, the shader trace data corresponds to a token type and position information in a token corresponding to the token type;

[0038] The obtained shader tracking data is spliced ​​into tokens according to a preset method, including:

[0039] For any token type, several shader tracking data belonging to the token type are spliced ​​according to the position information of each shader tracking data in the token of the corresponding token type to obtain the token corresponding to the token type.

[0040] The shader tracing data corresponds to a token type, a single shader tracing data corresponds to one token type, and a single token type can correspond to multiple different shader tracing data.

[0041] Specifically, in this embodiment, in order to facilitate transmission, storage and access, the token adopts a fixed bit width, which can be 64 bits. Since the bit width is fixed, for a token of a certain token type, the shader tracking data corresponding to each position should also be fixed, so as to facilitate the software side to parse the token, that is, the shader tracking data corresponds to the token type and the position information in the token of the corresponding token type.

[0042] In a specific embodiment, the token type includes at least an instruction type, an instruction count type, a performance count type, and a timestamp type.

[0043] The token type may also include user data type, thread start type, thread end type, global start type, global end type, etc.

[0044] It should be noted that implementers can construct new token types based on actual software requirements, and determine the shader tracking data required for the new token type and the location information of the required shader tracking data in the token of the new token type.

[0045] In a specific embodiment, the shader trace module further includes a mask register, the mask register including a first mask sub-register;

[0046] The first mask subregister includes B first mask bits, where B is the number of token types, and each first mask bit corresponds to a token type;

[0047] For any first mask bit, if the first mask bit is a first preset value, a token of the token type corresponding to the first mask bit is not generated.

[0048] The first mask bit may be binary, and the value of the first mask bit may be a first preset value or a second preset value. The first preset value may be 1, and the second preset value may be 0.

[0049] Specifically, since shader tracing data is continuously generated when the GPU performs rendering tasks, the shader tracing module needs to form a large number of tokens and then transfer the tokens to the cache module for storage. Considering the storage pressure of the cache module and the token generation pressure of the shader tracing module, a mask register is set in the shader tracing module. The mask register can be used to control the generation of only tokens that the implementer is interested in, and the first mask sub-register can be used to control the generation of only tokens of the token type that the implementer is interested in.

[0050] In a specific embodiment, the mask register includes a second mask sub-register;

[0051] The second mask subregister includes a plurality of second mask bits, wherein each second mask bit corresponds to an instruction type;

[0052] For any second mask bit, if the second mask bit is the first preset value, a token containing the instruction type corresponding to the second mask bit is not generated.

[0053] The second mask bit may be binary, and the value of the second mask bit may be the first preset value or the second preset value.

[0054] Specifically, the second mask subregister can be used to control the generation of tokens of only instruction types that are of interest to the implementer.

[0055] In a specific embodiment, the mask register includes a third mask sub-register;

[0056] The third mask sub-register includes a plurality of third mask bits, wherein each third mask bit corresponds to an instruction count type;

[0057] For any third mask bit, if the third mask bit is the first preset value, a token containing the instruction count type corresponding to the third mask bit is not generated.

[0058] The third mask bit may be binary, and the value of the third mask bit may be the first preset value or the second preset value.

[0059] Specifically, the third mask subregister can be used to control the generation of tokens of only instruction count types that are of interest to the implementer.

[0060] In a specific embodiment, the token corresponding to the performance counter type includes a high-order token and a low-order token, and the mask register includes a fourth mask sub-register;

[0061] The fourth mask subregister includes a plurality of fourth mask bits, wherein each fourth mask bit corresponds to a performance counter type;

[0062] For any fourth mask bit, if the fourth mask bit is the first preset value, no low-order token corresponding to the performance counter type is generated;

[0063] If the fourth mask bit is the second preset value, a high-order token corresponding to the performance counter type is not generated.

[0064] The fourth mask bit may be binary, and the value of the fourth mask bit may be the first preset value or the second preset value.

[0065] Specifically, since there are many performance count types, the tokens corresponding to the performance count types are divided into high-order tokens and low-order tokens. The fourth mask subregister can be used to control the generation of only high-order tokens or low-order tokens of the performance count type that the implementer is interested in.

[0066] In this embodiment, the shader tracing data of each sub-module is obtained by the shader tracing module in the shader, and the shader tracing data of each sub-module is spliced ​​into a token, and then the token is sent to the cache module to be provided to the software side, so that the software side can parse the token and perform performance analysis of the GPU chip, so that the obtained shader tracing data is more comprehensive, detailed and correlated, thereby improving the efficiency and accuracy of the software side in analyzing the GPU chip performance according to the token to find the performance bottleneck.

[0067] This embodiment 2 provides a token generation system based on GPU shader tracking data, see Figure 2 , is a schematic diagram of the architecture of a token generation system based on GPU shader tracing data provided by a second embodiment of the present invention, the system comprising: a GPU chip, wherein the GPU chip comprises a shader, the shader comprises A submodules and a shader tracing module, where A is an integer greater than zero;

[0068] The shader tracking module is used to act as a master device to obtain performance counting data of A submodules acting as slave devices, wherein the submodules include performance counters;

[0069] The shader tracking module is further used to obtain a token corresponding to the performance count type based on the obtained performance count data when the rendering task is executed and the positioning data corresponding to the rendering task;

[0070] The shader tracking module is further configured to obtain a token corresponding to a global startup type according to the first rendering command identifier and the first rendering subcommand identifier when a rendering task starts;

[0071] The shader tracking module is also used to downsample the first rendering command identifier and the first rendering sub-command identifier in the token corresponding to the global startup type to obtain the second rendering command identifier and the second rendering sub-command identifier when a thread starts to execute a rendering task, and to obtain the token corresponding to the thread startup type based on the second rendering command identifier and the second rendering sub-command identifier and the positioning data corresponding to the thread.

[0072] Among them, performance counters can be used to collect and record performance data of sub-modules in real time, and can quantify various performance-related indicators, such as CPU usage, memory occupancy, data transmission rate, bandwidth, etc.

[0073] In a sub-module, a performance counter in the sub-module records performance count data. Accordingly, the shader tracing module is used as a master device to obtain performance count data from the performance counters of A sub-modules that are slave devices.

[0074] Rendering tasks can include a series of processes such as scene setting, material and texture processing, lighting calculation to final image generation. In the vertex processing stage, the vertex shader is required to process the vertex data and pass the calculated vertex color, texture coordinates and other information to the pixel shader. The pixel shader combines the lighting model, material properties, texture data, etc. in the scene, and determines the color of each pixel through complex mathematical calculations.

[0075] The positioning data may include one or more of a queue identifier, a workgroup identifier, a processing unit identifier, an array processor identifier, a processing element unit identifier, a thread identifier, a block identifier, a chain identifier, and an event identifier. In this embodiment, the positioning data contained in the token corresponding to the performance count type may include a block identifier, a chain identifier, a processing unit identifier, and an event identifier.

[0076] In a rendering task, after vertex data processing is completed, primitives are constructed based on the processing results and converted into pixels on the screen. For each pixel covered by the primitive, corresponding calculation processing is required. The rendering task will include multiple rendering commands in multiple stages. The first rendering command identifier can be used to identify the rendering command corresponding to the current processing object, and the first rendering sub-command identifier can be used to identify the rendering command of the sub-stage related to the current processing object. In the same rendering task, the first rendering sub-command identifier is incremental. The first rendering command identifier and the first rendering sub-command identifier are used to effectively record the processing connection between the multi-level shaders, so as to evaluate the balance of rendering task distribution, the size of the graphics corresponding to the rendering task, the rendering pressure of the lines or points generated by the rendering task on the shader, etc.

[0077] For a single thread, the thread performs corresponding processing according to the assigned rendering command. In order to make the token corresponding to the thread record the rendering command information of the first enabled shader, the first rendering command identifier and the first rendering sub-command identifier can be provided to the token corresponding to the thread. However, since the first rendering command identifier and the first rendering sub-command identifier are both 32 bits, if the token corresponding to the thread directly uses the first rendering command identifier and the first rendering sub-command identifier, it will not be able to record the thread's positioning data, such as the queue identifier, workgroup identifier, processing unit identifier, array processor identifier, processing element unit identifier, thread identifier, etc. Therefore, in this embodiment, the first rendering command identifier and the first rendering sub-command identifier are downsampled to obtain the second rendering command identifier and the second rendering sub-command identifier.

[0078] Specifically, the second rendering command identifier can be the lower 16 bits of the first rendering command identifier, that is, the second rendering command identifier can be the lower 16 bits of the first rendering command identifier. 16 Performing a modulo calculation, the second rendering sub-command identifier may be the lower 8 bits of the first rendering sub-command identifier.

[0079] In rendering tasks, factors such as clipping, depth testing, and template testing may cause some rendering operations to not generate pixel shader execution. Therefore, in order to ensure the accuracy of the second rendering command identifier record, a 16-bit bit width is used instead of a smaller bit width. Similarly, the second rendering sub-command identifier may be continuous in the vertex shader but discontinuous in the pixel shader. Therefore, in order to ensure the accuracy of the second rendering sub-command identifier record, an 8-bit bit width is used instead of a smaller bit width.

[0080] In a specific embodiment, the step of obtaining a token corresponding to a performance count type by combining the acquired performance count data during the execution of the rendering task and the positioning data corresponding to the rendering task includes:

[0081] A token corresponding to the performance counting type is obtained by combining the obtained performance counting data during the execution of the rendering task, the positioning data corresponding to the rendering task, and the performance counting identifier;

[0082] If the performance count identifier is a first preset value, a low-order token corresponding to the performance count type is obtained by splicing the obtained performance count data when the rendering task is executed, the positioning data corresponding to the rendering task, and the performance count identifier;

[0083] If the performance count identifier is a second preset value, a high-order token corresponding to the performance count type is obtained by splicing the obtained performance count data when the rendering task is executed, the positioning data corresponding to the rendering task, and the performance count identifier.

[0084] Among them, the performance count identifier can be binary, and the performance count identifier can take the first preset value or the second preset value. Since there are many performance count types, the tokens corresponding to the performance count types are divided into high-order tokens and low-order tokens.

[0085] In a specific embodiment, the GPU chip further includes a temporary buffer;

[0086] The obtaining of performance counting data of A submodules serving as slave devices includes:

[0087] Obtain a timestamp token, and determine a sampling time point according to the timestamp token and a preset sampling period;

[0088] If there is no unfinished signal at the sampling time point, sending a performance counting data sampling request to the A submodules serving as slave devices at the sampling time point;

[0089] After receiving the performance counting data sampling request, the A submodules serving as slave devices respectively send the corresponding performance counting data to the temporary buffer;

[0090] When the performance counting data respectively corresponding to the A sub-modules serving as slave devices have not yet arrived at the temporary buffer, the incomplete signal is generated.

[0091] Among them, the temporary buffer can refer to a data viewing buffer (peek buffer). During the shader processing process, when the performance count data needs to be intermediately viewed or debugged, the performance count data will be sent to such a buffer, which makes it convenient for the implementer to obtain information such as the intermediate status of the performance count data without affecting the processing flow of the shader.

[0092] Specifically, a timestamp-type token may be used to represent an absolute timestamp, and then a number of sampling time points may be determined according to the absolute timestamp and a preset sampling period.

[0093] For each sampling time point, when there is no unfinished signal at the sampling time point, a performance counting data sampling request is sent to the A sub-modules serving as slave devices at the sampling time point.

[0094] When there is an unfinished signal at the sampling time point, the current sampling time point is skipped and the next sampling time point is waited for to determine whether there is an unfinished signal.

[0095] In one embodiment, the implementer may send a sampling signal to directly send a performance counter data sampling request to the A sub-modules serving as slave devices, without waiting for a sampling time point and without considering an unfinished signal.

[0096] In a specific implementation, the shader tracing module is further configured to generate a token corresponding to a global end type upon receiving a rendering completion enable signal.

[0097] Among them, since tokens usually contain instruction types and positioning data, tokens can be associated based on the instruction type and positioning data. For tokens containing performance count data, the performance count data may also be associated. When performing performance analysis on the software side, the associated tokens can be processed simultaneously to improve analysis efficiency and accuracy.

[0098] In a specific embodiment, the shader trace module further includes a target array register;

[0099] The target array register includes C array identification bits, where C is the number of array processors, and each array identification bit corresponds to an array processor;

[0100] For any array identification bit, if the array identification bit is a first preset value, a token is not generated according to the instruction in the array processor corresponding to the array identification bit.

[0101] Among them, since a large number of tokens will be generated when the rendering task is executed, resulting in excessive storage pressure on the cache module, this embodiment specifies a specific array processor through the target array register, and only the tokens generated by the rendering instructions executed in the specific array processor are sent to the cache module. In this embodiment, by default, only the first array identification bit is set to the second preset value, and the other array identification bits are all set to the first preset value.

[0102] In a specific embodiment, the GPU chip further includes a device memory, the device memory includes a cache module, and the token has a corresponding first priority according to its corresponding token type;

[0103] When at least two tokens need to be stored in the cache module at the same time point, the token with the highest first priority is stored in the cache module according to the first priorities corresponding to the tokens, and the other tokens are discarded.

[0104] When at least two tokens need to be stored in the cache module at the same time point, the token with the highest priority is selected and stored in the cache module according to a preset priority, and the other tokens are discarded.

[0105] In one embodiment, the implementer may adjust the first priority of each token according to its corresponding token type based on actual conditions, but should ensure that the first priority of each token is different according to its corresponding token type. It should be noted that for timestamp type tokens, the first priority is the highest by default and cannot be changed.

[0106] In a specific embodiment, the shader tracking module further includes a second priority register, the second priority register including B priority flags, where B is the number of token types, and each priority flag corresponds to a token type;

[0107] Accordingly, when at least two tokens need to be stored in the cache module at the same time point, the token with the highest first priority is stored in the cache module according to the first priorities corresponding to the respective tokens, and the other tokens are discarded, including:

[0108] When there are at least two tokens that need to be stored in the cache module at the same time point, the token with the highest first priority is stored in the cache module according to the first priority corresponding to each token. Among other tokens, the token corresponding to the instruction type with the priority identification bit being the second preset value is stored later, and the token corresponding to the instruction type with the priority identification bit being the first preset value is discarded.

[0109] Among them, the implementer can set the second priority register to identify the token type. When the token corresponding to the instruction type whose priority identification bit is the second preset value needs to be discarded, it is changed to delayed storage, that is, stored in the next cycle, thereby ensuring that the token that the implementer is interested in will not be discarded due to the first priority.

[0110] In a specific embodiment, when at least two tokens need to be stored in the cache module at the same time point, according to the first priorities corresponding to the respective tokens, the token with the highest first priority is stored in the cache module, and among the other tokens, the token corresponding to the instruction type with the priority identification bit being the second preset value is stored later, and the token corresponding to the instruction type with the priority identification bit being the first preset value is discarded, including:

[0111] When at least two tokens need to be stored in the cache module at the same time point, if there are tokens of the same token type, the tokens of the same token type are merged into a single token;

[0112] Then, according to the first priority corresponding to each token, the token with the highest first priority is stored in the cache module. Among other tokens, the token corresponding to the instruction type whose priority identification bit is the second preset value is delayed in storage, and the token corresponding to the instruction type whose priority identification bit is the first preset value is discarded.

[0113] Tokens of the same token type can be merged into a single token, thereby reducing the number of tokens.

[0114] In this embodiment, tokens of different token types are generated by the shader tracking module in the shader, so that the execution status of different aspects of a specific rendering task can be accurately represented by tokens of different token types, making the obtained shader tracking data more comprehensive, detailed and correlated, and thread start type tokens are formed by downsampling operations, which reduces the connection lines, improves the efficiency of token generation, and also improves the efficiency and accuracy of the software side in analyzing the GPU chip performance based on tokens to find performance bottlenecks.

[0115] This embodiment 3 provides a timestamp token generation system. Figure 3 , is a schematic diagram of a flow chart of a computer program being processed and executed in a timestamp token generation system provided in a third embodiment of the present invention. The system includes: a GPU chip, a processor, and a memory storing the computer program. The GPU chip includes a shader, and the shader includes a shader tracking module. When the computer program is executed by the processor, the following steps are implemented:

[0116] S301, after the shader tracking module generates a token, performing cycle statistics to obtain a cycle statistics value;

[0117] S302, when the shader tracing module generates a token other than a timestamp type, determining a relative timestamp of the current token based on a periodic statistical value after a previously generated token;

[0118] S303: When the periodic statistical value after the last generated token meets a first preset condition, generate a timestamp type token, where the timestamp type token includes an absolute timestamp.

[0119] The cycle may refer to the clock cycle of the GPU chip, and the cycle statistics may be used to represent the number of cycles between the current time point and the last generated token generation time point, so the cycle statistics may be regarded as a relative timestamp.

[0120] When the shader trace module generates a token of a type other than timestamp, the relative timestamp of the current token is determined based on the cycle statistics after the last generated token.

[0121] In a specific implementation, the first preset condition is that a periodic statistical value after a last generated token is greater than a preset periodic threshold.

[0122] The reason for generating a timestamp type token may be that no token is generated within a certain period of time, that is, the periodic statistical value after the last generated token is greater than a preset periodic threshold.

[0123] In a specific implementation, the bit width corresponding to the relative timestamp is 4 bits.

[0124] Since the relative timestamp only records the relative time, a lower bit width, such as 4 bits, can be used.

[0125] In a specific embodiment, when the computer program is executed by a processor, the following steps are further implemented:

[0126] S304: When a token discard operation occurs, a timestamp type token is generated.

[0127] Among them, the reason for generating a timestamp type token may be when a token discard operation occurs. The token discard operation may be due to the simultaneous generation of multiple tokens. According to the first priority, tokens that are not the highest first priority are discarded. The token discard operation may also be a token discard operation caused by the need to replace tokens in the cache module.

[0128] In a specific embodiment, when the computer program is executed by a processor, the following steps are further implemented:

[0129] S305: When the shader tracing module is turned on, a timestamp type token is generated.

[0130] Among them, the reason for generating a timestamp type token may be that it is generated when the shader tracing module is turned on to record the time when the shader tracing module is turned on. The time point when the shader tracing module is turned on may refer to the time point when the shader tracing module receives the instruction to turn on tracing.

[0131] In a specific embodiment, when the computer program is executed by a processor, the following steps are further implemented:

[0132] S306: When the shader tracing module is closed, a timestamp type token is generated.

[0133] Among them, the reason for generating a timestamp type token may be when the shader tracing module is closed to record the time when the shader tracing module is closed. The time point when the shader tracing module is closed may refer to the time point when the shader tracing module receives the instruction to close the tracing.

[0134] In a specific implementation, the timestamp-type token also includes a generation reason.

[0135] Among them, the timestamp type token includes a generation reason, and the bit width corresponding to the generation reason in the timestamp type token is G, where G is a positive integer. In this embodiment, G is 4, and each bit corresponding to the generation reason in the timestamp type token corresponds to a generation reason. When a bit corresponding to the generation reason in the timestamp type token is the first preset value, it indicates that the generation reason corresponding to the bit is effective. Normally, only one bit in each bit corresponding to the generation reason in the timestamp type token is the first preset value.

[0136] In a specific embodiment, the bit width corresponding to the absolute timestamp is 56 bits, and the absolute timestamp increases by one every time a cycle passes;

[0137] When the shader tracking module receives a reset signal or a refresh signal, resetting the absolute timestamp;

[0138] When the absolute timestamp exceeds its bit width representation range, the absolute timestamp is reset.

[0139] Among them, the absolute timestamp can be used to record the real time when the shader tracking module performs tracking, so a longer bit width is required, such as 56-bit bit width.

[0140] When the shader tracking module receives a reset signal or a refresh signal, or the absolute timestamp exceeds its bit width representation range, the absolute timestamp is reset to re-record the real time.

[0141] In this embodiment, the relative timestamp of the next token other than the timestamp type is determined based on the periodic statistical value after the token is generated, and a timestamp type token containing an absolute timestamp is generated based on preset conditions, thereby providing more detailed time information, avoiding GPU performance analysis, and improving the efficiency of performance analysis.

[0142] This fourth embodiment provides a cache system based on shader tracking data. Figure 4 , is a schematic diagram of the architecture of a cache system based on shader tracing data provided by a fourth embodiment of the present invention, the system comprising: a software side, a GPU chip, and a device memory, wherein the GPU chip comprises a shader, the shader comprises a shader tracing module, the device memory comprises a cache module, the cache module comprises a first cache submodule, a second cache submodule, and a submodule pointing register, the first cache submodule corresponds to a first flag bit of the first cache register, and the second cache submodule corresponds to a second flag bit of the second cache register;

[0143] The shader tracking module is configured to send the formed token to the first cache submodule when the register pointed to by the submodule is a first preset value;

[0144] The shader tracking module is further configured to send the formed token to the second cache submodule when the register pointed to by the submodule is a second preset value;

[0145] The first cache submodule is configured to store the token in the first cache submodule when receiving the token;

[0146] The second cache submodule is configured to store the token in the second cache submodule when receiving the token;

[0147] When the first flag bit is a second preset value, the first cache submodule generates first cache interruption information and sends it to the software side;

[0148] When the second flag bit is a second preset value, the second cache submodule generates second cache interruption information and sends it to the software side;

[0149] The software side is used to read the token from the first cache submodule after receiving the first cache interruption information;

[0150] The software side is further configured to read a token from the second cache submodule after receiving the second cache interruption information.

[0151] The submodule pointing register may be used to identify a storage location, and the storage location is one of the first cache submodule and the second cache submodule.

[0152] The first flag bit of the first cache register can be used to identify the empty or full state of the first cache submodule, and the second flag bit of the second cache register can be used to identify the empty or full state of the second cache submodule.

[0153] The first cache interruption information may be used to identify a full state of the first cache submodule, and the second cache interruption information may be used to identify a full state of the second cache submodule.

[0154] Specifically, the first cache submodule generates first cache interruption information and sends it to the driver on the software side, and the second cache submodule generates second cache interruption information and sends it to the driver on the software side.

[0155] In a specific embodiment, the cache module further includes a first control register and a second control register;

[0156] When the first control register is at a first preset value, and the first flag bit or the second flag bit is at a second preset value, the cache module stops receiving tokens.

[0157] The first control register and the second control register may be used to determine how subsequent tokens are stored after the currently stored cache submodule is full.

[0158] Specifically, when the first control register is at the first preset value, no matter which of the first cache submodule and the second cache submodule is in the full state, the cache module stops receiving tokens.

[0159] In a specific embodiment, when the first control register is at a second preset value, the second controller is at a first preset value, and the first flag bit is at a second preset value, the cache module overwrites the first cache submodule after receiving the token;

[0160] When the first control register is at the second preset value, the second controller is at the first preset value, and the second flag is at the second preset value, the cache module overwrites the second cache submodule after receiving the token.

[0161] Among them, when the first control register is the second preset value and the second controller is the first preset value, no matter which of the first cache sub-module and the second cache sub-module is the currently stored cache sub-module in the full state, it is overwritten in the currently stored cache sub-module without switching the cache sub-module.

[0162] In a specific embodiment, when the first control register is at a second preset value, the second controller is at a second preset value, and the first flag bit is at a second preset value, the submodule pointing register is set to the second preset value;

[0163] When the first control register is at the second preset value, the second controller is at the second preset value, and the second flag is at the second preset value, the submodule pointing register is set to the first preset value.

[0164] Among them, when the first control register is the second preset value and the second controller is the second preset value, no matter which of the first cache sub-module and the second cache sub-module is the currently stored cache sub-module in the full state, if the other cache sub-module is not full, the cache sub-module is switched.

[0165] In a specific embodiment, when the first control register is a second preset value, the second controller is a second preset value, and the first flag bit is a second preset value, setting the submodule pointing register to the second preset value includes:

[0166] When the first control register is at a second preset value, the second controller is at a second preset value, and the first flag bit is at a second preset value, acquiring the second flag bit;

[0167] If the second flag bit is the first preset value, setting the submodule pointing register to the second preset value;

[0168] If the second flag bit is the second preset value, then when the second flag bit is converted to the first preset value, the submodule pointing register is set to the second preset value;

[0169] When the first control register is at a second preset value, the second controller is at a second preset value, and the second flag bit is at a second preset value, setting the submodule pointing register to the first preset value includes:

[0170] When the first control register is at a second preset value, the second controller is at a second preset value, and the second flag bit is at a second preset value, acquiring the first flag bit;

[0171] If the first flag bit is a first preset value, setting the submodule pointing register to the first preset value;

[0172] If the first flag bit is the second preset value, the submodule pointing register is set to the first preset value when the first flag bit is converted to the first preset value.

[0173] Among them, when the first control register is the second preset value and the second controller is the second preset value, no matter which of the first cache sub-module and the second cache sub-module is the currently stored cache sub-module in the full state, if the other cache sub-module is also in the full state, then wait for the other cache sub-module to change to the empty state, and then immediately switch the cache sub-module.

[0174] In a specific implementation, the first preset value is 0, and the second preset value is 1.

[0175] In a specific embodiment, the software side is further configured to access the first flag bit, and when the first flag bit is a second preset value, read the token from the first cache submodule;

[0176] The software side is further used to access the second flag bit, and when the second flag bit is a second preset value, read the token from the second cache submodule.

[0177] Among them, the software side can obtain the empty and full status of the first cache sub-module and the second cache sub-module by directly accessing the first flag bit and the second flag bit, and then when the first cache sub-module or the second cache sub-module is in a full state, the cache sub-module in the full state is read without waiting for the first cache interruption information and the second cache interruption information.

[0178] In a specific embodiment, the software side is further configured to send a clear signal to the first cache register after reading the token from the first cache submodule, so as to clear the first cache register;

[0179] The software side is further configured to send a clear signal to the second cache register after reading the token from the second cache submodule, so as to clear the second cache register.

[0180] When the software side finishes reading a certain cache submodule, it sends a clear signal to the cache submodule, so that the cache submodule can receive tokens and store them again later.

[0181] In this embodiment, the cache module is divided into a first cache sub-module and a second cache sub-module, so that the software side can read the token and the shader tracking module can write the token at the same time, thereby improving the efficiency of performance analysis. Moreover, the empty and full states of the first cache sub-module and the second cache sub-module are indicated by the first flag bit of the first cache register and the second flag bit of the second cache register. When any cache sub-module is full, the software side is notified through the cache interrupt information, thereby improving the timeliness of the software side reading the token and also improving the efficiency of performance analysis.

[0182] This embodiment 5 provides an address translation system based on shader tracking data, see Figure 5 , is a schematic diagram of the architecture of an address translation system based on shader tracking data provided by a fourth embodiment of the present invention, the system comprising: a GPU chip and a device memory, wherein the GPU chip comprises a shader and an address translation unit, the shader comprises a shader tracking module, the device memory comprises a cache module, and the shader tracking module comprises a preheating unit;

[0183] The shader tracking module is used to send the virtual address corresponding to the generated token to the preheating unit;

[0184] The preheating unit is used to send the received virtual address to the address translation unit;

[0185] The address translation unit is used to translate the received virtual address into a corresponding physical address, and send the correspondence between the virtual address and the physical address to the preheating unit;

[0186] The preheating unit is further configured to store the correspondence between the received virtual address and the physical address;

[0187] The shader tracking module is further configured to send the formed token to the cache module according to the correspondence between the virtual address and the physical address stored in the preheating unit.

[0188] Among them, the address translation unit can be used to support the conversion of virtual addresses to physical addresses, and the preheating unit can be used to send the virtual addresses that need to be translated to the address translation unit in advance, and store the translation results of the address translation unit in its own storage space, so that the translation results can be directly provided when they are needed later, without having to wait for the address translation unit to translate.

[0189] In a specific implementation, sending the received virtual address to the address translation unit includes:

[0190] The received virtual addresses are sent to the address translation unit in sequence.

[0191] Among them, after receiving a virtual address, the preheating unit can send the received virtual address to the address translation unit, that is, send the received virtual address to the address translation unit in sequence, and each time the address translation unit returns a translation result, the translation result is stored in the preheating unit.

[0192] In a specific implementation, sending the received virtual address to the address translation unit includes:

[0193] The received virtual addresses are sent in batches to the address translation unit.

[0194] Among them, after receiving several virtual addresses, the preheating unit can send the received virtual addresses in batches to the address translation unit, that is, the address translation unit returns a batch of translation results, and stores the translation results of the batch in the preheating unit.

[0195] In a specific embodiment, the preheating unit includes D preheating storage pages, where D is a positive integer;

[0196] The storing of the correspondence between the received virtual address and the physical address includes:

[0197] The correspondence between the received virtual address and the physical address is stored in the corresponding preheating storage page.

[0198] The preheating storage page may be used to store the correspondence between the virtual address and the physical address.

[0199] In a specific embodiment, the cache module includes E cache areas, and the address translation module includes F translation storage pages;

[0200] D=min(E,F), where min() is the minimum value function.

[0201] The number of preheating storage pages may be set to the minimum value between the number of cache areas in the cache module and the number of translation storage pages in the address translation module to avoid wasting storage space.

[0202] In a specific embodiment, the shader further includes A submodules, where A is an integer greater than zero;

[0203] The shader tracing module is also used to obtain corresponding shader tracing data from each of the A sub-modules.

[0204] Among them, for any sub-module, the sub-module includes several target interfaces, each target interface corresponds to shader tracing data of different tracing data types, all target interfaces are connected to the shader tracing module, and the corresponding shader tracing data are obtained from A sub-modules respectively. It can mean that for any sub-module, the shader tracing data of the corresponding tracing data type is obtained from each target interface included in the sub-module.

[0205] In a specific embodiment, the shader tracing module is further configured to splice the acquired shader tracing data into tokens in a preset manner.

[0206] Among them, the shader tracking data corresponds to the token type and the position information in the token of the corresponding token type. The obtained shader tracking data is spliced ​​into tokens according to a preset method. It can mean that for any token type, several shader tracking data belonging to the token type are spliced ​​according to the position information of each shader tracking data in the token of the corresponding token type to obtain the token corresponding to the token type.

[0207] In a specific embodiment, the system further includes a software side;

[0208] The cache module is used to receive access from the software side to provide a token to support the software side in performing performance analysis of the GPU chip.

[0209] In this embodiment, a preheating unit is added to the shader tracing module, and the preheating unit sends the virtual address of the token to the address translation unit for address translation in advance, and the address translation result is stored in the preheating unit. When the shader tracing module sends the token to the cache module, the address translation result can be directly obtained from the preheating unit, thereby improving the storage efficiency of the token stored in the cache module, avoiding the address translation unit being in a miss state for a long time, and thus improving the efficiency of GPU performance analysis.

[0210] Although some specific embodiments of the present invention have been described in detail by way of example, it should be understood by those skilled in the art that the above examples are for illustration only and are not intended to limit the scope of the present invention. It should also be understood by those skilled in the art that various modifications may be made to the embodiments without departing from the scope and spirit of the present invention. The scope of the present invention is defined by the appended claims.

Claims

1. A GPU shader tracking and recording system, characterized in that: The system includes: a software side, a GPU chip, and a device memory, wherein the GPU chip includes a shader, the shader includes A submodules and a shader tracking module, where A is an integer greater than zero, and the device memory includes a cache module; The shader tracing module is used to obtain corresponding shader tracing data from the A sub-modules respectively; The shader tracing module is further configured to splice the acquired shader tracing data into tokens in a preset manner, wherein the shader tracing data corresponds to a token type and position information in a token of the corresponding token type, and splicing the acquired shader tracing data into tokens in a preset manner includes: For any token type, multiple shader tracking data belonging to the token type are spliced ​​according to the position information of each shader tracking data in the token of the corresponding token type to obtain a token corresponding to the token type, where the token type includes at least instruction type, instruction count type, performance count type, and timestamp type; The shader tracing module is further configured to act as a master device to obtain performance counter data of A submodules acting as slave devices, wherein the submodules include performance counters; The shader tracking module is further used to obtain a token corresponding to the performance count type based on the obtained performance count data when the rendering task is executed and the positioning data corresponding to the rendering task; The shader tracking module is further configured to obtain a token corresponding to a global startup type according to the first rendering command identifier and the first rendering subcommand identifier when a rendering task starts; The shader tracking module is further configured to, when a thread starts to execute a rendering task, downsample the first rendering command identifier and the first rendering subcommand identifier in the token corresponding to the global startup type to obtain a second rendering command identifier and a second rendering subcommand identifier, and concatenate the second rendering command identifier and the second rendering subcommand identifier with the positioning data corresponding to the thread to obtain a token corresponding to the thread startup type; The shader tracking module is further configured to send a token to the cache module; The cache module is used to receive access from the software side to provide a token to support the software side in performing performance analysis of the GPU chip.

2. The GPU shader tracking and recording system according to claim 1, wherein: For any submodule, the submodule includes several target interfaces, each target interface corresponds to shader tracing data of a different tracing data type, and all target interfaces are connected to the shader tracing module; The obtaining corresponding shader tracking data from the A sub-modules respectively includes: For any sub-module, shader tracing data of corresponding tracing data type is obtained from each target interface included in the sub-module.

3. The GPU shader tracking and recording system according to claim 1, wherein: The shader tracing module further includes a mask register, the mask register including a first mask sub-register; The first mask subregister includes B first mask bits, where B is the number of token types, and each first mask bit corresponds to a token type; For any first mask bit, if the first mask bit is a first preset value, a token of the token type corresponding to the first mask bit is not generated.

4. The GPU shader tracking and recording system according to claim 3, wherein: The mask register includes a second mask sub-register; The second mask subregister includes a plurality of second mask bits, wherein each second mask bit corresponds to an instruction type; For any second mask bit, if the second mask bit is the first preset value, a token containing the instruction type corresponding to the second mask bit is not generated.

5. The GPU shader tracking and recording system according to claim 3, wherein: The mask register includes a third mask sub-register; The third mask sub-register includes a plurality of third mask bits, wherein each third mask bit corresponds to an instruction count type; For any third mask bit, if the third mask bit is the first preset value, a token containing the instruction count type corresponding to the third mask bit is not generated.

6. The GPU shader tracking and recording system according to claim 3, wherein: The token corresponding to the performance counter type includes a high-order token and a low-order token, and the mask register includes a fourth mask sub-register; The fourth mask subregister includes a plurality of fourth mask bits, wherein each fourth mask bit corresponds to a performance counter type; For any fourth mask bit, if the fourth mask bit is the first preset value, no low-order token corresponding to the performance counter type is generated; If the fourth mask bit is the second preset value, a high-order token corresponding to the performance counter type is not generated.

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