Asymmetric double-gate control unit and device

Abstract

The invention provides an asymmetric double-gate control unit and device. The control unit comprises a first semiconductor structure, a gate oxide and a second semiconductor structure which are stacked in sequence, the first semiconductor structure and the second semiconductor structure are arranged in a mutually crossed manner and have different majority carrier types; the gate oxide is arranged at the intersection point of the first semiconductor structure and the second semiconductor structure; the first semiconductor structure and the second semiconductor structure can be respectively used as control gates, and two transistor structures are formed in the asymmetric double-gate control unit; the control unit can read and write data according to the cut-off state and the on state of the transistor structure. The device is a unique device structure, data reading and writing can be achieved through the characteristics of the transistors, synchronous miniaturization can be conducted along with the logic process, the unit size can be 4F2, each unit comprises two transistor structures, and the density of an existing device is greatly improved.

Description

Technical Field

[0001] This application relates to the field of semiconductor devices, and particularly to an asymmetric dual-gate control unit and device. Background Art

[0002] Currently, the mainstream volatile memory devices are SRAM (Static Random Access Memory) and DRAM (Dynamic Random Access Memory). The basic storage unit of the SRAM structure usually consists of multiple transistors, and commonly used ones include 4T / 6T / 8T / 9T / 10T units. The configuration method of multiple transistors results in a large size of its basic storage unit, low device density, and very limited SRAM capacity in a single chip. Moreover, the manufacturing process of SRAM is also relatively complex, with requirements for each transistor and high requirements for the performance constraints between transistors. The current mainstream of DRAM devices is the two-dimensional 1T1C structure, which differentiates 0 / 1 by the level of the capacitor and requires a refresh frequency at the microsecond level to maintain the data state. The entire device is restricted by multi-transistor control, and the unit storage density is not high.

[0003] In the data structure, L1 / L2 / L3 are used as caches, and their capacity sizes determine the operation speed of the entire chip. The memory capacity or bandwidth has restricted the high computing power requirements of current AI. However, with the continuous miniaturization of the feature size of the storage unit, planar processes and manufacturing technologies have become challenging and costly, and no obvious benefits can be seen at the 14nm - 7nm nodes. It is necessary to provide a new type of memory device that can effectively reduce the area of the storage unit and increase the storage device density.

[0004] In logical operations, the performance of logical devices is determined by the number of transistors. To meet the high computing power requirements, existing planar CMOS devices start to adopt the Finfet process at 14nm, and are further developing 2nm GAA Finfet or CFET CMOS processes to cope with the increasing demand for high computing volume. In the context where high-end equipment cannot be broken through in the short term, how to make more transistors per unit area is a way to solve the computing power problem.

[0005] Therefore, the present invention provides a new type of device structure that can effectively increase the transistor density per unit area, and this device structure can be used both for memory devices and as logical computing devices. It can also continuously stack this device according to the circuit complexity to solve the requirements for high-capacity and high-density transistors.

[0006] It should be noted that the above introduction to the technical background is only for the convenience of clearly and completely explaining the technical solution of the present application and facilitating the understanding of those skilled in the art. It cannot be considered that the above technical solutions are well-known to those skilled in the art just because these solutions are described in the background art part of the present application. Summary of the Invention

[0007] The object of the present invention is to provide an asymmetric double-gate control device structure, which can be used in the fields of logic devices and memory devices to obtain higher device density.

[0008] To solve the above problems, in a first aspect, an asymmetric double-gate control unit is provided, which includes a first semiconductor structure, a gate oxide, and a second semiconductor structure stacked in sequence; The first semiconductor structure and the second semiconductor structure are arranged crosswise, and the majority carrier types of the first semiconductor structure and the second semiconductor structure are different; The gate oxide is disposed at the intersection of the first semiconductor structure and the second semiconductor structure, and is respectively connected to the first semiconductor structure and the second semiconductor structure; The first semiconductor structure and the second semiconductor structure can respectively serve as control gates to form two transistor structures in the asymmetric double-gate control unit; The asymmetric double-gate control unit is configured to: be able to represent different data values according to the cut-off state and conduction state of the transistor structure.

[0009] The present invention realizes data operation by simultaneously forming two depletion-type transistor structures in each unit and using the on and off principles of transistors. The design of this basic unit can be synchronously scaled down with the logic process, greatly improving the storage capacity of existing static memories, achieving the effects of saving chip area, increasing capacity, further improving the operation speed, and reducing power consumption.

[0010] The asymmetric double-gate control unit is configured to: when the transistor structure is in the conduction state, it is used to represent the "1" signal, and when the transistor structure is in the cut-off state, it is used to represent the "0" signal.

[0011] The first semiconductor structure is a P-type semiconductor structure, and the second semiconductor structure is an N-type semiconductor structure; or, the first semiconductor structure is an N-type semiconductor structure, and the second semiconductor structure is a P-type semiconductor structure; the P-type semiconductor structure is a P-type low-resistance silicon material, and the N-type semiconductor structure is an N-type low-resistance silicon material. The formation process of the control unit has good compatibility with the existing logic process, the process is mature, and the manufacturing cost is low.

[0012] On the other hand, the present invention also provides an asymmetric double-gate control device, which includes an asymmetric double-gate control unit array and a peripheral circuit; The asymmetric double-gate control unit array includes a first semiconductor structure array, a gate oxide array, and a second semiconductor structure array stacked in sequence; The first semiconductor structure array includes a plurality of first semiconductor structures arranged in sequence along a first direction, and each of the first semiconductor structures extends along a second direction; The second semiconductor structure array includes a plurality of second semiconductor structures arranged in sequence along the second direction, and each of the second semiconductor structures extends along the first direction; The gate oxide array includes a plurality of gate oxides, and each of the gate oxides is correspondingly arranged at the intersection of the first semiconductor structure and the second semiconductor structure; The majority carrier types of the first semiconductor structure and the second semiconductor structure are different. Each of the gate oxides is respectively connected to the corresponding first semiconductor structure and the second semiconductor structure. Each of the first semiconductor structures and each of the second semiconductor structures can respectively serve as a control gate to correspondingly form a transistor structure; The cut-off state and the on state of the transistor structure are used to represent different data values.

[0013] By arraying the basic units of the first aspect, a large amount of data can be operated, and the effects of saving chip area, increasing capacity, thereby improving the operation speed and reducing power consumption can be achieved.

[0014] When the transistor structure is in the on state, it is used to represent the "1" signal. When the transistor structure is in the cut-off state, it is used to represent the "0" signal. Different data values are respectively represented by the on state and the off state of the transistor.

[0015] The first semiconductor structure is a P-type semiconductor structure, and the second semiconductor structure is an N-type semiconductor structure; or the first semiconductor structure is an N-type semiconductor structure, and the second semiconductor structure is a P-type semiconductor structure.

[0016] The N-type semiconductor structure is an N-type low-resistance silicon material; the gate oxide is stacked on the N-type semiconductor structure; the P-type semiconductor structure is a P-type low-resistance silicon material, and the P-type semiconductor structure is stacked on the N-type semiconductor structure and the gate oxide. The formation process of the device has good compatibility with the existing logic process, the process is mature, and the manufacturing cost is low.

[0017] It further includes a spacer medium, and the spacer medium is arranged between adjacent first semiconductor structures, between adjacent second semiconductor structures, and between the first semiconductor structure array and the second semiconductor structure array.

[0018] The peripheral circuit is used to operate the asymmetric double-gate control unit array; the peripheral circuit includes a word line driving circuit and a bit line driving circuit for driving any one of the transistor structures in the asymmetric double-gate control unit array to write data; the peripheral circuit further includes a reading circuit for reading the data of any one of the transistor structures.

[0019] It includes multiple layers of the asymmetric double-gate control unit arrays, and the multiple layers of the asymmetric double-gate control unit arrays are stacked in sequence along the third direction.

[0020] Compared with the prior art, the beneficial effects of the present invention mainly include the following: 1) The minimum feature unit area can reach 4F 2 , and there are also 2 transistor structures in each unit, greatly improving the device density; 2) The design of the basic unit can be miniaturized synchronously with the logic process and can also be stacked, greatly improving the storage capacity of the existing static memory. Description of the Drawings

[0021] In order to more clearly illustrate the technical solutions in the specific embodiments of the present invention, the following will briefly introduce the drawings required for the description of the embodiments. Obviously, the following described drawings are only some embodiments of the present invention. For those of ordinary skill in the art, without creative efforts, other drawings can also be obtained based on these drawings.

[0022] Figure 1 It is a schematic diagram of an asymmetric double-gate control unit structure provided by the present invention.

[0023] Figure 2 It is a schematic diagram of an asymmetric double-gate control device structure provided by the present invention.

[0024] Figure 3 It is a schematic diagram of the principle of a reading circuit provided by the present invention.

[0025] Figure 4 It is another schematic diagram of the principle of a reading circuit provided by the present invention. Detailed Embodiments

[0026] Regarding the foregoing and other technical contents, features and effects of the present invention, they will be clearly presented in the following detailed description of a preferred embodiment in conjunction with the reference drawings. The directional terms mentioned in the following embodiments, such as: up, down, left, right, front or back, etc., are only with reference to the directions of the attached drawings. Therefore, the directional terms used are for illustration and not for limiting the present invention.

[0027] The embodiments of the present application will be described in detail below with reference to the accompanying drawings. However, those of ordinary skill in the art can understand that in the embodiments of the present application, many technical details are proposed to help readers better understand the present application. However, even without these technical details and various changes and modifications based on the following embodiments, the technical solutions claimed in the present application can still be implemented.

[0028] The steps in the following embodiments do not correspond one by one to the content of the invention.

[0029] Embodiment 1 As Figure 1 shown in the schematic diagram of an asymmetric dual-gate control unit structure provided by an embodiment of the present invention.

[0030] Referring to Figure 1 , the asymmetric dual-gate control unit is a three-dimensional stacked structure, including a first semiconductor structure 1, a gate oxide 3, and a second semiconductor structure 2 stacked in sequence; in the asymmetric dual-gate control unit, the first semiconductor structure 1 and the second semiconductor structure 2 are arranged crosswise, and a gate oxide 3 is provided at the intersection of the first semiconductor structure 1 and the second semiconductor structure 2, and the gate oxide 3 is connected to the first semiconductor structure 1 and the second semiconductor structure 2 respectively.

[0031] In the asymmetric dual-gate control unit, two depletion-type transistor structures can be formed through the first semiconductor structure 1, the gate oxide 3, and the second semiconductor structure 2. Specifically, in order to form the transistor structure, the majority carrier types of the first semiconductor structure 1 and the second semiconductor structure 2 are different, that is, one is a P-type semiconductor and the other is an N-type semiconductor; and the gate oxide 3 is made of an insulating material. In this embodiment, the first semiconductor structure 1 is an N-type semiconductor structure, which is composed of N-type low-resistance silicon material formed by ion implantation process; the second semiconductor structure 2 is a P-type semiconductor structure, which is composed of P-type low-resistance silicon material formed by ion implantation process; the gate oxide 3 is made of silicon dioxide material. In other embodiments, the first semiconductor structure 1 can also be a P-type semiconductor structure, and the second semiconductor structure 2 can be an N-type semiconductor structure, and the formation method is not limited to the ion implantation process, as long as doping can be achieved to form a P / N-type semiconductor.

[0032] In this embodiment, each asymmetric dual-gate control unit contains two transistor structures, and the two transistor structures can be independently controlled. Specifically, referring to Figure 1, First, when looking from top to bottom, the second semiconductor structure 2 can serve as a control gate, the gate oxide 3 serves as an insulating layer, and the portions of the first semiconductor structure 1 on both sides of the gate oxide 3 can serve as the source and drain respectively. The portion of the first semiconductor structure 1 between the source and drain is the pre-set channel, and at this time, it is an N-channel depletion-mode transistor structure. At the same time, when looking from bottom to top, the first semiconductor structure 1 can also serve as a control gate, the gate oxide 3 serves as an insulating layer, and the portions of the second semiconductor structure 2 on both sides of the gate oxide 3 serve as the source and drain respectively. The portion of the second semiconductor structure 2 between the source and drain is the pre-set channel, and at this time, it is a P-channel depletion-mode transistor structure. Therefore, in the above structure, both the first semiconductor structure 1 and the second semiconductor structure 2 can serve as control gates to form two corresponding transistor structures.

[0033] It can be understood that in the above two transistor structures, the current flow directions are along the extension directions of the first semiconductor structure 1 and the second semiconductor structure 2 respectively, that is, the current flow directions of the two transistor structures cross each other and are different from each other, so they are called asymmetric. In the above asymmetric double-gate control unit, not only can the size of each unit be made to be 4F 2 , on this basis, there are also 2 transistor structures in each unit, and the device density is further improved; this unit structure can continue to be miniaturized along with logic devices and can also be stacked; the asymmetric double-gate control unit provided by this application can be applied to the fields of logic devices and memory devices. The following takes the application in memory devices as an example for illustration.

[0034] The above asymmetric double-gate control unit can be used as the basic storage unit of a memory device, that is, an asymmetric double-gate control storage unit. It should be understood that in a depletion-mode transistor structure, the source and drain can be conducting without a gate voltage, and by applying a corresponding gate voltage (for example, applying a negative gate voltage to an N-channel depletion-mode transistor or a positive gate voltage to a P-channel depletion-mode transistor), the channel can be closed to make the transistor turn off. That is, each transistor structure in the above basic storage unit can be programmed into different states or levels, that is, whether the transistor structure in the storage unit is in the cut-off state or the conducting state is used to represent different data values respectively, so information can be stored. For example, when the transistor structure is in the conducting state, there will be a current (usually about in the range of hundreds of nA - μA level) passing through, which can be used to represent the "1" signal; when the transistor structure is in the cut-off state, no current passes through, which is used to represent the "0" signal. Since there are two independently controllable transistor structures in each of the above basic storage units, and each of them can be set to any one of the two states, that is, each transistor structure stores one bit, and each unit can store two bits.

[0035] Embodiment 2 Embodiment 2 provides an asymmetric dual-gate control device, which is further formed based on the asymmetric dual-gate control unit in Embodiment 1. As Figure 2 shown is a schematic structural diagram of an asymmetric dual-gate control device provided by an embodiment of the present invention.

[0036] Referring to Figure 2 , the asymmetric dual-gate control device includes an asymmetric dual-gate control unit array and a peripheral circuit; it should be understood that the asymmetric dual-gate control unit array is obtained by arranging the asymmetric dual-gate control units in Embodiment 1 in an array. Referring to Figure 2 , the asymmetric dual-gate control unit array is also a three-dimensional stacked structure (not shown in the figure and schematically shown in a plan view), including a first semiconductor structure array, a gate oxide array, and a second semiconductor structure array stacked in sequence. Among them, the first semiconductor structure array includes: a plurality of first semiconductor structures 1 arranged in sequence along a first direction, and each first semiconductor structure 1 extends along a second direction; the second semiconductor structure array includes: a plurality of second semiconductor structures 2 arranged in sequence along the second direction, and each second semiconductor structure 2 extends along the first direction; the gate oxide array includes: a plurality of gate oxides 3, each gate oxide 3 is correspondingly arranged at the intersection of the first semiconductor structure 1 and the second semiconductor structure 2, and each gate oxide 3 is respectively connected to the corresponding first semiconductor structure 1 and second semiconductor structure 2. It should be understood that in this embodiment, the first direction and the second direction are perpendicular to each other.

[0037] As described in Embodiment 1, in each asymmetric dual-gate control unit, two depletion-type transistor structures can be formed through the first semiconductor structure 1, the gate oxide 3, and the second semiconductor structure 2. It should be understood that in order to form a transistor, the majority carrier types of the first semiconductor structure 1 and the second semiconductor structure 2 are different, that is, one is a P-type semiconductor and the other is an N-type semiconductor correspondingly. In this embodiment, the first semiconductor structure 1 is an N-type semiconductor structure, which is composed of an N-type low-resistance silicon material formed by an ion implantation process; the second semiconductor structure 2 is a P-type semiconductor structure, which is composed of a P-type low-resistance silicon material formed by an ion implantation process. In other embodiments, the first semiconductor structure 1 can also be a P-type semiconductor structure, while the second semiconductor structure 2 is an N-type semiconductor structure, and the formation method is not limited to the ion implantation process, as long as doping can be achieved to form a P / N-type semiconductor.

[0038] In this embodiment, the first semiconductor structure array, the gate oxide array, and the second semiconductor structure array are stacked upward in sequence, that is, the first semiconductor structure array is at the bottom layer, the gate oxide array is stacked on the first semiconductor structure array, and the second semiconductor structure array is stacked on the first semiconductor structure array and the gate oxide array.

[0039] In this embodiment, an example is given where the asymmetric double-gate control device includes a layer of asymmetric double-gate control unit arrays; in other embodiments, the asymmetric double-gate control device may include multiple layers of asymmetric double-gate control unit arrays, and the multiple layers of asymmetric double-gate control unit arrays are stacked in sequence along the third direction. Among them, the third direction is perpendicular to the first direction and the second direction at the same time.

[0040] In this embodiment, the asymmetric double-gate control device is also provided with a spacer medium for leakage isolation. The spacer medium uses an insulating medium, such as silicon oxide or silicon nitride, etc.; taking silicon oxide as an example, generally, it can be formed by thermal oxidation or atomic layer deposition process or plasma-enhanced chemical vapor deposition process, and the specific selection can be adjusted according to the process node. It can be understood that insulating media are provided for leakage isolation between adjacent first semiconductor structures 1, between adjacent second semiconductor structures 2, and between the first semiconductor structure array and the second semiconductor structure array.

[0041] As described in Embodiment 1, the asymmetric double-gate control unit can be applied to the fields of logic devices and memory devices, and then the corresponding asymmetric double-gate control device formed can also be applied to the fields of logic devices and memory devices. The following takes the application of a memory device as an example for illustration.

[0042] Taking each asymmetric double-gate control unit as a basic memory unit of a memory device, the above-mentioned asymmetric double-gate control device is a memory device, which can be called an asymmetric double-gate memory device. Each basic memory unit in the above-mentioned asymmetric double-gate control unit array simultaneously has two independently controllable transistor structures. Each of the two transistor structures can be programmed into different states or levels, that is, by whether each transistor structure is in the cut-off state or the on-state, it is respectively used to represent different data values for information storage. For example, when the transistor structure is in the on-state, there will be a current (usually about in the range of hundreds of nA - μA level) passing through, which can be used to represent the "1" signal; when the transistor structure is in the cut-off state, no current passes through, which is used to represent the "0" signal. Since there are two independently controllable transistor structures in each of the above basic memory units, each of them can be set to any one of the two states, that is, each transistor structure stores one bit, and each unit can store two bits. In the above-mentioned asymmetric double-gate memory device, by keeping the write data state by continuous power supply, long-term data storage can be realized.

[0043] To operate the transistor structures in each cell of the above-mentioned asymmetric double-gate control unit array, certain peripheral circuits need to be set up. For example, to access any one of the asymmetric double-gate control units, a word line driver circuit 50 and a bit line driver circuit 40 can be set up. The target cell can be accessed by selectively activating the word line and bit line corresponding to the cell. That is, through the word line driver circuit 50 and the bit line driver circuit 40, the corresponding first semiconductor structure 1 and second semiconductor structure 2 can be activated, and then the transistor structure formed by the first semiconductor structure 1, the second semiconductor structure 2, and the gate oxide at their intersection can be operated (such as data writing).

[0044] Similarly, in order to read the stored information, a readout circuit is also set up to read the data of the transistor structure in any one of the storage cells. For a selected asymmetric double-gate control unit, it can be regarded as an N-channel depletion-mode transistor structure and a P-channel depletion-mode transistor structure.

[0045] Taking the N-channel depletion-mode transistor structure as an example, refer to Figure 3 As shown in the principle of a readout circuit, the second semiconductor structure 2 (P-type low-resistance silicon) is the control gate, and the two sides of the first semiconductor structure 1 (N-type low-resistance silicon) are the source and drain electrodes. A current channel (i.e., in the word line direction) will be formed between the source and drain electrodes. When the channel is conducting, a current (usually about in the range of hundreds of nA - μA) will pass through, which is considered a successful write of "1". This "1" signal can be detected by the readout circuit. When an operating voltage is applied to the control gate to pinch off the channel to write "0" to the selected cell, no current will pass through at this time, and this "0" signal can be detected by the readout circuit. Refer to Figure 3 As shown in, for this N-channel depletion-mode transistor structure, its current flows out in the word line (WL) direction, and this current is denoted as I-WL, while Iref refers to the reference current or intermediate-level current according to the process and device characteristics. When the N-channel depletion-mode transistor structure is conducting, I-WL is a current in the range of about hundreds of nA to μA; when the N-channel depletion-mode transistor structure is not conducting, almost no current or only a leakage current of dozens of nA passes through, that is, I-WL is 0 or only at the level of dozens of nA. Thus, when the I-WL input to the differential amplifier circuit is in the range of hundreds of nA - μA (i.e., when conducting), when I-WL is compared with Iref, Iref will be pulled up, and finally a high level is read out; when the I-WL input to the differential amplifier circuit is 0 or only at the level of dozens of nA (i.e., when not conducting), when I-WL and Iref are compared, the Iref level is pulled down, and finally a low level is read out.

[0046] Taking the P-channel depletion-mode transistor structure as an example, refer to Figure 4As shown in the principle of a readout circuit, the first semiconductor structure 1 (N-type low-resistance silicon) serves as the control gate, and the source and drain electrodes are located on both sides of the second semiconductor structure 2 (P-type low-resistance silicon). A current channel (i.e., in the bit line direction) will be formed between the source and drain electrodes. When the channel is conducting, a current (usually on the order of hundreds of nA to μA) will pass through, which is considered a successful write of "1". This "1" signal can be detected by the readout circuit. When an operating voltage is applied to the control gate to pinch off the channel to write "0" to the selected cell, no current will pass through at this time, and this "0" signal can be detected by the readout circuit. Reference Figure 4 As shown in [reference], for this P-channel depletion-mode transistor structure, its current flows out in the direction of the bit line (BL), and this current is denoted as I-BL, while Iref refers to the reference current or intermediate-level current according to the process and device characteristics. When the P-channel depletion-mode transistor structure is conducting, I-BL is a current on the order of hundreds of nA to μA; when the P-channel depletion-mode transistor structure is not conducting, almost no current or only a leakage current of dozens of nA passes through, that is, I-BL is 0 or only on the order of dozens of nA. Thus, when I-BL input to the differential amplifier circuit is on the order of hundreds of nA to μA (i.e., when conducting), when I-BL is compared with Iref, Iref will be pulled up, and finally a high level is read out; when I-BL input to the differential amplifier circuit is 0 or only on the order of dozens of nA (i.e., when not conducting), when I-BL and Iref are compared, the Iref level is pulled down, and finally a low level is read out. It can be understood that in the same asymmetric double-gate control unit, the channels of the N-channel depletion-mode transistor structure and the P-channel depletion-mode transistor structure are perpendicular to each other, and thus their current directions are also perpendicular to each other.

[0047] In this embodiment, after the NMOS switch in the readout circuit is turned on, the high / low level is read out through the differential amplifier circuit. In this embodiment, the NMOS switch is selected because, on the same logic process platform and for devices of the same size, the driving ability of NMOS is greater.

[0048] The asymmetric double-gate control unit and device provided by this application can achieve a higher device density, and its minimum feature unit area is 2F 2F = 4F 2 , and two transistor structures are included in one unit. F refers to the half pitch of the feature unit size; and this device architecture can be scaled down synchronously with the logic process, and can be used for embedded storage or as an independent large storage array, with a wide range of application scenarios.

[0049] Some commonly used English nouns or letters adopted in this invention for the convenience of clear description are only for exemplary reference rather than restrictive interpretation or specific usage, and the protection scope of this invention should not be limited by their possible Chinese translations or specific letters.

[0050] It should also be noted that in this article, relational terms such as "first" and "second" are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations.

Claims

1. An asymmetric double-gate control unit, characterized in that, comprising a first semiconductor structure, a gate oxide, and a second semiconductor structure stacked in sequence; the first semiconductor structure and the second semiconductor structure are arranged to cross each other, and the majority carrier types of the first semiconductor structure and the second semiconductor structure are different; the gate oxide is disposed at the intersection of the first semiconductor structure and the second semiconductor structure, and is respectively connected to the first semiconductor structure and the second semiconductor structure; the first semiconductor structure and the second semiconductor structure can respectively serve as control gates to form two transistor structures in the asymmetric double-gate control unit; the asymmetric double-gate control unit is configured to: be capable of representing different data values according to the cut-off state and the on-state of the transistor structure.

2. The asymmetric double-gate control unit according to claim 1, wherein the asymmetric double-gate control unit is configured to: when the transistor structure is in the on-state, represent a "1" signal, and when the transistor structure is in the cut-off state, represent a "0" signal.

3. An asymmetric double-gate control unit according to claim 1, characterized in that the first semiconductor structure is a P-type semiconductor structure, and the second semiconductor structure is an N-type semiconductor structure; alternatively, the first semiconductor structure is an N-type semiconductor structure, and the second semiconductor structure is a P-type semiconductor structure; the P-type semiconductor structure is a P-type low-resistance silicon material, and the N-type semiconductor structure is an N-type low-resistance silicon material.

4. An asymmetric double-gate control device, characterized in that comprising an asymmetric double-gate control unit array and a peripheral circuit; the asymmetric double-gate control unit array comprises a first semiconductor structure array, a gate oxide array, and a second semiconductor structure array stacked in sequence; the first semiconductor structure array comprises: a plurality of first semiconductor structures arranged in sequence along a first direction, and each of the first semiconductor structures extends along a second direction; the second semiconductor structure array comprises: a plurality of second semiconductor structures arranged in sequence along the second direction, and each of the second semiconductor structures extends along the first direction; the gate oxide array comprises: a plurality of gate oxides, and each of the gate oxides is correspondingly disposed at the intersection of the first semiconductor structure and the second semiconductor structure; the majority carrier types of the first semiconductor structure and the second semiconductor structure are different, each of the gate oxides is respectively connected to the corresponding first semiconductor structure and the second semiconductor structure, and each of the first semiconductor structures and each of the second semiconductor structures can respectively serve as a control gate to correspondingly form a transistor structure; the cut-off state and the on-state of the transistor structure are used to represent different data values.

5. An asymmetric double-gate control device according to claim 4, characterized in that when the transistor structure is in the on-state, it represents a "1" signal, and when the transistor structure is in the cut-off state, it represents a "0" signal.

6. An asymmetric double-gate control device according to claim 4, characterized in that, the first semiconductor structure is a P-type semiconductor structure, and the second semiconductor structure is an N-type semiconductor structure; alternatively, the first semiconductor structure is an N-type semiconductor structure, and the second semiconductor structure is a P-type semiconductor structure.

7. An asymmetric double-gate control device according to claim 6, wherein the N-type semiconductor structure is an N-type low-resistance silicon material; the gate oxide is stacked on the N-type semiconductor structure; the P-type semiconductor structure is a P-type low-resistance silicon material, and the P-type semiconductor structure is stacked on the N-type semiconductor structure and the gate oxide.

8. An asymmetric double-gate control device according to claim 4, characterized in that, It further includes a spacer medium, and the spacer medium is disposed between adjacent ones of the first semiconductor structures, between adjacent ones of the second semiconductor structures, and between the first semiconductor structure array and the second semiconductor structure array.

9. An asymmetric double-gate control device according to claim 4, characterized in that The peripheral circuit is configured to operate on the asymmetric double-gate control unit array; The peripheral circuit includes a word line driving circuit and a bit line driving circuit, and is configured to drive any one of the transistor structures in the asymmetric double-gate control unit array to perform data writing; The peripheral circuit further includes a readout circuit, and is configured to read out the data of any one of the transistor structures.

10. An asymmetric double-gate control device according to claim 4, characterized in that, It includes multiple layers of the asymmetric double-gate control unit arrays, and the multiple layers of the asymmetric double-gate control unit arrays are stacked in sequence along a third direction.

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