Chip read-write capability test equipment, method, readable storage medium and system

Abstract

The invention relates to chip read-write capability testing equipment, a chip read-write capability testing method, a readable storage medium and a chip read-write capability testing system. The chip read-write capability test equipment is electrically connected with a chip to be tested, and the test equipment generates and sends a control signal, an address signal and sample data to the chip to be tested based on a received control instruction; the control signal comprises a clock selection signal; when the clock selection signal is a first selection signal, acquiring an on-chip clock signal of the to-be-tested chip, sending a control signal, an address signal and sample data to the to-be-tested chip, and receiving read data; the control signal comprises a clock signal generated based on an on-chip clock signal; when the clock selection signal is a second selection signal, a control signal, an address signal and sample data are sent to the chip to be tested, and read data are received; the control signal comprises a clock signal generated based on the working frequency of the to-be-tested chip; and determining a test result of the to-be-tested chip through the sample data and the read data. By adopting the equipment, the cost can be reduced, and the compatibility is improved.

Description

Technical Field

[0001] This application relates to the technical field of chip testing, and particularly to a chip read-write ability testing device, method, readable storage medium, and system. Background Art

[0002] With the development of the chip design and manufacturing fields, there are now different types of chips, such as microprocessors, memories, FPGAs, etc. These chips often have different electrical characteristics and communication protocols. However, due to the increase in the types of chips, for the testing of the chip read-write ability, corresponding testing devices need to be configured according to different chip types, resulting in poor compatibility and high costs.

[0003] The operating frequency of SRAM memory chips is generally in the range of 1 MHz to 2 MHz. If there is an on-chip clock source inside, the generated clock signal will also be in the range of 1 MHz to 2 MHz. This requires the corresponding chip testing device to be able to provide a clock signal of 1 MHz to 2 MHz and achieve good real-time control within this clock frequency range. Therefore, for this type of chip that has specific requirements for clock signals and real-time control during the testing process, the testing device needs to provide high-precision, stable, and flexible clock signals and real-time control capabilities to ensure the accuracy and effectiveness of the testing. Summary of the Invention

[0004] Based on this, in view of the above technical problems, it is necessary to provide a chip read-write ability testing device, method, readable storage medium, and system that can ensure the accuracy and effectiveness of the testing.

[0005] In a first aspect, this application provides a chip read-write ability testing device. The chip read-write ability testing device is electrically connected to a chip under test. The testing device is configured to generate and send a control signal, an address signal, and sample data to the chip under test based on a received control instruction. The control instruction includes a clock selection signal. When the clock selection signal is a first selection signal, obtain the on-chip clock signal of the chip under test, and send the control signal, address signal, sample data to the chip under test, and receive the read data. Wherein, the control signal includes a clock signal, and the clock signal is generated based on the on-chip clock signal. When the clock selection signal is a second selection signal, send the control signal, address signal, sample data to the chip under test, and receive the read data. Wherein, the control signal includes a clock signal, and the clock signal is generated based on the operating frequency of the chip under test. The chip read-write ability testing device is further configured to determine the test result of the chip under test through the sample data and the read data.

[0006] In some of these embodiments, the control instruction includes a test strategy, and the test strategy includes multiple ways to verify the read and write performance of the chip under test; the test device is further configured to determine sample data based on the test strategy.

[0007] In some of these embodiments, the chip read and write ability test device is further configured to: Determine the test result of the chip under test based on the matching situation between the sample data and the read data.

[0008] In some of these embodiments, the connection paths between the chip read and write ability test device and the chip under test include a first path, a second path, and a third path, and the chip read and write ability test device is further configured to: Transmit an address signal through the first path; the address signal includes read and write addresses; Transmit a data signal through the second path, and the data signal includes sample data or read data; Transmit a control signal through the third path, and the control signal includes read and write control signals and a clock signal.

[0009] In some of these embodiments, the control instruction includes configuration information and test instructions; the chip read and write ability test device includes a main control device and a test execution device, and the main control device is communicatively connected to the test execution device; The main control device is configured to: send the configuration information corresponding to the chip under test to the test execution device; send a test instruction to the test execution device; The test execution device is configured to: configure itself based on the configuration information; generate and send a control signal, an address signal, and sample data to the chip under test based on the test instruction, and receive read data; determine the test result of the chip under test through the sample data and the read data.

[0010] In some of these embodiments, the configuration information includes the bit width of the read and write path and the address range; the test execution device includes a general-purpose input / output module; The main control device is further configured to send an initialization instruction to the test execution device; The test execution device is configured to initialize the general-purpose input / output module based on the initialization instruction; configure the initialized general-purpose input / output module based on the bit width of the read and write path and the address range.

[0011] In some of these embodiments, the configuration information further includes the power supply voltage of the chip under test; the test execution device further includes a power supply module; The main control device is further configured to send an initialization instruction to the test execution device; The test execution device is used to initialize the power supply module based on the initialization instruction; the power supply module is used to power on the chip under test based on the power supply voltage of the chip under test.

[0012] In some embodiments, the configuration information includes a clock selection signal; the test execution device further includes a timer; The main control device is further used to send an initialization instruction to the test execution device; The test execution device is used to initialize the timer based on the initialization instruction; When the clock selection signal is the first selection signal, the timer is used to synchronize the on-chip clock signal of the chip under test; when the clock selection signal is the second selection signal, the timer is used to generate a clock signal based on the operating frequency of the chip under test and send the clock signal to the chip under test.

[0013] In some embodiments, the main control device is further used to send a query instruction to the test execution device; The test execution device is further used to send the test result of the chip under test and / or the test result that does not meet the preset conditions to the main control device based on the query instruction.

[0014] In some embodiments, the main control device is further used to send a standby instruction to the test execution device; The test execution device is used to disconnect the connection with the chip under test and power off the chip under test based on the standby instruction.

[0015] In a second aspect, the present application provides a method for testing the read and write capabilities of a chip, which is applied to a chip read and write capability testing device. The method for testing the read and write capabilities of the chip includes: Generating and sending a control signal, an address signal, and sample data to the chip under test based on the received control instruction; the control instruction includes a clock selection signal; When the clock selection signal is the first selection signal, obtaining the on-chip clock signal of the chip under test and sending a control signal, an address signal, sample data, and receiving read data to the chip under test; wherein, the control signal includes a clock signal, and the clock signal is generated based on the on-chip clock signal; When the clock selection signal is the second selection signal, sending a control signal, an address signal, sample data, and receiving read data to the chip under test; wherein, the control signal includes a clock signal, and the clock signal is generated based on the operating frequency of the chip under test; Determining the test result of the chip under test through the sample data and the read data.

[0016] In a third aspect, the present application provides a computer-readable storage medium, on which a computer program is stored. When the computer program is executed by a processor, the chip read-write ability test method described in the second aspect is implemented.

[0017] In a fourth aspect, the present application provides a chip read-write ability test system, including a chip to be tested and the chip read-write ability test device described in the first aspect; The chip to be tested uses a storage chip; the storage chip includes a clock selector, a configuration selector, an on-chip clock source, and a storage module; where: The clock selector is configured to determine the working clock signal of the storage chip from the clock signal input from the chip read-write ability test device and the on-chip clock signal generated by the on-chip clock source based on the control signal received from the chip read-write ability test device; The configuration selector is configured to set the on-chip clock source and / or the storage module based on the control signal received from the chip read-write ability test device; The on-chip clock source is configured to generate at least one on-chip clock signal based on the setting of the configuration selector; The storage module is configured to write the sample data and / or read data based on the control signal, address signal, sample data, and working clock signal received from the chip read-write ability test device.

[0018] The above chip read / write ability testing device, chip read / write ability testing method, computer-readable storage medium, and chip read / write ability testing system obtain the on-chip clock signal of the chip to be tested when the clock selection signal is the first selection signal, and generate a clock signal based on the on-chip clock signal. Generally, the clock signal is synchronized with the on-chip clock signal. When the clock selection signal is the second selection signal, a clock signal is generated externally to the testing device, and the clock signal is generated based on the operating frequency of the chip to be tested. And based on the received control instruction, a control signal, an address signal, and the sample data are sent to the chip to be tested, or the read data is received. The testing device is further configured to determine the test result of the chip to be tested through the sample data and the read data. Thus, the on-chip clock signal of the chip to be tested or the external clock signal of the testing device can be selected, and the read / write control is performed according to the selected clock signal, overcoming the limitation of the traditional device in clock source adaptability, and enabling the read / write test of multiple chip types with high compatibility, thereby achieving the effects of reducing costs and improving compatibility. On the other hand, the above chip read / write ability testing device, chip read / write ability testing method, computer-readable storage medium, and chip read / write ability testing system have excellent test effects on the read / write performance of storage chips, can meet the requirements of such storage chips for clock signals within their operating frequency range, and can achieve good real-time control within this clock frequency range. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] Figure 1 FIG. is a schematic connection diagram of a chip read / write ability testing device and a chip to be tested in an embodiment; Figure 2 FIG. is a schematic connection diagram of a chip read / write ability testing device and a chip to be tested in another embodiment; Figure 3 FIG. is a structural block diagram of a chip read / write ability testing device in an embodiment; Figure 4 FIG. is a schematic connection diagram of a chip read / write ability testing device and a chip to be tested in another embodiment; Figure 5 FIG. is a structural block diagram of a storage chip in an embodiment; Figure 6 FIG. is a structural block diagram of a storage chip in another embodiment; Figure 7 FIG. is a schematic structural diagram of a clock adjuster provided by an embodiment of the present application; Figure 8 FIG. is a circuit diagram of a current source component provided by an embodiment of the present application; Figure 9 FIG. is a schematic diagram of a ring oscillator provided by an embodiment of the present application; Figure 10It is a schematic circuit diagram of multiple on-chip clock generators provided by an embodiment of the present application; Figure 11 It is a schematic overall structure diagram of an on-chip clock signal generation circuit provided by an embodiment of the present application. Detailed implementation manners

[0020] In order to make the objectives, technical solutions and advantages of the present application more clearly understood, the present application will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.

[0021] All other embodiments obtained by those of ordinary skill in the art based on the embodiments provided by the present application without creative efforts belong to the scope of protection of the present application. In addition, it can also be understood that although the efforts made in such a development process may be complex and lengthy, for those of ordinary skill in the art related to the content disclosed in the present application, some design, manufacturing or production changes made on the basis of the technical content disclosed in the present application are only conventional technical means and should not be understood as insufficient disclosure of the content of the present application.

[0022] Referring to "embodiments" in the present application means that specific features, structures or characteristics described in connection with the embodiments can be included in at least one embodiment of the present application. The phrase appears in various places in the specification and does not necessarily refer to the same embodiment, nor is it an independent or alternative embodiment mutually exclusive with other embodiments. Those of ordinary skill in the art understand explicitly and implicitly that the embodiments described in the present application can be combined with other embodiments without conflict.

[0023] Unless otherwise defined, the technical terms or scientific terms involved in this application shall have the ordinary meanings understood by those with ordinary skills in the technical field to which this application belongs. The words such as "a", "an", "one kind", "the" and the like involved in this application do not indicate a limitation in quantity and may represent singular or plural. The terms "include", "comprise", "have" and any variations thereof involved in this application are intended to cover non-exclusive inclusion; for example, a process, method, system, product or device that includes a series of steps or modules (units) is not limited to the listed steps or units, but may further include steps or units not listed, or may further include other steps or units inherent to these processes, methods, products or devices. The similar words such as "connect", "be connected", "couple" and the like involved in this application are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. The "plurality" involved in this application means greater than or equal to two. "And / or" describes the association relationship of associated objects and indicates that three relationships may exist. For example, "A and / or B" may represent: A exists alone, A and B exist simultaneously, and B exists alone. The terms "first", "second", "third" and the like involved in this application are only used to distinguish similar objects and do not represent a specific order for the objects.

[0024] Embodiment 1 As Figure 1 shown, a chip read / write ability test device is provided. The chip read / write ability test device is electrically connected to a chip to be tested. The test device is configured to generate and send a control signal, an address signal and sample data to the chip to be tested based on a received control instruction. The control instruction includes a clock selection signal. When the clock selection signal is a first selection signal, an on-chip clock signal of the chip to be tested is obtained, and a control signal, an address signal, sample data are sent to the chip to be tested, and read data is received. Wherein, the control signal includes a clock signal, and the clock signal is generated based on the on-chip clock signal. When the clock selection signal is a second selection signal, a control signal, an address signal, sample data are sent to the chip to be tested, and read data is received. Wherein, the control signal includes a clock signal, and the clock signal is generated based on the operating frequency of the chip to be tested. The chip read / write ability test device is further configured to determine a test result of the chip to be tested through the sample data and the read data.

[0025] Among them, the control instruction can be a control instruction sent by a user or a host computer, which is used to control the chip read / write ability test device to generate or synchronize a clock signal, and further perform a read / write ability test on the chip to be tested.

[0026] Further, the control instruction includes a clock selection signal, which can be a first selection signal or a second selection signal. Among them, the first selection signal is used to select the on-chip clock signal on the chip under test, and the read-write ability test is performed through the on-chip clock signal; the second selection signal is used to select the external clock signal generated by the test device, and the read-write ability test is performed through the external clock signal.

[0027] When the clock selection signal is the first selection signal, after obtaining the on-chip clock signal on the chip under test, a synchronous clock signal is generated based on the on-chip clock signal.

[0028] When the clock selection signal is the second selection signal, the external clock signal generated by the test device is sent, and the external clock signal needs to be generated based on the operating frequency of the chip under test to conform to the operating frequency of the chip under test to ensure the accuracy and effectiveness of the test.

[0029] Further, according to the control instruction, a control signal, an address signal, and sample data can be generated. The control signal can include a read-write control signal and a clock signal. The read-write control signal can be used to control whether the current operation is a write operation or a read operation. The address signal can be used to control the address of the write or read. The sample data can be the write data corresponding to the write operation. The clock signal is very important for the read-write test of the chip under test. Especially in chips such as SRAM memory chips, since the SRAM circuit is a synchronous clock circuit and the start of the read-write operation is triggered by a specific clock edge, the actions of the chip read-write ability test device need to be driven and triggered by the same clock.

[0030] Further, the content of the test of the chip read-write ability can include, but is not limited to, write speed test, read speed test, accuracy test, etc. Among them, the accuracy test can be determined by comparing the received read data with the sent sample data, and then it can be determined whether the read-write performance of the chip meets the expectation.

[0031] A chip read-write ability testing device provided in this embodiment obtains the on-chip clock signal of the chip under test when the clock selection signal is the first selection signal, and sends a control signal, an address signal, sample data to the chip under test, and receives the read data; wherein, the control signal includes a clock signal, and the clock signal is generated based on the on-chip clock signal; when the clock selection signal is the second selection signal, a control signal, an address signal, sample data are sent to the chip under test, and the read data is received; wherein, the control signal includes a clock signal, and the clock signal is generated based on the operating frequency of the chip under test; the testing device is further configured to determine the test result of the chip under test through the sample data and the read data, so as to be able to select the on-chip clock signal of the chip under test or the external clock signal of the testing device, and perform clock control for the read-write test according to the selected clock signal, overcoming the limitations of traditional devices in clock signals, being able to realize the read-write tests of multiple chip types with high compatibility, thereby being able to achieve the effects of reducing costs and improving compatibility; at the same time, it can also meet some chips under test with requirements for the operating frequency range, and can achieve good real-time control within this clock frequency range.

[0032] In some of these embodiments, the control instruction includes a test strategy, and the test strategy includes multiple ways for verifying the read-write performance of the chip under test; the testing device is further configured to determine sample data based on the test strategy.

[0033] Among them, the test strategy includes preset test methods and steps, and can include multiple ways for verifying the read-write performance of the chip under test. Exemplarily, the ways for verifying the chip under test can be one or more of single read-write test, continuous read-write test, random address access test, extreme condition test, error injection test, etc., and can also include other verification ways, which are not limited in this embodiment.

[0034] Determining the sample data based on the test strategy can be to generate targeted sample data according to the verification ways in the test strategy. Exemplarily, when a random address access test is to be performed, it can include a series of randomly generated addresses and corresponding write data.

[0035] A chip read-write ability testing device provided in this embodiment can provide more comprehensive and in-depth test services for diverse test requirements by determining sample data based on the test strategy, and can achieve the effects of improving the quality and efficiency of the test.

[0036] In some of these embodiments, the testing device is further configured to: Determine the test result of the chip under test based on the matching situation between the sample data and the read data.

[0037] Among them, based on the matching situation between the sample data and the read data, the test result of the chip to be tested is determined. It can be to compare the sample data and the read data, so as to verify whether the data transmission in the read and write operations of the chip to be tested is correct, and thus evaluate its function and performance.

[0038] Furthermore, if the sample data and the read data are consistent, it is a complete match. The threshold for the proportion of consistent data can also be set, so as to be divided into partial match and complete non-match, and then a more detailed test result can be obtained, which helps to discover potential problems.

[0039] A chip read-write ability test device provided in this embodiment ensures the accuracy of the test result through bit-by-bit comparison of the sample data and the read data, and improves the efficiency of fault diagnosis through automated data comparison and error recording, so as to achieve the effect of improving the quality and efficiency of the test.

[0040] In some embodiments, as Figure 2 shown, the connection path between the test device and the chip to be tested includes a first path 101, a second path 102, and a third path 103 connected. The test device is further configured to: Transmit an address signal through the first path 101; the address signal includes read-write addresses, that is, the addresses for writing / reading data; Transmit a data signal through the second path 102, and the data signal includes sample data or read data, that is, the data to be written / read; Transmit a control signal through the third path 103, and the control signal includes: at least one read-write control signal for controlling whether the current operation is a write or a read, and at least one clock signal.

[0041] Among them, the first path 101 can be called an address channel, the second path 102 can be called a data channel, and the third path 103 can be called a control channel. The first path 101 is used to send an address signal, and the read-write addresses included in the address signal can be the addresses for read operations or the addresses for write operations. Among them, the address for the write operation is the address corresponding to the sample data to be written, and the address for the read operation is the address corresponding to the received read data.

[0042] Sending the address signal through the first path 101 can achieve independent transmission of the address signal and avoid interference from other signals. Sending the data signal through the second path 102, especially in the case of high-speed transmission or large data volume, can ensure the integrity and reliability of data transmission. The third path 103, that is, the control path, sends control signals, including at least read-write control signals and clock signals, which can ensure the timeliness and accuracy of control commands, so that the test device can precisely control the read and write operations of the chip to be tested.

[0043] A chip read-write ability testing device provided in this embodiment can complete the read-write ability testing of chips more efficiently and accurately by setting a first path, a second path, and a third path, meeting the testing requirements of different types of chips, and achieving the effects of improving testing quality and compatibility.

[0044] In some of the embodiments, the control instruction includes configuration information and a test instruction; as Figure 3 shown, the chip read-write ability testing device includes a main control device 11 and a test execution device 12, and the main control device 11 is communicatively connected to the test execution device 12; the main control device 11 is configured to send the configuration information corresponding to the chip under test to the test execution device 12; and send a test instruction to the test execution device 12; the test execution device 12 is configured to configure itself based on the configuration information; generate and send a control signal, an address signal, and sample data to the chip under test based on the test instruction, and receive read data; and determine the test result of the chip under test through the sample data and the read data.

[0045] Among them, the chip read-write ability testing device can be divided into a main control device 11 and a test execution device 12. Among them, the main control device 11 sends the configuration information in the control instruction to the test execution device 12 according to the configuration information, so that the test execution device 12 configures itself. Further, the configuration information may include one or more of a signal path bit width, an address range, a power supply voltage, a clock selection signal, etc.

[0046] The configured test execution device 12 generates a control signal, an address signal, and sample data according to the test instruction, and receives read data. The test result of the chip under test is determined through the sample data and the read data.

[0047] After obtaining the test result, the test execution device 12 can also feedback the test result to the main control device 11, and the main control device 11 can generate a detailed test report based on the test result and provide it to the user in a manner of user interface or file output.

[0048] A chip read-write ability testing device provided in this embodiment can flexibly configure and expand the test system through the separated design of the main control device and the test execution device to adapt to different types of chips and test requirements; the real-time communication connection between the main control device and the test execution device enables the user to monitor the test progress and results in real time, and can also adjust the test parameters in a timely manner, thereby achieving the effects of improving the test quality and test efficiency.

[0049] In some of these embodiments, the configuration information includes the read / write path bit width and the address range; as Figure 3 shown, the test execution device 12 includes a general-purpose input / output module 121; The main control device 11 is further configured to send an initialization instruction to the test execution device 12; The test execution device 12 is configured to initialize the general-purpose input / output module 121 based on the initialization instruction; and configure the initialized general-purpose input / output module 121 based on the read / write path bit width and the address range.

[0050] Among them, the read / write path bit width can be the path bit width during the read / write test. Exemplarily, it can include the data path bit width and the address path bit width. The data path bit width can be the path bit width of the second path, and the address path bit width can be the path bit width of the first path. Exemplarily, the bit width can be 8 bits, 16 bits, 32 bits, etc. The address range can be the address space range of the specified chip under test.

[0051] The main control device 11 is configured to send an initialization instruction to the test execution device 12, and the initialization instruction can be used to initialize the general-purpose input / output module 121. Further, the configuration information and the initialization instruction can be sent to the test execution device 12, so that the test execution device 12 responds to the initialization instruction and configures itself based on the configuration information.

[0052] When the general-purpose input / output module 121 is initialized, it is configured according to the read / write path bit width and the address range, so as to obtain the configured general-purpose input / output module 121.

[0053] In a specific embodiment, the configuration information can include the bit width of the data path, the bit width of the address path, the address range, the power supply voltage of the chip under test, the clock source of the chip under test, the measurement strategy, etc.

[0054] The chip read / write ability test device provided in this embodiment ensures that the test execution device can correctly configure the general-purpose input / output module through the read / write path bit width and the address range in the configuration information, so as to accurately send and receive signals, improve the accuracy of the test. The initialization and configuration of the general-purpose input / output module can be adjusted according to different chips and test requirements, improving the flexibility and adaptability of the system, and thus achieving the effect of improving the test quality and compatibility.

[0055] In some of these embodiments, the configuration information further includes the power supply voltage of the chip under test; the test execution device 12 further includes a power supply module 122; The main control device 11 is further configured to send an initialization instruction to the test execution device 12; The test execution device 12 is used to initialize the power supply module 122 based on the initialization instruction; the power supply module 122 is used to power on the chip under test based on the power supply voltage of the chip under test.

[0056] Among them, the main control device 11 sends an initialization instruction to the test execution device 12; enabling the test execution device 12 to initialize the power supply module 122 can be to enable the power supply module 122 to power on the chip under test according to the configured power supply voltage.

[0057] After the power-on of the chip under test is completed, the test execution device 12 can generate control signals, address signals, and sample data according to the test instructions, and perform the transmission or interaction of control signals, address signals, and data signals.

[0058] A chip read / write ability test device provided in this embodiment ensures the safe operation of the chip under test during the test through correct power supply voltage configuration, and avoids chip damage caused by voltage mismatch; the read / write path bit width, address range, and power supply voltage of the chip under test in the configuration information ensure that the test execution device can correctly configure the general-purpose input / output module and the power supply module, so as to accurately send and receive signals, improve the accuracy of the test, and thus achieve the effect of improving the test quality and compatibility.

[0059] In some of these embodiments, during the initialization process of the test execution device 12, the initialization of the timer 123 is further included. The configuration information further includes a clock selection signal; the test execution device 12 further includes a timer 123; The main control device 11 is further used to send an initialization instruction to the test execution device 12; The test execution device 12 is used to initialize the timer 123 based on the initialization instruction; When the clock selection signal is the first selection signal, the timer 123 is used to synchronize the on-chip clock signal of the chip under test; when the clock selection signal is the second selection signal, the timer 123 is used to generate the external clock signal and output the external clock signal to the chip under test.

[0060] Among them, the clock selection signal can be the clock source designation information for the chip under test, and is used to select the on-chip clock signal or the external clock signal. The timer 123 is used to obtain the clock selection signal according to the clock source signal, and is used to synchronize the on-chip clock signal on the chip under test, or generate an external clock signal and send it to the chip under test.

[0061] It should be noted that in this embodiment, a timer is used to synchronize the on-chip clock signal or generate an external clock signal. However, in other embodiments, different designs of the test execution device 12 can also be performed based on the requirements of different application scenarios. For example, the test execution device 12 can generate an external clock signal in the following ways: using a crystal oscillator, controlling the periodic change of the voltage source through programming, configuring a corresponding waveform generator or function generator, etc. Similarly, the test execution device 12 can also use other methods to synchronize the clock signal, and specific limitations are not made in this application. In this embodiment, after sending the initialization instruction, the general-purpose input / output module 121, the timer 123, and the power supply module 122 are respectively initialized according to the initialization instruction, so that the power supply module 122 powers on the chip under test, the timer 123 generates an external clock signal or synchronizes the on-chip clock signal, and the general-purpose input / output module 121 generates a control signal, an address signal, and sample data according to the configuration.

[0062] A chip read-write ability test device provided in this embodiment ensures that the test execution device can correctly configure the timer module and generate a suitable clock signal through the clock selection signal in the configuration information, thereby improving the accuracy of the test. Through the clock selection function of the timer module, accurate clock synchronization can be achieved both when using the on-chip clock or the external clock, improving the reliability and consistency of the test, and thus achieving the effect of improving the test quality and compatibility.

[0063] In some of the embodiments, the main control device is further configured to send a query instruction to the test execution device; the test execution device is further configured to send the test result of the chip under test and / or the test result that does not meet the preset conditions to the main control device based on the query instruction.

[0064] Among them, the query instruction can be used to query the chips under test with test results that do not meet the preset conditions. The main control device can send the query instruction in real time to obtain the real-time test results of the chips under test, or can also send it after some or all of the chips under test are tested, or can also send the query instruction based on user operations. This embodiment does not make any limitations here.

[0065] Based on the query instruction, sending the test results that do not meet the preset conditions in the test results of the chip under test to the main control device can be to screen the test results in response to the query instruction to obtain a set of test results that do not meet the preset conditions and send the test results to the main control device. Further, the test results can include information such as the exception type, exception address, and exception data to help the user quickly locate and solve the fault. Exemplarily, the exception type can include types such as data mismatch and read / write timeout.

[0066] A chip read-write ability testing device provided by this embodiment enables users to obtain and analyze test results more efficiently through a query instruction and a feedback mechanism for specific test results, especially those that do not meet the preset conditions, which helps to quickly locate and solve problems. At the same time, only sending the test results that do not meet the preset conditions reduces the data transmission volume, improves the response speed and efficiency of the system, and thus can achieve the effect of improving the test efficiency.

[0067] In some of the embodiments, the main control device is further configured to send a standby instruction to the test execution device; the test execution device is configured to, based on the standby instruction, close the connection with the chip under test and power down the chip under test.

[0068] Among them, the standby instruction is used to control the test execution device to be in a standby state. After the test execution device enters the standby state, when waiting to receive an initialization instruction again, it can power on the chip under test and configure the general-purpose input / output module and the timer.

[0069] A chip read-write ability testing device provided by this embodiment can prevent accidental current flow or signal interference in a non-test state by closing the connection with the chip under test and powering it down, protecting the safety of the chip under test and the testing device; safely closing the connection and powering down can also reduce the wear of the device and extend the service life of the testing device and the chip under test, achieving the effect of reducing the device maintenance cost.

[0070] To more clearly elaborate on the technical solution of this application, this application also provides a detailed embodiment.

[0071] In one embodiment, a chip read-write ability testing device is provided for performing read-write performance testing on an SRAM memory chip, as Figure 4 shown, including a main control device and a test execution device. Among them, the chip under test is a chip with SRAM memory cells, and its external interface can be divided into three groups: a data path, that is, the data written / read; an address path, that is, the address of the data written / read; and a control path.

[0072] In the control path, it at least includes: a read-write control signal for controlling whether the current operation is a write or a read; at least one clock signal, which can be generated inside the chip under test and needs to output this clock signal outside the chip, or can be input from the outside.

[0073] The test execution device is used for: (1) Generation or synchronization of the clock, that is: when the clock of the chip under test is input from the outside, generating the required clock; when the clock is generated inside the chip under test, synchronizing this clock.

[0074] (2) According to the clock signal, within the corresponding time window, output or read the signals of the required control, address, and data path.

[0075] (3) On the premise of not affecting the output and reading of the control, address, and data path signals, complete the real-time analysis of the read data, judge whether the data meets the expected results, and save the addresses and data that do not meet the expected results.

[0076] (4) On the premise of not affecting the output and reading of the control, address, and data path signals, respond to the requests from the master control device through short-distance communication cables and protocols, including: (a) requests to adjust the measurement strategy and (b) requests to query the addresses and data that do not meet the expected results. After the addresses and data that do not meet the expected results are fed back to the master control device, in order to reduce the storage space occupied by the test execution device, the already fed-back results can be discarded.

[0077] Among them, the generation of the external clock signal can be achieved by means such as using a crystal oscillator, programming and controlling the periodic change of the voltage source of the test execution device, configuring the corresponding waveform generator or function generator in the test execution device to generate the clock, etc. The generation of the on-chip clock signal of the chip under test can be achieved by using circuits such as a numerically controlled ring oscillator or a voltage-controlled ring oscillator, a phase-locked loop, etc.

[0078] The synchronous clock signal means that the output of the test execution device and the actions of capturing signals are synchronized with the working clock of the chip under test. Since the SRAM circuit is a synchronous clock circuit and the start of the read and write operations is triggered by a specific clock edge, a way to drive and trigger the synchronous clock signal with the same clock is required for the test equipment operation, such as a timer: there is a high-frequency clock with a known frequency inside the test equipment and it drives a counter to count. When a clock signal under test is input to the test equipment, the edge of the clock under test triggers the counter to be cleared, and the maximum count value recorded by the counter is the ratio of the internal and external clock frequencies. Thus, the frequency of the clock under test can be measured. The test equipment can use the counter value to complete the output and capture of signals at the corresponding time points.

[0079] The master control device is used for: (1) Send instructions to the test execution device through short-distance communication cables and protocols to control the measurement strategy of the latter and read the addresses and data that do not meet the expected results; (2) Send the collected addresses and data that do not meet the expected results to the database through long-distance communication or wireless communication; or store the addresses and data that do not meet the expected results in a large-capacity memory.

[0080] In a specific embodiment, the master control device has strong communication and / or storage capabilities and supports at least one short-range communication protocol. Exemplarily, it can be protocols such as I2C, SPI, UART, etc., and supports at least one long-range / wireless communication protocol. Exemplarily, it can be protocols such as Ethernet and WiFi. The test execution device has strong real-time control capabilities and supports at least one short-range communication protocol. Exemplarily, it can be protocols such as I2C, SPI, UART, etc. The test execution device also has high real-time control capabilities to meet the real-time requirements of signals on the data, address, and control paths.

[0081] For the scenario where the chip under test is an SRAM memory chip, the operating frequency of the chip under test is generally between 1 MHz and 2 MHz. When an internal clock signal is generated, the frequency of the clock signal will also be within the range of 1 MHz to 2 MHz. At this time, the test execution device needs to have the ability to provide a clock signal of 1 MHz to 2 MHz and can achieve good real-time control within this clock frequency range.

[0082] When the real-time requirements of the chip under test within the operating frequency range, as well as the requirements for long-range communication, wireless communication, or large-capacity storage, can be met, the master control device and the test execution device can be integrated into the same device. When the master control device and the test execution device are the same device, the short-range communication between them becomes internal data transmission, and at this time, standard protocols such as I2C, SPI, UART, etc. may not be required.

[0083] The operation process of the chip reading and writing ability test device may include the following steps: The master control device performs the following: (1) The master control device initializes and sends a command to the test execution device through short-range communication to initialize the latter.

[0084] (2) According to the design of the target chip under test, the master control device sends configuration information to the test execution device, including: data path bit width (e.g., 32), address path bit width (e.g., 18), address range (e.g., 0x00000 to 0x3FFFF, where 0x indicates that the subsequent numbers are in hexadecimal), power supply voltage of the chip under test, clock source (clock selection signal) of the chip under test, and measurement strategy. Exemplarily, one of the strategies includes four test steps, namely writing all 1s, reading all 1s, writing all 0s, and reading all 0s.

[0085] (3) The master control device sends a start measurement command to the test execution device.

[0086] (4) The master control device sends a measurement result query command to the test execution device at regular time intervals.

[0087] (5) If the test execution device finds unexpected results during the measurement process, it will feedback the relevant signals to the main control device. The main control device will send them to the database through long-distance communication or wireless communication according to the configuration, or store them in the mass storage.

[0088] (6) When the feedback of the query command is the end of the measurement, send a measurement standby command to the test execution device, and then end the measurement.

[0089] The test execution device performs the following: (1) After power-on, enter the standby state and wait for the command of the main control device.

[0090] (2) After receiving the initialization command, initialize each module, including the general-purpose input / output module, power module, timer, etc. Among them, the general-purpose input / output module is used to output and capture test signals; the power module is used to supply power to the chip under test; the timer is used to synchronize the on-chip clock signal of the test chip or provide an external clock signal for the test chip.

[0091] (3) After receiving the configuration information, power on the chip under test according to the power supply voltage information, configure the general-purpose input / output module into a data path, address path, and control path; save the data bit width, address bit width, and address range; configure the timer; if the clock source is the test execution device, output the timer clock after a certain step; if the clock source is the chip under test, input the clock signal into the timer to know the actual frequency; initialize the measurement data according to the measurement strategy.

[0092] (4) After receiving the start measurement command, read the chip under test in sequence according to the measurement strategy, data bit width, address bit width, and address range configuration. Taking the measurement strategy as "write all 1s, read all 1s, write all 0s, read all 0s", the data bit width as 32 bits, the address bit width as 18 bits, and the address range from 0x00000 to 0x3FFFF as an example. First, write 32-bit 1s in sequence from address 0x00000 to 0x3FFFF; then read the data in sequence from address 0x00000 to 0x3FFFF. At this time, the expected result should be all 32-bit 1s. If not, temporarily store the addresses and data that do not meet the expectations and wait for the main control device to query; then write 32-bit 0s in sequence from address 0x00000 to 0x3FFFF; then read the data in sequence from address 0x00000 to 0x3FFFF. At this time, the expected result should be all 32-bit 0s. If not, temporarily store the addresses and data that do not meet the expectations and wait for the main control device to query; finally, enter the measurement end state and wait for the main control device to query.

[0093] During measurement, a query command sent by the master control device will be received. At this time, if there are addresses and data that do not meet the expectations, the addresses and data that do not meet the expectations will be fed back, and then the relevant records will be discarded; if there is no data that does not meet the expectations, it will be fed back according to the current measurement status that the measurement is in progress or the measurement is completed.

[0094] (6)After receiving the standby command, if there is a clock output, the clock output will be turned off; the timer will be turned off; all general-purpose input / output modules will be configured in a high-impedance state, that is, disconnected from the chip under test, so that the chip under test is powered down. Then enter the standby state. When in the standby state, the power of the test execution device can be safely turned off at any time.

[0095] A chip read-write ability testing device provided in this embodiment can select either the on-chip clock signal of the chip under test or the external clock signal of the testing device as the test clock signal, overcoming the limitations of traditional devices in clock source adaptability. It can implement read-write tests for a variety of chip types with high compatibility, thereby achieving the effects of cost reduction and improved compatibility. By determining sample data based on the test strategy, it can provide more comprehensive and in-depth test services for diverse test requirements, and can achieve the effects of improving the quality and efficiency of testing. By comparing the sample data and the read data bit by bit, the accuracy of the test results is ensured. Through automated data comparison and error recording, the efficiency of fault diagnosis is improved, thus achieving the effects of improving the quality and efficiency of testing. By setting the first path, the second path, and the third path, the testing device can complete the chip read-write ability test more efficiently and accurately, meeting the test requirements of different types of chips, and can achieve the effects of improving the test quality and compatibility. Through the separate design of the main control device and the test execution device, the test system can be flexibly configured and expanded to adapt to different types of chips and test requirements; the real-time communication connection between the main control device and the test execution device enables users to monitor the test progress and results in real time, and can also adjust the test parameters in a timely manner, thus achieving the effects of improving the test quality and test efficiency. By configuring the bit width and address range of the read-write path in the configuration information, it is ensured that the test execution device can correctly configure the general-purpose input / output module, thereby accurately sending and receiving signals, improving the accuracy of the test. The initialization and configuration of the general-purpose input / output module can be adjusted according to different chips and test requirements, improving the flexibility and adaptability of the system, and thus achieving the effects of improving the test quality and compatibility. By correctly configuring the power supply voltage, it is ensured that the chip under test can operate safely during the test, avoiding chip damage caused by voltage mismatch; the bit width of the read-write path, the address range, and the power supply voltage of the chip under test in the configuration information ensure that the test execution device can correctly configure the general-purpose input / output module and the power supply module, thereby accurately sending and receiving signals, improving the accuracy of the test, and thus achieving the effects of improving the test quality and compatibility. By the clock source information in the configuration information, it is ensured that the test execution device can correctly configure the timer module to generate an appropriate clock signal, thereby improving the accuracy of the test. Through the clock selection function of the timer module, it is ensured that accurate clock synchronization can be achieved when using the on-chip clock or the external clock, improving the reliability and consistency of the test, and thus achieving the effects of improving the test quality and compatibility. Through the feedback mechanism of the query instruction and specific test results, users can obtain and analyze the test results more efficiently, especially those that do not meet the preset conditions, which helps to quickly locate and solve problems. At the same time, only sending the test results that do not meet the preset conditions reduces the data transmission volume, improves the response speed and efficiency of the system, and thus can achieve the effect of improving the test efficiency.By disconnecting the connection to the chip under test and powering it down, accidental current flow or signal interference in non-test states can be prevented, protecting the safety of the chip under test and the test equipment; safely disconnecting the connection and powering down can also reduce equipment wear and extend the service life of the test equipment and the chip under test, achieving the effect of reducing equipment maintenance costs.

[0096] Each module in the above chip read / write ability test equipment can be implemented in whole or in part by software, hardware, or a combination thereof. Each of the above modules can be embedded in the processor of a computer device in hardware form or be independent of it, or can be stored in the memory of a computer device in software form for the processor to call and execute the operations corresponding to each of the above modules.

[0097] Based on the same inventive concept, an embodiment of the present application also provides a chip read / write ability test method for implementing the above-mentioned chip read / write ability test equipment. The implementation solutions for solving problems provided by this method are similar to those recorded in the above chip read / write ability test equipment. Therefore, the specific limitations in one or more embodiments of the chip read / write ability test method provided below can refer to the limitations on the chip read / write ability test equipment in the above text and will not be elaborated here.

[0098] In one embodiment, the present application provides a chip read / write ability test method applied to a chip read / write ability test equipment. The chip read / write ability test method includes: Based on the received control instruction, generate and send a control signal, an address signal, and sample data to the chip under test; the control instruction includes a clock selection signal; When the clock selection signal is the first selection signal, obtain the on-chip clock signal of the chip under test, and send a control signal, an address signal, sample data to the chip under test, and receive the read data; wherein, the control signal includes a clock signal, and the clock signal is generated based on the on-chip clock signal; when the clock selection signal is the second selection signal, send a control signal, an address signal, sample data to the chip under test, and receive the read data; wherein, the control signal includes a clock signal, and the clock signal is generated based on the operating frequency of the chip under test; Determine the test result of the chip under test through the sample data and the read data.

[0099] In some of these embodiments, the control instruction includes a test strategy, and the test strategy includes various ways to verify the read / write performance of the chip under test; the test equipment is also used to determine the sample data based on the test strategy.

[0100] In some of these embodiments, determining the test result of the chip under test based on the sample data and the read data includes: determining the test result of the chip under test based on the matching condition between the sample data and the read data.

[0101] In some of these embodiments, the connection paths between the test device and the chip under test include a first path, a second path, and a third path connected. Sending the read / write control signal, sending the address signal, and sending the sample data or receiving the read data include: Transmitting the address signal through the first path; the address signal includes the read / write address; Transmitting the data signal through the second path, the data signal includes the sample data or the read data; Transmitting the control signal through the third path, the control signal includes the read / write control signal and the clock signal.

[0102] In some of these embodiments, configuring itself based on the configuration information corresponding to the chip under test; generating and sending a control signal, an address signal, and sample data to the chip under test based on a test instruction, and receiving the read data; determining the test result of the chip under test through the sample data and the read data.

[0103] In some of these embodiments, the configuration information includes the read / write path bit width and the address range; before generating the control signal, the address signal, and the sample data based on the received control instruction, it further includes: initializing the general-purpose input / output module; configuring the initialized general-purpose input / output module based on the read / write path bit width and the address range.

[0104] In some of these embodiments, the configuration information further includes the power supply voltage of the chip under test; before generating the control signal, the address signal, and the sample data based on the received control instruction, it further includes: initializing the power supply module; the power supply module is used to power on the chip under test based on the power supply voltage of the chip under test.

[0105] In some of these embodiments, the configuration information further includes a clock selection signal; before generating the control signal, the address signal, and the sample data based on the received control instruction, it further includes: initializing the timer; when the clock selection signal is the first selection signal, the timer is used to synchronize the on-chip clock signal of the chip under test; when the clock selection signal is the second selection signal, the timer is used to generate a clock signal based on the operating frequency of the chip under test and send the clock signal to the chip under test.

[0106] In some of these embodiments, after determining the test result of the chip under test through the sample data and the read data, the following steps are further included: generating a query instruction; and based on the query instruction, determining the test results in the test result of the chip under test that do not meet the preset conditions.

[0107] In some of these embodiments, after determining the test result of the chip under test through the sample data and the read data, the following steps are further included: generating a standby instruction; and based on the standby instruction, closing the connection with the chip under test and powering down the chip under test.

[0108] Embodiment 2 As Figure 1 shown, a chip read-write ability test system is provided, including a chip under test and a chip read-write ability test device according to any one of the above Embodiment 1; The chip under test uses a storage chip as Figure 5 shown; the storage chip includes a clock selector, a configuration selector, an on-chip clock source, and a storage module; wherein: The clock selector is configured to determine the working clock signal of the storage chip from the clock signal input from the chip read-write ability test device and the on-chip clock signal generated by the on-chip clock source based on the control signal received from the chip read-write ability test device; The configuration selector is configured to set the on-chip clock source and / or the storage module based on the control signal received from the chip read-write ability test device; The on-chip clock source is configured to generate at least one on-chip clock signal based on the setting of the configuration selector; The storage module is configured to write the sample data and / or read data based on the control signal, address signal, sample data, and working clock signal received from the chip read-write ability test device.

[0109] In one of the embodiments, the storage chip further includes data pads, address pads, and control pads for transmitting data signals, address signals, and control signals respectively as external interfaces.

[0110] In one of the embodiments, the control signal includes an input clock signal and a clock selection signal; when the clock selection signal is to use an external clock, the clock selector is configured to receive the input clock signal and use the input clock signal as the working clock signal of the storage chip.

[0111] In one embodiment, the control signal further includes a clock output signal; when the clock selection signal is to use the internal clock, the clock selector is configured to receive the on-chip clock signal generated by the on-chip clock source and use the on-chip clock signal as the working clock signal of the memory chip; the working clock signal is further used as the clock output signal and output to an external device.

[0112] In one embodiment, the control signal further includes a configuration selection signal and a configuration input signal; when the configuration selection signal is to use the input configuration, the configuration selector configures the on-chip clock source and / or the memory module based on the configuration input signal.

[0113] In one embodiment, the control signal further includes a configuration protocol signal; the memory chip further includes a configuration register for storing preset configuration information; when the configuration selection signal is to use the internal configuration, the configuration register is configured to receive the configuration protocol signal and transmit the configuration information to the configuration selector; the configuration selector is configured to configure the on-chip clock source and / or the memory module based on the configuration information.

[0114] In one embodiment, the memory module includes a timing balance module and a plurality of memory banks, and the timing balance module is respectively connected to the plurality of memory banks; the timing balance module is configured to receive the working clock signal, perform delay compensation on the working clock signal based on a delay parameter, and then transmit the compensated signal to the memory banks; the configuration selector further includes a delay configuration module, and the delay configuration module is configured to configure the delay parameter of the timing balance module based on the received signal.

[0115] In one embodiment, the memory bank includes a plurality of memory bank units; the timing balance module includes a delay main module and at least one delay adjustment module, and the delay adjustment module is connected to the output end of the delay main module, where: the delay main module is configured to delay the input working clock signal for a first time and then output a first signal; the delay adjustment module is configured to receive a corresponding delay parameter according to the delay requirement, delay the first signal for a second time, and then output a second signal to the plurality of memory bank units; the Chebyshev distance or Euclidean distance between the delay adjustment module and the plurality of memory bank units is equal.

[0116] In one embodiment, the on-chip clock source includes a clock adjuster and multiple on-chip clock generators. Different on-chip clock generators generate clock signals with different frequencies. Based on the configuration selector, a target clock generator is determined from the multiple on-chip clock generators, and the clock signal generated by the target clock generator is output to the clock adjuster. The clock adjuster finely tunes the clock signal generated by the target on-chip clock generator based on a control signal to obtain a finely tuned clock signal corresponding to the control signal, which is used as the final clock signal.

[0117] In a specific embodiment, the storage chip includes SRAM memory cells. As Figure 6 shown, it includes three groups of external interfaces, including a data path for transmitting written / read data, an address path for transmitting the address of the written / read data, and a control path. Among them, the signals transmitted by the control path at least include: a read / write control signal for controlling whether the current operation is a write or a read, and at least one clock signal. In addition, the signals transmitted by the control path may further include: (1) a configuration protocol signal for configuring the configuration register inside the chip; (2) a configuration selection signal and a configuration input signal; (3) a clock selection signal, a clock input signal, and a clock output signal.

[0118] In this embodiment, the storage chip is an SRAM chip controlled by a clock signal. The clock signal can be generated inside the SRAM chip. Correspondingly, the SRAM chip will output the internally generated clock signal outside the chip. The clock signal can also be input by a chip read / write ability test device.

[0119] The storage chip in this embodiment contains multiple banks. Each bank includes at least one bitcell array. Each bitcell array includes at least one bitcell. Multiple bitcells in the same bitcell array form a bitcell array. Each bitcell in the bitcell array can share the same control logic circuit to implement data storage. Since the area of the bank is large and may be scattered in various corners of the chip, and each bitcell array requires data, address, delay selection, and system clock, in this embodiment, in order to make the delay of the above signals reaching each bitcell array as consistent as possible, the timing balance module is used to solve the delay problem of the clock signal, so that the delay of the above signals reaching each bitcell is as consistent as possible.

[0120] The memory chip further includes a clock selector, which selects one of a clock input and an on-chip clock as a working clock signal according to a clock selection signal. When the clock selection signal is to use an external clock, the clock selector is configured to receive the input clock signal and use the input clock signal as the working clock signal of the memory chip. When the clock selection signal is to use an internal clock, the clock selector is configured to receive an on-chip clock signal generated by the on-chip clock source and use the on-chip clock signal as the working clock signal of the memory chip; the working clock signal is further used as the clock output signal and output to an external test device.

[0121] The memory chip further includes a configuration selector and a configuration register, and the configuration register is configured to store preset configuration information. When the configuration selection signal is to use an input configuration, the configuration selector configures the on-chip clock source and / or the memory module based on the configuration input signal. When the configuration selection signal is to use an internal configuration, the configuration register is configured to receive the configuration protocol signal and transmit the configuration information to the configuration selector; the configuration selector is configured to configure the on-chip clock source and / or the memory module based on the configuration information.

[0122] According to different clock selection signals and configuration selection signals in the control path, the memory chip of this embodiment can implement at least 4 working modes: Working mode 1: The clock selection signal selects to use the clock input as the working clock signal of the memory chip, the configuration selection signal selects to use the input configuration, and the configuration selector configures the on-chip clock source and / or the memory module based on the configuration input signal.

[0123] In this mode, since the configuration selection signal selects to use the input configuration, the configuration information output by the configuration register will be ignored internally, and in this mode, the working content of the configuration protocol and the configuration register will not be referenced.

[0124] Similarly, when the clock selection signal uses the clock input signal, the on-chip clock will be ignored, and correspondingly, the operation of the on-chip clock source will be disabled or ignored.

[0125] The signals input to the "timing balance module" include: a data signal and an address signal; a working clock signal, i.e., the system clock output by the clock selector via the clock input signal; and a configuration input signal, i.e., the delay selection signal output by the clock source and the delay configuration input via the configuration selector.

[0126] This working mode belongs to the basic working mode. The test signals, control signals, and clock signals are directly driven by an external test device, with high test flexibility. The storage chip will not be restricted by the test device. However, it cannot perform high-frequency tests, and there is a relatively large sacrifice in test speed and chip area.

[0127] Working Mode 2: The clock selection signal selects the clock input signal as the working clock signal of the system, and the configuration selection signal selects the internal configuration.

[0128] In this mode, when the clock selection signal uses the clock input signal, the on-chip clock will be ignored. Correspondingly, the operation of the on-chip clock source will be either disabled or ignored.

[0129] Since the configuration selection signal selects the internal configuration, that is, the clock source and delay configuration internal signals, correspondingly, through the configuration protocol signal, the corresponding configuration parameters are transmitted to the configuration register. The configuration selector configures the on-chip clock source and / or storage module based on the configuration parameters.

[0130] The signals input to the timing balance module include: data signals and address signals; the working clock signal, that is, the system signal output by the clock input signal via the clock selector; and the delay selection signal output by the configuration protocol signal via the configuration register and the configuration selector.

[0131] In this working mode, the external test device provides the clock and test signals, and the storage chip internally provides the control signals. While ensuring test flexibility, more control bits can be provided, and the number of IO ports for configuration input can be saved, but the test preparation time is sacrificed.

[0132] Working Mode 3: The clock selection signal selects the on-chip clock as the working clock signal of the system, that is, the on-chip clock signal as the working clock signal of the system. The configuration selection signal selects the input configuration, and the configuration selector configures the on-chip clock source and / or storage module based on the configuration input signal.

[0133] In this mode, since the configuration selection signal selects the input configuration, correspondingly, the configuration information output by the configuration register will be ignored internally. In this mode, the working content of the configuration protocol and the configuration register will not be referenced. Since the clock selection signal selects the on-chip clock signal, at this time, multiple on-chip clock generators in the on-chip clock source generate multiple clock sources, and the clock source selection signal output by the configuration selector determines which clock signal generated by the on-chip clock generator is output to the on-chip clock, that is, as the on-chip clock signal.

[0134] The signals input to the timing balance module include: data signals and address signals; the working clock signal, i.e., the system clock output by the on-chip clock signal via the clock selector; and the configuration input signal, i.e., the delay selection signal output by the clock source and the delay configuration input via the configuration selector.

[0135] In this working mode, the clock signal is generated inside the memory chip, and the external test device provides test signals and control signals, which can ensure a certain degree of test flexibility and improve the quality of the clock signal at the same time. However, the clock synchronization between the external test device and the inside of the memory chip and the real-time requirements of the external test device are relatively high.

[0136] Working mode 4: The clock selection signal selects the on-chip clock as the working clock signal of the system, and the configuration selection signal selects the internal configuration.

[0137] In this mode, since the configuration selection signal selects to use the internal configuration, i.e., the clock source and the internal delay configuration signals, the corresponding configuration parameters must be transmitted to the configuration register through the configuration protocol signal. The configuration selector configures the on-chip clock source and / or the memory module based on the configuration parameters. Since the clock selection signal selects to use the on-chip clock signal, at this time, multiple on-chip clock generators in the on-chip clock source generate multiple clock sources, and the clock source selection signal output by the configuration selector determines which clock signal generated by the on-chip clock generator is output to the on-chip clock, i.e., as the on-chip clock signal.

[0138] The signals input to the timing balance module include: data signals and address signals; the working clock signal, i.e., the system clock output by the on-chip clock signal via the clock selector; and the delay selection signal output by the configuration protocol signal via the configuration register and the configuration selector.

[0139] In this working mode, the test signal, the control signal, and the clock signal are all generated inside the memory chip, which can greatly improve the test frequency and better reflect the read and write performance of the chip. However, it sacrifices test flexibility, and additional design is required to complete the test and transmit the test results.

[0140] The memory chip in this embodiment can perfectly support at least four of the above working modes, can match the read and write test requirements of different scenarios, support high-frequency tests, can achieve precise timing control, and can be widely used in the read and write tests of different memory chips.

[0141] Further, on this basis, the on-chip clock source further includes a data control oscillator. A digital controlled oscillator (DCO) is an oscillator based on digital signal processing technology. Its working principle is to adjust the frequency of the oscillator by controlling the frequency of the digital signal. As an on-chip clock generation circuit, the DCO can provide different frequency ranges. In this embodiment, the internal generation of the clock signal is realized based on the DCO to ensure that the frequency of the clock signal generated on-chip is adapted to the corresponding operating frequency of the chip.

[0142] The on-chip clock source includes multiple on-chip clock generators and a clock adjuster. Different on-chip clock generators generate clock signals with different frequencies, and the clock signal generated by the target clock generator is output to the clock adjuster; the clock adjuster finely adjusts the clock signal generated by the target on-chip clock generator based on the control signal to obtain the finely adjusted clock signal corresponding to the control signal as the final clock signal. As Figure 11 shown is a schematic diagram of the overall structure of an on-chip clock signal generation circuit in this embodiment. As Figure 9 shown, digital control is used for path selection, and coarse frequency adjustment is achieved through the effective number of stages in the ring oscillator circuit, thereby generating multiple frequencies. At this time, the adjustable frequency range is wide. The single-stage delay of the ring oscillator in the clock adjuster is controlled based on the control current signal to finely adjust the clock signal using the ring oscillator and obtain the oscillation frequency of the finely adjusted clock signal.

[0143] Specifically, the generation of the clock signal by the on-chip clock source may include the following steps: Step S201: Determine the target on-chip clock generator from multiple on-chip clock generators based on the operating frequency of the chip.

[0144] Among them, the frequency of the clock signal generated by the target on-chip clock generator is within a preset frequency range; the operating frequency of the chip is within the preset frequency range, that is, this preset frequency range is preset based on the operating frequency of the chip, and the operating frequency of the chip will be within this preset frequency range.

[0145] The on-chip clock source may include multiple on-chip clock generators and a clock adjuster. Different on-chip clock generators generate clock signals with different frequencies, enabling the storage chip to operate at different frequencies.

[0146] Generally, a preset frequency range can be determined according to the operating frequency required by the storage chip. Specifically, the operating frequency of the storage chip is within the preset frequency range. Further, the on-chip clock generators among the multiple on-chip clock generators whose clock signal frequencies are within the preset frequency range are determined as the target on-chip clock generators, so that the frequency of the clock signal generated by the target on-chip clock generators is in the same frequency range as the operating frequency of the storage chip, realizing the coarse adjustment of the clock signal on the storage chip.

[0147] Step S202: Input multiple control signals into the clock adjuster to finely adjust the clock signal and obtain the oscillation frequency of the finely adjusted clock signal corresponding to each control signal.

[0148] The clock adjuster includes adjusting a single-stage delay based on the control signal.

[0149] Further, input multiple control signals into the clock adjuster, and the single-stage delay of the clock adjuster corresponding to each control signal is different. Thus, the adjustment of the single-stage delay of the clock adjuster by multiple control signals realizes the adjustment of the clock signal output by the target on-chip clock generator, and the oscillation frequency of the clock signal corresponding to each control signal is obtained.

[0150] Step S203: Determine the target control signal based on the operating frequency of the storage chip and the oscillation frequency of the finely adjusted clock signal corresponding to each control signal.

[0151] Further, the control signal corresponding to the oscillation frequency of the clock signal that is consistent with the operating frequency of the storage chip or within a preset error range is determined as the target control signal.

[0152] Step S204: Control the generation of the final clock signal based on the target on-chip clock generator and the target control signal.

[0153] Further, determine the target on-chip clock generator from multiple on-chip clock generators and input the target control signal into the clock adjuster, so as to finely adjust the clock signal generated by the target on-chip clock generator by using the clock adjuster to obtain the final clock signal, and make the oscillation frequency of the final clock signal be able to be consistent with the operating frequency of the chip or within a preset error range.

[0154] In the above implementation process, according to the operating frequency of the memory chip, the target on-chip clock generator is determined from multiple on-chip clock generators, so that the frequency of the clock signal generated by the target on-chip clock generator is within the same frequency range as the operating frequency of the memory chip, achieving coarse adjustment of the clock signal. Further, multiple control signals are input into the clock adjuster, and the single-stage delay of the clock adjuster is adjusted through each control signal, so as to adjust the clock signal output by the target on-chip clock generator. By determining the target control signal according to the operating frequency of the memory chip and the oscillation frequency of the fine-tuned clock signal corresponding to each control signal, fine adjustment of the clock signal is achieved, ensuring that the frequency of the finally output clock signal is consistent with the operating frequency of the chip or within a preset error range.

[0155] Further, the control signal is a digital signal. As Figure 7 shown, the clock adjuster includes a digitally controlled current source, a ring oscillator, and a feedback loop. The digital signal is input into the digitally controlled current source, and a control current signal is output. The control current signal can control the output frequency of the ring oscillator by controlling the single-stage delay of the ring oscillator. Inputting multiple control signals into the clock adjuster to finely adjust the clock signal and obtaining the oscillation frequency of the fine-tuned clock signal corresponding to each control signal may include the following steps: Step 1: The current source component in the clock adjuster converts the digital signal into a control current signal.

[0156] Step 2: Based on the control current signal, control the single-stage delay of the ring oscillator in the clock adjuster to finely adjust the clock signal using the ring oscillator and obtain the oscillation frequency of the fine-tuned clock signal.

[0157] Exemplarily, the control signal can be a digital signal, and the frequency formula of the ring oscillator is:

[0158] where f osc represents the frequency of the ring oscillator, n represents the number of stages of the ring oscillator, and τ represents the single-stage delay of the ring oscillator. It can be seen from this that the frequency of the ring oscillator can be adjusted by controlling its number of stages and single-stage delay.

[0159] Specifically, after multiple digital signals are input into the clock adjuster, the current source component in the clock adjuster converts the digital signals into control current signals. Further, the single-stage delay of the ring oscillator in the clock adjuster is controlled by the control current signal, and the clock signal is finely adjusted by adjusting the single-stage delay of the ring oscillator, and the oscillation frequency of the fine-tuned clock signal corresponding to each digital signal is obtained.

[0160] In the above implementation process, a digital signal is converted into a control current signal by a current source component in a clock adjuster, and the single-stage delay of a ring oscillator in the clock regulator is controlled by the control current signal, thereby realizing the fine-tuning of the clock signal by the ring oscillator.

[0161] Further, based on the operating frequency of the chip and the oscillation frequency of the fine-tuned clock signal corresponding to each control signal, a target control signal is determined, including: determining the control signal corresponding to the clock signal whose oscillation frequency is the same as or within a preset error range among the oscillation frequencies of the fine-tuned clock signals corresponding to multiple control signals as the target control signal.

[0162] Specifically, when determining the target control signal, the control signal corresponding to the clock signal whose oscillation frequency is the same as or within a preset error range among the oscillation frequencies of the fine-tuned clock signals corresponding to multiple control signals is determined as the target control signal, so that the frequency of the clock signal generated by the target on-chip clock generator is the same as or within a preset error range of the operating frequency of the chip, ensuring that the clock signal frequency of the on-chip generator in the chip is within the operating frequency range of the corresponding chip.

[0163] Further, when controlling the single-stage delay of the ring oscillator in the clock adjuster based on the control current signal to fine-tune the clock signal by using the ring oscillator and obtain the oscillation frequency of the fine-tuned clock signal, the following steps may be included: Step 1: Perform a frequency reduction process on the oscillation frequency to obtain the frequency-reduced oscillation frequency.

[0164] Step 2: Perform a duplicate removal process on the frequency-reduced oscillation frequency to obtain the oscillation frequency after duplicate removal.

[0165] Step 3: Convert the oscillation frequency after duplicate removal into a feedback current signal through a feedback loop in the clock adjuster.

[0166] Step 4: Based on the control current signal and the feedback current signal, control the single-stage delay of the ring oscillator in the clock adjuster to fine-tune the clock signal by using the ring oscillator and obtain the oscillation frequency of the fine-tuned clock signal.

[0167] In order to use a digitally controlled current source to implement a relatively linear oscillator, the DCO function can be improved by negative feedback technology. The feedback loop is formed by sampling the output and mixing it with the input. Since the frequency of the oscillator output is too high, there is no time to directly sample it through capacitor charging and discharging.

[0168] Specifically, a frequency divider circuit can be used to reduce the frequency of the output of the ring oscillator, obtaining a down-converted oscillation frequency, and the down-converted oscillation frequency is processed by a non-overlapping pulse generation circuit to remove duplicates, resulting in an oscillation frequency. Further, the oscillation frequency after duplicate removal is converted into a feedback current signal through a feedback loop in the clock adjuster.

[0169] Furthermore, the control current signal and the feedback current signal are combined, and the combined signal controls the single-stage delay of the ring oscillator in the clock adjuster to finely adjust the clock signal using the ring oscillator and obtain the oscillation frequency of the finely adjusted clock signal.

[0170] Based on the operating frequency of the chip and the oscillation frequency of the clock signal corresponding to each control signal, determining the target control signal further includes: the oscillation frequency stability of the finely adjusted clock signal is higher than a preset value.

[0171] Further, when the clock signal of the ring oscillator is finely adjusted, the oscillation frequency stability of the finely adjusted clock signal is higher than a preset value. Specifically, the preset value can be determined specifically according to the operating frequency of the chip, application scenario requirements, etc.

[0172] In the above implementation process, the frequency of the output of the ring oscillator is reduced by a frequency divider circuit, and the non-overlapping pulse generation circuit processes the down-converted oscillation frequency to remove duplicates. The oscillation frequency after duplicate removal is converted into a feedback current signal through a feedback loop in the clock adjuster. Further, the control current signal and the feedback current signal are combined, and the combined signal controls the single-stage delay of the ring oscillator in the clock adjuster, realizing the loop adjustment of the clock adjuster.

[0173] Furthermore, the current source component is also used to generate multiple different proportional currents under the control of a digital signal.

[0174] The current source component includes: a current source, a matching transistor, and a numerically controlled transistor. The first end of the matching transistor is connected to the current source, the second end of the matching transistor is connected to the numerically controlled transistor, and the third end of the matching transistor is connected to the ring oscillator. The matching transistor is used to stabilize the current output by the current source and input the stabilized current into the ring oscillator through the third end of the matching transistor. The first end of the numerically controlled transistor accesses a first digital signal, and the second end of the numerically controlled transistor is connected to the second end of the matching transistor. The numerically controlled transistor is used to control the magnitude of the current output by the matching transistor based on the first digital signal.

[0175] Specifically, the current source component generates multiple different proportional currents under the control of a digital signal. Figure 8 is a circuit diagram of a current source component provided by an embodiment of the present application, as Figure 8As shown, there are a current source, a matching transistor, and a digitally controlled transistor. The matching transistors in the solid-line box copy the current from the stable current source (Iref) in a binary manner through a current mirror. The digitally controlled parallel binary-weighted transistors in the dashed-line box, which are the digitally controlled transistors, turn on / off the transistors by using a digital code. In this way, the current passing through Ms1 will be determined by the input digital code. The output node is connected to a single transistor (MS2) that is always on, and the binary-weighted transistors are separated from this node, which helps to reduce the influence of voltage level changes in the digital control signal on the current value. Here, the size of the transistors increases in a binary manner. This part takes eight digital signals C0, C1, C2... and C8 as controllable signal inputs, corresponding to the inputs of 512 gears from 00000000 to 11111111 respectively, and can provide 512 different currents.

[0176] In the above implementation process, through the current source component composed of a current source, a matching transistor, and a digitally controlled transistor, a current source controlled by digital signals generates different proportional currents.

[0177] Furthermore, the ring oscillator in the clock adjuster includes multiple differential units. Each differential unit includes a latch and two inverters for driving current into the latch. The latch includes two cross-coupled inverters.

[0178] Exemplarily, Figure 9 is a schematic diagram of a ring oscillator provided by an embodiment of the present application. As Figure 9 shown, the oscillator in (a) is a ring structure, composed of four differential units. Figure 9 Among them, (c) is the current source component. Each differential unit (b) is implemented by using a cross-coupled structure, which includes two cross-coupled inverters (solid-line box) used as latches and two inverters (dashed-line box) responsible for driving current into the latch. In order to change the latch speed and thus change the delay of each unit, we change the current intensity (cs1 / cs2) of the driving inverter. In order to improve the jitter performance of the oscillator, at each output node, an inverter is used to adjust the swing level. The oscillator generates eight different phases at the output.

[0179] In the above implementation process, the ring oscillator structure composed of four differential units including a latch and two inverters for driving current into the latch, where the latch includes two cross-coupled inverters, can enable the ring oscillator to output multiple different phases.

[0180] In one of the embodiments, multiple on-chip clock generators include a ring oscillation circuit and a multiplexer. To determine the target on-chip clock generator from multiple on-chip clock generators based on the operating frequency of the chip, the following steps may be included: Step 1: The ring oscillator circuit adjusts the effective number of stages in the oscillation path through a multiplexer to generate clock signals of different frequencies; Step 2: Input the selection signal into the multiplexer to determine the effective number of stages of the ring oscillator circuit, so as to determine the target on-chip clock generator; the frequency of the clock signal generated by the target on-chip clock generator is within a preset frequency range; the operating frequency of the chip is within a preset frequency range.

[0181] Specifically, Figure 10 FIG. is a schematic circuit diagram of multiple on-chip clock generators (including a ring oscillator circuit and a multiplexer) provided in an embodiment of the present application, including a NAND gate, K delay units, and a 16-to-1 multiplexer to form a ring oscillator circuit, where K is an even number greater than 0; the NAND gate includes two input terminals and one output terminal, and one of the input terminals EN is used to externally connect a start control signal to control the switch of the circuit; the delay units are connected in series, and the input terminal of the first delay unit is connected to the output terminal of the NAND gate, and the output terminal of the last delay unit is connected to one input of the 16-to-1 multiplexer; each delay unit is composed of an odd number of inverters; the 16-to-1 multiplexer includes 16 inputs (dividing the K delay units into 16 segments on average), four digital control selection signals S1 / S2 / S3 / S4, and one output, and the output terminal of the 16-to-1 multiplexer is connected to the other input terminal of the NAND gate to form a ring oscillator structure. The four digital signals S1 / S2 / S3 / S4 are input as controllable signals, corresponding to 16 gears of input from 0000 to 1111, where 0000 corresponds to the maximum effective number of stages, and the oscillation frequency output is the smallest at this time. The 16-to-1 multiplexer is controlled by the selection signal to perform path selection, and the effective number of stages in the oscillation path is adjusted to achieve coarse frequency adjustment.

[0182] When determining the target on-chip clock generator, the ring oscillator circuit adjusts the effective number of stages in the oscillation path through a multiplexer to generate clock signals of different frequencies, and, input the selection signal into the multiplexer to determine the effective number of stages of the ring oscillator circuit. When the frequency of the clock signal generated by a certain on-chip clock generator is within the preset frequency range and the operating frequency of the chip is within the preset frequency range, this on-chip clock generator is determined as the target on-chip clock generator.

[0183] In the above implementation process, the 16-to-1 multiplexer is controlled by the selection signal to perform path selection, and the effective number of stages in the oscillation path is adjusted to determine the target on-chip clock generator, achieving coarse frequency adjustment, so as to ensure that the frequency of the clock signal generated by the target on-chip clock generator is within the preset frequency range and the operating frequency of the chip is within the preset frequency range.

[0184] It should be understood that although the steps in the flowcharts involved in the above-described embodiments are shown in sequence according to the arrows, these steps are not necessarily executed in the order indicated by the arrows. Unless there is a clear description in this article, the execution of these steps has no strict order limit, and these steps can be executed in other orders. Moreover, at least a part of the steps in the flowcharts involved in the above-described embodiments may include multiple steps or multiple stages. These steps or stages are not necessarily executed at the same moment, but can be executed at different moments. The execution order of these steps or stages is not necessarily sequential, but can be executed alternately or in turn with at least a part of other steps or steps or stages in other steps.

[0185] In one embodiment, a computer-readable storage medium is provided, on which a computer program is stored. When the computer program is executed by a processor, it implements the chip read-write ability test method of any of the above embodiments: Generate a control signal, an address signal, and sample data based on the received control instruction; the control signal includes a read-write control signal and a clock selection signal; and send the control signal to the chip under test; When the clock selection signal is the first selection signal, obtain the on-chip clock signal of the chip under test, and send the read-write control signal, the address signal, the sample data, and receive the read data based on the on-chip clock signal; When the clock selection signal is the second selection signal, send the external clock signal generated by the chip read-write ability test device to the chip under test, and send the read-write control signal, the address signal, the sample data, and receive the read data based on the external clock signal; Determine the test result of the chip under test through the sample data and the read data.

[0186] It should be noted that the user information (including but not limited to user device information, user personal information, etc.) and data (including but not limited to data for analysis, stored data, displayed data, etc.) involved in this application are all information and data authorized by the user or fully authorized by all parties.

[0187] Those of ordinary skill in the art can understand that all or part of the processes in the methods of the above embodiments can be completed by instructing relevant hardware through a computer program. The computer program can be stored in a non-volatile computer-readable storage medium. When the computer program is executed, it can include the processes of the embodiments of the above methods. Among them, any reference to a memory, database, or other medium used in the embodiments provided in the present application can include at least one of non-volatile and volatile memories. Non-volatile memories can include read-only memory (ROM), magnetic tapes, floppy disks, flash memories, optical memories, high-density embedded non-volatile memories, resistive random access memories (ReRAM), magnetoresistive random access memories (MRAM), ferroelectric random access memories (FRAM), phase change memories (PCM), graphene memories, etc. Volatile memories can include random access memory (RAM) or external cache memories, etc. By way of illustration and not limitation, RAM can be in various forms, such as static random access memory (SRAM) or dynamic random access memory (DRAM), etc. The databases involved in the embodiments provided in the present application can include at least one of relational databases and non-relational databases. Non-relational databases can include distributed databases based on blockchain, etc., without limitation. The processors involved in the embodiments provided in the present application can be general-purpose processors, central processing units, graphics processing units, digital signal processors, programmable logic devices, data processing logics based on quantum computing, etc., without limitation.

[0188] The technical features of the above embodiments can be combined arbitrarily. For the sake of brevity of description, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, it should be considered as the scope described in this specification.

[0189] The above-described embodiments merely represent several implementation manners of the present application. The description thereof is relatively specific and detailed, but it should not be construed as a limitation on the patent scope of the present application. It should be noted that for those of ordinary skill in the art, without departing from the concept of the present application, several modifications and improvements can still be made, and these all belong to the protection scope of the present application. Therefore, the protection scope of the present application shall be subject to the appended claims.

Claims

1. A chip read-write ability testing device, characterized in that, The chip read-write ability test device is electrically connected to the chip under test. The test device is used to generate and send a control signal, an address signal, and sample data to the chip under test based on a received control instruction. The control instruction includes a clock selection signal. When the clock selection signal is the first selection signal, obtain the on-chip clock signal of the chip under test, and send a control signal, an address signal, sample data to the chip under test, and receive the read data. Wherein, the control signal includes a clock signal, and the clock signal is generated based on the on-chip clock signal. When the clock selection signal is the second selection signal, send a control signal, an address signal, sample data to the chip under test, and receive the read data. Wherein, the control signal includes a clock signal, and the clock signal is generated based on the operating frequency of the chip under test. The chip read-write ability test device is further used to determine the test result of the chip under test through the sample data and the read data.

2. The chip read-write ability test device according to claim 1, wherein The control instruction includes a test strategy, and the test strategy includes multiple ways to verify the read-write performance of the chip under test. The test device is further used to determine sample data based on the test strategy.

3. The chip read-write ability testing device according to claim 1, wherein It is also used for: Determine the test result of the chip under test based on the matching condition of the sample data and the read data.

4. The chip read-write ability testing device according to claim 1, characterized in that, The connection path between the test device and the chip under test includes a first path, a second path, and a third path. The chip read-write ability test device is further used for: Transmit the address signal through the first path. The address signal includes a read-write address. Transmit the data signal through the second path. The data signal includes sample data or read data. Transmit the control signal through the third path. The control signal includes a read-write control signal and a clock signal.

5. The chip reading and writing ability testing device according to claim 1, wherein, The control instruction includes configuration information and a test instruction. The chip read-write ability test device includes a main control device and a test execution device, and the main control device is communicatively connected to the test execution device. The main control device is used to include: send the configuration information corresponding to the chip under test to the test execution device; send a test instruction to the test execution device. The test execution device is used to include: configure itself based on the configuration information; generate and send a control signal, an address signal, and sample data to the chip under test based on the test instruction, and receive the read data; determine the test result of the chip under test through the sample data and the read data.

6. The chip read-write ability testing device according to claim 5, wherein, The configuration information includes the read-write path bit width and the address range. The test execution device includes a general-purpose input / output module. The main control device is further used to send an initialization instruction to the test execution device. The test execution device is used to initialize the general-purpose input / output module based on the initialization instruction; configure the initialized general-purpose input / output module based on the read-write path bit width and the address range.

7. The chip read-write ability test device according to claim 5, characterized in that, The configuration information further includes the power supply voltage of the chip under test. The test execution device further includes a power supply module. The main control device is further used to send an initialization instruction to the test execution device. The test execution device is used to initialize the power supply module based on the initialization instruction; the power supply module is used to power on the chip under test based on the power supply voltage of the chip under test.

8. The chip read-write ability testing device according to claim 5, characterized in that The configuration information includes a clock selection signal; the test execution device further includes a timer; The main control device is further used to send an initialization instruction to the test execution device; The test execution device is used to initialize the timer based on the initialization instruction; When the clock selection signal is the first selection signal, the timer is used to synchronize the on-chip clock signal of the chip under test; when the clock selection signal is the second selection signal, the timer is used to generate a clock signal based on the operating frequency of the chip under test and send the clock signal to the chip under test.

9. The chip reading and writing ability test device according to claim 5, wherein The main control device is further used to send a query instruction to the test execution device; The test execution device is further used to send the test result of the chip under test and / or the test result that does not meet the preset conditions to the main control device based on the query instruction.

10. The chip reading and writing ability test device according to claim 5, wherein The main control device is further used to send a standby instruction to the test execution device; The test execution device is used to close the connection with the chip under test and power off the chip under test based on the standby instruction.

11. A method for testing the read and write capabilities of a chip, characterized in that, Applied to a chip reading and writing ability test device, the chip reading and writing ability test method includes: Generating and sending a control signal, an address signal, and sample data to the chip under test based on the received control instruction; the control instruction includes a clock selection signal; When the clock selection signal is the first selection signal, obtaining the on-chip clock signal of the chip under test and sending the control signal, the address signal, the sample data, and receiving the read data to the chip under test; wherein, the control signal includes a clock signal, and the clock signal is generated based on the on-chip clock signal; When the clock selection signal is the second selection signal, sending the control signal, the address signal, the sample data, and receiving the read data to the chip under test; wherein, the control signal includes a clock signal, and the clock signal is generated based on the operating frequency of the chip under test; Determining the test result of the chip under test through the sample data and the read data.

12. A computer-readable storage medium having a computer program stored thereon, characterized in that, The computer program, when executed by a processor, implements the chip reading and writing ability test method described in claim 11.

13. A chip read-write ability testing system, characterized in that, Including a chip under test and the chip reading and writing ability test device according to any one of claims 1 to 10; The chip under test uses a storage chip; the storage chip includes a clock selector, a configuration selector, an on-chip clock source, and a storage module; wherein: The clock selector is used to determine the working clock signal of the storage chip between the clock signal input from the chip reading and writing ability test device and the on-chip clock signal generated by the on-chip clock source based on the control signal received from the chip reading and writing ability test device; The configuration selector is used to set the on-chip clock source and / or the storage module based on the control signal received from the chip read / write ability test device; The on-chip clock source is used to generate at least one on-chip clock signal based on the setting of the configuration selector; The storage module is used to write the sample data and / or read data based on the control signal, address signal, sample data, and working clock signal received from the chip read / write ability test device.

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