Memory chip and semiconductor test system

Abstract

The invention relates to a memory chip and a semiconductor test system. The storage chip comprises a clock selector, a configuration selector, an on-chip clock source and a storage module; wherein the clock selector is used for determining a working clock signal of the storage chip in an external input clock signal and an on-chip clock signal generated by the on-chip clock source based on a received signal; the configuration selector is used for setting the on-chip clock source and / or the storage module based on the received signal; the on-chip clock source is used for generating at least one on-chip clock signal based on the setting of the configuration selector; and the storage module is used for writing and / or reading data based on the received signal and the work clock signal. By adopting the storage chip, the compatibility and the flexibility can be improved.

Description

Technical Field

[0001] This application relates to the technical field of memory, and particularly to a storage chip and a semiconductor test system. Background Art

[0002] A storage chip is an integrated circuit used to store programs and data, which can include SRAM (Static Random Access Memory), DRAM (Dynamic Random Access Memory), read-only memory, flash memory, etc. As the application fields of storage chips are increasing, users and manufacturers have higher and higher requirements for the performance of storage chips. However, it is very troublesome to test the read and write performance of storage chips. Since the speed of SRAM etc. is very fast, precise timing control is required during testing to ensure the correct reading and writing of data, which involves issues such as controlling the timing of addresses, data buses, and read / write signals. In addition, in the face of different test scenarios and requirements, the storage chip may also be restricted in its test working mode due to test equipment, such as affecting high-frequency testing. In traditional technologies, storage chips are difficult to meet the requirements of different test scenarios, and there are problems of poor accuracy, compatibility, and flexibility. Summary of the Invention

[0003] Based on this, it is necessary to provide a storage chip and a semiconductor test system that can meet the requirements of different test scenarios and improve accuracy, compatibility, and flexibility for the above technical problems.

[0004] In a first aspect, this application provides a storage chip, which includes a clock selector, a configuration selector, an on-chip clock source, and a storage module; where: The clock selector is used to determine the working clock signal of the storage chip between an external input clock signal and an on-chip clock signal generated by the on-chip clock source based on the received signal; The configuration selector is used to set the on-chip clock source and / or the storage module based on the received signal; The on-chip clock source is used to generate at least one on-chip clock signal based on the setting of the configuration selector; The storage module is used to write data and / or read data based on the received signal and the working clock signal.

[0005] In one embodiment, the received signal includes a data signal, an address signal, and a control signal; The storage chip further includes data pads, address pads, and control pads, which are used as external interfaces to transmit the data signal, the address signal, and the control signal respectively.

[0006] In one embodiment, the control signal includes an input clock signal and a clock selection signal; When the clock selection signal uses an external clock, the clock selector is used to receive the input clock signal and use the input clock signal as the working clock signal of the memory chip.

[0007] In one embodiment, the control signal further includes a clock output signal; When the clock selection signal uses an internal clock, the clock selector is used to receive the on-chip clock signal generated by the on-chip clock source and use the on-chip clock signal as the working clock signal of the memory chip; The working clock signal is further used as the clock output signal and output to an external device.

[0008] In one embodiment, the control signal further includes a configuration selection signal and a configuration input signal; When the configuration selection signal uses an input configuration, the configuration selector configures the on-chip clock source and / or the memory module based on the configuration input signal.

[0009] In one embodiment, the control signal further includes a configuration protocol signal; The memory chip further includes a configuration register for storing preset configuration information; When the configuration selection signal uses an internal configuration, the configuration register is used to receive the configuration protocol signal and transmit the configuration information to the configuration selector; the configuration selector is used to configure the on-chip clock source and / or the memory module based on the configuration information.

[0010] In one embodiment, the memory module includes a timing balance module and a plurality of memory banks, and the timing balance module is respectively connected to the plurality of memory banks; The timing balance module is used to receive the working clock signal and, after delaying and compensating the working clock signal based on a delay parameter, transmit it to the memory bank; The configuration selector further includes a delay configuration module, and the delay configuration module is used to configure the delay parameter of the timing balance module based on the received signal.

[0011] In one embodiment, the memory bank includes a plurality of memory bank units; The timing balance module includes a delay main body module and at least one delay adjustment module, and the delay adjustment module is connected to the output end of the delay main body module, where: The delay main body module is used to delay the input working clock signal for a first time and then output a first signal; The delay adjustment module is configured to receive corresponding delay parameters according to the delay requirement, delay the first signal by a second time, and output a second signal to the multiple repository units; The Chebyshev distance or Euclidean distance between the delay adjustment module and the multiple repository units is equal.

[0012] In one embodiment, the on-chip clock source includes a clock adjuster and multiple on-chip clock generators, and different on-chip clock generators generate clock signals with different frequencies; Based on the configuration selector, a target clock generator is determined from the multiple on-chip clock generators, and the clock signal generated by the target clock generator is output to the clock adjuster; The clock adjuster finely adjusts the clock signal generated by the target on-chip clock generator based on a control signal to obtain a finely adjusted clock signal corresponding to the control signal as the final clock signal.

[0013] In a second aspect, the present application provides a semiconductor test system, including a test device and the storage chip as described in the first aspect above.

[0014] For the above storage chip and semiconductor test system, based on the received signal, the clock selector determines the working clock signal of the storage chip among the external input clock signal and the on-chip clock signal generated by the on-chip clock source; the configuration selector sets the on-chip clock source and / or the storage module based on the received signal; the on-chip clock source generates at least one on-chip clock signal based on the setting of the configuration selector; the storage module writes and / or reads data based on the received signal and the working clock signal. The storage chip can flexibly switch between the external clock signal and the on-chip clock signal, realizing dynamic configuration and multi-mode compatibility, enabling the storage chip to adapt to a variety of different test scenarios, achieving precise timing control under different test working scenarios, and thus achieving the effects of improving accuracy, compatibility, and flexibility. Description of the Drawings

[0015] Figure 1 It is a structural block diagram of a storage chip in one embodiment; Figure 2 It is a structural block diagram of a storage chip in another embodiment; Figure 3 It is a test environment diagram of a storage chip in one embodiment; Figure 4 It is a schematic structural diagram of a clock adjuster provided by an embodiment of the present application; Figure 5 It is a circuit diagram of a current source component provided by an embodiment of the present application; Figure 6It is a schematic diagram of a ring oscillator provided by an embodiment of the present application; Figure 7 It is a schematic circuit diagram of multiple on-chip clock generators provided by an embodiment of the present application; Figure 8 It is a schematic overall structure diagram of an on-chip clock signal generation circuit provided by an embodiment of the present application. Detailed implementation manners

[0016] In order to make the objectives, technical solutions and advantages of the present application clearer, the present application will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.

[0017] Embodiment 1 As Figure 1 shown, a storage chip is provided. The storage chip includes a clock selector 1, a configuration selector 2, an on-chip clock source 3, and a storage module 4; wherein: The clock selector 1 is configured to determine the working clock signal of the storage chip from an external input clock signal and an on-chip clock signal generated by the on-chip clock source 3 based on the received signal; The configuration selector 2 is configured to set the on-chip clock source 3 and / or the storage module 4 based on the received signal; The on-chip clock source 3 is configured to generate at least one on-chip clock signal based on the setting of the configuration selector 2; The storage module 4 is configured to write data and / or read data based on the received signal and the working clock signal.

[0018] Among them, the clock selector 1 can determine the clock signal for the read and write operations of the storage chip according to the received signal, and can dynamically select the working clock signal from at least two clock signal sources according to the input signal, so as to provide multi-mode compatibility. The received signal can be a clock signal from outside the storage chip or a clock signal of other modules inside the storage chip.

[0019] Exemplarily, the clock selector 1 may include a logic circuit and a signal port. The signal port is used to receive the signal, and the logic circuit is used to judge the result according to the received signal. Further, the clock selector 1 may be one or more of components such as a multiplexer, an analog switch, or a digital logic gate. Exemplarily, when the clock selector 1 receives a signal, it judges the required clock signal source based on this signal, and according to the input port of the selected clock, the selected clock signal source is used as the working clock signal of the storage chip.

[0020] The configuration selector 2 is a circuit component capable of setting or adjusting the on-chip clock source 3 and the storage module 4 according to the received signal. Exemplarily, the configuration selector 2 may include one or more components such as registers, decoders, and control logic circuits. Exemplarily, the configuration selector 2 can convert the received signal into specific setting instructions. Further, the setting of the on-chip clock source 3 by the configuration selector 2 may include setting the enabling state, frequency, phase, etc. of the on-chip clock source 3, and the setting of the storage module 4 may include setting the enabling state, delay parameter, read speed, write speed, power consumption mode, etc. of the storage module 4.

[0021] Exemplarily, the configuration selector 2 can receive the configuration-related signal and parse its content, and then send the parsing result to the on-chip clock source 3 or the storage module 4. Thus, the storage chip can adjust the working mode according to the actual needs, improving flexibility and energy efficiency.

[0022] The on-chip clock source 3 can be a clock signal generation module integrated inside the chip for providing a stable clock signal. Exemplarily, the on-chip clock source 3 may include oscillators, such as RC oscillators, LC oscillators, crystal oscillators, etc., so that the basic clock signal can be generated by the oscillators.

[0023] Further, the on-chip clock source 3 may also include a frequency divider for generating clock signals with different frequencies according to the basic clock signal. The on-chip clock source 3 can provide a clock signal independent of the external clock source, enhancing the robustness and autonomy of the system, and at the same time supporting the output of clock signals with multiple frequencies to meet the requirements of different application scenarios. Exemplarily, the frequency divider can divide or multiply the basic clock signal according to the configuration selection to output the on-chip clock signal, thereby reducing the dependence on the external clock signal and improving the reliability of the system.

[0024] The storage module 4 can be a module in the storage chip for storing data and programs. The storage module 4 may include a storage cell array, such as DRAM storage cells, SRAM storage cells, flash storage cells, etc., and control the implementation of data writing and reading in the storage cells. Exemplarily, the storage module 4 can adjust the read and write processes according to the working clock signal and the settings of the configuration selector 2. Further, the storage module 4 may also include an address decoder and a data input / output buffer. Among them, the address decoder is used to locate the target storage cell, and the data input / output buffer can be used to implement data transmission.

[0025] A storage chip provided in this embodiment determines the working clock signal of the storage chip from the externally received input clock signal and the on-chip clock signal generated by the on-chip clock source 3 through a clock selector 1 based on the received signal; a configuration selector 2 sets the on-chip clock source 3 and / or the storage module 4 based on the received signal; the on-chip clock source 3 generates at least one on-chip clock signal based on the setting of the configuration selector 2; the storage module 4 writes and / or reads data based on the received signal and the working clock signal. The storage chip can flexibly switch between the external clock signal and the on-chip clock signal, achieving dynamic configuration and multi-mode compatibility, enabling the storage chip to adapt to a variety of application scenarios, thereby improving the compatibility and flexibility.

[0026] In one embodiment, the received signals include data signals, address signals, and control signals; the storage chip further includes data pads, address pads, and control pads for respectively transmitting data signals, address signals, and control signals as external interfaces.

[0027] The external interfaces of the storage chip are set in three groups: the data path, that is, the data signals for writing / reading, is transmitted by the data pads; the address path, that is, the addresses for writing / reading data, is transmitted by the address pads; the control path, that is, the control signals required for writing / reading operations, is transmitted by the control pads. In different application scenarios, some of the data signals, address signals, and / or control signals can also be selectively generated on the chip and some are input through these external interfaces. This application does not require that all data signals, address signals, and control signals are correspondingly input through external interfaces. For example, the clock signal in the control signals and the address signals, etc., can also be implemented by setting signal generation modules on the chip, and this application does not make specific limitations.

[0028] A storage chip provided in this embodiment provides an efficient data transmission channel through the data pads to achieve data interaction between the storage chip and external devices; provides accurate address positioning through the address pads to achieve effective management of large-scale storage spaces by the storage chip; and enables the storage chip to adjust its working mode according to external instructions through the flexible control of the control pads, achieving the effect of improving the adaptability and flexibility of the storage chip.

[0029] In one embodiment, the control signals include an input clock signal and a clock selection signal; When the clock selection signal is to use an external clock, the clock selector is used to receive the input clock signal and use the input clock signal as the working clock signal of the storage chip.

[0030] Among them, the input clock signal can be a periodic clock signal provided by an external device, which is used to drive the write and read operations of the memory chip. Exemplarily, the input clock signal can be transmitted to the clock selector through a control pad. The frequency and phase of the input clock signal can be determined and generated by the external device. The input clock signal can provide an externally reliable clock source for the memory chip to control the read and write operations of the memory cells in the memory chip.

[0031] Exemplarily, the external device generates the input clock signal and transmits it to the clock selector through a control pad. When the clock selection signal is to use the external clock, the clock selector uses the input clock signal as the working clock signal of the memory chip.

[0032] The clock selection signal can be a control signal used to indicate that the clock selector selects an external input clock signal or an on-chip clock signal as the working clock signal of the memory chip. Exemplarily, this signal can be transmitted to the clock selector through a control pad. Exemplarily, when selecting one of the two clock signals as the working clock signal, the form of the clock selection signal can be a logic level distinguished by high and low levels. Exemplarily, when selecting one of two or more clock signals as the working clock signal, the form of the clock selection signal can also be distinguished by an encoded signal for selection.

[0033] The memory chip provided in this embodiment can realize the clock signal selection function by dynamically adjusting the selection of the working clock signal according to the indication of the clock selection signal by the clock selector, thereby enhancing the flexibility and robustness of the memory chip operation, and achieving the effect of improving the adaptability and flexibility of the memory chip.

[0034] In one embodiment, the control signal further includes a clock output signal; When the clock selection signal is to use the internal clock, the clock selector is used to receive the on-chip clock signal generated by the on-chip clock source and use the on-chip clock signal as the working clock signal of the memory chip; The working clock signal is further used as the clock output signal and output to an external device.

[0035] Among them, the clock selection signal can be a control signal used to indicate that the clock selector selects an external input clock signal or an on-chip clock signal as the working clock signal of the memory chip. Regarding the form of the clock selection signal, this embodiment will not elaborate here.

[0036] When the clock selection signal uses the internal clock signal, the on-chip clock signal is generated by the on-chip clock source. The frequency and phase of the on-chip clock signal can be determined and generated according to the settings of the configuration selector. As the clock source signal generated inside the memory chip, the on-chip clock signal is used to synchronize the operations of the external test device's output and capture signals with the working clock signal of the memory chip by providing it as the clock output signal to the external test device. For example, since the SRAM circuit is a synchronous clock circuit and the start of read and write operations is triggered by a specific clock edge, the actions of the external test device need to be driven and triggered by the same clock.

[0037] A memory chip provided in this embodiment, the clock signal generated by the on-chip clock source is used for the internal read and write operations of the memory chip and can be output as the clock signal for external devices, which can ensure a certain degree of test flexibility, improve the clock quality at the same time, thus significantly enhancing the integration and autonomy of the system, optimizing resource utilization, and being compatible with various application scenarios requiring master-slave clock synchronization, achieving the effect of improving the adaptability and flexibility of the memory chip.

[0038] In one embodiment, the control signal further includes a configuration selection signal and a configuration input signal; When the configuration selection signal is for using the input configuration, the configuration selector configures the on-chip clock source and / or the memory module based on the configuration input signal.

[0039] Among them, the configuration selection signal can be used to indicate that the configuration selector configures using the configuration parameters of external input or internal storage. The configuration selection signal can be generated by an external device and transmitted to the configuration selector through the control pad.

[0040] Exemplarily, after the external device generates the configuration selection signal, the signal is transmitted to the configuration selector through the control pad. The configuration selector analyzes the configuration selection signal to determine whether to use the externally input configuration input signal for parameter configuration currently. If the configuration selection signal indicates to use the input configuration, the configuration selector can configure the on-chip clock source and / or the memory module based on the configuration input signal.

[0041] The configuration input signal can include the configuration parameters provided by the external device for indicating the settings of the on-chip clock source and / or the memory module. Exemplarily, the configuration input signal can contain configuration parameters such as the frequency, phase, and delay of the clock signal.

[0042] By receiving a configuration input signal sent by an external device, determining whether to use the configuration input signal according to a configuration selection signal, and applying configuration parameters to actual operations. When the configuration selection signal indicates to adopt an external input configuration, the configuration selector parses the configuration input signal, and can send the parsing result to an on-chip clock source and / or a storage module. These modules adjust their working states according to the received configuration parameters, which can better improve the test frequency and better reflect the chip performance.

[0043] The configuration selector can receive a configuration selection signal and / or a configuration input signal, and determine whether to adopt an external input configuration currently through internal logic. Exemplarily, the configuration selector can include a decoding module and an output module, which are respectively used for parsing signals and generating configuration instructions.

[0044] A storage chip provided in this embodiment allows the storage chip to select whether to adopt configuration parameters of external input according to actual needs through a configuration selection signal, which can improve the flexibility of the storage chip; the storage chip dynamically adjusts the working states of the on-chip clock source and / or the storage module according to the requirements of external devices, which can enhance the adaptability of the storage chip, so as to achieve the effect of improving the adaptability and flexibility of the storage chip.

[0045] In one of the embodiments, the control signal further includes a configuration protocol signal; The storage chip further includes a configuration register for storing preset configuration information; When the configuration selection signal is to adopt an internal configuration, the configuration register is used to receive the configuration protocol signal and transmit the configuration information to the configuration selector; the configuration selector is used to configure the on-chip clock source and / or the storage module based on the configuration information.

[0046] Among them, the configuration protocol signal can be a control signal used to instruct the configuration register inside the storage chip to transmit preset configuration information to the configuration selector. Exemplarily, the configuration protocol signal can be generated by an external device and transmitted to the configuration register.

[0047] The configuration register can be a storage unit for storing configuration information. Further, the configuration information can be stored based on the configuration protocol signal. Exemplarily, the configuration register can be composed of flip-flops and latches.

[0048] When the configuration selection signal indicates to adopt an internal configuration, the configuration register can receive the configuration protocol signal, store the configuration information in the configuration protocol signal, and transmit the configuration information to the configuration selector. The configuration selector configures the on-chip clock source and / or the storage module according to the configuration information.

[0049] A storage chip provided in this embodiment can adjust the output of the configuration register by configuring protocol signals, providing flexible internal configuration switching capabilities, enabling the storage chip to dynamically adjust its working mode according to preset configuration information. The configuration register stores the configuration information and can operate independently without external input, reducing the dependence on external devices, thereby achieving the effect of improving the adaptability and flexibility of the storage chip.

[0050] In one of the embodiments, the storage module includes a timing balance module and multiple memory banks, and the timing balance module is respectively connected to the multiple memory banks; The timing balance module is configured to receive a working clock signal and transmit the working clock signal to the memory bank after performing delay compensation on the working clock signal based on a delay parameter; The configuration selector further includes a delay configuration module, and the delay configuration module is configured to configure the delay parameter of the timing balance module based on the received signal.

[0051] Among them, the timing balance module can be a component for performing delay compensation on the working clock signal to ensure the timing consistency between multiple memory banks. The timing balance module can receive the working clock signal from the clock selector and adjust the input working clock signal according to the delay parameter set by the configuration selector, and then output the clock signal after delay compensation.

[0052] Exemplarily, the timing balance module can receive the working clock signal from the clock selector and perform delay compensation on the working clock signal through a delay unit according to the currently set delay parameter, and transmit the working clock signal after delay compensation to multiple memory banks.

[0053] The configuration selector further includes a delay configuration module, and the delay configuration module can be used to configure the delay parameter of the timing balance module according to the received signal. Further, the configuration selector configures a selection signal, and resolves the delay parameter value according to the configuration input signal or the configuration information provided by the configuration register, and sends the delay parameter value to the timing balance module to adjust its delay compensation amount. Exemplarily, the delay configuration module can include a register and a decoder, etc. Among them, the register is used to store the delay parameter, and the decoder can be a binary decoder, a multiplex decoder, etc., and its function is to resolve the delay parameter in the configuration information.

[0054] A storage chip provided in this embodiment parses configuration information through a delay configuration module and sends delay parameters. A timing balance module performs delay compensation on the working clock signal according to the delay parameters, which can ensure that multiple memory banks work in the same clock domain, thereby reducing data errors or performance degradation caused by clock offset, and thus achieving the technical effects of improving timing consistency and enhancing chip flexibility.

[0055] In one embodiment, the memory bank includes a plurality of memory bank units; The timing balance module includes a delay main body module and at least one delay adjustment module, and the delay adjustment module is connected to the output end of the delay main body module, where: The delay main body module is configured to delay the input working clock signal for a first time and then output a first signal; The delay adjustment module is configured to receive corresponding delay parameters according to the delay requirement, delay the first signal for a second time, and then output a second signal to the plurality of memory bank units; The Chebyshev distance or Euclidean distance between the delay adjustment module and the plurality of memory bank units is equal.

[0056] The delay main body module can be a component for performing preliminary delay compensation on the input working clock signal, so that the delays of the clock signal to each memory bank are the same, providing a unified time reference for the delay adjustment module. The delay adjustment module is used to solve the delay problem between different memory bank units in the same memory bank; generally, one delay adjustment module is set in each memory bank, and the Chebyshev distance or Euclidean distance from the delay adjustment module to each memory bank unit in the memory bank is made equal.

[0057] A storage chip provided in this embodiment provides basic delay compensation through a delay main body module to ensure that subsequent modules are adjusted based on a unified time reference, and a delay adjustment module performs further delay compensation to optimize the timing consistency of multiple memory bank units. By optimizing the structural design and physical layout of the timing balance module, the delay problem in the clock signal transmission process can be solved, thereby improving the timing consistency and reliability between different memory bank units, optimizing the resource utilization efficiency, and achieving the technical effects of improving timing consistency and enhancing chip flexibility.

[0058] In one embodiment, the on-chip clock source includes a clock adjuster and a plurality of on-chip clock generators, and different on-chip clock generators generate clock signals with different frequencies; Based on the configuration selector, a target clock generator is determined from the plurality of on-chip clock generators, and the clock signal generated by the target clock generator is output to the clock adjuster; The clock adjuster finely adjusts the clock signal generated by the target on-chip clock generator based on a control signal to obtain the finely adjusted clock signal corresponding to the control signal, which is used as the final clock signal.

[0059] Among them, the on-chip clock source includes multiple on-chip clock generators, and the on-chip clock generators can be used to generate clock signals with different frequencies or different frequency ranges, so as to provide clock signals with multiple frequencies for the storage chip to meet the requirements of different scenarios. Exemplarily, the on-chip clock generator may include an oscillator and a frequency divider. Among them, the oscillator generates a basic clock signal, and the frequency divider divides or multiplies the basic clock signal according to the settings of the configuration selector and outputs the clock signal to the clock adjuster.

[0060] The clock adjuster is used to finely adjust the clock signal generated by the target on-chip clock generator, so as to improve the accuracy and stability of the clock signal. Exemplarily, the clock adjuster may include a digital delay locked loop (DLL), an analog delay locked loop (ADLL), a programmable delay unit, etc.

[0061] A storage chip provided in this embodiment has an on-chip clock source built-in, can provide the generation of multi-frequency clock signals through multiple on-chip clock generators for selection, and can finely adjust the selected clock signal through a clock adjuster, so as to improve the accuracy and stability of the clock signal, achieving the technical effects of improving timing consistency and enhancing chip stability.

[0062] To more clearly elaborate on the technical solution of the present application, this embodiment also provides a detailed embodiment in a specific application scenario.

[0063] In one embodiment, as Figure 2 shown, a storage chip is provided, which is applied to a test environment as Figure 3 shown, includes SRAM storage units, includes three groups of external interfaces, includes a data path for transmitting the written / read data, an address path for transmitting the address of the written / read data, and a control path. Among them, the signals transmitted by the control path at least include: a read / write control signal for controlling whether the current operation is a write or a read, and at least one clock signal; in addition, the signals transmitted by the control path may further include: (1) a configuration protocol signal for configuring the configuration registers inside the chip; (2) a configuration selection signal and a configuration input signal; (3) a clock selection signal, a clock input signal, and a clock output signal.

[0064] In this embodiment, the storage chip is an SRAM chip controlled by a clock signal. The clock signal can be generated inside the SRAM chip, and correspondingly, the SRAM chip will output the internally generated clock signal outside the chip; the clock signal can also be input from the outside.

[0065] The storage chip in this embodiment includes multiple banks, each bank includes at least one bitcell array, each bitcell array includes at least one bitcell, multiple bitcells in the same bitcell array form a bitcell array, and each bitcell in the bitcell array can share the same control logic circuit to achieve data storage. Since the area of the bank is large and may be scattered in various corners of the chip, and each bitcell array requires data, address, delay selection, and system clock, in this embodiment, in order to make the delay of the above signals reaching each bitcell array as consistent as possible, the timing balance module is used to solve the delay problem of the clock signal, so that the delay of the above signals reaching each bitcell is as consistent as possible.

[0066] The storage chip also includes a clock selector, which selects one of the clock input and the on-chip clock as the working clock signal according to the clock selection signal. When the clock selection signal is to use an external clock, the clock selector is used to receive the input clock signal and use the input clock signal as the working clock signal of the storage chip. When the clock selection signal is to use an internal clock, the clock selector is used to receive the on-chip clock signal generated by the on-chip clock source and use the on-chip clock signal as the working clock signal of the storage chip; the working clock signal is also used as the clock output signal and output to an external test device.

[0067] The storage chip also includes a configuration selector and a configuration register, and the configuration register is used to store preset configuration information. When the configuration selection signal is to use an input configuration, the configuration selector configures the on-chip clock source and / or the storage module based on the configuration input signal. When the configuration selection signal is to use an internal configuration, the configuration register is used to receive the configuration protocol signal and transmit the configuration information to the configuration selector; the configuration selector is used to configure the on-chip clock source and / or the storage module based on the configuration information.

[0068] According to the differences in the clock selection signal and the configuration selection signal in the control path, the storage chip in this embodiment can implement at least 4 working modes: Working mode 1: The clock selection signal selects to use the clock input as the working clock signal of the storage chip, the configuration selection signal selects to use the input configuration, and the configuration selector configures the on-chip clock source and / or the storage module based on the configuration input signal.

[0069] In this mode, since the configuration selection signal selects to use the input configuration, the configuration information output by the configuration register will be ignored internally. In this mode, the working content of the configuration protocol and the configuration register will not be referenced.

[0070] Similarly, when the clock selection signal uses the clock input signal, the on-chip clock will be ignored. Correspondingly, the operation of the on-chip clock source will be either disabled or ignored.

[0071] The signals input to the "Timing Balance Module" include: data signals and address signals; the working clock signal, that is, the system clock output by the clock input signal via the clock selector; and the configuration input signal, that is, the delay selection signal output by the clock source and the delay configuration input via the configuration selector.

[0072] This working mode belongs to the basic working mode. The test signals, control signals, and clock signals are directly driven by an external test device, with high test flexibility. The storage chip will not be restricted by the test device, but it cannot perform high-frequency tests, and there is a greater sacrifice in test speed and chip area.

[0073] Working Mode 2: The clock selection signal selects to use the clock input signal as the working clock signal of the system, and the configuration selection signal selects to use the internal configuration.

[0074] In this mode, when the clock selection signal uses the clock input signal, the on-chip clock will be ignored. Correspondingly, the operation of the on-chip clock source will be either disabled or ignored.

[0075] Since the configuration selection signal selects to use the internal configuration, that is, the internal signals of the clock source and the delay configuration, correspondingly, through the configuration protocol signal, the corresponding configuration parameters are transmitted to the configuration register. The configuration selector configures the on-chip clock source and / or the storage module based on the configuration parameters.

[0076] The signals input to the timing balance module include: data signals and address signals; the working clock signal, that is, the system signal output by the clock input signal via the clock selector; and the delay selection signal output by the configuration protocol signal via the configuration register and the configuration selector.

[0077] In this working mode, the external test device provides the clock and test signals, and the storage chip internally provides the control signals. While ensuring test flexibility, more control bits can be provided and the number of IO ports for configuration input can be saved, but the test preparation time is sacrificed.

[0078] Working Mode 3: The clock selection signal selects the on-chip clock as the working clock signal of the system, that is, the on-chip clock signal is used as the working clock signal of the system. The configuration selection signal selects to use the input configuration. The configuration selector configures the on-chip clock source and / or the storage module based on the configuration input signal.

[0079] In this mode, since the configuration selection signal selects the input configuration, correspondingly, the configuration information output by the configuration register will be ignored internally. In this mode, the working content of the configuration protocol and the configuration register will not be referenced. Since the clock selection signal selects the on-chip clock signal, at this time, multiple on-chip clock generators in the on-chip clock source generate multiple clock sources, and the clock source selection signal output by the configuration selector determines which clock signal generated by the on-chip clock generator is output to the on-chip clock, that is, used as the on-chip clock signal.

[0080] The signals input to the timing balance module include: data signals and address signals; the working clock signal, that is, the system clock output by the on-chip clock signal via the clock selector; and the configuration input signal, that is, the delay selection signal output by the clock source and the delay configuration input via the configuration selector.

[0081] In this working mode, the clock signal is generated inside the storage chip, and the external test device provides test signals and control signals, which can ensure a certain degree of test flexibility and improve the quality of the clock signal at the same time. However, the clock synchronization between the external test device and the inside of the storage chip and the real-time requirements of the external test device are relatively high.

[0082] Working mode 4: The clock selection signal selects the on-chip clock as the working clock signal of the system, and the configuration selection signal selects the internal configuration.

[0083] In this mode, since the configuration selection signal selects to use the internal configuration, that is, the internal signals of the clock source and the delay configuration, therefore, the corresponding configuration parameters must be transmitted to the configuration register through the configuration protocol signal. The configuration selector configures the on-chip clock source and / or the storage module based on the configuration parameters. Since the clock selection signal selects to use the on-chip clock signal, at this time, multiple on-chip clock generators in the on-chip clock source generate multiple clock sources, and the clock source selection signal output by the configuration selector determines which clock signal generated by the on-chip clock generator is output to the on-chip clock, that is, used as the on-chip clock signal.

[0084] The signals input to the timing balance module include: data signals and address signals; the working clock signal, that is, the system clock output by the on-chip clock signal via the clock selector; and the delay selection signal output by the configuration protocol signal via the configuration register and the configuration selector.

[0085] In this working mode, the test signal, control signal, and clock signal are all generated inside the memory chip, which can greatly improve the test frequency and better reflect the read / write performance of the chip. However, it sacrifices test flexibility and requires additional design to complete the test and transmit the test results.

[0086] The memory chip design in this embodiment can perfectly support at least four of the above working modes, can match the read / write test requirements of different scenarios, support high-frequency tests, can achieve precise timing control, and can be widely applied to the read / write tests of different memory chips.

[0087] Furthermore, on this basis, the on-chip clock source further includes a data control oscillator. A data control oscillator (DCO, Digital Controlled Oscillator) is an oscillator based on digital signal processing technology. Its working principle is to adjust the frequency of the oscillator by controlling the frequency of the digital signal. As an on-chip clock generation circuit, the DCO can provide different frequency ranges. In this embodiment, the internal generation of the clock signal is realized based on the DCO to ensure that the frequency of the clock signal generated on the chip is adapted to the corresponding operating frequency of the chip.

[0088] The on-chip clock source includes multiple on-chip clock generators and a clock adjuster. Different on-chip clock generators generate clock signals with different frequencies, and the clock signal generated by the target clock generator is output to the clock adjuster; the clock adjuster finely adjusts the clock signal generated by the target on-chip clock generator based on the control signal to obtain the finely adjusted clock signal corresponding to the control signal as the final clock signal. As Figure 8 shown is the overall structural schematic diagram of an on-chip clock signal generation circuit in this embodiment. As Figure 7 shown, digital control is used for path selection, and coarse frequency adjustment is realized through the effective number of stages in the ring oscillator circuit, thereby generating multiple frequencies. At this time, the adjustable frequency range is wide. The single-stage delay of the ring oscillator in the clock adjuster is controlled based on the control current signal to finely adjust the clock signal using the ring oscillator and obtain the oscillation frequency of the finely adjusted clock signal.

[0089] Specifically, the generation of the clock signal by the on-chip clock source may include the following steps: Step S201: Determine the target on-chip clock generator from multiple on-chip clock generators based on the operating frequency of the chip.

[0090] Among them, the frequency of the clock signal generated by the target on-chip clock generator is within the preset frequency range; the operating frequency of the chip is within the preset frequency range, that is, this preset frequency range is preset based on the operating frequency of the chip, and the operating frequency of the chip will be within this preset frequency range.

[0091] The on-chip clock source may include multiple on-chip clock generators and clock regulators. Different on-chip clock generators generate clock signals with different frequencies, enabling the storage chip to operate at different frequencies.

[0092] Generally, a preset frequency range can be determined according to the operating frequency required by the storage chip. Specifically, the operating frequency of the storage chip is within the preset frequency range. Further, the on-chip clock generator whose clock signal frequency is within the preset frequency range among the multiple on-chip clock generators is determined as the target on-chip clock generator, so that the frequency of the clock signal generated by the target on-chip clock generator is within the same frequency range as the operating frequency of the storage chip, achieving a coarse adjustment of the clock signal on the storage chip.

[0093] Step S202: Input multiple control signals into the clock regulator to finely adjust the clock signal, and obtain the oscillation frequency of the finely adjusted clock signal corresponding to each control signal.

[0094] The clock regulator includes adjusting a single-stage delay based on the control signal.

[0095] Further, input multiple control signals into the clock regulator. The single-stage delay of the clock regulator corresponding to each control signal is different. Thus, by adjusting the single-stage delay of the clock regulator through multiple control signals, the clock signal output by the target on-chip clock generator is adjusted, and the oscillation frequency of the clock signal corresponding to each control signal is obtained.

[0096] Step S203: Determine the target control signal based on the operating frequency of the storage chip and the oscillation frequency of the finely adjusted clock signal corresponding to each control signal.

[0097] Further, the control signal corresponding to the oscillation frequency of the clock signal that is the same as or within the preset error range of the operating frequency of the storage chip is determined as the target control signal.

[0098] Step S204: Control the generation of the final clock signal based on the target on-chip clock generator and the target control signal.

[0099] Further, determine the target on-chip clock generator from multiple on-chip clock generators, and input the target control signal into the clock regulator. Thus, the clock signal generated by the target on-chip clock generator is finely adjusted by the clock regulator to obtain the final clock signal, so that the oscillation frequency of the final clock signal can be the same as or within the preset error range of the operating frequency of the chip.

[0100] In the above implementation process, according to the operating frequency of the memory chip, a target on-chip clock generator is determined from multiple on-chip clock generators, so that the frequency of the clock signal generated by the target on-chip clock generator is in the same frequency range as the operating frequency of the memory chip, achieving coarse adjustment of the clock signal. Further, multiple control signals are input into the clock adjuster, and the single-stage delay of the clock adjuster is adjusted by each control signal, thereby realizing the adjustment of the clock signal output by the target on-chip clock generator. By determining the target control signal according to the operating frequency of the memory chip and the oscillation frequency of the fine-tuned clock signal corresponding to each control signal, fine adjustment of the clock signal is achieved, ensuring that the frequency of the finally output clock signal is consistent with the operating frequency of the chip or within a preset error range.

[0101] Further, the control signal is a digital signal. As Figure 4 shown, the clock adjuster includes a digitally controlled current source, a ring oscillator, and a feedback loop. The digital signal is input into the digitally controlled current source, and a control current signal is output. The control current signal can control the output frequency of the ring oscillator by controlling the single-stage delay of the ring oscillator. Inputting multiple control signals into the clock adjuster to finely adjust the clock signal and obtaining the oscillation frequency of the fine-tuned clock signal corresponding to each control signal may include the following steps: Step 1: The current source component in the clock adjuster converts the digital signal into a control current signal.

[0102] Step 2: Based on the control current signal, control the single-stage delay of the ring oscillator in the clock adjuster to finely adjust the clock signal by using the ring oscillator and obtain the oscillation frequency of the fine-tuned clock signal.

[0103] Exemplarily, the control signal can be a digital signal, and the frequency formula of the ring oscillator is:

[0104] where f osc represents the frequency of the ring oscillator, n represents the number of stages of the ring oscillator, and τ represents the single-stage delay of the ring oscillator. It can be seen from this that the frequency of the ring oscillator can be adjusted by controlling its number of stages and single-stage delay.

[0105] Specifically, after multiple digital signals are input into the clock adjuster, the current source component in the clock adjuster converts the digital signals into control current signals. Further, the single-stage delay of the ring oscillator in the clock adjuster is controlled by the control current signal, and the fine adjustment of the clock signal is achieved by adjusting the single-stage delay of the ring oscillator, and the oscillation frequency of the fine-tuned clock signal corresponding to each digital signal is obtained.

[0106] In the above implementation process, the digital signal is converted into a control current signal by the current source component in the clock adjuster, and the single-stage delay of the ring oscillator in the clock regulator is controlled by the control current signal, so as to realize the fine-tuning of the clock signal by the ring oscillator.

[0107] Further, based on the operating frequency of the chip and the oscillation frequency of the fine-tuned clock signal corresponding to each control signal, a target control signal is determined, including: determining the control signal corresponding to the clock signal whose oscillation frequency is the same as or within a preset error range among the oscillation frequencies of the fine-tuned clock signals corresponding to multiple control signals as the target control signal.

[0108] Specifically, when determining the target control signal, the control signal corresponding to the clock signal whose oscillation frequency is the same as or within a preset error range among the oscillation frequencies of the fine-tuned clock signals corresponding to multiple control signals is determined as the target control signal, so that the frequency of the clock signal generated by the target on-chip clock generator is the same as or within a preset error range of the operating frequency of the chip, ensuring that the clock signal frequency of the on-chip generator in the chip is within the operating frequency range of the corresponding chip.

[0109] Further, when controlling the single-stage delay of the ring oscillator in the clock adjuster based on the control current signal to fine-tune the clock signal by using the ring oscillator and obtain the oscillation frequency of the fine-tuned clock signal, the following steps may be included: Step 1: Perform a frequency reduction process on the oscillation frequency to obtain the frequency-reduced oscillation frequency.

[0110] Step 2: Perform a duplicate removal process on the frequency-reduced oscillation frequency to obtain the oscillation frequency after duplicate removal.

[0111] Step 3: Convert the oscillation frequency after duplicate removal into a feedback current signal through the feedback loop in the clock adjuster.

[0112] Step 4: Based on the control current signal and the feedback current signal, control the single-stage delay of the ring oscillator in the clock adjuster to fine-tune the clock signal by using the ring oscillator and obtain the oscillation frequency of the fine-tuned clock signal.

[0113] In order to use a digitally controlled current source to implement a relatively linear oscillator, the DCO function can be improved through negative feedback technology. The feedback loop is formed by sampling the output and mixing it with the input. Since the frequency of the oscillator output is too high, there is no time to directly sample it through capacitor charging and discharging.

[0114] Specifically, a frequency divider circuit can be used to reduce the frequency of the output of the ring oscillator, obtain the reduced-frequency oscillation frequency, and perform de-duplication processing on the reduced-frequency oscillation frequency through a non-overlapping pulse generation circuit to obtain the oscillation frequency. Further, the de-duplicated oscillation frequency is converted into a feedback current signal through the feedback loop in the clock adjuster.

[0115] Furthermore, the control current signal and the feedback current signal are combined, and the combined signal is used to control the single-stage delay of the ring oscillator in the clock adjuster, so as to finely adjust the clock signal by using the ring oscillator and obtain the oscillation frequency of the finely adjusted clock signal.

[0116] Determining the target control signal based on the operating frequency of the chip and the oscillation frequency of the clock signal corresponding to each control signal further includes: the oscillation frequency stability of the finely adjusted clock signal is higher than a preset value.

[0117] Further, when the clock signal of the ring oscillator is finely adjusted, the oscillation frequency stability of the finely adjusted clock signal is higher than a preset value. Specifically, the preset value can be specifically determined according to the operating frequency of the chip, application scenario requirements, etc.

[0118] In the above implementation process, the frequency divider circuit is used to reduce the frequency of the output of the ring oscillator, and the non-overlapping pulse generation circuit performs de-duplication processing on the reduced-frequency oscillation frequency, and the de-duplicated oscillation frequency is converted into a feedback current signal through the feedback loop in the clock adjuster. Further, the control current signal and the feedback current signal are combined, and the combined signal is used to control the single-stage delay of the ring oscillator in the clock adjuster, realizing the loop adjustment of the clock adjuster.

[0119] Furthermore, the current source component is also used to generate multiple different proportional currents under the control of a digital signal.

[0120] The current source component includes: a current source, a matching transistor, and a numerically controlled transistor. The first end of the matching transistor is connected to the current source, the second end of the matching transistor is connected to the numerically controlled transistor, and the third end of the matching transistor is connected to the ring oscillator. The matching transistor is used to stabilize the current output by the current source and input the stabilized current into the ring oscillator through the third end of the matching transistor. The first end of the numerically controlled transistor accesses a first digital signal, and the second end of the numerically controlled transistor is connected to the second end of the matching transistor. The numerically controlled transistor is used to control the magnitude of the current output by the matching transistor based on the first digital signal.

[0121] Specifically, the current source component generates multiple different proportional currents under the control of a digital signal. Figure 5 is a circuit diagram of a current source component provided by an embodiment of the present application, as Figure 5The current source component within the large blue dashed-line box shown includes a current source, a matching transistor (black solid-line box), and a numerically controlled transistor (yellow dashed-line box). The matching transistor within the black solid-line box replicates the current from the stable current source in a binary manner through a current mirror. The numerically controlled transistor within the yellow dashed-line box includes numerically controlled parallel binary weighted transistors. By using a digital code to turn the transistors on / off, the current passing through Ms1 will be determined by the input digital code. The output node is connected to a single transistor (Ms2) that is always on, and the numerically controlled transistor is separated from this node, which helps to reduce the impact of voltage level variations in the digital control signal on the current value. The size of the numerically controlled transistor increases in a binary manner. This section takes eight digital signals C0, C1, …, C8 as controllable signal inputs, corresponding to inputs of 512 levels from 00000000 to 11111111, and can provide 512 different currents.

[0122] In the above implementation process, through the current source component composed of a current source, a matching transistor, and a numerically controlled transistor, a current source controlled by digital signals generates different proportional currents.

[0123] Furthermore, the ring oscillator in the clock adjuster includes multiple differential units. Each differential unit includes a latch and two inverters for driving current into the latch. The latch includes two cross-coupled inverters.

[0124] Exemplarily, Figure 6 is a schematic diagram of a ring oscillator provided by an embodiment of the present application. As Figure 6 shown, the oscillator in (a) has a ring structure and is composed of four differential units. Figure 6 Among them, (c) is the current source component. Each differential unit (b) includes a cross-coupled structure. This cross-coupled structure includes two cross-coupled inverters (black solid-line boxes) used as latches and two inverters (green dashed-line boxes) responsible for driving current into the latch. To change the latch speed and thus change the delay of each unit, we change the current intensity (cs1 / cs2) of the driving inverter. To improve the jitter performance of the oscillator, at each output node, an inverter is used to adjust the swing level. The oscillator generates eight different phases at the output.

[0125] In the above implementation process, a ring oscillator structure composed of four differential units including a latch and two inverters for driving current into the latch, where the latch includes two cross-coupled inverters, can enable the ring oscillator to output multiple different phases.

[0126] In one embodiment, the multiple on-chip clock generators include a ring oscillator circuit and a multiplexer. Determining a target on-chip clock generator from the multiple on-chip clock generators based on the operating frequency of the chip may include the following steps: Step 1: The ring oscillator circuit adjusts the effective number of stages in the oscillation path through the multiplexer to generate clock signals of different frequencies; Step 2: Input the selection signal into the multiplexer to determine the effective number of stages of the ring oscillator circuit so as to determine the target on-chip clock generator; the frequency of the clock signal generated by the target on-chip clock generator is within a preset frequency range; the operating frequency of the chip is within a preset frequency range.

[0127] Specifically, Figure 7 FIG. is a schematic circuit diagram of the multiple on-chip clock generators (including a ring oscillator circuit and a multiplexer) provided by an embodiment of the present application, including a ring oscillator circuit composed of a NAND gate, K delay units, and a 16-to-1 multiplexer, where K is an even number greater than 0; the NAND gate includes two input terminals and an output terminal, and one of the input terminals EN is used to externally connect a start control signal to control the switch of the circuit; the delay units are connected in series, and the input terminal of the first delay unit is connected to the output terminal of the NAND gate, and the output terminal of the last delay unit is connected to one input of the 16-to-1 multiplexer; each delay unit is composed of an odd number of inverters; the 16-to-1 multiplexer includes 16 inputs (dividing the K delay units into 16 segments on average), four digital control selection signals S1 / S2 / S3 / S4, and an output, and the output terminal of the 16-to-1 multiplexer is connected to the other input terminal of the NAND gate to form a ring oscillator structure. The four digital signals S0 / S2 / S3 / S4 are input as controllable signals, corresponding to the inputs of 16 gears from 0000 to 1111, where 0000 corresponds to the maximum effective number of stages and the oscillation frequency output is the smallest at this time. The 16-to-1 multiplexer is controlled by the selection signal to perform path selection, and the effective number of stages in the oscillation path is adjusted to achieve coarse frequency adjustment.

[0128] When determining the target on-chip clock generator, the ring oscillator circuit adjusts the effective number of stages in the oscillation path through the multiplexer to generate clock signals of different frequencies, and input the selection signal into the multiplexer to determine the effective number of stages of the ring oscillator circuit. When the frequency of the clock signal generated by a certain on-chip clock generator is within the preset frequency range and the operating frequency of the chip is within the preset frequency range, determine this on-chip clock generator as the target on-chip clock generator.

[0129] In the above implementation process, the 16-to-1 multiplexer is controlled by a selection signal to select a path, and the effective number of stages in the oscillation path is adjusted to determine the target on-chip clock generator, realizing coarse frequency adjustment, so as to ensure that the frequency of the clock signal generated by the target on-chip clock generator is within the preset frequency range, and the operating frequency of the chip is within the preset frequency range.

[0130] It should be understood that although the steps in the flowcharts involved in the above-described embodiments are shown in sequence according to the indications of the arrows, these steps are not necessarily executed in the order indicated by the arrows. Unless there is a clear indication in this article, there is no strict order restriction for the execution of these steps, and these steps can be executed in other orders. Moreover, at least some of the steps in the flowcharts involved in the above-described embodiments may include multiple steps or multiple stages. These steps or stages are not necessarily executed at the same time, but can be executed at different times. The execution order of these steps or stages is not necessarily sequential, but can be executed alternately or in turn with at least some of the steps or stages in other steps or other steps.

[0131] Based on the same inventive concept, an embodiment of the present application further provides a semiconductor test system, including a test device and the storage chip involved above, and the test device can be used to test the read and write performance of the storage chip. In one or more embodiments of the semiconductor test system provided below, the specific limitations on the storage chip can be referred to the limitations on the storage chip in the above text, and will not be repeated here.

[0132] In one embodiment, a semiconductor test system is provided, including a test device and the storage chip in any one of the above embodiments. Further, the test device may include a processor, a storage chip, a communication interface, a display screen, and an input device connected through a system bus, and performs data interaction with the storage chip through a control path, an address path, and a data path. Among them, the processor of the test device is used to provide computing and control capabilities. The communication interface of the test device is used to communicate with an external terminal in a wired or wireless manner, and the wireless manner can be implemented through WIFI, a mobile cellular network, NFC (Near Field Communication), or other technologies. The display screen of the test device can be a liquid crystal display screen or an electronic ink display screen, and the input device of the test device can be a touch layer covered on the display screen, or a button, a trackball, or a touchpad provided on the outer shell of the test device, or an external keyboard, a touchpad, or a mouse, etc.

[0133] The technical features of the above embodiments can be combined arbitrarily. For the sake of concise description, not all possible combinations of the technical features in the above embodiments are described. However, as long as the combinations of these technical features do not conflict, they should all be considered as the scope described in this specification.

[0134] The embodiments described above only represent several implementation manners of the present application. The description is relatively specific and detailed, but it should not be construed as a limitation on the scope of the patent of the present application. It should be noted that for those of ordinary skill in the art, without departing from the concept of the present application, several modifications and improvements can still be made, and these all belong to the protection scope of the present application. Therefore, the protection scope of the present application should be subject to the appended claims.

Claims

1. A storage chip, characterized in that, The storage chip includes a clock selector, a configuration selector, an on-chip clock source, and a storage module; wherein: The clock selector is configured to determine the working clock signal of the storage chip from an external input clock signal and an on-chip clock signal generated by the on-chip clock source based on the received signal; The configuration selector is configured to set the on-chip clock source and / or the storage module based on the received signal; The on-chip clock source is configured to generate at least one on-chip clock signal based on the setting of the configuration selector; The storage module is configured to write data and / or read data based on the received signal and the working clock signal.

2. The storage chip according to claim 1, wherein The received signal includes a data signal, an address signal, and a control signal; The storage chip further includes a data pad, an address pad, and a control pad for transmitting the data signal, the address signal, and the control signal as external interfaces, respectively.

3. The storage chip according to claim 2, wherein The control signal includes an input clock signal and a clock selection signal; When the clock selection signal is to use an external clock, the clock selector is configured to receive the input clock signal and use the input clock signal as the working clock signal of the storage chip.

4. The storage chip according to claim 3, characterized in that, The control signal further includes a clock output signal; When the clock selection signal is to use an internal clock, the clock selector is configured to receive the on-chip clock signal generated by the on-chip clock source and use the on-chip clock signal as the working clock signal of the storage chip; The working clock signal is further configured to be output to an external device as the clock output signal.

5. The storage chip according to claim 2, wherein The control signal further includes a configuration selection signal and a configuration input signal; When the configuration selection signal is to use an input configuration, the configuration selector configures the on-chip clock source and / or the storage module based on the configuration input signal.

6. The storage chip according to claim 5, characterized in that The control signal further includes a configuration protocol signal; The storage chip further includes a configuration register for storing preset configuration information; When the configuration selection signal is to use an internal configuration, the configuration register is configured to receive the configuration protocol signal and transmit the configuration information to the configuration selector; the configuration selector is configured to configure the on-chip clock source and / or the storage module based on the configuration information.

7. The storage chip according to claim 1, characterized in that The storage module includes a timing balance module and a plurality of memory banks, and the timing balance module is respectively connected to the plurality of memory banks; The timing balance module is configured to receive the working clock signal and perform delay compensation on the working clock signal based on a delay parameter and then transmit it to the memory bank; The configuration selector further includes a delay configuration module, and the delay configuration module is configured to configure the delay parameter of the timing balance module based on the received signal.

8. The memory chip according to claim 7, wherein The memory bank includes a plurality of memory bank units; The timing balance module includes a delay main body module and at least one delay adjustment module, and the delay adjustment module is connected to the output end of the delay main body module, wherein: The delay main body module is configured to delay the input working clock signal for a first time and then output a first signal; The delay adjustment module is configured to receive corresponding delay parameters according to the delay requirement, and after delaying the first signal by a second time, output a second signal to the plurality of repository units; The Chebyshev distance or Euclidean distance between the delay adjustment module and the plurality of repository units is equal.

9. The storage chip according to claim 1, wherein The on-chip clock source includes a clock adjuster and a plurality of on-chip clock generators, and different on-chip clock generators generate clock signals with different frequencies; Based on the configuration selector, a target clock generator is determined from the plurality of on-chip clock generators, and the clock signal generated by the target clock generator is output to the clock adjuster; The clock adjuster finely adjusts the clock signal generated by the target on-chip clock generator based on the control signal to obtain the finely adjusted clock signal corresponding to the control signal as the final clock signal.

10. A semiconductor test system, characterized in that, It includes a test device and a storage chip according to any one of claims 1 to 9.

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