Semiconductor memory device and method of operating same

Abstract

The invention discloses a semiconductor memory device and a method of operating the same. The method includes: providing NBTI information including a row address of an NBTI vulnerable cell among a plurality of memory cells, in which a decrease in a threshold voltage of a cell transistor in the NBTI vulnerable cell due to application of a normal off voltage is greater than a reference decrease value; providing PBTI information including a row address of a PBTI-susceptible cell among the plurality of memory cells, in which an increase in a threshold voltage of a cell transistor in the PBTI-susceptible cell due to the application of the normal on-voltage is greater than a reference increase value; increasing a threshold voltage of the NBTI vulnerable unit by performing an NBTI compensation operation based on the NBTI information; and reducing a threshold voltage of the PBTI vulnerable unit by performing a PBTI compensation operation based on the PBTI information.

Description

[0001] This application is based on and claims priority to Korean Patent Application No. 10-2023-0195223, filed with the Korean Intellectual Property Office on December 28, 2023, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0002] The disclosure relates to semiconductor integrated circuits, and more particularly, to semiconductor memory devices and methods of operating semiconductor memory devices. Background Art

[0003] In semiconductor integrated circuits, such as semiconductor memory devices, negative bias temperature instability (NBTI) or positive bias temperature instability (PBTI) occurs due to stress caused by external high voltage or high temperature. The threshold voltage of a transistor may sometimes change due to NBTI or PBTI, and thus the performance of the semiconductor memory device may deteriorate.

[0004] For example, in the case of NBTI in a P-channel metal oxide semiconductor (PMOS) transistor, when a negative gate voltage is applied and the operating temperature increases due to device driving, the absolute value of the drain current decreases, and the absolute values of the threshold voltage and the gate induced drain leakage (GIDL) current increase. Specifically, if the cell transistors included in the memory cells deteriorate due to NBTI or PBTI, serious problems such as data loss or distortion stored in the memory cells may occur. Summary of the Invention

[0005] A semiconductor memory device and a method of operating a semiconductor memory device are provided. A semiconductor memory device and a method capable of effectively compensating for degradation caused by NBTI and PBTI of memory cells are provided.

[0006] According to one aspect of the disclosure, a semiconductor memory device includes: a plurality of memory cells, each memory cell including a cell transistor, the cell transistor including a gate electrode connected to a word line corresponding to a row address, wherein the cell transistor is configured to switch based on a normal conduction voltage and a normal cutoff voltage applied to the word line during normal operation; an address manager configured to provide negative bias temperature instability (NBTI) information and positive bias temperature instability (PBTI) information, wherein the NBTI information includes row addresses of NBTI-vulnerable cells among the plurality of memory cells such that a decrease in a threshold voltage of the cell transistor caused by applying the normal cutoff voltage to the NBTI-vulnerable cells is greater than a reference decrease value, and wherein the PBTI information includes row addresses of PBTI-vulnerable cells among the plurality of memory cells such that an increase in the threshold voltage of the cell transistor caused by applying the normal conduction voltage to the PBTI-vulnerable cells is greater than a reference increase value; and a compensation controller configured to: increase the threshold voltage of the NBTI-vulnerable cells by performing an NBTI compensation operation based on the NBTI information, and decrease the threshold voltage of the PBTI-vulnerable cells by performing a PBTI compensation operation based on the PBTI information.

[0007] According to one aspect of the disclosure, a semiconductor memory device includes: a plurality of memory cells, each memory cell including a cell transistor, the cell transistor including a gate electrode connected to a word line corresponding to a row address, wherein the cell transistor is configured to: switch based on a normal conduction voltage and a normal cutoff voltage applied to the word line during normal operation; an address manager configured to provide negative bias temperature instability (NBTI) information and positive bias temperature instability (PBTI) information, wherein the NBTI information includes row addresses of NBTI-vulnerable cells among the plurality of memory cells such that a decrease in a threshold voltage of the cell transistor caused by applying the normal cutoff voltage to the NBTI-vulnerable cells is greater than a reference decrease value, and wherein the PBTI information includes row addresses of PBTI-vulnerable cells among the plurality of memory cells such that an increase in the threshold voltage of the cell transistor caused by applying the normal conduction voltage to the PBTI-vulnerable cells is greater than a reference increase value among the plurality of memory cells; and a compensation controller configured to: increase the threshold voltage of the NBTI-vulnerable cells by applying a compensation conduction voltage higher than the normal conduction voltage to the word line corresponding to the row address of the NBTI-vulnerable cells and by performing an NBTI compensation operation based on the NBTI information, and decrease the threshold voltage of the PBTI-vulnerable cells by applying a compensation cutoff voltage lower than the normal cutoff voltage to the word line corresponding to the row address of the PBTI-vulnerable cells and by performing a PBTI compensation operation based on the PBTI information.

[0008] According to one aspect of the disclosure, a method of operating a semiconductor memory device includes a plurality of memory cells, each memory cell including a cell transistor, the cell transistor including a gate electrode connected to a word line corresponding to a row address, the cell transistor being configured to switch based on a normal turn-on voltage and a normal turn-off voltage applied to the word line during normal operation. The method includes: providing negative bias temperature instability (NBTI) information including a row address of an NBTI-vulnerable cell among the plurality of memory cells such that a decrease in a threshold voltage of the cell transistor due to application of the normal turn-off voltage to the NBTI-vulnerable cell is greater than a reference decrease value; providing positive bias temperature instability (PBTI) information including a row address of a PBTI-vulnerable cell among the plurality of memory cells such that an increase in the threshold voltage of the cell transistor due to application of the normal turn-on voltage to the PBTI-vulnerable cell is greater than a reference increase value; increasing the threshold voltage of the NBTI-vulnerable cell by performing an NBTI compensation operation based on the NBTI information; and decreasing the threshold voltage of the PBTI-vulnerable cell by performing a PBTI compensation operation based on the PBTI information.

[0009] The semiconductor memory device and the method of operating the semiconductor memory device according to the exemplary embodiments can improve the performance and reliability of the semiconductor memory device by effectively managing NBTI-vulnerable cells and PBTI-vulnerable cells and by effectively compensating for changes in the threshold voltage. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] The exemplary embodiments of the disclosure will be understood more clearly from the following detailed description in conjunction with the accompanying drawings.

[0011] The above and other aspects, features, and advantages of the specific embodiments of the disclosure will become more apparent from the following description in conjunction with the accompanying drawings, in which: Figure 1 is a flowchart showing a method of operating a semiconductor memory device according to an exemplary embodiment; Figure 2 is a block diagram showing a memory system according to an exemplary embodiment; Figure 3 is a block diagram showing a semiconductor memory device according to an exemplary embodiment; Figure 4 is a diagram showing an exemplary embodiment of a sub-word line driver included in a semiconductor memory device according to an exemplary embodiment; Figure 5 and Figure 6is a diagram illustrating an example embodiment of negative bias temperature instability (NBTI) compensation in a method of operating a semiconductor memory device according to an example embodiment; Figure 7 and Figure 8 is a diagram illustrating an example embodiment of positive bias temperature instability (PBTI) compensation in a method of operating a semiconductor memory device according to an example embodiment; Figure 9 is a block diagram illustrating an example embodiment of an address manager included in a Figure 3 semiconductor memory device; Figure 10 is a diagram illustrating an example embodiment of accessing a storage device included in an Figure 9 address manager; Figure 11 is a block diagram illustrating an example embodiment of a refresh controller included in a Figure 3 semiconductor memory device; Figure 12 is a diagram illustrating a part of a memory cell array for describing data loss due to word line coupling and degradation of NBTI and PBTI characteristics of word lines; Figures 13A to 13D is a diagram for describing an example embodiment of access counting by a Figure 9 address manager; Figure 14A 、 Figure 14B and Figure 14C is a timing diagram illustrating an example operation of a refresh controller included in a Figure 3 semiconductor memory device; Figure 15 is a diagram illustrating adjustment of a compensation period in a method of operating a semiconductor memory device according to an example embodiment; Figure 16 is a diagram illustrating a compensation operation for each bank of a semiconductor memory device according to an example embodiment; Figure 17 and Figure 18 is a diagram illustrating an example embodiment of providing NBTI information in a method of operating a semiconductor memory device according to an example embodiment; Figure 19 and Figure 20 is a diagram illustrating an example embodiment of providing PBTI information in a method of operating a semiconductor memory device according to an example embodiment; Figure 21 is a diagram illustrating an example embodiment of determining a weak cell in a method of operating a semiconductor memory device according to an example embodiment; Figure 22is a diagram showing a schematic layout of a memory core circuit of a semiconductor memory device according to an exemplary embodiment; Figure 23 is a cross-sectional view taken along Figure 22 line A-A in; Figure 24 is a cross-sectional view taken along Figure 22 line B-B in; Figure 25 is a diagram showing NBTI characteristics and PBTI characteristics of an indium gallium zinc oxide (IGZO) vertical channel transistor; Figure 26 and Figure 27 is a diagram showing a stacked semiconductor memory device according to an exemplary embodiment; and Figure 28 is a block diagram showing a mobile system according to an exemplary embodiment. DETAILED DESCRIPTION

[0012] Hereinafter, exemplary embodiments will be described more fully with reference to the accompanying drawings showing some exemplary embodiments. In the drawings, like reference numerals always denote like elements. Redundant descriptions may be omitted.

[0013] The description only shows the disclosed principles. Those skilled in the art will be able to design one or more arrangements that, although not explicitly described herein, embody the disclosed principles. In addition, all examples listed herein are mainly intended for clearly explanatory purposes only, to help the reader understand the disclosed principles and the concepts contributed by the inventors to advance the art, and should be construed as not being limited to such specifically listed examples and conditions. In addition, all the expositions of the disclosed principles, aspects, and embodiments herein, as well as their specific examples, are intended to cover their equivalents.

[0014] The terms used in the disclosure are only for describing specific embodiments and may not be intended to limit the scope of other embodiments. Unless clearly differently indicated in the context, singular expressions may include plural expressions. The terms used herein (including technical terms or scientific terms) may have the same meaning as commonly understood by those of ordinary skill in the technical field described in the disclosure. Among the terms used in the disclosure, the terms defined in a general dictionary may be interpreted with the same or similar meaning as the context meaning of the related art, and are not interpreted in an idealized or overly formalized meaning unless clearly defined in the disclosure. In some cases, even the terms defined in the disclosure may not be interpreted as excluding the disclosed embodiments.

[0015] In one or more of the disclosed embodiments described below, hardware methods are described as examples. However, since one or more of the disclosed embodiments include techniques using both hardware and software, the various disclosed embodiments do not exclude software-based methods.

[0016] In addition, in the disclosure, for determining whether a specific condition is met or achieved, expressions of greater than or less than may be used, but this is merely for illustrative description and does not exclude descriptions of greater than or equal to or less than or equal to. A condition described as "greater than or equal to" may be replaced with "greater than", a condition described as "less than or equal to" may be replaced with "less than", and a condition described as "greater than or equal to and less than" may be replaced with "greater than and less than or equal to".

[0017] The terms "comprises" and "comprising" and their derivatives mean including but not limited to. The term "or" is an inclusive term meaning "and / or". The phrase "associated with" and its derivatives mean including, being included within, interconnected with, containing, being contained within, connected to or coupled with, bonded to or coupled with, capable of communicating with, cooperating with, interlacing, juxtaposing, being adjacent to, joined to or coupled with, having, having the property of, having a relationship with, etc. When the phrase "at least one of" is used with a list of items, it means different combinations of one or more of the listed items may be used and possibly only one item in the list is required. For example, "at least one of A, B, and C" includes any combination of the following combinations: A, B, C, A and B, A and C, B and C, and A and B and C, and any variations thereof. As an additional example, the expression "at least one of a, b, or c" may indicate only a, only b, only c, both a and b, both a and c, both b and c, all of a, b, and c, or variations thereof. Similarly, the term "group" means one or more. Thus, a group of terms can be a single term or a collection of two or more terms.

[0018] A semiconductor memory device according to an exemplary embodiment may include a plurality of memory cells, and each memory cell may include a cell transistor. The cell transistor includes a gate electrode connected to a word line corresponding to a row address, and the cell transistor may be switched (i.e., turned on and off) based on a normal conduction voltage and a normal cutoff voltage applied to the word line during normal operation. As will be described with reference to Figure 22 、 Figure 23 and Figure 24 described, the cell transistor may be implemented as a vertical channel transistor including a channel layer formed of indium gallium zinc oxide (IGZO or InxGayZnzO). As will be described with reference to Figure 25As described, an IGZO vertical channel transistor can have both negative bias temperature instability (NBTI) and positive bias temperature instability (PBTI).

[0019] Figure 1 FIG. is a flowchart illustrating a method of operating a semiconductor memory device according to an exemplary embodiment.

[0020] Referring to Figure 1 , NBTI information (S100) can be provided, and the NBTI information includes row addresses of NBTI-vulnerable cells among a plurality of memory cells. The decrease value of the threshold voltage of the cell transistors in the NBTI-vulnerable cells due to the application of a normal cut-off voltage is greater than a reference decrease value.

[0021] In addition, PBTI information (S200) can be provided, and the PBTI information includes row addresses of PBTI-vulnerable cells among a plurality of memory cells. The increase value of the threshold voltage of the cell transistors in the PBTI-vulnerable cells due to the application of a normal conduction voltage is greater than a reference increase value. Exemplary embodiments of providing the NBTI information and the PBTI information will be described below with reference to Figures 9 to 13D and Figures 17 to 21 An exemplary embodiment of providing the NBTI information and the PBTI information will be described.

[0022] Based on the NBTI information, an NBTI compensation operation can be performed to increase the threshold voltage of the NBTI-vulnerable cells (S300). In addition, based on the PBTI information, a PBTI compensation operation can be performed to decrease the threshold voltage of the PBTI-vulnerable cells (S400). Exemplary embodiments of the NBTI compensation operation and the PBTI compensation operation will be described below with reference to Figures 5 to 8 An exemplary embodiment of the NBTI compensation operation and the PBTI compensation operation will be described.

[0023] According to an exemplary embodiment, the performance and reliability of a semiconductor memory device can be improved by effectively managing NBTI-vulnerable cells and PBTI-vulnerable cells, and by effectively compensating for changes in the threshold voltage.

[0024] Figure 2 FIG. is a block diagram illustrating a memory system according to an exemplary embodiment.

[0025] Referring to Figure 2, the memory system 10 includes a memory controller 20 and a semiconductor memory device 400. The memory controller 20 and the semiconductor memory device 400 include corresponding interfaces for communicating with each other. The interfaces can be connected via a control bus 21 (for transmitting commands CMD, addresses ADDR, clock signals CLK, etc.) and a data bus 22 (for transferring data). According to some standards of the semiconductor memory device, the address ADDR can be incorporated into the command CMD. The memory controller 20 can generate commands CMD for controlling the semiconductor memory device 400, and under the control of the memory controller 20, data can be written into the semiconductor memory device 400 or read from the semiconductor memory device 400.

[0026] According to an exemplary embodiment, the semiconductor memory device 400 may include an address manager (ADMNG) 300 and a compensation controller (CMCON) 600. The address manager 300 can store NBTI information generated through a test operation, and the compensation controller 600 can perform an NBTI compensation operation based on the NBTI information. In addition, the address manager 300 can generate PBTI information by monitoring access addresses for normal operations (including read operations and write operations) regarding a plurality of memory cells. The compensation controller 600 can perform a PBTI compensation operation based on the PBTI information.

[0027] Figure 3 is a block diagram showing a semiconductor memory device according to an exemplary embodiment.

[0028] Referring to Figure 3 , the semiconductor memory device 400 may include a control logic 410, an address register 420, a bank control logic 430, a row selection circuit 460 (or row decoder), a column decoder 470, a memory cell array 480, a sense amplifier 485, an input / output (I / O) gating circuit 490, a data input / output (I / O) buffer 495, an address manager 300, and a refresh controller 500. Figure 3 An embodiment is shown in which the compensation controller 600 is included in the refresh controller 500, but the exemplary embodiment is not limited thereto. According to an exemplary embodiment, the compensation controller 600 can be implemented as a separate logic circuit different from the refresh controller 500.

[0029] The memory cell array 480 may include a plurality of bank arrays 480a to 480h. The row selection circuit 460 may include a plurality of bank row selection circuits 460a to 460h respectively coupled to the bank arrays 480a to 480h. The column decoder 470 may include a plurality of bank column decoders 470a to 470h respectively coupled to the bank arrays 480a to 480h. The sense amplifier 485 may include a plurality of bank sense amplifiers 485a to 485h respectively coupled to the bank arrays 480a to 480h.

[0030] The address register 420 may receive an address ADDR including a bank address BANK_ADDR, a row address ROW_ADDR, and a column address COL_ADDR from a memory controller. The address register 420 may provide the received bank address BANK_ADDR to the bank control logic 430, may provide the received row address ROW_ADDR to the row selection circuit 460, and may provide the received column address COL_ADDR to the column decoder 470.

[0031] The bank control logic 430 may generate bank control signals in response to the bank address BANK_ADDR. One of the bank row selection circuits 460a to 460h corresponding to the bank address BANK_ADDR may be activated in response to the bank control signals, and one of the bank column decoders 470a to 470h corresponding to the bank address BANK_ADDR may be activated in response to the bank control signals.

[0032] The row address ROW_ADDR from the address register 420 may be applied to the bank row selection circuits 460a to 460h. One of the activated bank row selection circuits 460a to 460h may decode the row address ROW_ADDR and may activate the word line corresponding to the row address ROW_ADDR. For example, the activated bank row selection circuit may apply a word line drive voltage to the word line corresponding to the row address ROW_ADDR.

[0033] The column decoder 470 may include a column address latch. The column address latch may receive the column address COL_ADDR from the address register 420 and may temporarily store the received column address COL_ADDR. In some embodiments, in burst mode, the column address latch may generate a column address incremented from the received column address COL_ADDR. The column address latch may apply the temporarily stored column address or the generated column address to the bank column decoders 470a to 470h.

[0034] One of the activated bank column decoders among the bank column decoders 470a to 470h can decode the column address COL_ADDR and can control the input / output strobe circuit 490 to facilitate outputting data corresponding to the column address COL_ADDR.

[0035] The I / O strobe circuit 490 can include a circuit for strobing input / output data. The I / O strobe circuit 490 can also include a read data latch for storing data output from the bank arrays 480a to 480h, and a write driver for writing data into the bank arrays 480a to 480h.

[0036] Data to be read from one of the bank arrays 480a to 480h can be sensed by one of the bank sense amplifiers 485a to 485h coupled to the bank array from which the data is to be read, and can be stored in the read data latch. The data stored in the read data latch can be provided to the memory controller via the data I / O buffer 495. Data DQ to be written into one of the bank arrays 480a to 480h can be provided to the data I / O buffer 495 from the memory controller. The write driver can write the data DQ into one of the bank arrays 480a to 480h.

[0037] The control logic 410 can control the operation of the semiconductor memory device 400. For example, the control logic 410 can generate control signals for the semiconductor memory device 400 to facilitate performing a write operation, a read operation, or a refresh operation. The control logic 410 can generate internal command signals (e.g., an activation signal IACT, a precharge signal IPRE, a refresh signal IREF, a read signal IRD, a write signal IWR, etc.) based on a command CMD transmitted from Figure 2 the memory controller 20 therein. The control logic 410 can include a command decoder 411 that decodes the command CMD received from the memory controller 20 and a mode register 412 that sets the operation mode of the semiconductor memory device 400.

[0038] Figure 3 The control logic 410 and the address register 420 are shown to be different from each other. In some embodiments, the control logic 410 and the address register 420 can be implemented as a single inseparable circuit. In addition, Figure 3 the command CMD and the address ADDR are shown to be provided as different signals. In some embodiments, the command CMD and the address ADDR can be provided as a combined signal specified by, for example, the LPDDR5 standard.

[0039] The address manager 300 may comprehensively manage access addresses for multiple memory bank arrays 480a to 480h based on the bank address BANK_ADDR and the row address ROW_ADDR. The address manager 300 may provide row addresses of "hammer addresses HADD among the access addresses and / or NBTI-vulnerable cells and PBTI-vulnerable cells" for hammer refresh operations, NBTI compensation operations, and PBTI compensation operations. The hammer address HADD is an access address that is accessed more intensively than other access addresses. The row addresses of the NBTI-vulnerable cells and the PBTI-vulnerable cells may be referred to as compensation addresses CMPADD. The refresh controller 500 may generate a hammer refresh address signal based on the hammer address HADD, and the hammer refresh address signal indicates a row physically adjacent to the row corresponding to the hammer address HADD (e.g., a sacrificial row). In addition, the refresh controller 500 may perform NBTI compensation operations and PBTI compensation operations based on the hammer address HADD and / or the compensation address CMPADD.

[0040] Figure 4 FIG. is a diagram illustrating an example embodiment of a sub-word line driver included in a semiconductor memory device according to an example embodiment. Figure 4 FIG. shows an example in which a plurality of word lines WL1 to WL4 are connected to one main word line NWE through sub-word line drivers SWD1 to SWD4.

[0041] Signals PXID1 to PXID4 and PXIB1 to PXIB4 are generated through address decoding. The voltage levels of signals PXID1 to PXID4 correspond to the selected word line voltages. Signals PXID1 to PXID4 may be generated by the above Figure 3 row selection circuit 460. The row selection circuit 460 may generate signals PXID1 to PXID4 by decoding a part or all of the bits in the row address. During normal operation, the voltage level of the signal among signals PXID1 to PXID4 corresponding to the selected word line may have a level of a normal on voltage VON. The pull-down voltage (or sinking voltage) VBB of the sub-word line drivers SWD1 to SWD4 may correspond to a normal off voltage VOFF. In Figure 4 FIG., a plurality of memory cells MC may be disposed at positions where a plurality of word lines (e.g., WL1 to WL4) intersect a plurality of bit lines (e.g., BL1 to BL6), and each memory cell MC may include a cell transistor CT and a capacitor CC.

[0042] Figure 5 and Figure 6 FIG. is a diagram illustrating an example embodiment of NBTI compensation in a method of operating a semiconductor memory device according to an example embodiment.

[0043] Reference Figure 3 , Figure 5 and Figure 6 , the address manager 300 may store a compensation address CMPADD (S11) corresponding to the row address of the NBTI-vulnerable cell. In one embodiment, the compensation address CMPADD corresponding to the NBTI-vulnerable cell may be generated through a test operation of the semiconductor memory device 400.

[0044] As will be described below, the compensation controller 600 may periodically perform the NBTI compensation operation at a compensation period tCM. If the compensation period tCM has not elapsed (S12: No), the compensation controller 600 may remain in the standby state. When the compensation period tCM has elapsed (S12: Yes), the compensation controller 600 may perform the NBTI compensation operation (S13) by applying a compensation turn-on voltage CVON to the word line corresponding to one compensation address CMPADD of the NBTI-vulnerable cell.

[0045] Then, the compensation address CMPADD may be changed to another compensation address CMPADD among the compensation addresses CMPADD corresponding to the NBTI-vulnerable cell (S14), and the same operation may be repeated. By increasing the reduced threshold voltage of the cell transistor of the NBTI-vulnerable cell through the NBTI compensation operation, the reliability of the semiconductor memory device may be improved.

[0046] Reference Figure 6 , in normal operation, a normal turn-on voltage VON may be applied to the selected word line, and a normal turn-off voltage VOFF may be applied to the unselected word line. According to an exemplary embodiment, as shown in Figure 6 , in the NBTI compensation operation, a compensation turn-on voltage CVON higher than the normal turn-on voltage VON may be applied to the word line corresponding to the row address of the NBTI-vulnerable cell based on the NBTI information. In addition, since the NBTI characteristic degradation increases as the operating temperature of the semiconductor memory device 400 increases, the compensation turn-on voltage CVON may increase as the operating temperature of the semiconductor memory device 400 increases.

[0047] Figure 7 and Figure 8 are diagrams showing an exemplary embodiment of positive bias temperature instability (PBTI) compensation in a method of operating a semiconductor memory device according to an exemplary embodiment.

[0048] Reference Figure 3 , Figure 7 and Figure 8, during normal operation, the address manager 300 may monitor access addresses for read operations and write operations with respect to a plurality of memory cells to provide PBTI information (S21) that "includes a compensation address CMPADD corresponding to a row address of a PBTI-vulnerable cell". In one embodiment, the compensation address CMPADD corresponding to the PBTI-vulnerable cell may be provided based on a hammering address for a hammering refresh operation of the semiconductor memory device 400.

[0049] As will be described below, the compensation controller 600 may perform a PBTI compensation operation periodically at a compensation period tCM. If the compensation period tCM has not elapsed (S22: No), the compensation controller 600 may remain in a standby state. If the compensation period tCM has elapsed (S22: Yes), the compensation controller 600 may determine whether there is a compensation address CMPADD corresponding to the PBTI-vulnerable cell (S23). If there is a compensation address CMPADD corresponding to the PBTI-vulnerable cell (S23: Yes), the compensation controller 600 may apply a compensation cut-off voltage CVOFF to a word line corresponding to one compensation address CMPADD of the PBTI-vulnerable cell to perform a PBTI compensation operation (S24). Then, the compensation address CMPADD may be changed to another compensation address CMPADD among the compensation addresses CMPADD corresponding to the PBTI-vulnerable cell, and the same operation may be repeated. By reducing the increased threshold voltage of the cell transistors of the PBTI-vulnerable cells through the PBTI compensation operation, the reliability of the semiconductor memory device can be improved.

[0050] Referring to Figure 8 , during normal operation, a normal conduction voltage VON may be applied to a selected word line, and a normal cut-off voltage VOFF may be applied to an unselected word line. According to an exemplary embodiment, as Figure 8 shown, during the PBTI compensation operation, a compensation cut-off voltage CVOFF lower than the normal cut-off voltage VOFF may be applied to a word line corresponding to the row address of the PBTI-vulnerable cell based on the PBTI information. In addition, as the operating temperature of the semiconductor memory device 400 increases, the PBTI characteristic deterioration increases. Therefore, as the operating temperature of the semiconductor memory device 400 increases, the compensation cut-off voltage CVOFF may be further reduced.

[0051] Figure 9 is a block diagram showing an exemplary embodiment of an address manager included in Figure 3 a semiconductor memory device. Figure 10 is a diagram showing an exemplary embodiment of an access storage device included in Figure 9 the address manager.

[0052] Referring toFigure 9 , the address manager 300 may include an access storage device 320 and a controller (or storage device controller) 340. The access storage device 320 may store information about the hammer address HADD and the compensation address CMPADD. In some example embodiments, as Figure 10 shown, the access storage device 320 may include a plurality of storage devices SU1 to SUk.

[0053] Each storage device SUi may include a bank register BREGi configured to store a bank address of each access address, a row register RREGi configured to store a row address of each access address, and a count register CREGi configured to store each access count value (i = 1 to k).

[0054] As Figure 3 shown, the controller 340 may control the access storage device 320 based on the access addresses BANK_ADDR and ROW_ADDR transmitted from the memory controller 20 to the semiconductor memory device 400. The access addresses may include a bank address BANK_ADDR and a row address ROW_ADDR. The controller 340 may determine and provide the hammer address HADD and the compensation address CMPADD among the stored access addresses based on the access count value. The management scheme of the hammer address HADD and the compensation address CMPADD used by the controller 340 may be differently determined according to the memory system. According to an example embodiment, the compensation address CMPADD for the PBTI compensation operation may be the same as the hammer address HADD.

[0055] Figure 11 is a block diagram showing an example embodiment of a refresh controller included in a Figure 3 semiconductor memory device. Referring to Figure 11 , the refresh controller 500 may include a timing controller 510, a refresh counter 520, an address generator 530, and a compensation controller 600.

[0056] Figure 11 shows an embodiment in which the compensation controller 600 is included in the refresh controller 500, but the example embodiment is not limited thereto. According to an example embodiment, the compensation controller 600 may be implemented as a separate logic circuit different from the refresh controller 500.

[0057] The timing controller 510 generates a counter refresh signal CREF indicating the timing of a normal refresh operation, a hammer refresh signal HREF indicating the timing of a hammer refresh operation, and a compensation signal TCM indicating the timing of a compensation operation. As will be described later with reference to Figure 14A , Figure 14B and Figure 14CAs described, the timing controller 510 may selectively activate the counter refresh signal CREF and the compensation signal TCM.

[0058] In one embodiment, as Figure 11 shown, the timing controller 510 may be included in the refresh controller 500. In other embodiments, the timing controller 510 may be omitted, and the counter refresh signal CREF, the hammer refresh signal HREF, and the compensation signal (TCM) may be provided from other control logic within the semiconductor memory device.

[0059] The refresh counter 520 generates an address that indicates a sequential change synchronously with the counter refresh signal CREF. For example, the refresh counter 520 may increment the value of the counter refresh address signal CRFADD by 1 each time the counter refresh signal CREF is activated. In this way, the word lines for normal refresh operations may be sequentially selected one by one by incrementing the value of the counter refresh address signal CRFADD by 1.

[0060] The address generator 530 stores the hammer address HADD provided from the address manager 300, and generates a hammer refresh address signal HRFADD that indicates a row physically adjacent to the row "corresponding to the hammer address HADD" synchronously with the hammer refresh signal HREF. The address generator 530 may include a hammer address storage device 540 and a mapper 550.

[0061] The hammer address storage device 540 stores the hammer address HADD provided from the address manager 300. The mapper 550 generates the hammer refresh address signal HRFADD based on the hammer address HADD provided from the hammer address storage device 540. According to an exemplary embodiment, the hammer address storage device 540 may be omitted, and in this case, the mapper 550 may directly receive the hammer address HADD from the address manager 300.

[0062] The compensation controller 600 provides a compensation address CMPADD based on the compensation signal TCM indicating a compensation period. For example, each time the compensation signal TCM is activated, the compensation controller 600 may sequentially change the compensation address CMPADD. In this way, the word lines for NBTI compensation operations or PBTI compensation operations may be alternately selected one by one by sequentially changing the compensation address CMPADD.

[0063] Figure 12 is a diagram showing a part of a memory cell array for describing data loss due to word line coupling and degradation of NBTI and PBTI characteristics of word lines.

[0064] Figure 12Shows five word lines WLs-2, WLs-1, WLs, WLs+1, and WLs+2 in a memory cell array, three bit lines BLp-1, BLp, and BLp+1, and memory cells MC coupled to "word lines WLs-2, WLs-1, WLs, WLs+1, and WLs+2 and bit lines BLp-1, BLp, and BLp+1". The five word lines WLs-2, WLs-1, WLs, WLs+1, and WLs+2 extend along the row direction (e.g., the X direction) and are arranged sequentially along the column direction (e.g., the Y direction). The three bit lines BLp-1, BLp, and BLp+1 extend along the column direction and are arranged sequentially along the row direction.

[0065] For example, the middle word line WLs may correspond to a hammered address HADD that has been intensively accessed. In some embodiments, an intensively accessed word line or a hammered word line represents a word line having a relatively high number of activations and / or a relatively high activation frequency (e.g., greater than a predetermined threshold or a number of activations and / or activation frequency greater than that of other accessed addresses). Whenever the hammered word line (e.g., the middle word line WLs) is accessed, the hammered word line WLs is enabled and precharged, and the voltage level of the hammered word line WLs increases and decreases. Word line coupling may cause the voltage levels of the adjacent word lines WLs-2, WLs-1, WLs+1, and WLs+2 to change as the voltage level of the hammered word line WLs changes. Accordingly, the cell charge of the memory cells MC coupled to the adjacent word lines WLs-2, WLs-1, WLs+1, and WLs+2 is affected. As the hammered word line WLs is accessed more frequently, the cell charge of the memory cells MC coupled to the adjacent word lines WLs-2, WLs-1, WLs+1, and WLs+2 may be lost more quickly.

[0066] In Figure 11 it, the address generator 530 may provide a hammered refresh address signal HRFADD representing addresses HRFADDa, HRFADDb, HRFADDc, and HRFADDd of rows (e.g., word lines WLs-1, WLs+1, WLs-2, and WLs+2) physically adjacent to "the row of the hammered address HADD (e.g., the middle word line WLs)", and a hammered refresh operation for the adjacent word lines WLs-1, WLs+1, WLs-2, and WLs+2 may be performed based on (e.g., in response to) the hammered refresh address signal HRFADD to reduce or possibly prevent loss of data stored in the memory cells MC. The word line refresh operation may be performed for two word lines WLs-1 and WLs+1 directly adjacent to the word line WLs or for four word lines WLs-2, WLs-1, WLs+1, and WLs+2 including the next adjacent word lines WLs-2 and WLs+2.

[0067] In addition, in Figure 11 the compensation controller may provide a hammering address HADD as a compensation address CMPADD for PBTI compensation operations. By reducing, via the PBTI compensation operation, the increased threshold voltage of the cell transistors of the PBTI-vulnerable cells connected to the word line WL corresponding to the compensation address CMPADD, the reliability of the semiconductor memory device can be improved.

[0068] Figures 13A to 13D is a diagram for describing an example embodiment of access counting performed by the Figure 9 address manager. Hereinafter, an example embodiment of managing access addresses for PBTI compensation operations (and / or hammering refresh operations) and providing compensation addresses will be described with reference to Figures 13A to 13D .

[0069] Provided Figures 13A to 13D are one or more examples for describing the comprehensive management of access addresses for multiple bank arrays, and specific operation scenarios may be implemented differently.

[0070] Although, for ease of explanation and description, Figures 13A to 13D an example is shown in which the access storage device 320 includes four storage devices SU1, SU2, SU3, and SU4, the number of storage devices may be changed differently. Figures 13A to 13D shows the bank address BANK_ADDR, the row address ROW_ADDR, and the access count value indicating "the activation time point ta of the activation signal IACT at the reception time of the activation command provided from the memory controller", and the states of the access storage device 320 before and after the activation time point ta of the activation signal IACT.

[0071] Referring to Figure 9 and Figure 13A , when the input access address (A, RA3), which is a combination of the bank address A and the row address RA3 provided by the addresses BANK_ADDR and ROW_ADDR, corresponds to "one of the access addresses (A, RA2), (B, RA4), (A, RA1), and (A, RA3) stored in the access storage device 320", the controller 340 may increase the access count value corresponding to the input access address (A, RA3) from 22 by 1 to 23. In this way, the address manager 300 can accumulate the access count value.

[0072] Referring to Figure 9 and Figure 13B, when the input access address (A, RA5) provided by accessing the address through the address BANK_ADDR and ROW_ADDR does not correspond to "any one of the access addresses (A, RA2) and (B, RA4) stored in the access storage device 320", and some storage devices (e.g., SU3 and SU4) have been initialized to the reset bank address BRST and the reset row address RRST, the controller 340 can store the input access address (A, RA5) and the corresponding access count value in one of the storage devices (e.g., SU3) that has been initialized. For example, the reset addresses BRST and RRST can correspond to predetermined values (such as, "0000", "1111", etc.). When the reset addresses BRST and RRST are stored in the storage device, the storage device can be regarded as an unoccupied space without storing a valid address.

[0073] Refer to Figure 9 , Figure 13C and Figure 13D , when all the accessed addresses in the storage devices SU1, SU2, SU3, and SU4 are occupied and a new input access address (B, RA5) is accessed, the storage device controller 340 in the address manager 300 can store the new input access address (B, RA5) by replacing "the stored access address (A, RA1) corresponding to the minimum access count value '3' among the access count values '47, 6, 3, and 22'". Throughout the disclosure, the "minimum access count value" represents the lowest access count value among the access count values stored in the access storage device 320. In some example embodiments, as Figure 13C shown, the access count value '3' corresponding to the replaced access address (A, RA1) can be maintained, and the access count value of the new input access address (B, RA5) can be stored as '4'. In some embodiments, as Figure 13D shown, the access count value '3' corresponding to the replaced access address (A, RA1) can be initialized to '0', and the access count value of the new input access address (B, RA5) can be stored as '1'.

[0074] Figure 14A , Figure 14B and Figure 14C are timing diagrams showing example operations of the refresh controller included in the Figure 3 semiconductor memory device.

[0075] Figure 14A , Figure 14B and Figure 14CThe generation of a counter refresh signal CREF, a compensation signal TCM, a counter refresh address signal CRFADD, and a compensation address signal HRFADD with respect to a refresh signal IREF activated in a pulse shape is shown. The intervals between the activation time points t1 to t19 of the refresh signal IREF may be regular or irregular. In some example embodiments, the compensation signal TCM for NBTI compensation operations and / or PBTI compensation operations may be periodically activated at a compensation period tCM.

[0076] Referring to Figure 11 and Figure 14A , the timing controller 510 may activate the counter refresh signal CREF synchronously with the time points t1 to t4, t6 to t10, t12 to t16, and t18 to t19 among the activation time points t1 to t19 of the refresh signal IREF, and may activate the compensation signal TCM synchronously with the time points t5, t11, and t17. Although Figure 14A it is shown that the counter refresh signal CREF is activated five times for each activation of the compensation signal TCM, the activation ratio of the counter refresh signal CREF to the compensation signal TCM may be changed.

[0077] The refresh counter 121 may generate a counter refresh address signal CRFADD representing "successively changing addresses X + 1 to X + 15" synchronously with the activation time points t1 to t4, t6 to t10, t12 to t16, and t18 to t19 of the counter refresh signal CREF. The compensation controller 600 may generate a compensation address signal CMPADD representing "addresses Ha, Hb, and Hc for the above PBTI compensation operations" synchronously with the activation time points t5, t11, and t17 of the compensation signal TCM.

[0078] Referring to Figure 11 and Figure 14B , the timing controller 510 may activate the counter refresh signal CREF synchronously with the activation time points t1 to t19 of the refresh signal IREF, and may activate the compensation signal TCM synchronously with the time points ta, tb, and tc while the refresh signal IREF is deactivated. Although Figure 14B it is shown that the counter refresh signal CREF is activated six times for each activation of the compensation signal TCM, the activation ratio of the counter refresh signal CREF to the compensation signal TCM may be changed.

[0079] The refresh counter 121 can generate a counter refresh address signal CRFADD that "represents addresses X+1 to X+18 that change sequentially" in synchronization with the activation time points t1 to t19 of the counter refresh signal CREF. The compensation controller 600 can generate a compensation address signal CMPADD that "represents addresses Ha, Hb, and Hc for the above PBTI compensation operation" in synchronization with the activation times ta, tb, and tc of the compensation signal TCM.

[0080] Referring to Figure 11 and Figure 14C , the timing controller 510 can activate the counter refresh signal CREF in synchronization with some of the activation time points t1 to t19 of the refresh signal IREF, namely t1 to t4, t7 to t10, t13 to t16, and t19, and activate the compensation signal TCM in synchronization with the time points t5, t6, t11, t12, t17, and t18. Although Figure 14C shows that for every two activations of the compensation signal TCM, the counter refresh signal CREF is activated four times, the activation ratio of the counter refresh signal CREF to the compensation signal TCM can be changed.

[0081] The refresh counter 121 can generate a counter refresh address signal CRFADD that "represents addresses X+1 to X+12 that change sequentially" in synchronization with the activation time points t1 to t4, t7 to t10, t13 to t16, and t19 of the counter refresh signal CREF. The compensation controller 600 can generate a compensation address CMPADD that "represents addresses Ha, Hb, and Hc for the above PBTI compensation operation" in synchronization with the activation time points t5, t6, t11, t12, t17, and t18 of the compensation signal TCM.

[0082] In one embodiment, as Figure 14A and Figure 14B shown, the compensation controller 600 can provide one compensation address each time the compensation signal TCM is activated. In another embodiment, as Figure 14C shown, the compensation controller 600 can sequentially provide two compensation addresses each time the compensation signal TCM is activated.

[0083] Figure 15 is a diagram showing the adjustment of the compensation period in a method of operating a semiconductor memory device according to an exemplary embodiment.

[0084] Referring to Figure 11 and Figure 15 , the compensation controller 600 can perform the NBTI compensation operation and the PBTI compensation operation periodically according to the compensation period based on the compensation signal TCM that is activated every compensation period.

[0085] In Figure 15Here, HT represents a case where the operating temperature of the semiconductor memory device is high temperature (e.g., 85 °C or higher), and MT represents a case where the operating temperature of the semiconductor memory device is intermediate temperature (e.g., between 85 °C and 60 °C). LT indicates a case where the operating temperature of the semiconductor memory device is low temperature (e.g., 60 °C or lower).

[0086] As Figure 15 shown, the compensation period tCM2 at the intermediate temperature MT is set to be shorter than the compensation period tCM3 at the low temperature LT, and the compensation period tCM1 at the high temperature HT is set to be shorter than the compensation period tCM2 at the intermediate temperature MT. In other words, the compensation controller 600 can decrease the compensation period as the operating temperature of the semiconductor memory device increases.

[0087] Figure 16 is a diagram showing the compensation operation of each bank of the semiconductor memory device according to an exemplary embodiment. Referring to Figure 11 and Figure 16 , at the activation time point th of the compensation signal TCM, the compensation address signals CMPADD1, CMPADD2, CMPADD3, and CMPADD4 representing the compensation addresses RAa, RAb, RAc, and RAd can be respectively provided to the banks 531, 532, 533, and 534. Accordingly, the NBTI compensation operation can be simultaneously performed for "memory cells in rows having different addresses RAa, RAb, RAc, and RAd included in the respective banks 531, 532, 533, and 534".

[0088] In this way, a plurality of memory cells can be grouped into a plurality of banks, and the compensation controller 600 can perform the PBTI compensation operation and the NBTI compensation operation separately for each bank.

[0089] Figure 17 and Figure 18 is a diagram showing an exemplary embodiment of providing NBTI information in a method of operating a semiconductor memory device according to an exemplary embodiment.

[0090] Referring to Figure 3 , Figure 17 and Figure 18 , for example, a test cut-off voltage TVOFF lower than the normal cut-off voltage VOFF can be applied to the word line corresponding to the test row address through a wafer state test process (S110). The test can be an aging test, and the test cut-off voltage TVOFF can be set to be lower than Figure 8 the compensation cut-off voltage CVOFF to reduce the test time.

[0091] A read operation for the word line corresponding to the test row address can be performed (S120). As will be described below with reference toFigure 21 As described above, based on the result of the above read operation, it can be determined whether the test row address is the row address of an NBTI-vulnerable cell (S130).

[0092] Figure 19 and Figure 20 FIG. is a diagram illustrating an example embodiment of providing PBTI information in a method of operating a semiconductor memory device according to an example embodiment.

[0093] Referring to Figure 3 、 Figure 19 and Figure 20 , for example, a test conduction voltage higher than the normal conduction voltage VON can be applied to the word line corresponding to the test row address through a wafer state test process (S210). The test can be an aging test, and the test conduction voltage TVON can be set to be higher than Figure 6 the compensation conduction voltage CVON to reduce the test time.

[0094] A read operation can be performed on the word line corresponding to the test row address (S220). As will be described below with reference to Figure 21 , based on the result of the above read operation, it can be determined whether the test row address is the row address of a PBTI-vulnerable cell (S230).

[0095] Figure 21 FIG. is a diagram illustrating an example embodiment of determining weak cells (e.g., NBTI-vulnerable cells or PBTI-vulnerable cells) in a method of operating a semiconductor memory device according to an example embodiment. Referring to Figure 21 , defective cells (e.g., defective memory cells) and weak cells can be determined based on the threshold voltage VTH(normal) of normal unit transistors before the degradation of NBTI and PBTI occurs.

[0096] Through a test process for generating NBTI information, if the decrease value of the threshold voltage of the unit transistor is greater than the first reference decrease value Δ3 (i.e., if the threshold voltage decreases below Vth - Δ3), the memory cell corresponding to the test row address can be determined as a defective memory cell. As described above, if the decrease value of the threshold voltage of the unit transistor is less than the first reference decrease value Δ3 and greater than the second reference decrease value Δ4 (i.e., if the threshold voltage is between Vth - Δ3 and Vth - Δ4), the memory cell corresponding to the test row address can be determined as an NBTI-vulnerable cell. The degree of NBTI degradation can be detected by directly measuring the threshold voltage, or the degree of NBTI degradation can be estimated by applying dynamic test coverage. In this way, NBTI compensation behavior can be effectively performed based on the addresses of NBTI-vulnerable cells determined during the test process.

[0097] On the other hand, through a test process for generating PBTI information, if the increase value of the threshold voltage of a cell transistor is greater than a first reference increase value Δ1 (i.e., if the threshold voltage increases to be greater than VTH+Δ1), the memory cell corresponding to the test row address can be determined as a defective memory cell. As described above, if the increase value of the threshold voltage of the cell transistor is less than the first reference increase value Δ1 and greater than a second reference increase value Δ2 (i.e., if the threshold voltage is between VTH+Δ1 and VTH+Δ2), the memory cell corresponding to the test row address can be determined as a PBTI-vulnerable cell. The degree of PBTI degradation can be detected by directly measuring the threshold voltage, or the degree of PBTI degradation can be estimated by applying a test coverage associated with the increased resistance of the memory cell. In this way, the "address of the PBTI-vulnerable cell determined during the test process" and the "address of the PBTI-vulnerable cell determined by monitoring the above access address" can be considered together to more effectively perform PBTI compensation behavior. Defective cells can be screened out before the shipment of the semiconductor memory device. The screening can include replacing the defective cells with redundant cells.

[0098] Hereinafter, a memory core circuit including a vertical channel transistor structure to which an exemplary embodiment can be applied will be described with reference to Figure 22 、 Figure 23 and Figure 24 。

[0099] Figure 22 is a diagram showing a schematic layout of a memory core circuit of a semiconductor memory device according to an exemplary embodiment. Figure 23 is a cross-sectional view taken along line A-A in Figure 22 , Figure 24 is a cross-sectional view taken along line B-B in Figure 22 。

[0100] Referring to Figure 22 、 Figure 23 and Figure 24 ,a semiconductor memory device according to some embodiments includes a first substrate 100, a wire 120, a first interlayer insulating film 112, gate electrodes 150A and 150B, a gate insulating layer 140, a channel layer 130, a second interlayer insulating film 114, bonding pads 160A and 160B, and capacitor structures 170A and 170B. In some embodiments, the first substrate 100 may have a structure in which a substrate base and an epitaxial layer are stacked. The disclosure is not limited thereto. The first substrate 100 can be a silicon substrate, a gallium arsenide substrate, a silicon germanium substrate, or an SOI (semiconductor-on-insulator) substrate.

[0101] The wire 120 may be formed on the first substrate 100. For example, the lower insulating film 110 may be formed on the first substrate 100, and the wire 120 may be disposed on the lower insulating film 110. The wire 120 may extend longitudinally along the column direction Y. A plurality of wires 120 all extend along the column direction Y and may be spaced apart from each other at equal intervals along the row direction X intersecting the column direction Y. The lower insulating film 110 may be formed in the space between the wires 120 (e.g., for filling the space between the wires 120). In some embodiments, the upper surface of the lower insulating film 110 may be disposed at the same height as the upper surface of the wire 120. According to some embodiments, the wire 120 may be used as a bit line of a semiconductor memory device.

[0102] The wire 120 may include doped polysilicon, metal, conductive metal nitride, conductive metal silicide, conductive metal oxide, or a combination thereof. For example, the wire 120 may include, but is not limited to, doped polysilicon, aluminum (Al), copper (Cu), titanium (Ti), tantalum (Ta), ruthenium (Ru), tungsten (W), molybdenum (Mo), platinum (Pt), nickel (Ni), cobalt (Co), titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), niobium nitride (NbN), titanium aluminide (TiAl), titanium aluminum nitride (TiAlN), titanium silicide (TiSi), titanium silicon nitride (TiSiN), tantalum silicide (TaSi), tantalum silicon nitride (TaSiN), ruthenium titanium nitride (RuTiN), nickel silicide (NiSi), cobalt silicide (CoSi), iridium oxide (IrOx), ruthenium oxide (RuOx), or a combination thereof. Optionally, the wire 120 may include a two-dimensional semiconductor material. The two-dimensional semiconductor material may include, for example, graphene, carbon nanotubes, or a combination thereof. The wire 120 may include a single layer or multiple layers of the above-mentioned conductive materials.

[0103] The first interlayer insulating film 112 may be formed on the first substrate 100. The first interlayer insulating film 112 may include (e.g., define) unit trenches 112t extending longitudinally along the row direction X and intersecting the wire 120. A plurality of unit trenches 112t all extend along the row direction X and may be spaced apart from each other at equal intervals along the column direction Y. Thus, each first interlayer insulating film 112 may form a needle-shaped (or pin-shaped) insulating pattern extending along the row direction X and spaced apart from each other by the unit trenches 112t.

[0104] In some embodiments, the first interlayer insulating film 112 may be disposed on the upper surface of the lower insulating film 110 to cover the wire 120. In some embodiments, the lower portion / lower surface of the unit trench 112t may be spaced apart from the upper surface of the wire 120. In some embodiments, the width of the unit trench 112t may decrease toward the upper surface of the first substrate 100. Here, the width of the unit trench 112t refers to the width in the column direction Y. This decrease in width may be due to the characteristics of the etching process for forming the unit trench 112t.

[0105] The first interlayer insulating film 112 may include at least one of, for example, but not limited to, silicon oxide, silicon oxynitride, silicon nitride, and a low dielectric constant (low-k) material having a lower dielectric constant than silicon oxide. The gate electrodes 150A and 150B may be formed in the unit trench 112t. For example, the gate electrodes 150A and 150B may extend along the lower surface and the side surfaces of the unit trench 112t. In addition, both the gate electrodes 150A and 150B may extend longitudinally along the row direction X and cross the wire 120.

[0106] In some embodiments, the gate electrodes 150A and 150B may include a first gate electrode 150A and a second gate electrode 150B that are spaced apart from each other along the column direction Y. The first gate electrode 150A and the second gate electrode 150B may face each other in the unit trench 112t. For example, the first gate electrode 150A may extend along the lower surface and the first side surface of the unit trench 112t, and the second gate electrode 150B may extend along the lower surface of the unit trench 112t and the second side surface of the unit trench 112t that faces the first side surface. As an example, in a cross-section that crosses the row direction X (e.g., in Figure 23 ), both the gate electrodes 150A and 150B may have an "L" shape. According to some embodiments, the first gate electrode 150A may be used as the first word line of the semiconductor memory device, and according to some embodiments, the second gate electrode 150B may be used as the second word line of the semiconductor memory device.

[0107] In some embodiments, the isolation trench 150t may be formed in the first interlayer insulating film 112 and the gate electrodes 150A and 150B. The separation trench 150t may extend along the row direction X to separate the first gate electrode 150A and the second gate electrode 150B. In addition, the isolation trench 150t may overlap a part of the wire 120 (e.g., expose a part of the wire 120). For example, the lower portion / lower surface of the isolation trench 150t may overlap / expose a part of the upper surface of the wire 120.

[0108] Both the gate electrodes 150A and 150B may include doped polysilicon, metal, conductive metal nitride, conductive metal silicide, conductive metal oxide, or a combination thereof. For example, the gate electrodes 150A and 150B may include, but are not limited to: doped polysilicon, Al, Cu, Ti, Ta, Ru, W, Mo, Pt, Ni, Co, TiN, TaN, WN, NbN, TiAl, TiAlN, TiSi, TiSiN, TaSi, TaSiN, RuTiN, NiSi, CoSi, IrOx, RuOx, or a combination thereof.

[0109] In some embodiments, both the first gate electrode 150A and the second gate electrode 150B may include a first conductive pattern 152 and a first barrier conductive film 154. The first conductive pattern 152 and the first barrier conductive film 154 may be sequentially stacked in the cell trench 112t. For example, the first conductive pattern 152 may conformally extend along the lower surface and the side surface of the cell trench 112t. The first barrier conductive film 154 may conformally extend along the contour of the first conductive pattern 152. The first barrier conductive film 154 may be disposed between the first conductive pattern 152 and the gate insulating layer 140 to be described below.

[0110] The first barrier conductive film 154 may reduce / prevent the diffusion of elements included in the first conductive pattern 152. As an example, the first conductive pattern 152 may include at least one of tungsten (W), aluminum (Al), and copper (Cu), and the first barrier conductive film 154 may include at least one of titanium (Ti), titanium nitride (TiN), tantalum (Ta), and tantalum nitride (TaN).

[0111] The gate insulating layer 140 may be stacked on the gate electrodes 150A and 150B. For example, the gate insulating layer 140 may conformally extend along the contours of the gate electrodes 150A and 150B. The gate insulating layer 140 may be disposed between the gate electrodes 150A and 150B and the channel layer 130 to be described below. In some embodiments, the gate insulating layer 140 may also extend along the upper surface of the first interlayer insulating film 112. In some embodiments, the gate insulating layer 140 may extend along the side surface of the isolation trench 150t.

[0112] In some embodiments, the gate insulating layer 140 may have a gap / openings therein that overlap with a portion of the wire 120 (e.g., expose a portion of the wire 120). For example, the gate insulating layer 140 may include contact trenches 140t "inside the isolation trench 150t". The lower part / lower surface of the contact trenches 140t may overlap with / expose a portion of the upper surface of the wire 120. Figure 22It is shown that the contact trench 140t has a rectangular shape. As another example, the contact trench 140t may have a circular or other polygonal shape. In addition, Figure 22 It is shown that one contact trench 140t overlaps / exposes one wire 120. As another example, one contact trench 140t may extend longitudinally along the row direction X to overlap / expose multiple wires 120.

[0113] The gate insulating layer 140 may include silicon oxide, silicon oxynitride, a high-k material having a higher dielectric constant than silicon oxide, or a combination thereof. The high-k material may include, for example but not limited to, hafnium oxide (HfO2), hafnium silicon oxide (HfSiO), hafnium silicon oxynitride (HfSiON), hafnium tantalum oxide (HfTaO), hafnium titanium oxide (HfTiO), hafnium zirconium oxide (HfZrO), zirconium oxide (ZrO2), aluminum oxide (Al2O3), or a combination thereof.

[0114] In some embodiments, the gate insulating layer 140 may provide a semiconductor memory device according to some embodiments as a ferroelectric memory element (ferroelectric random access memory (RAM), FeRAM). As an example, the gate insulating layer 140 may include a ferroelectric (such as barium titanate (BaTiO3), lead zirconate titanate (PbZrTiO3, PZT), strontium bismuth tantalate (STB, SrBi2Ta2O9), bismuth iron oxide (BiFeO3, BFO), and hafnium oxide (HfO2)).

[0115] The channel layer 130 may be stacked on the gate insulating layer 140 (e.g., on the upper surface of the gate insulating layer 140). The channel layer 130 may be inside the cell trench 112t (e.g., may fill at least a part of the cell trench 112t). For example, the channel layer 130 may extend along the contours of the gate electrodes 150A and 150B and the gate insulating layer 140. Thus, each of the gate electrodes 150A and 150B and the gate insulating layer 140 may be disposed between the first interlayer insulating film 112 and the channel layer 130.

[0116] The channel layer 130 may be connected to the wire 120. In some embodiments, the channel layer 130 may be electrically connected to the upper surface of the wire 120 by extending through the isolation trench 150t and the contact trench 140t. As Figure 22 shown, multiple channel layers 130 may be spaced apart from each other along the column direction Y and the row direction X, and may be arranged in a matrix form.

[0117] In a semiconductor memory device according to some embodiments, the channel layer 130 may include a first source / drain region and a second source / drain region arranged along a vertical direction Z intersecting the column direction Y and the row direction X. For example, the lower portion of the channel layer 130 may be used as the first source / drain region, and the upper portion of the channel layer 130 may be used as the second source / drain region. The portion of the channel layer 130 between the first source / drain region and the second source / drain region may be used as a channel region.

[0118] The channel layer 130 may include a semiconductor material. As an example, the channel layer 130 may include an oxide semiconductor material. The oxide semiconductor material may reduce the leakage current of the semiconductor memory device. The oxide semiconductor material may include, for example, IGZO (indium gallium zinc oxide, InxGayZnzO), IGSO (indium gallium silicon oxide, InxGaySizO), ITZO (indium tin zinc oxide, InxSnyZnzO), IZO (indium zinc oxide, InxZnyO), ZnO (zinc oxide, ZnxO), ZTO (zinc tin oxide, ZnxSnyO), ZnON (zinc oxynitride, ZnxOyN), ZZTO (zirconium zinc tin oxide, ZrxZnySnzO), SnO (tin oxide, SnxO), HIZO (hafnium indium zinc oxide, HfxInyZnZO), GZTO (gallium zinc tin oxide, GaxZnySnzO), AZTO (aluminum zinc tin oxide, AlxZnySnzO), YGZO (ytterbium gallium zinc oxide, YbxGayZnzO), IGO (indium gallium oxide, InxGayO), or a combination thereof.

[0119] As another example, the channel layer 130 may include silicon (Si) and germanium (Ge) as elemental semiconductor materials, or materials doped into them. Optionally, the channel layer 130 may further include a group-IV-IV compound semiconductor or a group-III-V compound semiconductor. The group-IV-IV compound semiconductor may be, for example, a binary compound or a ternary compound including at least two or more of carbon (C), silicon (Si), germanium (Ge), and tin (Sn), or a compound obtained by doping these elements with group-IV elements.

[0120] As another example, the channel layer 130 may include a two-dimensional semiconductor material. The two-dimensional semiconductor material may include, for example, graphene, carbon nanotubes, transition metal dichalcogenides (TMDs), or a combination thereof. The TMD may include, for example, one metal element among Mo, W, Nb, vanadium (V), Ta, Ti, Zr, Hf, technetium (Tc), rhenium (Re), Cu, Ga, In, Sn, Ge, and Pb, and one chalcogen element among sulfur (S), selenium (Se), and tellurium (Te).

[0121] According to some embodiments, the channel layer 130 may include a single layer or multiple layers of the above-described semiconductor material. Preferably, the channel layer 130 may include IGZO. Also, in other embodiments, the channel layer 130 may have a bandgap energy greater than that of silicon (Si). For example, the channel layer 130 may have a bandgap energy of about 1.5 electron volts (eV) to 5.6 eV. Preferably, the channel layer 130 may have a bandgap energy of about 2.0 eV to 4.0 eV. The channel layer 130 may be, but is not limited to, polycrystalline or amorphous, for example.

[0122] As shown, the channel layer 130 may be a continuous layer including a penetrating portion 132, a first extending portion 134A, and a second extending portion 134B. The penetrating portion 132 may be disposed between the first gate electrode 150A and the second gate electrode 150B. The penetrating portion 132 may penetrate the first interlayer insulating film 112 and be connected (e.g., electrically connected) to the wire 120. For example, the penetrating portion 132 may be inside the contact trench 140t (e.g., may fill the contact trench 140t). The first extending portion 134A may extend from the penetrating portion 132 along the side surface of the first gate electrode 150A. The second extending portion 134B may extend from the penetrating portion 132 along the side surface of the second gate electrode 150B.

[0123] In a semiconductor memory device according to some embodiments, the first extending portion 134A may serve as a first channel region of a first transistor including the first gate electrode 150A, and the second extending portion 134B may serve as a second channel region of a second transistor including the second gate electrode 150B. Thus, two transistor structures may be provided for each channel layer 130.

[0124] In some embodiments, the first extending portion 134A and the second extending portion 134B may face each other (e.g., may be opposite to each other, may be parallel to each other) inside the cell trench 112t. As an example, in a cross-section intersecting the row direction X (e.g., in Figure 23 ), the first extending portion 134A and the second extending portion 134B may commonly have a "U" shape.

[0125] In some embodiments, a part of the first extending portion 134A and a part of the second extending portion 134B may be disposed on the upper surface of the first interlayer insulating film 112. For example, the first extending portion 134A may further extend along the upper surface of the first gate electrode 150A, and the second extending portion 134B may further extend along the upper surface of the second gate electrode 150B.

[0126] The second interlayer insulating film 114 may be formed on the channel layer 130. For example, the second interlayer insulating film 114 may be formed on the gate insulating layer 140. The second interlayer insulating film 114 may separate a plurality of channel layers 130 "spaced apart from each other and arranged in a matrix form". In some embodiments, the upper surface of the second interlayer insulating film 114 may be arranged at the same height as the upper surface of the channel layer 130. That is, the second interlayer insulating film 114 may be on the side surface of the channel layer 130 (e.g., may cover the side surface of the channel layer 130). In some embodiments, the second interlayer insulating film 114 may be disposed between the first extension portion 134A and the second extension portion 134B. For example, the second interlayer insulating film 114 may be formed on the channel layer 130 to fill the unit trench 112t. The second interlayer insulating film 114 may include, but is not limited to, at least one of, for example, silicon oxide, silicon oxynitride, silicon nitride, and a low dielectric constant (low-k) material having a lower dielectric constant than silicon oxide.

[0127] Bonding pads 160A and 160B may be formed on the first interlayer insulating film 112 and the second interlayer insulating film 114. Each of the bonding pads 160A and 160B may be electrically connected to the channel layer 130. For example, a third interlayer insulating film 116 may be formed on the first interlayer insulating film 112 and the second interlayer insulating film 114. The bonding pads 160A and 160B are both formed in the third interlayer insulating film 116 and may be electrically connected to the upper portion of the channel layer 130.

[0128] In some embodiments, each of the bonding pads 160A and 160B may be arranged to overlap at least a portion of the channel layer 130 along the vertical direction Z. The plurality of bonding pads 160A and 160B are spaced apart from each other along the column direction Y and the row direction X and may be arranged in a matrix form. However, this is only an example, and the layout of the bonding pads 160A and 160B is not limited as long as the bonding pads are electrically connected to the channel layer 130. As another example, the plurality of bonding pads 160A, 160B may also be arranged in a honeycomb form.

[0129] In some embodiments, the bonding pads 160A and 160B may include a first bonding pad 160A and a second bonding pad 160B spaced apart from each other along the column direction Y. The first bonding pad 160A may contact one end (e.g., the first end) of the channel layer 130 adjacent to the first gate electrode 150A, and the second bonding pad 160B may contact the other end (e.g., the second end opposite to the first end) of the channel layer 130 adjacent to the second gate electrode 150B. For example, the first bonding pad 160A may contact the first extension portion 134A, and the second bonding pad 160B may contact the second extension portion 134B.

[0130] In some embodiments, the first bonding pad 160A may be in contact with the upper surface of the first extension portion 134A that "extends along the upper surface of the first gate electrode 150A", and the second bonding pad 160B may be in contact with the upper surface of the second extension portion 134B that "extends along the upper surface of the second gate electrode 150B".

[0131] The drawings show that the first bonding pad 160A is stacked with the first gate electrode 150A in the vertical direction Z, and the second bonding pad 160B is stacked with the second gate electrode 150B in the vertical direction Z. In some embodiments, the layout of the first bonding pad 160A and the second bonding pad 160B may vary as long as each of the first bonding pad 160A and the second bonding pad 160B is electrically connected to the channel layer 130. In some embodiments, the bonding pads 160A and 160B may each include doped polysilicon, metal, conductive metal nitride, conductive metal silicide, conductive metal oxide, or a combination thereof. For example, the bonding pads 160A and 160B may include, but are not limited to: doped polysilicon, Al, Cu, Ti, Ta, Ru, W, Mo, Pt, Ni, Co, TiN, TaN, WN, NbN, TiAl, TiAlN, TiSi, TiSiN, TaSi, TaSiN, RuTiN, NiSi, CoSi, IrOx, RuOx, or a combination thereof.

[0132] Capacitor structures 170A and 170B may be formed on the bonding pads 160A and 160B. The capacitor structures 170A and 170B may be arranged corresponding to the bonding pads 160A and 160B. The bonding pads 160A and 160B may electrically connect the channel layer 130 and the capacitor structures 170A and 170B. The capacitor structures 170A and 170B may include lower electrodes 173A and 173B, a capacitor dielectric layer 175, and upper electrodes 178.

[0133] In some embodiments, the capacitor structures 170A and 170B may provide a semiconductor memory device according to some embodiments as a dynamic memory element (dynamic RAM, DRAM). For example, the capacitor structures 170A and 170B may store data (charges) inside the capacitor dielectric layer 175 by utilizing the potential difference that appears between the lower electrodes 173A and 173B and the upper electrode 178.

[0134] The lower electrodes 173A and 173B can be electrically connected to the bonding pads 160A and 160B. Each of the lower electrodes 173A and 173B can have, but is not limited to, a columnar shape extending along the vertical direction Z. In some embodiments, the lower electrodes 173A and 173B can be arranged to overlap with the bonding pads 160A and 160B in the vertical direction Z. For example, a plurality of the lower electrodes 173A and 173B can be spaced apart from each other along the column direction Y and the row direction X, and can be arranged in a matrix form.

[0135] In some embodiments, the lower electrodes 173A and 173B can be spaced apart from each other along the column direction Y. The lower electrode 173A can be in contact with the upper surface of the first bonding pad 160A, and the lower electrode 173B can be in contact with the upper surface of the second bonding pad 160B. Accordingly, the capacitor structures 170A and 170B can include a first capacitor structure 170A and a second capacitor structure 170B arranged along the column direction Y.

[0136] The capacitor dielectric layer 175 can be disposed between the lower electrodes 173A and 173B and the upper electrode 178. As an example, the capacitor dielectric layer 175 can conformally extend along the outer peripheral surfaces of the lower electrodes 173A and 173B and the upper surface of the third interlayer insulating film 116. The upper electrode 178 can be formed on the upper surface of the capacitor dielectric layer 175.

[0137] In some embodiments, the upper electrode 178 can be a plate-like structure extending along a plane intersecting the vertical direction Z. As an example, a fourth interlayer insulating film 118 filling the space between the lower electrodes 173A and 173B can be formed on the capacitor dielectric layer 175. The upper electrode 178 can extend along the upper surface of the fourth interlayer insulating film 118. However, this is merely an example, and the fourth interlayer insulating film 118 can be omitted. As another example, the upper electrode 178 can be formed on the capacitor dielectric layer 175 to fill the space between the lower electrodes 173A and 173B.

[0138] Both the lower electrodes 173A and 173B and the upper electrode 178 can include doped polysilicon, metal, conductive metal nitride, conductive metal silicide, conductive metal oxide, or a combination thereof. For example, the lower electrodes 173A and 173B and the upper electrode 178 can include, but are not limited to: doped polysilicon, Al, Cu, Ti, Ta, Ru, W, Mo, Pt, Ni, Co, TiN, TaN, WN, NbN, TiAl, TiAlN, TiSi, TiSiN, TaSi, TaSiN, RuTiN, NiSi, CoSi, IrOx, RuOx, or a combination thereof.

[0139] The capacitor dielectric layer 175 may include silicon oxide, silicon oxynitride, a high-k material having a higher dielectric constant than silicon oxide, or a combination thereof. The high-k material may include, but is not limited to: hafnium oxide (HfO2), hafnium silicon oxide (HfSiO), hafnium silicon oxynitride (HfSiON), hafnium tantalum oxide (HfTaO), hafnium titanium oxide (HfTiO), hafnium zirconium oxide (HfZrO), zirconium oxide (ZrO2), aluminum oxide (Al2O3), or a combination thereof.

[0140] In some embodiments, each of the lower electrodes 173A and 173B may include a second conductive pattern 171 and a second barrier conductive film 172. The second conductive pattern 171 and the second barrier conductive film 172 may be sequentially stacked on the bonding pads 160A and 160B. For example, the second conductive pattern 171 may have a columnar shape extending in the vertical direction Z on the bonding pads 160A and 160B. The second barrier conductive film 172 may conformally extend along the side surface and the upper surface of the second conductive pattern 171. The second barrier conductive film 172 may be disposed between the second conductive pattern 171 and the capacitor dielectric layer 175.

[0141] The second barrier conductive film 172 may reduce / prevent the diffusion of elements included in the second conductive pattern 171. As an example, the second conductive pattern 171 may include at least one of tungsten (W), aluminum (Al), and copper (Cu), and the second barrier conductive film 172 may include at least one of titanium (Ti), titanium nitride (TiN), tantalum (Ta), and tantalum nitride (TaN).

[0142] In some embodiments, the upper electrode 178 may include a third barrier conductive film 177 and a third conductive pattern 176. The third barrier conductive film 177 and the third conductive pattern 176 may be sequentially stacked on the capacitor dielectric layer 175. For example, the third barrier conductive film 177 may conformally extend along the capacitor dielectric layer 175. In some embodiments, the third barrier conductive film 177 may extend between the capacitor dielectric layer 175 and the fourth interlayer insulating film 118.

[0143] The third conductive pattern 176 may be a plate-like structure extending in a plane intersecting the vertical direction Z. The third conductive pattern 176 may extend along the upper surface of the third barrier conductive film 177. In some embodiments, the third conductive pattern 176 may extend along the upper surface of the fourth interlayer insulating film 118. For example, the upper surface of the fourth interlayer insulating film 118 may be disposed at the same height as the upper surface of the third barrier conductive film 177.

[0144] The third blocking conductive film 177 may reduce / prevent the diffusion of elements included in the third conductive pattern 176. As an example, the third conductive pattern 176 may include at least one of tungsten (W), aluminum (Al), and copper (Cu), and the third blocking conductive film 177 may include at least one of titanium (Ti), titanium nitride (TiN), tantalum (Ta), and tantalum nitride (TaN).

[0145] To increase the integration degree of a semiconductor memory device, a semiconductor memory device including a vertical channel transistor having a channel extending in a vertical direction has been proposed. To implement such a semiconductor memory device, a gate insulating layer and a gate electrode may be stacked on a side surface of a channel layer extending in the vertical direction. However, in such a case, in the process of forming the gate insulating layer and the gate electrode (which may include heat treatment, etc.), the channel layer may be damaged or the characteristics of the channel layer may be deteriorated, and a reduction in the performance and reliability of the semiconductor memory device may be caused.

[0146] In a semiconductor memory device according to some embodiments, the channel layer 130 may be formed by being stacked on the gate electrodes 150A and 150B and the gate insulating layer 140. Accordingly, a semiconductor memory device having improved performance and reliability may be provided. In addition, the semiconductor memory device according to some embodiments may have a two-transistor structure for each channel layer 130. For example, as described above, the gate electrodes 150A and 150B may include a first gate electrode 150A and a second gate electrode 150B that are "spaced apart from each other in the cell trench 112t". Accordingly, it is possible to provide a semiconductor memory device having a higher integration degree.

[0147] In addition, in a semiconductor memory device according to some embodiments, a part of the channel layer 130 may be disposed on an upper surface of the first interlayer insulating film 112. For example, as described above, the first extension part 134A may further extend along an upper surface of the first gate electrode 150A, and the second extension part 134B may further extend along an upper surface of the second gate electrode 150B. In such a case, the distances between the bonding pads 160A and 160B and the gate electrodes 150A and 150B may be adjusted by the thickness of the channel layer 130. Accordingly, it is possible to provide a semiconductor memory device according to some embodiments in which the distances between the bonding pads 160A and 160B and the gate electrodes 150A and 150B can be easily adjusted.

[0148] An insulating film 210 between the peripheral circuit element PT and the wiring may be formed on the first substrate 100. The peripheral circuit element PT may control the functions of semiconductor memory elements (including control elements and dummy elements) formed on the first substrate 100. The inter-wiring insulating film 210 may cover the peripheral circuit element PT. In some embodiments, the peripheral circuit element PT may include a fourth conductive pattern 220 and a fifth conductive pattern 230 sequentially formed on the upper surface of the first substrate 100. The fourth conductive pattern 220 and the fifth conductive pattern 230 may form various circuit elements for controlling the functions of the semiconductor memory elements. The peripheral circuit element PT may include not only various active elements (such as transistors), but also various passive elements (such as capacitors, resistors, and inductors) and combinations thereof.

[0149] In some embodiments, the peripheral circuit element PT and the inter-wiring insulating film 210 may be disposed under the first interlayer insulating film 112. For example, the lower insulating film 110 may be stacked on the upper surface of the inter-wiring insulating film 210. The first interlayer insulating film 112 may be stacked on the upper surface of the lower insulating film 110. That is, the semiconductor memory device according to some embodiments may have a CoP (Periphery on the Unit) structure.

[0150] In some embodiments, the peripheral circuit element PT may be electrically connected to the wire 120. For example, a wiring pattern 240 electrically connected to the peripheral circuit element PT may be further formed in the inter-wiring insulating film 210. In addition, a connection via 250 penetrating the lower insulating film 110 and electrically connecting the wire 120 and the wiring pattern 240 may be formed. Thus, the wire 120 may be electrically controlled through the peripheral circuit element PT.

[0151] Figure 25 is a diagram showing the NBTI characteristics and PBTI characteristics of an IGZO vertical channel transistor.

[0152] In Figure 25 , the horizontal axis represents the duty ratio, and the vertical axis represents the change in the threshold voltage dVTH of the vertical channel transistor. The duty ratio represents the ratio of the application time of the normal cut-off voltage VOFF to the elapsed time. Figure 25 is an example of the NBTI characteristics and PBTI characteristics as a function of the duty ratio, and Figure 25 the variations in

[0153] As Figure 25 shown in , as the duty ratio decreases, PBTI degradation becomes dominant, and at zero duty ratio, due to electron trapping in the channel layer, the PBTI effect becomes 100%. On the other hand, it can be seen that as the duty ratio increases, NBTI degradation becomes dominant, and when the duty ratio is 1, the NBTI effect becomes 100%.

[0154] Referring to Figure 22 、 Figure 23 and Figure 24 above, the above-described memory cell using an IGZO vertical channel transistor has both NBTI degradation characteristics and PBTI degradation characteristics, and the operation method of the semiconductor memory device according to the above exemplary embodiment can be more usefully applied to a semiconductor memory device including a memory cell using an IGZO vertical channel transistor.

[0155] Figure 26 and Figure 27 are diagrams showing a stacked semiconductor memory device according to an exemplary embodiment.

[0156] Referring to Figure 26 , the semiconductor memory device 900 may include a first semiconductor integrated circuit layer LA1 to a k-th semiconductor integrated circuit layer LAk. Herein, it is assumed that the lowermost first semiconductor integrated circuit layer LA1 is an interface or control chip, and it is assumed that the other semiconductor integrated circuit layers LA2 to LAk are slave chips including core memory chips. As described above, the slave chips may form a plurality of memory ranks.

[0157] The first semiconductor integrated circuit layer LA1 to the k-th semiconductor integrated circuit layer LAk may transmit and receive signals between the layers through through-substrate vias TSVs (e.g., through-silicon vias (or silicon through holes)). The lowermost first semiconductor integrated circuit layer LA1, which is an interface or control chip, may communicate with an external memory controller through a conductive structure formed on the outer surface.

[0158] Each of the first semiconductor integrated circuit layer 910 to the k-th semiconductor integrated circuit layer 920 may include a memory region 921 and a peripheral circuit 922 for driving the memory region 921. For example, the peripheral circuit 922 may include a row driver for driving the word lines of the memory, a column driver for driving the bit lines of the memory, a data input-output circuit for controlling data input-output, a command buffer for receiving commands from an external source and buffering the commands, and an address buffer for receiving addresses from an external source and buffering the addresses.

[0159] The first semiconductor integrated circuit layer 910 may further include a control circuit. The control circuit may control access to the memory region 921 based on commands and address signals from the memory controller, and may generate control signals for accessing the memory region 921.

[0160] Each of the semiconductor integrated circuit layers LA2 to LAk corresponding to the slave chips may include a compensation controller as described above. The compensation controller may perform the NBTI compensation operation and / or the PBTI compensation operation as described above.

[0161] Figure 27 Illustrates an example high - bandwidth memory (HBM) organization.

[0162] Referring Figure 27 , the HBM 1100 may have a stack of multiple DRAM semiconductor dies 1120, 1130, 1140, and 1150. The HBM with a stacked structure can be optimized through multiple independent interfaces called channels. According to the HBM standard, each DRAM stack can support up to 8 channels. Figure 27 Illustrates an example stack including 4 DRAM semiconductor dies 1120, 1130, 1140, and 1150, and each DRAM semiconductor die supports two channels CHANNEL0 and CHANNEL1.

[0163] Each channel provides access to an independent set of DRAM banks. Requests from one channel cannot access data attached to a different channel. The channels are clocked independently and do not need to be synchronized.

[0164] The HBM 1100 may also include an interface die 1110 or a logic die "at the bottom of the stacked structure" to provide signal routing and other functions. Some functions of the DRAM semiconductor dies 1120, 1130, 1140, and 1150 may be implemented in the interface die 1110.

[0165] Each of the DRAM semiconductor dies 1120, 1130, 1140, and 1150 may include a compensation controller as described above. The compensation controller may perform the NBTI compensation operation and / or the PBTI compensation operation as described above.

[0166] Figure 28 Is a block diagram showing a mobile system according to an example embodiment.

[0167] Referring Figure 28 , the mobile system 1200 includes an application processor (AP) 1210, a connection device 1220, a volatile semiconductor memory device (VM) 1230, a non - volatile semiconductor memory device (NVM) 1240, a user interface 1250, and a power supply 1260. In some embodiments, the mobile system 1200 may be, for example, a mobile phone, a smart phone, a personal digital assistant (PDA), a portable multimedia player (PMP), a digital camera, a music player, a portable game console, a navigation system, or another type of electronic device.

[0168] The application processor 1210 can execute applications (e.g., a web browser, a game application, a video player, etc.). The connection device 1220 can execute wired communication or wireless communication with an external device. The volatile semiconductor memory device 1230 can store data processed by the application processor 1210 or can operate as a working memory. The non-volatile semiconductor storage device 1240 can store a boot image for booting the mobile system 1200. The user interface 1250 can include at least one input device (such as a keyboard, a touch screen, etc.) and at least one output device (such as a speaker, a display device, etc.). The power supply 1260 can supply a power voltage to the mobile system 1200.

[0169] As described above, the volatile semiconductor memory device 1230 can include the address manager (ADMNG) 300 and the compensation controller (CMCON) 600 as described above. As described above, the address manager 300 can provide NBTI information and PBTI information, and the compensation controller can perform NBTI compensation operations and / or PBTI compensation operations.

[0170] In one embodiment, the address manager 300 can be included in the memory controller of the application processor 1210, and the compensation controller 600 can be included in the volatile semiconductor memory device 1230.

[0171] As described above, the semiconductor memory device and the method of operating the semiconductor memory device according to the example embodiments can improve the performance and reliability of the semiconductor memory device by effectively managing NBTI-vulnerable cells and PBTI-vulnerable cells and by effectively compensating for the change in the threshold voltage.

[0172] The example embodiments can be applied to any electronic device and system. For example, the disclosure can be applied to systems such as memory cards, solid state drives (SSDs), embedded multimedia cards (eMMCs), universal flash storage (UFSs), mobile phones, smart phones, personal digital assistants (PDAs), portable multimedia players (PMPs), digital cameras, camcorders, personal computers (PCs), server computers, workstations, laptop computers, digital televisions (TVs), set-top boxes, portable game consoles, navigation systems, wearable devices, Internet of Things (IoT) devices, Internet of Everything (IoE) devices, e-books, virtual reality (VR) devices, augmented reality (AR) devices, server systems, automotive driving systems, etc.

[0173] The foregoing is an illustration of example embodiments and should not be construed as a limitation of the example embodiments. Although some example embodiments have been described, those skilled in the art will readily understand that many modifications are possible in the example embodiments without substantially departing from the disclosure.

Claims

1. A semiconductor memory device, comprising: a plurality of memory cells, each memory cell including a cell transistor including a gate electrode connected to a word line corresponding to a row address, the cell transistor being configured to switch during normal operation based on a normal on voltage and a normal off voltage applied to the word line; an address manager configured to provide negative bias temperature instability (NBTI) information and positive bias temperature instability (PBTI) information, the NBTI information including row addresses of NBTI vulnerable cells among the plurality of memory cells, wherein a decrease value of a threshold voltage of a cell transistor in the NBTI vulnerable cell due to application of a normally off voltage is greater than a reference decrease value, and the PBTI information including row addresses of PBTI vulnerable cells among the plurality of memory cells, wherein an increase value of a threshold voltage of a cell transistor in the PBTI vulnerable cell due to application of a normally on voltage is greater than a reference increase value; and The compensation controller is configured as: increasing a threshold voltage of the NBTI vulnerable cell by performing an NBTI compensation operation based on the NBTI information, and The threshold voltage of the PBTI vulnerable cell is reduced by performing a PBTI compensation operation based on the PBTI information.

2. The semiconductor memory device according to claim 1, wherein The compensation controller is further configured to apply a compensation on-voltage higher than a normal on-voltage to a word line corresponding to a row address of the NBTI vulnerable cell based on the NBTI information during the NBTI compensation operation.

3. The semiconductor memory device according to claim 2, wherein: The compensation controller is further configured to increase the compensation on-voltage as the operating temperature of the semiconductor memory device increases.

4. The semiconductor memory device according to claim 1, wherein: The compensation controller is further configured to apply a compensation cut-off voltage lower than a normal cut-off voltage to a word line corresponding to a row address of the PBTI vulnerable cell based on the PBTI information during the PBTI compensation operation.

5. The semiconductor memory device according to claim 4, wherein: The compensation controller is further configured to reduce the compensation cutoff voltage as the operating temperature of the semiconductor memory device increases.

6. The semiconductor memory device according to claim 1, wherein: The compensation controller is further configured to periodically perform the NBTI compensation operation and the PBTI compensation operation based on a compensation period.

7. The semiconductor memory device according to claim 6, wherein: The compensation controller is further configured to reduce the compensation period as an operating temperature of the semiconductor memory device increases.

8. The semiconductor memory device according to any one of claims 1 to 7, wherein: The address manager is further configured to store NBTI information generated by a test operation of the semiconductor memory device.

9. The semiconductor memory device according to any one of claims 1 to 7, wherein: The address manager is further configured to provide PBTI information by monitoring access addresses with respect to normal operations of the plurality of memory cells during normal operations, the normal operations including read operations and write operations.

10. The semiconductor memory device according to any one of claims 1 to 7, further comprising: a refresh controller configured to control a hammer refresh operation with respect to a first row physically adjacent to a second row, wherein the second row corresponds to each hammer address among a plurality of access addresses for normal operation of the plurality of memory cells, the normal operation including a read operation and a write operation, wherein the hammer address is accessed more intensively than other access addresses among the plurality of access addresses, Therein, the address manager is configured to provide the hammer address as PBTI information.

11. The semiconductor memory device according to any one of claims 1 to 7, wherein: The cell transistor is a vertical channel transistor including a channel layer formed of indium gallium zinc oxide.

12. The semiconductor memory device according to any one of claims 1 to 7, wherein: The plurality of memory cells are grouped into a plurality of memory banks, The compensation controller is configured to independently perform a PBTI compensation operation and a NBTI compensation operation on each memory bank.

13. A semiconductor memory device comprising: a plurality of memory cells, each memory cell including a cell transistor including a gate electrode connected to a word line corresponding to a row address, the cell transistor being configured to switch during normal operation based on a normal on voltage and a normal off voltage applied to the word line; an address manager configured to provide negative bias temperature instability (NBTI) information and positive bias temperature instability (PBTI) information, the NBTI information including row addresses of NBTI vulnerable cells among the plurality of memory cells, wherein a decrease value of a threshold voltage of a cell transistor in the NBTI vulnerable cell due to application of a normally off voltage is greater than a reference decrease value, and the PBTI information including row addresses of PBTI vulnerable cells among the plurality of memory cells, wherein an increase value of a threshold voltage of a cell transistor in the PBTI vulnerable cell due to application of a normally on voltage is greater than a reference increase value; and The compensation controller is configured as: increasing a threshold voltage of the NBTI vulnerable cell by applying a compensation turn-on voltage higher than a normal turn-on voltage to a word line corresponding to a row address of the NBTI vulnerable cell and by performing an NBTI compensation operation based on the NBTI information, and The threshold voltage of the PBTI vulnerable cell is reduced by applying a compensation cut-off voltage lower than a normal cut-off voltage to a word line corresponding to a row address of the PBTI vulnerable cell and by performing a PBTI compensation operation based on the PBTI information.

14. A method of operating a semiconductor memory device, the semiconductor memory device comprising a plurality of memory cells, each memory cell comprising a cell transistor, the cell transistor comprising a gate electrode connected to a word line corresponding to a row address, the cell transistor being configured to switch during normal operation based on a normal on voltage and a normal off voltage applied to the word line, the method comprising: providing negative bias temperature instability (NBTI) information, the NBTI information including a row address of an NBTI vulnerable cell among the plurality of memory cells, wherein a reduction value of a threshold voltage of a cell transistor in the NBTI vulnerable cell caused by application of a normally off voltage is greater than a reference reduction value; providing positive bias temperature instability (PBTI) information, the PBTI information including a row address of a PBTI-vulnerable cell among the plurality of memory cells, wherein an increase value of a threshold voltage of a cell transistor in the PBTI-vulnerable cell caused by application of a normal on voltage is greater than a reference increase value; increasing a threshold voltage of the NBTI vulnerable cell by performing an NBTI compensation operation based on the NBTI information; and The threshold voltage of the PBTI vulnerable cell is reduced by performing a PBTI compensation operation based on the PBTI information.

15. The method according to claim 14, wherein: The steps to provide NBTI information include: applying a test cutoff voltage lower than a normal cutoff voltage to a word line corresponding to a test row address; performing a read operation with respect to a word line corresponding to a test row address; and It is determined whether the test row address is a row address of an NBTI vulnerable cell based on a result of the read operation.

16. The method according to claim 15, further comprising: determining a memory cell corresponding to the test row address as a defective memory cell when a decrease value of a threshold voltage of a cell transistor due to application of a test cutoff voltage is greater than a first reference decrease value, and When a decrease value of a threshold voltage of a cell transistor due to application of a test cutoff voltage is less than a first reference decrease value and greater than a second reference decrease value, a memory cell corresponding to the test row address is determined as an NBTI vulnerable cell.

17. The method according to claim 14, wherein: Steps to providing PBTI information include: applying a test on-voltage higher than a normal on-voltage to a word line corresponding to a test row address; performing a read operation with respect to a word line corresponding to a test row address; and Whether the test row address is a row address of a PBTI vulnerable cell is determined based on a result of the read operation.

18. The method according to claim 17, further comprising: When an increase value of the threshold voltage of the cell transistor due to application of the test-on voltage is greater than a first reference increase value, determining a memory cell corresponding to the test row address as a defective memory cell, and When an increase value of a threshold voltage of a cell transistor due to application of a test-on voltage is less than a first reference increase value and greater than a second reference increase value, a memory cell corresponding to the test row address is determined as a PBTI vulnerable cell.

19. The method according to any one of claims 14 to 18, wherein: The step of performing the NBTI compensation operation includes applying a compensation turn-on voltage higher than a normal turn-on voltage to a word line corresponding to a row address of the NBTI vulnerable cell based on the NBTI information.

20. The method according to any one of claims 14 to 18, wherein: The step of performing the PBTI compensation operation includes applying a compensation cut-off voltage lower than a normal cut-off voltage to a word line corresponding to a row address of the PBTI vulnerable cell based on the PBTI information.

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