Power switching semiconductor device and method of packaging at least one power switching semiconductor device die in package

Abstract

A power switch semiconductor device includes: a power switch semiconductor device die having three electrodes, namely a substrate electrode and two front electrodes; and a package having a substrate with an island to which the die conductive die is attached with the backside electrode facing a top side of the package. The package has an insulating portion that encapsulates the electronic molding compound of the die. There is an aperture through the insulating portion of the package to access at least one electrode of the die, and a conductive path through the aperture connects the at least one electrode of the die. Comprising the one or more electrodes of the die to respective pin output connection ports on a bottom side of the package. A method of packaging at least one of the power switch semiconductor device dies in a package is also disclosed.

Description

Technical Field

[0001] The present invention relates to a power switch semiconductor device or module and a method of encapsulating at least one power switch semiconductor device die in a package. Background Art

[0002] Discrete power switch semiconductor device products are typically encapsulated by attaching a power switch semiconductor device die substrate (back) conductive die to a die pad (metal island) on a metal lead frame structure, which is connected in the metal lead frame to a pin output connection port of the package corresponding to the substrate of the power switch semiconductor device die. The other two electrodes on the other (front) side of the power switch semiconductor device die are bonded and connected to the other two corresponding pin output ports in the metal lead frame, where all three pin output connection ports are shorted by the metal lead frame due to the mechanical strength requirements of the structure. After the bonding process, molding of an electronic molding compound (EMC) is performed to form an insulating body, and then multiple encapsulated units are separated into individual units. If necessary, the metal pins of the pin output connection ports are trimmed and formed, and finally tested.

[0003] The difference in the coefficient of thermal expansion (CTE) between the metal bonding wire and the EMC insulating package body is a major consideration for the reliability of the encapsulation process. During the operating life of the encapsulated power switch semiconductor device, thermal cycling will occur due to the temperature rise during actual application operation, as well as cooling after power-off. Due to the thermal cycling and the CTE difference between the metal and the CTE insulating body, mechanical stress will be generated between the bonding wire and the plastic package body during daily operation.

[0004] Various package designs of power switch semiconductor devices typically face the substrate side of the power switch semiconductor device die downward, such that the pin output ports of the substrate electrodes of the power switch semiconductor device die will be in the same plane as the other two pin output connection ports. Therefore, the heat generated during the operation of such encapsulated power switch semiconductor devices needs to pass through the body of the package, or travel a long distance to near the periphery of the metal substrate before the heat can be conducted to the environment or air. As a result, the thermal resistance of the package increases. Figure 1 is a TOLL-type package of a single MOSFET, which shows the concept under discussion. In Figure 1 it, the substrate (back) 101 is connected to the die substrate by conductive die attachment, while the other two contacts 102 and 103 are bonded and connected to the front electrodes of the power semiconductor die by wires, foils or clips.

[0005] In practical applications, the thermal resistance of the package is a limiting factor that restricts the maximum power consumption that can be addressed by the die of the same power switch semiconductor device. For the same power switch semiconductor die, a packaging method that reduces the thermal resistance is always preferred because it means an increase in the maximum power handling capacity in practical applications.

[0006] In addition, a short circuit during the packaging of the pin output connection ports of the packaged power switch semiconductor devices impedes the concurrent testing of multiple units before separating the multiple packaged devices into individual units, and thus limits manufacturing efficiency. Therefore, it is desirable to design a method to enable the possibility of concurrent testing of multiple packaged devices before separating them into individual packaged units.

[0007] Therefore, solving or alleviating these known problems in the packaging of power switch semiconductor devices can improve device reliability, power handling capacity, and the efficiency of packaging operations. SUMMARY OF THE INVENTION

[0008] A first object of the present invention is to eliminate packaging reliability problems of one or more power switch semiconductor devices due to the use of a bonding process. A second object of the present invention is to reduce the thermal resistance of the packaging of one or more power switch semiconductor devices. A third object of the present invention is to enable the possibility of concurrent testing of multiple packaging units of one or more power switch semiconductor devices before separating them into individual packaging units. The present invention aims to mitigate or at least alleviate problems associated with at least one or more of the foregoing problems.

[0009] According to one aspect of the present invention, there is provided a method of packaging at least one power switch semiconductor device die in a package, the power switch semiconductor device die having three electrodes, namely a back electrode and two front electrodes, the method comprising the following steps:

[0010] (A) attaching the conductive die of the power switch semiconductor device to an island of a substrate of the package, wherein the back electrode faces the top side of the package;

[0011] (B) encapsulating the power switch semiconductor device die with an electronic molding compound to form an insulating portion of the package;

[0012] (C) forming a hole through the insulating portion of the package to access at least one electrode of the power switch semiconductor device die;

[0013] (D) forming a conductive path through the hole for connecting the at least one electrode of the power switch semiconductor device die; and

[0014] (E) forming conductive connections from the one or more electrodes of the power switch semiconductor device die to corresponding pin-out connection ports on the bottom side of the package.

[0015] In a preferred embodiment, step (C) includes forming a hole through the insulating portion of the package to access at least one other electrode; step (D) includes forming a conductive path through the hole for connecting the at least one other electrode; and step (E) includes forming a conductive connection from the at least one other electrode to a corresponding pin output connection port on the bottom side of the package.

[0016] Preferably, the method comprises the step (F): processing the surface of the one or more pin-out connection ports of the package.

[0017] More preferably, in step (F), the surface of the one or more pin-out connection ports is processed by related processes such as solder mask, gold / silver plating or solder hot air leveling as is well known in bare PCB manufacturing.

[0018] Preferably, the method comprises step (G): testing the power switch semiconductor device die through the one or more pin-out connection ports of the package.

[0019] In a preferred embodiment, the method involves packaging a plurality of the power switching semiconductor device dies in a same package having a common packaging substrate, wherein each power switching semiconductor device die undergoes the aforementioned steps.

[0020] More preferably, the method comprises the step (H): cutting the obtained package into a plurality of smaller packages, each of the smaller packages comprising one or more of the power switch semiconductor device dies.

[0021] In another preferred embodiment, the method involves packaging a plurality of the power switching semiconductor device dies in the same package having a common packaging substrate, wherein each power switching semiconductor device die undergoes the aforementioned steps, and the method includes a step (H) after step (G): cutting the resulting package into a plurality of smaller packages, each smaller package including one or more of the power switching semiconductor device dies.

[0022] Preferably, the substrate of the package is selected from a lead frame and a bare PCB.

[0023] More preferably, the substrate of the package comprises a bare PCB selected from a double-sided or multi-layer PCB and a metal-based PCB to enhance heat dissipation.

[0024] Even more preferably, the substrate of the package includes a PCB having blind vias for heat transfer from the one or more power switching semiconductor device dies to the metal on the top side of the package.

[0025] Even more preferably, the substrate of the package includes a PCB having ceramic insulation between the one or more power switching semiconductor device dies and the metal on the top side of the package to reduce the junction-to-case thermal resistance.

[0026] Preferably, in step (B), an electronic molding compound is applied by a process selected from injection molding and dispensing and high-temperature curing.

[0027] Preferably, in step (C), the one or more holes are formed by laser drilling.

[0028] Preferably, in steps (D) and (E), the one or more conductive paths and conductive connectors are formed by related processes known in bare PCB manufacturing such as electroless plating or patterning of the conductive paths.

[0029] In a further preferred embodiment, the method includes: after step (D) and before step (E), repeating steps (B), (C), and (D) as steps (B'), (C'), and (D') respectively at least once as follows:

[0030] (B') Encapsulating the resulting assembly with an electronic molding compound to form another layer of the insulating portion of the package;

[0031] (C’) Forming holes through all the insulating portions of the package to access at least one additional electrode of the power switching semiconductor device die; and

[0032] (D’) Forming conductive paths through the holes for connecting the at least one additional electrode of the power switching semiconductor device die.

[0033] According to another aspect of the present invention, there is provided a power switching semiconductor device, comprising:

[0034] A power switching semiconductor device die having three electrodes, namely a back electrode and two front electrodes;

[0035] A package having a substrate with islands, to which the power switching semiconductor device conductive die is attached, wherein the back electrode faces the top side of the package, and the package has an insulating portion encapsulating the power switching semiconductor device die with an electronic molding compound;

[0036] a hole that passes through the insulating portion of the package to access at least one electrode of the power switch semiconductor device die;

[0037] a conductive path through the hole for connecting the at least one electrode of the power switch semiconductor device die; and

[0038] a conductive connection from the one or more electrodes of the power switch semiconductor device die to a corresponding pin output connection port on the bottom side of the package.

[0039] In a preferred embodiment, the power switch semiconductor device includes: a hole that passes through the insulating portion of the package to access at least one other electrode, a conductive path through the hole for connecting the at least one other electrode, and a conductive connection from the at least one other electrode to a corresponding pin output connection port on the bottom side of the package.

[0040] Preferably, the one or more pin output connection ports of the package have a treated surface.

[0041] In another preferred embodiment, the power switch semiconductor device includes: a plurality of the power switch semiconductor device dies encapsulated in the same package, wherein each power switch semiconductor device die conductive die is attached to the same package substrate and the back electrode faces the top side of the package.

[0042] More preferably, the package has an insulating portion encapsulating the respective power switch semiconductor device die, each insulating portion having the hole and the conductive path through the hole.

[0043] Preferably, the substrate of the package is selected from a lead frame and a bare PCB.

[0044] More preferably, the substrate of the package includes a bare PCB selected from a double-sided or multi-layer PCB and a metal-based PCB to enhance heat dissipation.

[0045] Even more preferably, the substrate of the package includes a PCB having blind vias for heat transfer from the one or more power switch semiconductor device dies to metal on the top side of the package.

[0046] Even more preferably, the substrate of the package includes a PCB having ceramic insulation between the one or more power switch semiconductor device dies and metal on the top side of the package to reduce the junction-to-case thermal resistance.

[0047] In a further preferred embodiment, the insulating portion includes at least one additional layer encapsulating the power switch semiconductor device die and the previous layer of the electronic molding compound, wherein the holes and the conductive paths through the holes are associated with each layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0048] Embodiments of the present invention will now be described by way of example with reference to the accompanying drawings, in which:

[0049] Figure 1 A TOLL-type package of a single power MOSFET device product is shown by a top view, a bottom view, and two side views;

[0050] Figure 2 Some typical power switch semiconductor devices that can be encapsulated into a product according to the present invention are shown by five schematic diagrams;

[0051] Figures 3(a) to 3(d) A first design embodiment of encapsulating a single power switch semiconductor device into a product of the present invention is shown by a bottom view and three progressive cross-sectional side views respectively;

[0052] Figure 4 (a) to Figure 4 (c) respectively disclose the encapsulation of multiple power switch power semiconductor dies into various module products using the first design embodiment of the present invention by a circuit diagram and a bottom view;

[0053] Figure 5 is a circuit diagram of a three-phase bridge driver that can be encapsulated as a module product using the present invention; and

[0054] Figures 6(a) to 6(d) A second design embodiment of encapsulating a circuit as shown in Figure 5 into a module product using the present invention is shown by a bottom view and a cross-sectional side view respectively. DETAILED DESCRIPTION OF THE INVENTION

[0055] In Figure 2 , some typical power switch semiconductor devices that can be encapsulated using the present invention are shown, namely an NPN bipolar device 201, an N-type MOSFET device 202, an IGBT device 203, a PNP bipolar device 204, and a P-type MOSFET device 205. It should be noted that the list is only used as an example and is by no means exhaustive.

[0056] A common characteristic of all such power switch semiconductor devices is that they all have three electrodes, namely a substrate electrode on one side of the substrate (usually referred to as the back side) that serves as a switching terminal of the power switch semiconductor device die, and two other electrodes on the other side of the power switch semiconductor device die (usually referred to as the front side), namely a control electrode that controls the on / off state of the power switch semiconductor device die and another switching electrode for the power switch semiconductor device die.

[0057] Now referring to the Figures 3(a) to 6(d) drawings, there are shown embodiments of a method of encapsulating at least one power switch semiconductor device die in a single package according to the present invention and the resulting packaged power switch semiconductor device.

[0058] Figures 3(a) to 3(d) There is shown a first preferred embodiment of a method of using the present invention to encapsulate at least one, or in this particular instance a single, power switch semiconductor device die 301. The encapsulation method process begins by attaching the substrate (back side) 302 of the power switch semiconductor device die 301 to the internal metal surface 309 of the substrate of the package 30301 or 30302 or 30303 by means of a conductive die attach compound 304.

[0059] The substrate of the package is preferably a metal lead frame 30301 for achieving a lower thermal resistance. Both heat conduction and electrical conduction are achieved between the power switch semiconductor device die 301 and the metal surface 309(a) of the package that is on the opposite side of the power switch semiconductor device die. The substrate of the package can also be various types of bare PCBs 30302 (metal-based PCBs, such as aluminum- or copper-based PCBs, or ordinary PCBs), where one exposed metal surface 309(a) serves as a heat conduction medium to the external environment (such as air), and the other (internal) metal surface 309 serves as a die attach surface, and the two surfaces are interconnected by blind vias 305. As a specific example, a PCB without blind vias can also be used, with an increase in thermal resistance while achieving electrical isolation between the die attach pad and the exposed metal surface 309(a) of the package. A PCB using ceramic as a dielectric or ceramic insert 306 between the die attach pad and the exposed metal surface 309(a) can also be used to increase the thermal conductivity while also achieving electrical isolation. Then, the front electrodes of the power switch semiconductor device die 301, namely the control electrode 307 and the switching electrode 308, together with the internal metal surface 309 of the package substrate 30301 or 30302 or 30303 can be used in further processes according to the present invention. The bottom view and cross-sectional side view of the package after this processing step are shown in Fig. 3(a).

[0060] After the die attach process, an insulating portion 310 of the body of the package is formed by applying an electronic molding compound (EMC). Preferably, an injection molding process is used for this processing step. Alternative processing methods, such as drop dispensing followed by thermal curing, may also be applied.

[0061] Then, preferably, selective drilling through the insulating body of the package to reach the three electrodes 302, 307, and 308 of the power switch semiconductor device die 301 is performed by laser drilling. Generally, the drilled holes 311 will reach directly the two electrodes 307 and 308 at the bonding pads on the front side of the power switch semiconductor device die 301, and will reach indirectly the substrate electrode 302 of the power switch semiconductor device die 301 through metal connections along the internal metal surfaces 309 within the substrate of the package 30301 or 30302, 30303. An underside view and a cross-sectional side view of the package up to the above processing steps are shown in Fig. 3(b).

[0062] Then, metal interconnections between the three electrodes 302, 307, and 308 of the power switch semiconductor device die 301 and the corresponding pin-out connection ports of the package are preferably performed by a process similar to that for bare PCB manufacturing. The processing steps involved may include, but are not limited to, a combination of electroless metal plating, photographic processes, and metal etching to define the electrical connection paths within the package as required. An underside view and a cross-sectional side view of the package up to the above processing steps are shown in Fig. 3(c). In Fig. 3(c), the metal patterns 312, 313, and 314 are the connecting metals from the bottom side of the package to the corresponding switching electrodes 308, control electrode 307, and substrate electrode 302 of the switched power semiconductor device die 301 through the respective holes 311 in Fig. 3(b) below such metal patterns 312, 313, and 314. Further processing steps will then be taken to define the pin-out connection ports on these metal connection patterns.

[0063] The surface treatment of the pin-out connection ports is similar to that for bare PCB manufacturing processes, such as solder mask, gold / silver plating, or hot air solder leveling. An underside view and a cross-sectional side view of the package up to the above processing steps are shown in Fig. 3(d). In Fig. 3(d), 316, 317, and 318 are the pin-out connection ports for the switching electrode 308, substrate electrode 302, and control electrode 307, respectively. The solder mask 315 covers the areas other than the pin-out connection ports 316 - 318, and the dashed shapes 312, 313, and 314 in the underside view are the metal traces located below the solder mask as in Fig. 3(c).

[0064] Optionally, an isolation polymer similar to the solder mask in bare PCB manufacturing may be deposited on the top side of the package to achieve heat transfer coverage of the exposed metal to the environment.

[0065] Based on the foregoing description, a method of encapsulating at least one power switch semiconductor device die in a package may generally include at least the following steps:

[0066] (A) attaching the conductive die of the power switch semiconductor device to an island of a substrate of the package, with the back or substrate electrode facing the top side of the package;

[0067] (B) encapsulating the power switch semiconductor device die with an electronic molding compound to form an insulating portion of the package;

[0068] (C) forming a hole through the insulating portion of the package to access at least one, e.g., a front electrode, of the power switch semiconductor device die;

[0069] (D) forming a conductive path through the hole in the package for connecting the at least one electrode of the power switch semiconductor device die; and

[0070] (E) forming a conductive connection from the one or more electrodes of the power switch semiconductor device die to corresponding pin output connection ports on the bottom side of the package.

[0071] It should be noted that step (C) may include forming a hole through the insulating portion of the package to access at least one other, e.g., a back electrode. In this case, step (D) includes forming a conductive path through the hole in the package for connecting the at least one other electrode, and step (E) includes forming a conductive connection from the at least one other electrode to corresponding pin output connection ports on the bottom side of the package.

[0072] The encapsulation method of the present subject matter may include step (F): treating the surface of the one or more pin output connection ports of the package; and step (G): testing the power switch semiconductor device die through the one or more pin output connection ports of the package.

[0073] As a variant of the described embodiment, after the processing steps of obtaining the component of FIG. 3(c), the package body molding, selective drilling, and internal connection implementation may be repeated until the last layer of the pin output connection ports (i.e., the bottom side of the package) is reached, and then the solder mask and pin output connection port surface treatment are performed. It is contemplated that this variant and similar variants fall within the scope of the present invention.

[0074] Referring to the repeated steps, they are:

[0075] · Package body molding - step (B') encapsulating the obtained component with an electronic molding compound to form another layer of the insulating portion of the package;

[0076] · Selective drilling - Step (C’) forms holes that penetrate all the insulating portions of the package to reach at least one additional electrode of the power switch semiconductor device die; and

[0077] · Internal connection implementation - Step (D') forms a conductive path for the via hole that connects the at least one additional electrode of the power switch semiconductor device die within the package.

[0078] Considering these repeated steps, the packaging method of this subject includes: after Step (D) and before Step (E), repeating Steps (B), (C), and (D) respectively as Steps (B'), (C'), and (D') one or more times, depending on the number of additional layers of the insulating portion of the required package.

[0079] Based on the foregoing description, the power switch semiconductor device packaged by the described method can be generally summarized as at least including: a power switch semiconductor device die having three electrodes, namely a substrate electrode and two front electrodes; and a package having a substrate with islands, to which the conductive die of the power switch semiconductor device is attached, wherein the back electrode faces the top side of the package. The package has an insulating portion of an electronic molding compound that encapsulates the power switch semiconductor device die. There are holes that penetrate the insulating portion of the package to reach at least one, for example, a front electrode of the power switch semiconductor device die, and a conductive path within the package connects the at least one electrode of the power switch semiconductor device die through the holes. It also includes conductive connectors from one or more electrodes of the power switch semiconductor device die to the corresponding pin output connection ports on the bottom side of the package.

[0080] For some circuits, the power switch semiconductor device may include holes that penetrate the insulating portion of the package to reach at least one other, for example, a back electrode within the package, a conductive path within the package that connects the at least one other electrode through a via hole, and a conductive connector from the at least one other electrode to the corresponding pin output connection ports on the bottom side of the package.

[0081] Since all the interconnections between the electrodes 302, 307, and 308 of the power switch semiconductor device die 301 and the corresponding pin output connection ports 316, 317, and 318 of the package are integrated within the package, eliminating the wire bonding process, there are no package reliability problems related to bonding in the packaged power switch semiconductor device of the present invention.

[0082] In addition, since the substrate - side die pad that is thermally linked to the top - side metal 309(a) of the package will face upward and be exposed to the environment (air or through an additional heat sink) after being soldered in the PCBA, the thermal resistance will be reduced compared to the existing packaging method where the substrate electrode faces downward.

[0083] In addition, all three pin output connection ports 316, 317, and 318 of each package are essentially insulated. Additionally, the two pin output connection ports connected to the front electrode of the power switch semiconductor device die 301 of each individual packaged device are isolated from all other such pin output connection ports of other packages fabricated in multiple packages in a single pass, where only the substrate pin output connection ports of the multiple packages are connected. For these reasons, concurrent testing of multiple package units becomes possible.

[0084] As discussed, the final testing of the packaged device is preferably performed by concurrent testing of multiple package units in the form of a panel before they are separated into individual units. Of course, the normal process of separating into individual units before the final testing is still possible.

[0085] Another variation of the described embodiment is to package multiple power switch semiconductor devices having a common substrate electrode for an application in a single package. In this regard, Figure 4 (a) through 4(c) show some typical examples of semiconductor circuits that can be packaged using the present invention.

[0086] In Figure 4 (a), the circuit diagrams of three N-type MOSFET devices 401, 402, and 403 having a common drain (substrate) electrode connected to VDD and the corresponding bottom views of the packages are shown as potential candidates for using the present invention and multi-die packaging.

[0087] Using the processing steps described in the previous embodiment, the corresponding gate electrodes and source electrodes of the N-type MOSFET device dies 401, 402, and 403, namely G1, G2, G3, S1, S2, and S3, are connected to the corresponding pin output connection ports of the package, and the substrate electrodes of the N-type MOSFET device dies 401, 402, and 403 are connected to the VDD pin output connection port of the package. Figure 4 (a) also shows the corresponding bottom view of the pin output connection ports of the package, where the dashed shape represents the metal pattern under the solder mask. The three packaged power switch semiconductor device dies (N-type MOSFETs) can be used as the three high-side devices in a three-phase bridge for various applications such as BLDC or induction motor drivers.

[0088] In Figure 4 (b), the circuit diagram and bottom view of the corresponding package for one P-type MOSFET device 404 and one N-type MOSFET device 405 are shown, where the common drain (substrate) electrode connected to the output pins outside the package is shown as another potential candidate for using the present invention and multi-die packaging.

[0089] The source electrodes of the P-type MOSFET device 404 and the N-type MOSFET device 405 are respectively connected to the VDD lead connection port and the VSS lead connection port of the package. The gate electrodes of the P-type MOSFET device 404 and the N-type MOSFET device 405 are respectively connected to the lead connection ports G4 and G5 of the package. The substrate electrodes of the P-type MOSFET device 404 and the N-type MOSFET device 405 are connected to the output lead connection port of the package. The processing steps for such a package are as described in the previous embodiments. The corresponding bottom view of the pin output connection port of the package is also shown as a metal pattern under the solder mask in a dashed shape. This packaged circuit can be used as a half-bridge driver or a motor driver for power switch conversion.

[0090] In Figure 4 (c), the circuit diagrams of two N-type MOSFET devices 406 and 407 having a common drain (substrate) electrode and the corresponding bottom view of the package are shown as another potential candidate for using the present invention and multi-die packaging.

[0091] The corresponding gate electrodes and source electrodes of the N-type MOSFET devices 406 and 407, namely G6, G7, S6, and S7, are connected to the corresponding pin output connection ports of the package using the processing steps described in the previous embodiments. The corresponding bottom view of the pin output connection port of the package is also shown as a metal pattern under the solder mask in a dashed shape. The target application of this packaged module is overcharge and over-discharge protection of lithium batteries. Since there is no need for an external pin output connection to the substrate node, the drilling of holes to reach the substrate during the selective drilling process can be omitted.

[0092] Generally speaking, for multi-die packaging, the method involves packaging multiple power switch semiconductor device dies in the same package having a common package substrate, where each power switch semiconductor device die undergoes at least steps (A) to (E) and optionally steps (F) and (G). In the packaged product, the substrate has corresponding portions or islands to which the power switch semiconductor device die conductive dies are attached. Each power switch semiconductor device die conductive die is attached to the same substrate, with its back electrode facing the top side of the package. The package has corresponding insulating portions that encapsulate the power switch semiconductor device dies, and each insulating portion has the holes of step (C) and the conductive paths through the holes of step (D).

[0093] For more complex circuits, more interconnect layers will be required. Using additional layers or more layers sandwiching the PCB package substrate can be used to solve the routing problem. Alternatively, reuse of EMC molding, selective via drilling, and conductive path fabrication using processes similar to those described for bare PCB fabrication can also be used. Thus, in the resulting power switch semiconductor device product, the insulating portion includes at least one additional layer encapsulating the power switch semiconductor device die and the previous layer's electronic molding compound, wherein the holes of step (C) and the conductive paths through the holes of step (D) are associated with each layer.

[0094] It should be noted that the examples described are given only as typical examples and are by no means exhaustive.

[0095] In the description so far, there are limitations to the common substrate connections within the package for encapsulating multiple switch semiconductor device dies. This may limit the adoption of the present invention because the separation of substrate electrodes is quite common in many application circuits.

[0096] A second embodiment of the present invention is disclosed herein, where the limitations of the common substrate can be avoided. Figure 5 is a circuit diagram of a three-phase bridge driver having six N-type MOSFET device dies 501 - 506, the dies having substrate electrodes that cannot be shorted together. A typical application of this semiconductor circuit is a power driver for a BLDC or induction motor. This semiconductor circuit will now be used as a candidate to illustrate the second embodiment of the present invention for packaging the circuit as a module.

[0097] In Figure 5 , the N-type MOSFET devices 501, 502, and 503 have a common drain (substrate) connection to the pin output connection pad VDD and thus share a common die attachment island in the package substrate. However, each of the N-type MOSFET devices 504, 505, and 506 requires a separate die attachment island isolated in the package substrate for circuit connection. Thus, a package substrate having multiple (in this case, four) isolated die attachment islands will be required.

[0098] For the first embodiment, it is possible to use a metal lead frame having multiple die attachment islands as the package substrate, provided that multiple package modules do not need to be concurrently tested before being separated into individual modules. By using a PCB substrate, the advantages of such concurrent testing can also be utilized.

[0099] Figures 6(a) to 6(d) Illustrates the use of the method of the present invention according to Figure 5A preferred embodiment of packaging six N-type MOSFET device dies 501-506 of a circuit into a packaging module. In these figures, although only a PCB with blind vias is disclosed for use between the die attachment island and the exposed metal surface of the package as the packaging substrate, it should be understood that the use of other types of packaging substrates is equally possible.

[0100] The packaging method flow of this second embodiment begins with attaching the substrates of the power switch semiconductor device dies 501-506 to the corresponding die attachment islands of the packaging substrate through a conductive die attachment compound.

[0101] The substrate of the package is preferably one selected from various types of bare PCBs (metal-based PCBs such as aluminum- or copper-based PCBs, or ordinary PCBs), where multiple exposed metal surfaces are used as heat conduction media to the external environment (such as air), and the other side is used as the die attachment surface, and the two sides are interconnected by blind vias.

[0102] As a specific example, a PCB without blind vias can also be used, with an increase in thermal resistance while achieving electrical isolation between the die attachment pads and the exposed metal surface of the package. A PCB using ceramics as a dielectric or ceramic insert between the die attachment island and the exposed metal surface side can also be used to improve thermal conductivity while also achieving electrical isolation.

[0103] The bottom view and cross-sectional side view of the package produced by the method of this subject using a metal-based PCB with blind vias connecting the top metal island for heat dissipation to the environment and the internal die attachment island are shown in Figure 6(a). In Figure 6(a), the N-type MOSFET device dies 501, 502, and 503 are attached to the internal metal island 602 of the packaging substrate 601 using a conductive die attachment compound 606. The N-type MOSFET device dies 504, 505, and 506 are attached to the corresponding internal metal islands 603, 604, and 605 of the packaging substrate 601 using a conductive die attachment compound 606. Thermal conduction and electrical conduction are established between the internal metal island 602 and the exposed metal surface 608 at the top of the packaging substrate 601 through the blind via 607. Thermal conduction and electrical conduction are established between the internal metal islands 603, 604, and 605 and the exposed metal surfaces 609, 610, and 611 respectively located at the top of the packaging substrate 601 through the blind via 607. Reference numerals 612-617 correspond to Figure 5 the gate electrodes GUU, GUV, GUW, GLU, GLV, and GLW of the N-type MOSFET device dies 501-506. Reference numerals 618-623 correspond to the source electrodes of the N-type MOSFET device dies 501-506.

[0104] The substrate of the package can also be a metal lead frame to achieve a lower thermal resistance. Heat conduction and electrical conduction are achieved between the power switch semiconductor device die and the exposed top metal surface of the package located on the opposite side of the power switch semiconductor device die. After the die attachment process, an insulating portion of the body of the package is formed by applying an electronic molding compound (EMC) 624. Preferably, an injection molding process is used for this processing step. Alternative processing methods, such as drop dispensing followed by thermal curing, can also be used.

[0105] Then, preferably, selective hole drilling through the insulating body 624 of the package is performed by laser drilling to reach the corresponding three electrodes of the six N-type MOSFET device dies 501-506. An underside view and a cross-sectional side view of the package up to the above processing steps are shown in Fig. 6(b). In Fig. 6(b), there are two types of holes, namely hole 625 and hole 626. The drilled hole 625 will reach directly two electrodes at the bonding pads on the front of the six N-type MOSFET device dies 501-506. The drilled hole 626 will reach indirectly the substrate electrodes (backsides) of the six N-type MOSFET device dies 501-506 through the internal metal islands 602-605 in Fig. 6(a) of the package substrate.

[0106] Then, preferably, a metal interconnect is made between the electrodes of the six N-type MOSFET device dies 501-506 and the corresponding positions of the pin output connection ports at the periphery of the package by a process similar to that of bare PCB manufacturing.

[0107] The processing steps involved can include, but are not limited to, a combination of electroless metal plating, photographic processes, and metal etching to define the required electrical connection paths. An underside view and a cross-sectional side view of the package module after making the metal connections between the electrodes of the six N-type MOSFET device dies 501-506 and the corresponding positions of the pin output connection ports at the periphery of the package are shown in Fig. 6(c).

[0108] In Fig. 6(c), the metal pattern 639 is connected to the metal island 602 in Fig. 6(a) through the hole 626 in Fig. 6(b) under the metal pattern 639. Since the drain (substrate) electrodes of the N-type MOSFET device dies 501, 502, and 503 are all conductively die-attached to the metal island 602, this means that the metal pattern 639 is Figure 5 the equivalent circuit node VDD as shown. The metal patterns 627-632 are connected to the gate electrodes of the N-type MOSFET device dies 501-506 respectively through the holes 625 in Fig. 6(b) under the metal patterns 627-632. The electrical equivalent circuit nodes of the metal patterns 627-632 are respectively Figure 5The GUU, GUV, GUW, GLU, GLV, and GLW as shown. The metal patterns 633 - 635 are connected to the source electrodes of the N-type MOSFET device dies 501 - 503 through the holes 625 in FIG. 6(b) under the metal patterns 633 - 635, and are respectively connected to the metal islands 603 - 605 in FIG. 6(a) through the holes 626 in FIG. 6(b) under the metal patterns 633 - 635. The metal patterns 633 - 635 are also connected to the die attachment metal islands 603 - 605 in FIG. 6(a) through the holes 626 in FIG. 6(b), and are thus respectively electrically connected to the substrate electrodes (drains) of the N-type MOSFET device dies 504 - 506. The equivalent circuit nodes of the metal patterns 633 - 635 are respectively Figure 5 U, V, and W. The metal patterns 636 - 638 are connected to the source electrodes of the N-type MOSFET device dies 504 - 506 through the holes 625 in FIG. 6(b) under the metal patterns 636 - 638. The equivalent circuit nodes of the metal patterns 636 - 638 are respectively Figure 5 VSU, VSV, and VSW.

[0109] Then, surface treatment of the pin output connection ports is performed, such as solder mask, gold / silver plating, or solder reflow. The bottom view and cross-sectional side view of the package module after the surface treatment of the pin output connection ports are shown in FIG. 6(d). In FIG. 6(d), the pattern shown by the dashed line in the bottom view is the same as the metal pattern in the bottom view of FIG. 6(c). The solder mask treatment is applied such that the isolated solder mask 653 covers the entire bottom side of the package except the pin output connection ports 640 - 652. Then, further surface treatment, such as gold / silver plating or solder reflow, is applied to the pin output connection ports 640 - 652. The equivalent circuit nodes of the pin output connection ports 640 - 645 are respectively Figure 5 GUU, GUV, GUW, GLU, GLV, and GLW. The equivalent circuit nodes of the pin output connection ports 646 - 651 are respectively Figure 5 U, V, W, VSU, VSV, and VSW. The equivalent circuit node of the pin output connection port 652 is Figure 5 VDD.

[0110] As a variant of this embodiment, after the processing steps for generating the components in FIG. 6(c), the package body molding, selective drilling, and internal connection implementation can be repeated until the last layer of the pin output connection ports is achieved, and then surface treatment of the pin output connection ports such as solder mask is performed. It is contemplated that this variant and similar variants fall within the scope of the present invention.

[0111] In the case of using a PCB substrate, the final test of the packaging module is preferably carried out by concurrently testing a plurality of packaging units in the form of a panel and then dividing the packaging units into individual power switch units. When using a metal lead frame substrate, the normal process of dividing the packaging units into individual units applies before the final test.

[0112] Thus, for a multi-die package, the packaging method of the present subject matter may include step (H): cutting the resulting package into a plurality of smaller packages to form individual power switch units, each power switch unit including one or more of the power switch semiconductor device dies among the power switch semiconductor device dies. Generally speaking, the method involves packaging a plurality of power switch semiconductor device dies in the same package having a common packaging substrate, wherein each power switch semiconductor device die undergoes steps (A) to (G). The method may include step (H) after step (G): cutting the resulting package into a plurality of smaller packages, each smaller package including one or more of the power switch semiconductor device dies among the power switch semiconductor device dies.

[0113] The foregoing description so far has only covered the packaging of one or more power switch semiconductors. It is envisioned that co-packaging one or more power switch semiconductors with one or more other semiconductor devices using the same basic concept of the present invention clearly falls within the scope of the present invention.

[0114] The packaging method of the present invention replaces the electrical connection between the pin-out connection port of the package and the corresponding metal connection pads of one or more power switch semiconductor device dies typically made by a bonding process through a process similar to PCB manufacturing. Additionally, the substrate side (back side) of one or more power switch semiconductor device dies of the metal island attached to the packaging substrate of the package faces upward, while the pin-out connection port of the package faces downward. Through heat conduction from the die attach metal island to the environment (air), this packaging design provides a direct heat dissipation path from the exposed metal surface of the package directly to the environment for reducing thermal resistance. Furthermore, when performing packaging in batches of a plurality of packaging units, this packaging method isolates the other pin-out connection ports from each other except for the substrates of one or more power switch device dies. Therefore, concurrent testing is possible before dividing the plurality of packaged devices into individual units.

Claims

1. A method for packaging at least one power switch semiconductor device die in a package, wherein the power switch semiconductor device die has three electrodes, namely a back electrode and two front electrodes, the method comprising the following steps: (A) attaching the power switch semiconductor device die conductive die to an island of a substrate of the package, wherein the back electrode faces the top side of the package; (B) encapsulating the power switch semiconductor device die with an electronic molding compound to form an insulating portion of the package; (C) forming a hole through the insulating portion of the package to access at least one electrode of the power switching semiconductor device die; (D) forming a conductive path through the hole for connecting the at least one electrode of the power switching semiconductor device die; as well as (E) forming conductive connections from the one or more electrodes of the power switch semiconductor device die to corresponding pin-out connection ports on the bottom side of the package.

2. The method of claim 1, wherein: Step (C) includes forming a hole through the insulating portion of the package to access at least one other electrode; Step (D) comprises forming a conductive path through the hole for connecting to the at least one other electrode; and Step (E) includes forming an electrically conductive connection of the at least one other electrode to a corresponding pin-out connection port on the bottom side of the package.

3. The method of claim 1 or claim 2, wherein the method comprises the step (F) of treating a surface of the one or more pin-out connection ports of the package.

4. The method of claim 3, wherein in step (F), the surface of the one or more pin-out connection ports is processed by related processes commonly known in bare PCB manufacturing such as solder mask, gold / silver plating, or solder hot air leveling.

5. The method of claim 3 or claim 4, wherein the method comprises the step (G) of testing the power switch semiconductor device die through the one or more pin-out connection ports of the package.

6. The method of any one of claims 1 to 5, wherein the method involves packaging a plurality of the power switching semiconductor device dies in a same package having a common packaging substrate, wherein each power switching semiconductor device die undergoes the aforementioned steps. 7 . The method of claim 6 , wherein the method comprises step (H): cutting the obtained package into a plurality of smaller packages, each smaller package comprising one or more of the power switch semiconductor device dies.

8. A method as claimed in claim 5, wherein the method involves packaging a plurality of the power switching semiconductor device dies in the same package having a common packaging substrate, wherein each power switching semiconductor device die undergoes the aforementioned steps, and wherein the method includes a step (H) after step (G): cutting the resulting package into a plurality of smaller packages, each smaller package including one or more of the power switching semiconductor device dies.

9. The method of any one of claims 1 to 8, wherein the substrate of the package is selected from a lead frame and a bare PCB.

10. The method of claim 9, wherein the substrate of the package comprises a bare PCB selected from a double-sided or multi-layer PCB and a metal-based PCB to enhance heat dissipation.

11. The method of claim 10, wherein the substrate of the package comprises a PCB having blind vias for heat transfer from the one or more power switching semiconductor device dies to metal on a top side of the package.

12. The method of claim 10, wherein the substrate of the package comprises a PCB having ceramic insulation between the one or more power switching semiconductor device dies and metal on the top side of the package to reduce junction-to-case thermal resistance.

13. The method of any one of claims 1 to 12, wherein in step (B), the electronic molding compound is applied by a process selected from injection molding and drop dispensing and high temperature hardening.

14. The method of any one of claims 1 to 13, wherein in step (C), the one or more holes are formed by laser drilling.

15. The method of any one of claims 1 to 14, wherein in steps (D) and (E), the one or more conductive paths and conductive connectors are formed by related processes known in bare PCB manufacturing such as chemical plating or patterning of conductive paths.

16. The method according to any one of claims 1 to 15, wherein the method comprises: After step (D) and before step (E), steps (B), (C) and (D) are repeated at least once as steps (B'), (C') and (D'), respectively, as follows: (B') encapsulating the resulting assembly with an electronic molding compound to form another layer of the insulating portion of the package; (C') forming a hole through all insulating portions of the package to access at least one other electrode of the power switching semiconductor device die; and (D') forming a conductive path through the hole for connecting the at least one other electrode of the power switching semiconductor device die.

17. A power switch semiconductor device, comprising: A power switch semiconductor device die having three electrodes, namely a back electrode and two front electrodes; a package having a substrate with an island, the power switching semiconductor device die being conductively die attached to the island, wherein the back electrode faces a top side of the package, the package having an insulating portion of an electronic molding compound encapsulating the power switching semiconductor device die; a hole extending through the insulating portion of the package to access at least one electrode of the power switch semiconductor device die; a conductive path through the hole, the conductive path being used to connect the at least one electrode of the power switch semiconductor device die; as well as Conductive connections of the one or more electrodes of the power switching semiconductor device die to corresponding pin-out connection ports on a bottom side of the package.

18. The power switch semiconductor device according to claim 17, comprising: a hole through the insulating portion of the package to access at least one other electrode, a conductive path through the hole for connecting the at least one other electrode, and a conductive connection from the at least one other electrode to a corresponding pin-out connection port on the bottom side of the package.

19. A power switch semiconductor device as claimed in claim 17 or claim 18, wherein the one or more pin-out connection ports of the package have a processed surface.

20. The power switch semiconductor device according to any one of claims 17 to 19, comprising: A plurality of the power switch semiconductor device dies are packaged in the same package, wherein each power switch semiconductor device die is conductively die attached to the same package substrate, and the back electrode faces the top side of the package.

21. The power switch semiconductor device of claim 20, wherein the package has respective insulating portions encapsulating the power switch semiconductor device die, each insulating portion having the hole and the conductive path through the hole.

22. The power switching semiconductor device of any one of claims 17 to 21, wherein the substrate of the package is selected from a lead frame and a bare PCB.

23. The power switch semiconductor device of claim 22, wherein the substrate of the package comprises a bare PCB selected from a double-sided or multi-layer PCB and a metal-based PCB to enhance heat dissipation.

24. The power switching semiconductor device of claim 23, wherein the substrate of the package comprises a PCB having blind vias for heat transfer from the one or more power switching semiconductor device dies to metal on the top side of the package.

25. The power switching semiconductor device of claim 23, wherein the substrate of the package comprises a PCB having ceramic insulation between the one or more power switching semiconductor device dies and metal on the top side of the package to reduce junction-to-case thermal resistance.

26. A power switching semiconductor device as described in any one of claims 17 to 25, wherein the insulating portion includes at least one other layer of electronic molding compound encapsulating the power switching semiconductor device die and a previous layer, wherein the hole and the conductive path through the hole are associated with each layer.

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