Defect detection method of semiconductor structure
By detecting the dimensional difference of the recessed structure in the semiconductor structure, it is quickly judged whether there is insufficient etching in the wet etching process. Combined with secondary verification, the problem of long detection cycle in the prior art is solved, and product yield and quality stability are improved.
Patent Information
- Application Number
- CN202510386938.X
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-03-27
- Publication Date
- 2025-07-01
AI Technical Summary
In the prior art, the detection period of insufficient capacitance hole etching in semiconductor structures is relatively long, resulting in timely feedback on etching defect problems, affecting product yield.
By detecting the bottom size of the first depression structure and the bottom size of the second depression structure formed after wet etching, and calculating the difference between the two, it is quickly judged whether there is insufficient etching in the wet etching process, and combining the secondary verification step to ensure the accuracy and reliability of the detection results.
The detection cycle is shortened, real-time feedback and precise positioning of insufficient etching problems are achieved, and the overall yield and quality stability of the product are improved.
Smart Images
Figure CN120237035A_ABST
Abstract
Description
Technical Field
[0001] The present disclosure relates to the field of semiconductor technology, and in particular to a defect detection method for a semiconductor structure. Background Art
[0002] Memory is widely used in mobile devices such as mobile phones and tablets due to its advantages of small size, high integration and fast access speed. Capacitors are the core components of memory and are mainly used to store charges.
[0003] Usually, in the process of manufacturing capacitors, a stacking structure needs to be formed, and a hole-shaped structure for accommodating the capacitor is formed in the stacking structure. However, due to the limitations of the manufacturing process, the etching depth of the film layer in different etching areas is different, which easily leads to insufficient etching of the capacitor hole, affecting the product yield; therefore, it is necessary to detect this. However, the current detection method has a long detection cycle, so the problem of etching defects cannot be fed back in time.
[0004] It should be noted that the information disclosed in the above background technology section is only used to enhance the understanding of the background of the present disclosure, and therefore may include information that does not constitute the prior art known to ordinary technicians in the field. Summary of the invention
[0005] The present invention provides a semiconductor structure defect detection method, which shortens the detection cycle and improves the product yield.
[0006] According to one aspect of the present disclosure, a defect detection method for a semiconductor structure is provided, comprising:
[0007] A stacked structure is provided, the stacked structure comprising a substrate, and a first material layer, a second material layer, and a third material layer stacked in sequence on the substrate, a plurality of first recessed structures are formed in the stacked structure, the first recessed structures penetrate through the second material layer and the third material layer, and expose the first material layer;
[0008] detecting a bottom size of the first recessed structure as a first size;
[0009] Etching the exposed first material layer and the second material layer by a wet etching process to form a second recessed structure, wherein the etching rate of the first material layer by the wet etching process is greater than that of the second material layer;
[0010] detecting a bottom size of the second recessed structure as a second size;
[0011] calculating a difference between the second size and the first size;
[0012] When the difference is less than a preset threshold, it is determined that insufficient etching occurs in the wet etching process.
[0013] In an exemplary embodiment of the present disclosure, detecting the bottom dimension of the first recessed structure as a first dimension includes:
[0014] Obtaining a microscopic morphology map of the first recessed structure;
[0015] Determining the first dimension corresponding to the first recessed structure according to the microscopic morphology map of the first recessed structure;
[0016] Detecting the bottom dimension of the second recessed structure as a second dimension includes:
[0017] Obtaining a microscopic morphology map of the second recessed structure;
[0018] Determining the second dimension corresponding to the second recessed structure according to the microscopic morphology map of the second recessed structure.
[0019] In an exemplary embodiment of the present disclosure, providing the stacked structure includes:
[0020] Forming a first material layer on a substrate;
[0021] Successively forming the second material layer and the third material layer on the first material layer;
[0022] Performing anisotropic etching on the second material layer and the third material layer to form a plurality of first recessed structures respectively exposing the first material layer.
[0023] In an exemplary embodiment of the present disclosure, the stacked structure includes a plurality of the second material layers and a plurality of the third material layers, the second material layer and the third material layer are alternately stacked on the first material layer, and the first recessed structure penetrates through all the second material layers and the third material layers;
[0024] The first material layer contacts the second material layer.
[0025] In an exemplary embodiment of the present disclosure, the first material layer includes alumina.
[0026] In an exemplary embodiment of the present disclosure, the second material layer includes silicon oxide; the third material layer includes silicon nitride, polysilicon or metal.
[0027] In an exemplary embodiment of the present disclosure, the thickness of the first material layer is 25 nm to 35 nm, and the preset threshold includes 0.3 nm to 0.6 nm.
[0028] In an exemplary embodiment of the present disclosure, the stacked structure includes a plurality of regions sequentially distributed from the center to the edge, and the first concave structure is distributed in each of the regions.
[0029] In an exemplary embodiment of the present disclosure, the determination that the wet etching process has an under-etching phenomenon when the difference is less than a preset threshold includes:
[0030] When the difference corresponding to any one of the second concave structures in any one of the regions is less than the preset threshold, it is determined that the region where the second concave structure with the difference less than the preset threshold is located has an under-etching phenomenon in the wet etching process.
[0031] In an exemplary embodiment of the present disclosure, an electrode layer is provided in the substrate, the first material layer covers the surface of the electrode layer, the orthographic projection of the second concave structure on the substrate coincides with at least a part of the electrode layer, and the defect detection method further includes:
[0032] Performing a secondary verification on whether the wet etching process has the under-etching phenomenon; the secondary verification includes:
[0033] Forming a dielectric layer on the sidewall of the second concave structure;
[0034] Forming a conductive layer in each of the second concave structures having the dielectric layer, and the conductive layer fills the second concave structure;
[0035] Applying electricity to the electrode layer and each of the conductive layers, and observing whether the corresponding regions of each of the second concave structures are lit; if the corresponding regions of the second concave structures are not lit, it is determined that the second concave structures that are not lit have an under-etching phenomenon.
[0036] The defect detection method of the semiconductor structure of the present disclosure quickly determines whether the wet etching process has an under-etching phenomenon by detecting the bottom dimension (first dimension) of the first concave structure and the bottom dimension (second dimension) of the second concave structure formed after wet etching, and calculating the difference between the two. In the above process, the wet etching result can be directly detected in real time during the manufacturing process without waiting until the entire manufacturing process is completed, which greatly shortens the detection cycle. At the same time, by detecting and discovering the under-etching problem in time, the process parameters of the wet etching can be immediately adjusted or other remedial measures can be taken to prevent defective products from flowing into the subsequent processes, thereby improving the overall yield of the product.
[0037] It should be understood that the above general description and the following detailed description are only exemplary and explanatory, and cannot limit the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS
[0038] The accompanying drawings herein are incorporated into and form a part of the specification, showing embodiments consistent with the present disclosure, and are used together with the specification to explain the principles of the present disclosure. Obviously, the accompanying drawings in the following description are only some embodiments of the present disclosure, and those of ordinary skill in the art can obtain other drawings based on these drawings without creative efforts.
[0039] Figure 1 It is a flowchart of a method for defect detection of a semiconductor structure in an embodiment of the present disclosure.
[0040] Figure 2 It is a schematic diagram of the partition of a stacked structure in an embodiment of the present disclosure.
[0041] Figure 3 It is a schematic diagram of a stacked structure and a first recess structure in an embodiment of the present disclosure.
[0042] Figure 4 It is a microscopic morphology diagram of the first recess structure in an embodiment of the present disclosure.
[0043] Figure 5 It is a schematic diagram of a second recess structure in an embodiment of the present disclosure.
[0044] Figure 6 It is a schematic diagram of a second recess structure with a second material layer completely etched in an embodiment of the present disclosure.
[0045] Figure 7 It is a schematic diagram of a second recess structure with a second material layer not completely etched in an embodiment of the present disclosure.
[0046] Figure 8 It is a microscopic morphology diagram of the second recess structure in an embodiment of the present disclosure.
[0047] Figure 9 It is a schematic diagram of a dielectric layer and a conductive layer in an embodiment of the present disclosure.
[0048] Figure 10 It is a schematic diagram of the second recess structure being lit in an embodiment of the present disclosure.
[0049] Figure 11 It is a difference distribution diagram that does not meet the process requirements.
[0050] Figure 12 It is a difference distribution diagram that meets the process requirements.
[0051] Explanation of reference numerals:
[0052] 1. Stacked structure; 11. Substrate; 110. Central region; 120. Intermediate region; 130. Edge region; 12. First material layer; 13. Second material layer; 14. Third material layer; 101. First recessed structure; 102. Second recessed structure; 2. Dielectric layer; 3. Conductive layer; a. First dimension; b. Second dimension. Detailed implementation
[0053] Example embodiments will now be described more fully with reference to the accompanying drawings. However, the example embodiments can be implemented in various forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of the example embodiments to those skilled in the art. Like reference numerals in the figures denote like or similar structures, and thus their detailed description will be omitted. In addition, the drawings are only schematic illustrations of the present disclosure and are not necessarily drawn to scale.
[0054] Although relative terms such as "upper" and "lower" are used in this specification to describe the relative relationship of one component of an icon to another component, these terms are used in this specification only for convenience, for example, according to the orientation of the examples described in the drawings. It can be understood that if the device of the icon is turned upside down, the component described as "upper" will become the component "lower". When a structure is "on" another structure, it may mean that a structure is integrally formed on another structure, or that a structure is "directly" disposed on another structure, or that a structure is "indirectly" disposed on another structure through another structure.
[0055] The terms "a", "an", "the", "said" and "at least one" are used to indicate the presence of one or more elements / components / etc.; the terms "comprising" and "having" are used to mean an open inclusion and mean that there may be additional elements / components / etc. in addition to the listed elements / components / etc.; the terms "first", "second" and "third", etc. are used only as labels and are not a limitation on the quantity of their objects.
[0056] When detecting the phenomenon of insufficient etching of the capacitor holes, it is usually necessary to fill the capacitor holes with a conductive material. After chemical mechanical polishing of the material, the capacitor holes are detected for the phenomenon of insufficient etching by means of an energization test. However, the phenomenon of insufficient etching generally already exists after the wet etching process for forming the capacitor holes. Although the above method can detect the phenomenon of insufficient etching of the capacitor holes, the required cycle is relatively long, and when etching problems occur, it cannot be timely feedback and improvement, which will cause more quality problems to occur.
[0057] Based on this, the present disclosure provides a method for detecting defects of a semiconductor structure, as Figure 1As shown, the detection method may include steps S110 - S160, where:
[0058] Step S110: Provide a stacked structure, which includes a substrate, and a first material layer, a second material layer, and a third material layer stacked in sequence on the substrate. A plurality of first recessed structures are formed in the stacked structure. The first recessed structures penetrate through the second material layer and the third material layer and expose the first material layer.
[0059] Step S120: Detect the bottom size of the first recessed structure as a first size.
[0060] Step S130: Use a wet etching process to etch the exposed first material layer and the second material layer to form second recessed structures. The etching rate of the wet etching process for the first material layer is greater than that for the second material layer.
[0061] Step S140: Detect the bottom size of the second recessed structure as a second size.
[0062] Step S150: Calculate the difference between the second size and the first size.
[0063] Step S160: When the difference is less than a preset threshold, determine that there is an under-etching phenomenon in the wet etching process.
[0064] As Figure 2 shown, the stacked structure 1 includes a plurality of regions distributed in sequence from the center to the edge, and each region is distributed with first recessed structures. When the difference corresponding to any second recessed structure in any region is less than the preset threshold, it is determined that there is an under-etching phenomenon in the region where the second recessed structure with the difference less than the preset threshold is located. Thus, the under-etching defects can be detected to the greatest extent, and the defective region can be confirmed in advance. However, it is not limited to this. In some embodiments, the basis for determining that there is an under-etching phenomenon in the region is that the number of second recessed structures with a difference less than the preset threshold in the region exceeds the preset number, or the statistical value of the difference in the region is less than the preset threshold, depending on the specific situation.
[0065] In some embodiments of the present disclosure, the defect detection method of the present disclosure may further include:
[0066] Step S170: Perform a secondary verification on whether there is an under-etching phenomenon in the wet etching process.
[0067] The semiconductor structure defect detection method of the present disclosure can quickly determine whether there is an under-etching phenomenon in the wet etching process by detecting the bottom size (the first size) of the first recess structure and the bottom size (the second size) of the second recess structure formed after wet etching, and calculating the difference between the two. Without waiting for the preparation of the conductive plug in the second recess to be completed, it realizes instant feedback, greatly shortens the discovery and solution cycle of the under-etching problem, and makes the production process smoother and more efficient. By detecting and discovering the under-etching problem in a timely manner, the process parameters of wet etching can be immediately adjusted or other remedial measures can be taken to prevent defective products from flowing into subsequent processes, thereby improving the overall yield of the product. At the same time, this method realizes the precise positioning of the under-etching phenomenon by dividing the stacked structure 1 into regions and analyzing the size difference of the recess structures in each region. This regional detection strategy not only helps to quickly lock the root cause of the problem but also provides detailed data support for the subsequent adjustment of the wet etching process, making the adjustment more accurate and effective. In addition, this method also introduces a secondary verification step to reconfirm the preliminary judgment result, ensuring the accuracy and reliability of the detection result, effectively preventing defective products from flowing into subsequent processes due to misjudgment, and further improving the overall yield and quality stability of the product.
[0068] The following will describe in detail each step and its specific details of the semiconductor structure defect detection method of the present disclosure:
[0069] As Figure 1 shown, in step S110, a stacked structure 1 is provided. The stacked structure 1 includes a substrate 11, and a first material layer 12, a second material layer 13, and a third material layer 14 sequentially stacked on the substrate 11. A plurality of first recess structures 101 are formed in the stacked structure 1. The first recess structures 101 penetrate the second material layer 13 and the third material layer 14 and expose the first material layer 12.
[0070] As Figure 3 shown, the substrate 11 can be in a flat plate structure, which can be rectangular, circular, elliptical, polygonal or irregular. Its material can be an insulating material or a semiconductor material. For example, its material can be silicon, but it is not limited to silicon or other semiconductor materials. The shape and material of the substrate 11 are not specifically limited here.
[0071] Please continue to refer to Figure 3As shown, the first material layer 12 can be a thin film or a coating formed on the substrate 11. The material of the first material layer 12 can include aluminum oxide. The thickness of the first material layer 12 can be 25 nm to 35 nm. For example, the thickness can be 25 nm, 28 nm, 31 nm, 34 nm, or 35 nm. Of course, the first material layer 12 can also have other thicknesses, which will not be listed one by one here. Since the thickness of the first material layer 12 is relatively thin and the material itself is also a transparent material, the first material layer 12 is a transparent film layer.
[0072] The second material layer 13 can be located on the side of the first material layer 12 away from the substrate 11. The material of the second material layer 13 can be an insulating material. The third material layer 14 can be located on the side of the second material layer 13 away from the substrate 11. The material of the third material layer 14 can be a conductive material or a sacrificial layer material. Both the second material layer 13 and the third material layer 14 are opaque materials. For example, the material of the second material layer 13 can include silicon oxide; the material of the third material layer 14 can include titanium nitride, polysilicon, or metal, etc.
[0073] It should be noted that transparent or opaque refers to whether it is in a transparent state under a detection device (such as a scanning electron microscope).
[0074] In an exemplary embodiment of the present disclosure, please continue to refer to Figure 3 As shown, the stacked structure 1 can include a plurality of second material layers 13 and a plurality of third material layers 14. The plurality of second material layers 13 and the plurality of third material layers 14 are alternately stacked on the first material layer 12 in a direction perpendicular to the substrate 11, and the second material layer 13 closest to the substrate 11 side is in contact with the first material layer 12. For example, the number of layers of the second material layer 13 can be 4 to 12 layers. For example, the number of layers is 4 layers, 6 layers, 8 layers, 10 layers, or 12 layers; the number of layers of the third material layer 14 can also be 4 to 12 layers. For example, the number of layers is 4 layers, 6 layers, 8 layers, 10 layers, or 12 layers. Of course, the numbers of the second material layer 13 and the third material layer 14 can also be other values, and no special limitation is imposed on the number of layers of the second material layer 13 and the third material layer 14 here.
[0075] In an exemplary embodiment of the present disclosure, as Figure 4 shown, a plurality of first recessed structures 101 are formed in the stacked structure 1. The plurality of first recessed structures 101 can be arranged in an array, or be staggeredly distributed in the form of rows and / or columns. As Figure 3As shown, the first recessed structure 101 penetrates through the second material layer 13 and the third material layer 14 and exposes the first material layer 12. It should be noted that when the numbers of both the second material layer 13 and the third material layer 14 are multiple, the first recessed structure 101 can penetrate through all the second material layers 13 and the third material layers 14. In some embodiments of the present disclosure, the first recessed structure 101 can be a hole-like structure or a groove-like structure, and no special limitation is made on the specific form of the first recessed structure 101 here. For example, the first recessed structure 101 can be a circular hole, an oval hole, a rectangular hole, a polygonal hole or a hole-like structure with an irregular shape; or, the first recessed structure 101 can be a groove with a rectangular cross-section or a groove with an oval cross-section, etc.
[0076] In an exemplary embodiment of the present disclosure, please continue to refer to Figure 2 As shown, the stacked structure 1 can include a plurality of regions sequentially distributed from its center to its edge, and the first recessed structure 101 is distributed in each region. For example, the stacked structure 1 can include a central region 110, an intermediate region 120 and an edge region 130 sequentially distributed from its center to its edge. Among them, the central region 110, the intermediate region 120 and the edge region 130 can be 1 or more respectively. The intermediate region 120 is distributed around the outer periphery of the central region 110, and the edge region 130 is distributed around the outer periphery of the intermediate region 120. A plurality of first recessed structures 101 are distributed in the central region 110, the intermediate region 120 and the edge region 130. It should be noted that the above division of regions can be for the purpose of statistically detecting defect results, and the stacked structure 1 may not include actual physical partitions.
[0077] In an exemplary embodiment of the present disclosure, providing the stacked structure 1 (i.e., step S110) includes steps S210 - S230, where:
[0078] Step S210, forming the first material layer 12 on the substrate 11.
[0079] The material of the first material layer 12 can be alumina. The first material layer 12 can be formed on the substrate 11 by chemical vapor deposition, physical vapor deposition or atomic layer deposition, etc. Of course, the first material layer 12 can also be formed by other means, and no special limitation is made on the formation method of the first material layer 12 here.
[0080] Step S220, sequentially forming the second material layer 13 and the third material layer 14 on the first material layer 12.
[0081] The second material layer 13 can be formed on the first material layer 12 by means of chemical vapor deposition, physical vapor deposition, atomic layer deposition, etc. Subsequently, the third material layer 14 can also be formed on the second material layer 13 by means of chemical vapor deposition, physical vapor deposition, atomic layer deposition, etc. It should be noted that when the numbers of the second material layer 13 and the third material layer 14 are both multiple, they can be alternately deposited in sequence to form multiple layers of the second material layer 13 and multiple layers of the third material layer 14.
[0082] Step S230: Anisotropically etch the second material layer 13 and the third material layer 14 to form a plurality of first recessed structures 101 that respectively expose the first material layer 12.
[0083] After forming the second material layer 13 and the third material layer 14 that are stacked and distributed in multiple layers, the second material layer 13 and the third material layer 14 can be anisotropically etched through a dry etching process, thereby forming a plurality of first recessed structures 101 that respectively expose the first material layer 12. It should be noted that in the present disclosure, in order to ensure that the second material layer 13 and the third material layer 14 can be penetrated, over-etching can be performed during the formation of the first recessed structure 101; that is, when etching to form the first recessed structure 101, it can be synchronously etched into the first material layer 12. However, due to the difference in the etching rate in different regions during the etching process, the etching degrees of different regions of the first material layer 12 on the substrate 11 are uneven, resulting in different depths of the first recessed structure 101 extending into the first material layer 12 in different regions of the substrate 11, or different bottom sizes of the first recessed structure 101.
[0084] As Figure 1 shown, in step S120, detect the bottom size of the first recessed structure 101 as the first size a.
[0085] The bottom size of the first recessed structure 101 can be detected by means of a high-precision measuring device or technology and used as the first size a. The first size a can be used as the basis for evaluating the effect of the subsequent wet etching process.
[0086] In an exemplary embodiment of the present disclosure, detecting the bottom size of the first recessed structure 101 as the first size a (i.e., step S120) may include step S310 and step S320, where:
[0087] Step S310: Obtain a microscopic morphology map of the first recessed structure 101.
[0088] For example, the surface morphology of the stacked structure 1 can be detected by a Scanning Electron Microscope (SEM), and a micro-morphology image of the stacked structure 1 can be obtained (i.e., the micro-morphology image is a SEM image). As Figure 4 shown, the micro-morphology of the first recessed structure 101 is included in the micro-morphology image.
[0089] Step S320: Determine a first dimension a corresponding to the first recessed structure 101 according to the micro-morphology image of the first recessed structure 101.
[0090] After obtaining the micro-morphology image, the micro-morphology image can be analyzed to identify the first recessed structure 101. Among them, identifying the first recessed structure 101 includes: identifying the boundary of the first recessed structure 101, determining its shape (such as circular, elliptical, irregular, etc.), and evaluating its planar dimension. The first dimension a corresponding to the first recessed structure 101 can be directly determined by measuring its diameter (when the first recessed structure 101 is a hole) or width (when the first recessed structure 101 is a groove). For example, the planar dimension (such as diameter, width, etc.) of the first recessed structure 101 can be measured by the measurement software equipped in the scanning electron microscope. In the present disclosure, in order to ensure the reliability of the measurement result, multiple measurements can be performed and the average value can be taken to reduce the influence of random errors and improve the accuracy of the measurement result.
[0091] As Figure 1 shown, in step S130, a wet etching process is used to etch the exposed first material layer 12 and second material layer 13 to form a second recessed structure 102, and the etching rate of the wet etching process for the first material layer 12 is greater than that of the second material layer 13.
[0092] After detecting the bottom dimension of the first recessed structure 101, an isotropic etching can be performed on the first material layer 12 exposed at the bottom of the first recessed structure 101 by using a wet etching process to form a second recessed structure 102, as Figure 5As shown. During this process, there is almost no reaction between the etching solution and the third material layer 14, that is, the third material layer 14 is hardly etched. In one embodiment, the etching rate ratio of the first material layer 12 to the second material layer 13 is greater than or equal to 80. For example, the etching rate ratio of the first material layer 12 to the second material layer 13 can be 80:1, 85:1, 90:1, 95:1, or 100:1; of course, the etching rate ratio of the first material layer 12 and the second material layer 13 can also be larger, which will not be listed one by one here. In the present disclosure, as long as the etching solution for wet etching can satisfy that its etching rate for the first material layer 12 is greater than its etching rate for the second material layer 13 (for example, the etching rate ratio of the first material layer 12 to the second material layer 13 is greater than or equal to 80), and does not etch the third material layer 14, the specific type of the etching solution for wet etching is not specifically limited here.
[0093] In some embodiments of the present disclosure, during the above wet etching process, although the etching rate ratio of the first material layer 12 to the second material layer 13 is large and the mainly etched film layer is the first material layer 12, part of the end of the second material layer 13 will also be removed, thereby expanding the opening of the second material layer 13 at the bottom of the first recess structure 101, exposing more of the surface of the first material layer 12, and forming the second recess structure 102 in the present disclosure. The structure after etching is as Figure 6 shown. Compared with the situation where the first material layer 12 is not completely etched during the preparation of the second recess structure (as Figure 7 shown), the opening of the second recess structure 102 formed after completely etching the first material layer by wet etching in this application is larger (that is, b is greater than c), and the substrate 11 can be completely exposed. It should be noted that when both the second material layer 13 and the third material layer 14 are multi-layers, during the wet etching process, part of the end of other second material layers 13 close to the first recess structure 101 will also be removed synchronously. However, since the etching rate ratio of the first material layer 12 to the second material layer 13 is greater than 80, the damage to each second material layer 13 during the wet etching process is small, and this damage has almost no impact on the characteristics of the second material layer 13 and subsequent process steps. That is, during the process of forming the second recess structure 102 by wet etching, although it will cause slight damage to the end of the second material layer 13, this damage helps to detect the etching degree of the first material layer 12, immediately detect the under-etching phenomenon, and does not affect the function of the second material layer 13.
[0094] It should also be noted that the first recessed structure obtained by anisotropic etching usually has a contour that is wider at the top and narrower at the bottom. Since the etching rate ratio of the first material layer 12 to the second material layer 13 is relatively large (for example, greater than 80), when the first material layer 12 is etched through by wet etching, the end size of the second material layer 13 removed is small, so it will not be affected by the third material layer 14, which is also opaque, above the second material layer 13 in the monitoring result.
[0095] As Figure 1 shown, in step S140, the bottom size of the second recessed structure 102 is detected as the second size b.
[0096] The bottom size of the second recessed structure 102 can be detected by means of a high-precision measuring device or technology and used as the second size b. The second size b can be an important parameter for evaluating the effect of the subsequent wet etching process.
[0097] In an exemplary embodiment of the present disclosure, detecting the bottom size of the second recessed structure 102 as the second size b (i.e., step S140) may include step S410 and step S420, where:
[0098] Step S410, obtaining a microscopic morphology map of the second recessed structure 102.
[0099] The surface morphology of the stacked structure 1 after wet etching can be detected by a scanning electron microscope, and a microscopic morphology map of the stacked structure 1 can be obtained. As Figure 8 shown, the microscopic morphology map includes the microscopic morphology of the second recessed structure 102. It should be noted that since the first material layer 12 is a transparent film layer and the second material layer 13 and the third material layer 14 are both opaque film layers, the morphology of the second recessed structure 102 shown in the microscopic morphology map (as Figure 8 shown) is not very different from the morphology of the first recessed structure 101 (as Figure 4 shown). Therefore, it is impossible to determine whether there is an under-etching phenomenon only by observing the microscopic morphology maps before and after wet etching. In the prior art, it is only possible to determine whether there is an under-etching phenomenon after filling the second recessed structure with a conductive material in the subsequent process, and this determination method requires several process steps and the detection is not timely.
[0100] Step S420, determining the second size b corresponding to the second recessed structure 102 according to the microscopic morphology map of the second recessed structure 102.
[0101] After obtaining the microscopic morphology map, the microscopic morphology map can be analyzed to further identify the second recessed structure 102. Among them, identifying the second recessed structure 102 includes: identifying the boundary of the second recessed structure 102, determining its shape (such as circular, elliptical, irregular, etc.), and evaluating its planar dimension. The second dimension b corresponding to the second recessed structure 102 can be directly determined by measuring its diameter (when the second recessed structure 102 is in the shape of a hole) or width (when the second recessed structure 102 is in the shape of a groove). For example, the planar dimension of the second recessed structure 102 can be measured by the measurement software equipped in the scanning electron microscope. It should be noted that when measuring the dimension of the second recessed structure 102, since both the second material layer 13 and the third material layer 14 are opaque film layers, the change in the dimension of the second material layer 13 can be detected. In the present disclosure, in order to ensure the reliability of the measurement result, multiple measurements can be performed and the average value can be taken to reduce the influence of random errors and improve the accuracy of the measurement result.
[0102] As Figure 1 shown, in step S150, calculate the difference between the second dimension b and the first dimension a.
[0103] Due to the stable etching rate difference between the first material layer 12 and the second material layer 13, the process of wet-etching the first material layer 12 to form the second recessed structure 102 is isotropic etching. When removing a preset thickness of the first material layer 12, the first material layer 12 will synchronously remove the corresponding width, so that in the measurement result, the bottom width of the second recessed structure 102 is the second dimension b, and the second dimension b is greater than the first dimension a.
[0104] In the present disclosure, in order to avoid the influence of the phenomenon of uneven etching in each region during the formation of the first recessed structure 101 on the difference value, the difference value between the first dimension a and the second dimension b corresponding to the same first recessed structure 101 can be calculated, and then the removal amount of the first material layer 12 during the wet-etching process can be determined through this difference value. That is, the dimension difference of the same first recessed structure 101 before and after wet-etching can be calculated to facilitate the evaluation of the influence of the wet-etching process on the dimension change of the same recessed structure.
[0105] As Figure 1 shown, in step S160, when the difference value is less than the preset threshold, it is determined that there is a phenomenon of insufficient etching in the wet-etching process.
[0106] In the present disclosure, the phenomenon of under-etching may be that the first material layer 12 remains at the bottom of the second recess structure 102. When the difference is less than a preset threshold, it indicates that the amount of the first material layer 12 etched during the wet etching process is less than expected, that is, the etching effect of the wet etching does not meet the design requirements, which may lead to connection problems or performance degradation in subsequent process steps, seriously affecting the quality and reliability of the product. In the present disclosure, by detecting the bottom dimensions of the recess structure before and after wet etching and calculating the difference between the two, it is possible to quickly determine whether there is a phenomenon of under-etching in the wet etching process. There is no need to wait until the entire manufacturing process is completed before detection, greatly shortening the detection cycle. At the same time, by detecting and discovering the problem of under-etching in a timely manner, the process parameters of the wet etching can be immediately adjusted or other remedial measures can be taken to prevent defective products from flowing into subsequent processes, thereby improving the overall yield of the product.
[0107] The value range of the preset threshold is related to the thickness of the first material layer 12. For example, when the thickness of the first material layer 12 is 25 nm to 35 nm, the preset threshold may include 0.3 nm to 0.6 nm. Within this range, it can be ensured that the second recess structure 102 completely penetrates the first material layer 12, that is, the second recess structure 102 can expose the surface of the substrate 11. For example, the preset threshold may be 0.3 nm, 0.4 nm, 0.5 nm, or 0.6 nm, etc.
[0108] It should be noted that the depths at which the first recess structure 101 extends into the first material layer 12 may be the same or different, but by controlling the difference to be greater than the preset threshold, it is possible to control the thickness of the removed first material layer 12 to be greater than its complete thickness, thereby ensuring that the second recess structure 102 penetrates the first material layer 12.
[0109] Similarly, the first dimensions a of different first recess structures 101 may be the same or different, but by controlling the difference to be greater than the preset threshold, it is possible to control the thickness of the removed first material layer 12 to be greater than its complete thickness, thereby ensuring that the second recess structure 102 penetrates the first material layer 12.
[0110] In an exemplary embodiment of the present disclosure, determining that there is an under-etching phenomenon in the wet etching process when the difference is less than a preset threshold includes: when the difference corresponding to any second recessed structure 102 in any region is less than the preset threshold, it is determined that there is an under-etching phenomenon in the region where the second recessed structure 102 with the difference less than the preset threshold is located, that is, there are defects in this region. For example, when the stacked structure 1 includes a central region 110, an intermediate region 120, and an edge region 130, if the difference corresponding to any second recessed structure 102 in the central region 110 is less than the preset threshold, it can be determined that there is an under-etching phenomenon in the central region 110; if the difference corresponding to any second recessed structure 102 in the intermediate region 120 is less than the preset threshold, it can be determined that there is an under-etching phenomenon in the intermediate region 120; if the difference corresponding to any second recessed structure 102 in the edge region 130 is less than the preset threshold, it can be determined that there is an under-etching phenomenon in the edge region 130.
[0111] It should be noted that when the difference is greater than or equal to the preset threshold, it can be determined that there is no under-etching phenomenon in the wet etching process.
[0112] In an exemplary embodiment of the present disclosure, an electrode layer (not shown in the figure) may be provided in the substrate 11, and the electrode layer may be strip-shaped. The material of the electrode layer may be a conductive material or a semiconductor material. When the bottom of all the second recessed structures 102 is opened, that is, there is no under-etching phenomenon in the wet etching process, different regions of the electrode layer can be respectively exposed by the multiple second recessed structures 102. However, when there is an under-etching phenomenon in the second recessed structures 102, the bottom of at least some of the second recessed structures 102 does not expose the electrode layer or the exposed area of the electrode layer is small.
[0113] In some embodiments of the present disclosure, the method for detecting defects of the semiconductor structure of the present disclosure further includes:
[0114] Step S170, performing a secondary verification on whether there is an under-etching phenomenon in the wet etching process.
[0115] The primary judgment result can be reconfirmed through the secondary verification, thereby ensuring the accuracy and reliability of the detection result, effectively avoiding the inflow of defective products into the subsequent processes due to misjudgment, and further improving the overall yield and quality stability of the product.
[0116] In an exemplary embodiment of the present disclosure, the secondary verification (i.e., step S170) may include steps S510 - S530, where:
[0117] Step S510, forming a dielectric layer 2 on the sidewall of the second recessed structure 102.
[0118] The material of the dielectric layer 2 can be an insulating material. Further, the material of the dielectric layer 2 can be a material with a relatively high dielectric constant. For example, the material can be alumina, hafnium oxide, lanthanum oxide, titanium oxide, zirconium oxide, tantalum oxide, niobium oxide, strontium oxide, or a mixture thereof. Of course, it can also be other materials, which will not be listed one by one here. As Figure 9 shown, the dielectric layer 2 can be formed on the sidewalls and bottom of the second recessed structure 102 by means of chemical vapor deposition, physical vapor deposition, atomic layer deposition, etc. Subsequently, the dielectric layer 2 located at the bottom of the second recessed structure 102 can be removed by a dry etching process to expose the electrode layer in the substrate 11.
[0119] Step S520: A conductive layer 3 is respectively formed in each of the second recessed structures 102 having the dielectric layer 2, and the conductive layer 3 fills the second recessed structure 102.
[0120] The material of the conductive layer 3 can include tungsten or titanium nitride. Please continue to refer to Figure 9 shown. A conductive material layer can be formed on the stacked structure 1 having the dielectric layer 2 by means of chemical vapor deposition, physical vapor deposition, atomic layer deposition, etc. The conductive material layer can fill each of the second recessed structures 102. Subsequently, the conductive material layer located on the top surface of the stacked structure 1 can be removed by a chemical mechanical polishing process, and only the conductive material layer located in the second recessed structure 102 is retained, and the remaining conductive material layer in the second recessed structure 102 can be used as the conductive layer 3. It should be noted that when the bottom surface of the second recessed structure 102 is completely opened (i.e., there is no under-etching phenomenon in the second recessed structure 102), the second recessed structure 102 exposes the electrode layer at its bottom, and the end portion of the conductive layer 3 in the second recessed structure 102 close to the substrate 11 is in contact connection with the electrode layer; when the bottom surface of the second recessed structure 102 is not completely opened (i.e., there is an under-etching phenomenon in the second recessed structure 102), the second recessed structure 102 does not expose or exposes less of the electrode layer below it. At this time, the end portion of the conductive layer 3 in the second recessed structure 102 close to the substrate 11 is not in contact connection with the electrode layer, or the contact area is too small and the connection impedance is large.
[0121] Step S530: Electric power is supplied to the electrode layer and each conductive layer 3, and it is observed whether the corresponding area of each second recessed structure 102 is lit; if the corresponding area of the second recessed structure 102 is not lit, it is determined that there is a problem of insufficient time in the unlit second recessed structure 102.
[0122] In some embodiments of the present disclosure, it can be observed whether the corresponding area of the second recessed structure 102 is lit through the current-voltage detection mode of a scanning electron microscope.
[0123] In some embodiments of the present disclosure, as Figure 10As shown, when the difference corresponding to the second recessed structure 102 is less than the preset threshold, but the area corresponding to the second recessed structure 102 is lit, it can be determined that there is no under-etching phenomenon in the second recessed structure 102. That is, in the present disclosure, even if the dimensional difference indicates that there may be under-etching, but if the area can be lit, it proves that the wet etching is at least sufficient in this area and there is no under-etching phenomenon, which can enhance the reliability of the detection result and reduce misjudgment.
[0124] Figure 11 and Figure 12 shows the detection result obtained by the defect detection method proposed in the present disclosure, where the depth of the filled color in each area represents the statistical value of the difference between the second dimension b and the first dimension a in that area, and the darker the color, the smaller the difference. The statistical value is, for example, the average value, and the present application does not specifically limit the method of obtaining the statistical value of this difference. As Figure 11 shown in the detection result, the under-etching phenomenon of the first material layer 12 exists more in the edge area 130, and the process conditions need to be adjusted to obtain better etching results; as Figure 12 shown in the detection result, in multiple areas, the distribution of the difference between the second dimension b and the first dimension a is relatively uniform, and the etching uniformity of the first material layer 12 is better. When the difference is greater than the preset threshold, the process conditions meet the requirements.
[0125] It should be noted that although the steps of the defect detection method of the semiconductor structure in the present disclosure are described in a specific order in the drawings, however, this does not require or imply that these steps must be executed in this specific order, or that all the shown steps must be executed to achieve the desired result. Additionally or alternatively, some steps may be omitted, multiple steps may be combined into one step for execution, and / or one step may be decomposed into multiple steps for execution, etc.
[0126] Those skilled in the art will readily think of other embodiments of the present disclosure after considering the specification and practicing the invention disclosed herein. The present disclosure is intended to cover any variations, uses, or adaptations of the present disclosure, which follow the general principles of the present disclosure and include the common general knowledge or conventional technical means in the technical field not disclosed in the present disclosure. The specification and embodiments are only regarded as exemplary, and the true scope and spirit of the present disclosure are pointed out by the appended claims.
Claims
1. A method for detecting defects in a semiconductor structure, characterized in that: include: A stacked structure is provided, the stacked structure comprising a substrate, and a first material layer, a second material layer, and a third material layer stacked in sequence on the substrate, a plurality of first recessed structures are formed in the stacked structure, the first recessed structures penetrate through the second material layer and the third material layer and expose the first material layer; detecting a bottom size of the first recessed structure as a first size; Etching the exposed first material layer and the second material layer by a wet etching process to form a second recessed structure, wherein the etching rate of the first material layer by the wet etching process is greater than that of the second material layer; detecting a bottom size of the second recessed structure as a second size; calculating a difference between the second size and the first size; When the difference is less than a preset threshold, it is determined that insufficient etching occurs in the wet etching process.
2. The defect detection method according to claim 1, characterized in that: The detecting the bottom size of the first recessed structure as the first size includes: Obtaining a microscopic morphology image of the first concave structure; Determining the first size corresponding to the first recessed structure according to the microscopic morphology image of the first recessed structure; The detecting the bottom size of the second recessed structure as the second size includes: Obtaining a microscopic morphology image of the second recessed structure; The second size corresponding to the second recessed structure is determined according to the microscopic morphology image of the second recessed structure.
3. The defect detection method according to claim 1, characterized in that: Providing the stacking structure comprises: forming a first material layer on a substrate; sequentially forming the second material layer and the third material layer on the first material layer; The second material layer and the third material layer are anisotropically etched to form a plurality of first recessed structures respectively exposing the first material layer.
4. The defect detection method according to claim 1, characterized in that: The stacked structure includes a plurality of the second material layers and a plurality of the third material layers, the second material layers and the third material layers are alternately stacked on the first material layer, and the first recessed structure penetrates all of the second material layers and the third material layers; The first material layer contacts the second material layer.
5. The defect detection method according to claim 1, characterized in that: The first material layer includes aluminum oxide.
6. The defect detection method according to claim 5, characterized in that: The second material layer includes silicon oxide; and the third material layer includes silicon nitride, polysilicon or metal.
7. The defect detection method according to claim 6, characterized in that: The thickness of the first material layer is 25 nm to 35 nm, and the preset threshold value includes 0.3 nm to 0.6 nm.
8. The defect detection method according to any one of claims 1 to 7, characterized in that: The stacked structure includes a plurality of regions distributed sequentially from the center to the edge, and the first recessed structure is distributed in each of the regions.
9. The defect detection method according to claim 8, characterized in that: The step of judging that insufficient etching exists in the wet etching process when the difference is less than a preset threshold value includes: When the difference value corresponding to any second recessed structure in any of the regions is smaller than the preset threshold, it is determined that insufficient wet etching occurs in the region where the second recessed structure corresponding to the difference value smaller than the preset threshold is located.
10. The defect detection method according to claim 9, characterized in that: An electrode layer is provided in the substrate, the first material layer covers the surface of the electrode layer, the orthographic projection of the second recessed structure on the substrate at least partially overlaps with the electrode layer, and the defect detection method further includes: A secondary verification is performed on whether the wet etching process has the insufficient etching phenomenon; the secondary verification includes: forming a dielectric layer on the sidewalls of the second recessed structure; forming a conductive layer in each of the second recessed structures having the dielectric layer, wherein the conductive layer fills up the second recessed structures; Power is supplied to the electrode layer and each of the conductive layers, and it is observed whether the corresponding area of each of the second recessed structures is illuminated; if the corresponding area of the second recessed structure is not illuminated, it is determined that the second recessed structure that is not illuminated has insufficient etching.