Semiconductor devices and methods for fabricating devices

Abstract

This disclosure provides a semiconductor device and a method for fabricating the device. The semiconductor device includes: a first chip having a first thermally conductive element formed therein; and a second chip having a second thermally conductive element thermally connected to the first thermally conductive element. The first chip is bonded to a first side of the second chip, and the area of ​​the second chip is larger than the area of ​​the first chip to form an exposed portion. The second thermally conductive element is partially located in the exposed portion to be partially exposed to the environment.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and more specifically, to a semiconductor device and a method for fabricating the device. Background Technology

[0002] Semiconductor devices typically generate heat during operation, causing their temperature to rise. If the semiconductor device cannot be cooled in time, it will operate in a high-temperature environment for a long time, leading to performance degradation or malfunction.

[0003] Therefore, there is a need to dissipate heat from semiconductor devices. Summary of the Invention

[0004] One of the objectives of this disclosure is to provide a semiconductor device and a method for fabricating the device.

[0005] According to a first aspect of this disclosure, a semiconductor device is provided, comprising:

[0006] A first chip, wherein a first heat-conducting element is formed in the first chip;

[0007] The second chip has a second heat-conducting element that is thermally connected to the first heat-conducting element.

[0008] In this configuration, the first chip is bonded to a first side of the second chip, and the area of ​​the second chip is larger than that of the first chip to form an exposed portion. The second thermal conductive element is partially located in the exposed portion to be partially exposed to the environment.

[0009] In some embodiments, the first thermally conductive element includes a first thermally conductive portion and / or a second thermally conductive portion.

[0010] The first thermally conductive portion fills the first through-hole formed in the first chip.

[0011] The first chip has one or more first wirings extending in a plane perpendicular to the thickness direction, at least a portion of which is configured to serve as the second heat-conducting portion.

[0012] In some embodiments, the second thermal conductive element includes one or more layers of second wiring extending in a plane perpendicular to the thickness direction, the one or more layers of second wiring being partially located in the exposed portion.

[0013] In some embodiments, the second chip includes a passivation layer, a first side of which is used for bonding with the first chip, and one or more second wiring layers are located on a second side of the passivation layer opposite to the first side.

[0014] The second thermal conductive element further includes a third thermal conductive portion filled in a second through hole opened in the passivation layer. One end of the third thermal conductive portion is thermally connected to the first thermal conductive element, and the other end is thermally connected to the one or more layers of second wiring.

[0015] In some embodiments, the semiconductor device further includes:

[0016] A heat dissipation device, wherein the heat dissipation device is located on the portion of the second heat-conducting element exposed to the environment and is in thermal communication with the second heat-conducting element.

[0017] In some embodiments, the semiconductor device further includes:

[0018] A bonding layer, located between the first chip and the second chip and configured to bond the first chip and the second chip.

[0019] The first thermally conductive element and the second thermally conductive element are thermally connected via bonding pads in the bonding layer.

[0020] In some embodiments, the semiconductor device further includes a third chip bonded to a second side of the second chip opposite to the first side.

[0021] The first chip is configured to perform computing tasks, the second chip is configured to perform signal transmission, or the third chip is configured to store data.

[0022] According to a second aspect of this disclosure, a method for preparing an apparatus is provided, comprising:

[0023] Forming the first heat-conducting component in the first chip;

[0024] Forming a second heat-conducting element in the second chip; and

[0025] The first chip and the second chip are joined to make the first thermally conductive element and the second thermally conductive element thermally connected, wherein the area of ​​the second chip is larger than the area of ​​the first chip to form an exposed portion, and the second thermally conductive element is partially located in the exposed portion to be partially exposed to the environment.

[0026] In some embodiments, the first thermal conductive element forming the first chip includes:

[0027] A first through-hole is formed in a first preset layer of the first chip, and a thermally conductive material is filled into the first through-hole to form a first thermally conductive portion of the first thermally conductive element; and / or

[0028] One or more first wirings are formed on the second preset layer of the first chip to form the second heat-conducting portion of the first heat-conducting component, wherein the one or more first wirings extend in a plane perpendicular to the thickness direction.

[0029] In some embodiments, the second thermal conductive element forming the second chip includes:

[0030] One or more second wirings are formed on the third preset layer of the second chip, extending in a plane perpendicular to the thickness direction, wherein the one or more second wirings are partially located in the exposed portion when the first chip and the second chip are joined.

[0031] In some embodiments, the second thermal conductive element forming the second chip further includes:

[0032] A passivation layer is formed on the one or more layers of the second wiring;

[0033] A patterned anti-etching layer is formed on the passivation layer;

[0034] The passivation layer is etched under the protection of the etch-resistant layer until at least partially exposing one or more layers of second wiring; and

[0035] Remove the remaining anti-etching layer.

[0036] In some embodiments, etching the passivation layer under the protection of the anti-etching layer includes forming a second via in the passivation layer, wherein forming the second heat-conducting element in the second chip further includes:

[0037] A thermally conductive material is filled into the second through hole to form a third thermally conductive portion of the second thermally conductive element. One end of the third thermally conductive portion is used to thermally communicate with the first thermally conductive element, and the other end is used to thermally communicate with the one or more layers of the second wiring.

[0038] Other features and advantages of this disclosure will become clearer from the following detailed description of exemplary embodiments with reference to the accompanying drawings. Attached Figure Description

[0039] The accompanying drawings, which form part of this specification, illustrate embodiments of this disclosure and, together with the specification, serve to explain the principles of this disclosure.

[0040] This disclosure will become clearer with reference to the accompanying drawings and the following detailed description, wherein:

[0041] Figure 1 A schematic diagram of the temperature distribution before and after proper chip layout is shown in an example.

[0042] Figure 2A schematic diagram of heat dissipation for a chip is shown in one example;

[0043] Figure 3 A schematic diagram of the structure of a semiconductor device according to an exemplary embodiment of the present disclosure is shown;

[0044] Figure 4 A schematic diagram of the arrangement of a second wiring according to an exemplary embodiment of the present disclosure is shown;

[0045] Figure 5 A schematic flowchart of a method for fabricating an apparatus according to an exemplary embodiment of the present disclosure is shown;

[0046] Figure 6 A schematic diagram of a first thermally conductive portion of a first thermally conductive element in a first chip is shown in an exemplary embodiment of the present disclosure.

[0047] Figure 7 A schematic diagram of a second thermally conductive portion of a first thermally conductive element in a first chip is shown in an exemplary embodiment of the present disclosure.

[0048] Figure 8 A schematic diagram of forming a second heat-conducting element according to an exemplary embodiment of the present disclosure is shown.

[0049] Note that in the embodiments described below, the same reference numerals are sometimes used across different figures to denote the same parts or parts having the same function, and repeated descriptions are omitted. In this specification, similar reference numerals and letters are used to denote similar items; therefore, once an item is defined in one figure, it does not need to be discussed further in subsequent figures.

[0050] For ease of understanding, the positions, dimensions, and extents of the structures shown in the accompanying drawings and other materials may not represent actual positions, dimensions, and extents. Therefore, the disclosed invention is not limited to the positions, dimensions, and extents disclosed in the accompanying drawings and other materials. Furthermore, the drawings are not necessarily drawn to scale, and some features may be enlarged to show details of specific components. Detailed Implementation

[0051] Various exemplary embodiments of the present disclosure will now be described in detail with reference to the accompanying drawings. It should be noted that, unless otherwise specifically stated, the relative arrangement, numerical expressions, and values ​​of the components and steps set forth in these embodiments do not limit the scope of the present disclosure.

[0052] The following description of at least one exemplary embodiment is merely illustrative and is in no way intended to limit this disclosure or its application or use. Those skilled in the art will understand that they merely illustrate exemplary ways that can be used to implement this disclosure, and are not exhaustive.

[0053] Techniques, methods, and equipment known to those skilled in the art may not be discussed in detail, but where appropriate, such techniques, methods, and equipment should be considered part of the specification.

[0054] Three-dimensional integrated chips offer advantages such as high density, high performance, and small size, making them widely used in various modern electronic devices. However, as the number of stacked structures increases in three-dimensional integrated chips, the thermal resistance between internal hotspots and the external surface increases significantly, hindering effective heat dissipation. This causes heat generated during chip operation to easily accumulate internally, potentially leading to overheating, performance degradation, and reduced reliability.

[0055] In some examples, the components within a chip can be strategically arranged to ensure even distribution of hotspots and reduce thermal coupling. Figure 1 Figures (a) and (b) show schematic diagrams of chip temperature before and after optimized chip layout, respectively. Figure 1 (c) in the middle is related to Figure 1 The grayscale diagram corresponding to (a) in the image. Figure 1 (d) in the context is related to Figure 1 The grayscale diagram corresponding to (b) in the image. While this method can alleviate the problem of excessively high local temperatures caused by overly concentrated hotspots to some extent, heat from each hotspot area still tends to accumulate inside the chip, resulting in poor heat dissipation. Alternatively, in some examples, such as... Figure 2 As shown, thermal interface materials (TIMs) 3, integrated heat sinks 4, and heat sinks 5 can be used on the ball grid array (BGA) substrate 1 and silicon substrate 2 of the chip to reduce the thermal resistance from the chip to the boundary, thereby assisting in heat dissipation from the chip surface. However, this method of heat dissipating heat from the chip surface by additionally introducing TIM materials, heat sinks, and heat sinks is difficult to effectively handle the heat accumulated inside the three-dimensional integrated chip. Alternatively, in some examples, microfluidic technology can be used to create channels for coolant flow inside or around the chip, using the flowing coolant to cool the chip. However, this method introduces additional microfluidic fabrication technology, which is difficult and costly.

[0056] To address the aforementioned issues, this disclosure provides a semiconductor device that efficiently conducts heat from within the chip to the environment through a heat-conducting component in the exposed portion of the second chip relative to the first chip, thereby effectively reducing heat accumulation and improving the chip's heat dissipation capability.

[0057] like Figure 3As shown, a semiconductor device 400 according to some embodiments of the present disclosure may include a first chip 100 and a second chip 200, wherein the first chip 100 may be bonded to a first side of the second chip 200.

[0058] The first chip 100 may have a first heat-conducting element 130 formed therein, and the second chip 200 may have a second heat-conducting element 230 thermally connected to the first heat-conducting element 130, so that the heat-conducting channel formed by the thermal connection between the first heat-conducting element 130 and the second heat-conducting element 230 can conduct heat in the chip. In some embodiments, other components may also be formed in the first chip 100 and the second chip 200, for example, the first chip 100 may have a first conductive element formed therein, and the second chip 200 may have a second conductive element formed therein, for implementing corresponding circuit connections.

[0059] The area of ​​the second chip 200 can be larger than the area of ​​the first chip 100, such that a portion of the second chip 200 forms an exposed portion 420 relative to the first chip 100 and exposed to the environment. Here, the chip area can be the maximum cross-sectional area of ​​the chip. The second heat-conducting element 230 can be partially located in the exposed portion 420, so as to be partially exposed to the environment.

[0060] Alternatively, in some embodiments, the area of ​​the first chip 100 may be larger than the area of ​​the second chip 200, such that a portion of the first chip 100 forms an exposed portion 420 relative to the second chip 200 exposed to the environment. The first heat-conducting element 130 may be partially located in the exposed portion 420 to be partially exposed to the environment.

[0061] Thus, the heat conduction channel formed by the thermal connection between the first heat conduction element 130 and the second heat conduction element 230 can promptly conduct the heat in the first chip 100 and / or the second chip 200 from the exposed part 420 to the environment, reducing heat accumulation inside the chip and improving heat dissipation capacity.

[0062] In some embodiments, such as Figure 3 and Figure 4 As shown, when the area of ​​the second chip 200 is larger than the area of ​​the first chip 100, the first chip 100 can be located in the central region of the second chip 200, so that a portion of the second chip 200 forms an exposed portion that is exposed to the environment on all sides relative to the first chip 100. In this way, with appropriate heat-conducting components, heat from within the chip can be conducted to the environment more quickly through the exposed portion, improving heat dissipation efficiency.

[0063] In some embodiments, such as Figure 3 , Figure 6As shown, the first heat-conducting element 130 may include a first heat-conducting portion 131 extending in the thickness direction to conduct heat in the thickness direction. Alternatively, in some embodiments, the first heat-conducting element 130 may include a second heat-conducting portion extending in a plane parallel to or coinciding with the main plane of the first chip 100, or extending in a plane perpendicular to the thickness direction, to conduct heat in a plane perpendicular to the thickness direction.

[0064] In some embodiments, the first chip 100 may include a first substrate 160, a first device layer 170, a first wiring layer 180, and a first passivation layer 190 stacked sequentially in the thickness direction. In a specific example, such as... Figure 3 As shown, the first substrate 160 may be disposed close to the second chip 200 in the thickness direction to bond with the second chip 200. Alternatively, in another specific example, the first passivation layer 190 may be disposed close to the second chip 200 in the thickness direction to bond with the second chip 200.

[0065] like Figure 3 As shown, the first thermally conductive portion 131 of the first thermally conductive element 130 can be filled within the first via 120. The first via 120 can be formed in at least one of the first substrate 160, the first device layer 170, the first wiring layer 180, and the first passivation layer 190. When the first substrate 160 is disposed close to the second chip 200, the first via 120 can be formed at least in the first substrate 160, and a first thermally conductive portion 131 for thermal communication with the second thermally conductive element 230 can be formed by filling it with a corresponding thermally conductive material. For example, as... Figure 3 As shown, the first via 120 may be formed only in the first substrate 160, or the first via 120 may be formed in one or more of the first device layer 170, the first wiring layer 180, and the first passivation layer 190, in addition to being formed in the first substrate 160. When the first passivation layer 190 is disposed close to the second chip 200, the first via 120 may be formed at least in the first passivation layer 190, and a first thermally conductive portion 131 for thermal communication with the second thermally conductive element 230 may be formed by filling it with a corresponding thermally conductive material. For example, the first via 120 may be formed only in the first passivation layer 190, or the first via 120 may be formed in one or more of the first substrate 160, the first device layer 170, and the first wiring layer 180, in addition to being formed in the first passivation layer 190.

[0066] Alternatively, in some other embodiments, the first passivation layer 190 may be omitted, that is, the first chip 100 may include a first substrate 160, a first device layer 170 and a first wiring layer 180 stacked sequentially in the thickness direction. The first substrate 160 or the first wiring layer 180 may be disposed close to the second chip 200 in the thickness direction to be bonded to the second chip 200. Accordingly, when the first wiring layer 180 is disposed close to the second chip 200, the first via 120 may be formed at least in the first wiring layer 180.

[0067] In some embodiments, such as Figure 7 As shown, the first chip 100 may have one or more layers of first wiring 132 extending in a plane perpendicular to the thickness direction. At least a portion of the one or more layers of first wiring may be configured as a second heat-conducting portion of the first heat-conducting element 130 to conduct heat in a plane perpendicular to the thickness direction. For example, a portion of the one or more layers of first wiring 132 may be configured as a second heat-conducting portion of the first heat-conducting element 130, and another portion may be configured as a conductive portion for implementing related circuit connections, wherein these two portions may be electrically isolated to prevent short circuits in the related circuits. In a specific example, the one or more layers of first wiring 132 may be located as follows: Figure 3 In the first wiring layer 180 of the first chip 100 shown.

[0068] In a specific example, the location of the first through-hole 120 in the first chip 100 can be determined in advance by, for example, thermal simulation, thereby determining the location of the first heat-conducting portion 131 in the first chip 100. Through the corresponding first heat-conducting portion 131 and / or one or more layers of first wiring 132, heat in the first chip 100 can be conducted to the second heat-conducting element 230 of the second chip 200.

[0069] like Figure 3 and Figure 4 The second heat-conducting element 230 in the second chip 200 may include one or more layers of second wiring 232. These layers of second wiring 232 may extend in a plane parallel to or coinciding with the main plane of the second chip 200, or in a plane perpendicular to the thickness direction, to conduct heat in the plane perpendicular to the thickness direction. The layers of second wiring 232 may be partially located in the exposed portion 420, thus partially exposed to the environment. This arrangement increases the heat exchange area between the second wiring 232 and the environment. The portion of the second wiring 232 exposed to the environment facilitates rapid heat conduction from inside the chip to the outside, improving heat dissipation capacity.

[0070] In some embodiments, to avoid short circuits in related circuits, such as Figure 3As shown, the second chip 200 may include a second passivation layer 290, wherein a first side of the second passivation layer 290 may be used to bond with the first chip, and one or more layers of second wiring 232 may be located on a second side of the second passivation layer 290 opposite to the first side.

[0071] In some embodiments, the second heat-conducting element 230 may include a third heat-conducting portion 231 extending in the thickness direction to conduct heat in the thickness direction. For example... Figure 3 As shown, the second heat-conducting element 230 may include a third heat-conducting portion 231 filled within a second through-hole 220 formed in the second passivation layer 290. One end of the third heat-conducting portion 231 may be thermally connected to the first heat-conducting element 130, and the other end may be thermally connected to one or more layers of second wiring 232. The one or more layers of second wiring 232 can achieve thermal communication with the first heat-conducting element 130 via the third heat-conducting portion 231 in the second passivation layer 290, allowing heat in the first chip 100 to be conducted through the first heat-conducting element 130 to the second wiring 232, and then quickly dissipated into the environment from the exposed portion of the second wiring 232. This improves the heat dissipation capacity of the first chip 100 and extends its service life.

[0072] like Figure 3 As shown, the second chip may further include a second substrate 260, a second device layer 270, and a second wiring layer 280 stacked sequentially in the thickness direction, wherein the second wiring layer 280 is located between the second device layer 270 and the second passivation layer 290, and one or more layers of second wiring 232 may be located in the second wiring layer. In some embodiments, the third thermally conductive portion 231 of the second thermally conductive element 230 may fill not only the second via 220 formed in the second passivation layer 290, but also the second via 220 formed in one or more of the second substrate 260, the second device layer 270, and the second wiring layer 280. In a specific example, the location of the second via 220 to be formed in the second chip 200 can be determined in advance by, for example, thermal simulation, thereby determining the location of the third thermally conductive portion 231 in the second chip 200. By using one or more layers of second wiring 232 and the corresponding third thermally conductive portion 231, the heat in the second chip 200 can also be quickly dissipated to the environment, thereby improving the heat dissipation capacity of the second chip 200 and increasing its service life.

[0073] Alternatively, in some other embodiments, the second passivation layer 290 may be omitted. For example, one or more layers of the second wiring 232 may be directly thermally connected to the first heat-conducting element 130 of the first chip 100, without limitation.

[0074] like Figure 3As shown, in some embodiments, the semiconductor device 400 may further include a bonding layer 410, wherein the bonding layer 410 is located between the first chip 100 and the second chip 200 and can be configured to bond the first chip 100 and the second chip 200 to improve the package integration of the semiconductor device 300. The first thermal conductive element 130 and the second thermal conductive element 230 can be thermally connected via bonding pads 411 in the bonding layer 410. In a specific example, such as... Figure 3 As shown, the first heat-conducting portion 131 of the first heat-conducting component 130 can be thermally connected to the third heat-conducting portion 231 of the second heat-conducting component 230 via the bonding pad 411, so that the heat in the first chip 100 can be dissipated into the environment via the first heat-conducting portion 131, the bonding pad 411, the third heat-conducting portion 231 and one or more layers of second wiring 232.

[0075] The heat distribution inside individual chips in a semiconductor device is typically uneven during operation, for example, in areas closer to the device's location within the chip (e.g., Figure 3 and Figure 4 The hot spot region 430 shown typically has higher heat generation. To reduce heat accumulation in the hot spot region 430, in some embodiments, the heat conduction channel formed by the first heat conductor 130 and the second heat conductor 230 can be configured to transfer heat from the hot spot region 430 in the first chip 100 and / or the second chip 200, wherein the hot spot region 430 can be determined by thermal simulation based on the layout of the first chip 100 and / or the second chip 200. Specifically, in some embodiments, the first heat conductor 130 can be configured to conduct heat from the hot spot region 430 in the first chip 100 to the second heat conductor 230 in the second chip 200, so that the heat from the hot spot region 430 in the first chip 100 is transferred to the environment from the exposure portion 420 via the first heat conductor 130 and the second heat conductor 230. One end of the first heat conductor 130 can be configured to be close to the hot spot region 430, and the other end of the first heat conductor 130 can be configured to be in thermal communication with the second heat conductor 230, for example, as shown in the figure. Figure 3 As shown, one end of the first heat-conducting portion 131 can be configured to be close to the hot spot area 430, and the other end can be configured to be thermally connected to one or more layers of second wiring 232, so that the heat of the hot spot area 430 of the first chip 100 can be conducted through the first heat-conducting element 130 and the second heat-conducting element 230. Figure 3 and Figure 4In the example shown, heat at the hot spot region 430 of the first chip 100 can be conducted to the bonding layer 410 via the first thermally conductive portion 131 of the first thermally conductive element 130, and then conducted to one or more layers of second wiring 232 of the second thermally conductive element 230 via the bonding pads 411 of the bonding layer 410, and then dissipated into the environment via the exposed portions of the one or more layers of second wiring 232. This reduces heat accumulation in the hot spot region 430 of the first chip 100, effectively improving the heat dissipation efficiency of the first chip 100, thereby increasing the heat dissipation capacity and lifespan of the semiconductor device 400.

[0076] Figure 4 This disclosure illustrates two arrangements of one or more second wiring layers 232 extending in a plane perpendicular to the thickness direction in some embodiments. In some embodiments, one or more second wiring layers 232 can be flexibly arranged according to actual space conditions. This maximizes the arrangement area of ​​one or more second wiring layers 232 while avoiding interference with signal transmission and obstruction of device layout in the chip, thus ensuring heat dissipation. The exposed portion 420 of the second chip 200 relative to the first chip 100 can be used to increase the total area of ​​the second wiring 232 exposed to the environment, thereby enhancing heat dissipation. Furthermore, depending on the availability of wiring resources, the second wiring 232 can be extended in the thickness direction to bypass areas with dense signal transmission and working device placement, thereby reducing the impact of the second wiring 232 on other components in the chip. In a specific example, the arrangement of the second wiring 232 can be flexibly adjusted according to the chip's power consumption and thermal management requirements to adapt to different application scenarios.

[0077] To further improve the heat dissipation capability of the semiconductor device, in some embodiments, the semiconductor device 400 may further include a heat dissipation device, wherein the heat dissipation device may be located on the portion of the second heat-conducting element 230 exposed to the environment and thermally connected to the second heat-conducting element 230 to facilitate the second heat-conducting element 230 to conduct heat to the environment. Figure 3 As shown, the exposed portion 420 can provide space for the installation of a heat dissipation device, and the heat dissipation device can be thermally connected to the portion of the second wiring 232 exposed to the environment to facilitate the conduction of heat by the second wiring 232, thereby improving the heat dissipation efficiency of the chip.

[0078] like Figure 3As shown, in some embodiments, the semiconductor device 400 may further include a third chip 300, wherein the third chip 300 may be bonded to a second side of the second chip 200 opposite to the first side. In a specific example, the third chip 300 may be bonded to the second chip 200 via a bonding layer 440. In some embodiments, by forming corresponding thermally connected thermally conductive portions in the third chip 300 and the second chip 200, heat within the third chip 300 can be conducted to one or more layers of second wiring 232, and then dissipated into the environment via environmentally exposed portions of the second wiring 232.

[0079] The first chip 100 can be configured to perform computational tasks; in one specific example, the first chip 100 can be configured as a logic layer in a three-dimensional integrated chip. The second chip 200 can also be configured to perform signal transmission, such as transmitting data between the first chip 100 and the third chip 300. In one specific example, the second chip 200 can be configured as a buffer layer in a three-dimensional integrated chip. The third chip 300 can be configured to store data; in one specific example, the third chip 300 can be configured as a storage layer in a three-dimensional integrated chip.

[0080] In 3D integrated chips, the logic layer, which performs computational tasks, typically generates more heat than other layers, and heat is more prone to accumulation. According to some embodiments of this disclosure, heat in hot spots within the logic layer can be effectively conducted away. For example, heat can be dissipated from the logic layer to the environment in a timely manner through second wiring in the second chip exposed to the environment, reducing heat accumulation within the logic layer and thus effectively improving the overall heat dissipation capacity and lifespan of the 3D integrated chip. Furthermore, the logic layer typically has complex computational circuitry. By setting a buffer layer to be exposed relative to the logic layer, facilitating the placement of corresponding heat-conducting components within the buffer layer and heat-dissipating components on the exposed portion of the buffer layer, more space can be provided for the computational circuitry within the logic layer while simultaneously promoting rapid heat conduction to the environment. This allows for optimized circuit layout, reduced thermal coupling between circuits, and helps reduce local peak temperatures.

[0081] According to another aspect of this disclosure, a method for preparing the apparatus is also provided. For example... Figure 3 , Figures 5 to 7 As shown, the method for preparing the device disclosed herein may include:

[0082] Step S110: Form the first heat-conducting element 130 in the first chip 100.

[0083] like Figure 6As shown, forming the first thermal conductive element 130 in the first chip 100 may include: forming a first through hole 120 in the first preset layer 110 of the first chip 100, and filling the first through hole 120 with thermally conductive material to form a first thermally conductive portion 131 of the first thermal conductive element 130.

[0084] In a specific example, forming a first via 120 in the first preset layer 110 of the first chip 100 may include: forming a patterned first resist layer on the first preset layer 110 of the first chip 100 using a photolithography process, and etching the first preset layer 110 under the protection of the first resist layer to form the first via 120. Specifically, a resist material may be deposited on the first preset layer 110, followed by electron beam exposure or ion beam exposure, and then development to form the patterned first resist layer on the first preset layer 110 of the first chip 100. Alternatively, a pattern from a photomask may be transferred onto the resist material using a photolithography process based on a photomask to form the patterned first resist layer.

[0085] In some embodiments, the first preset layer 110 may be, for example, as shown below. Figure 3 The first chip 100 shown may contain one or more of the following: a first substrate 160, a first device layer 170, a first wiring layer 180, and a first passivation layer 190. For example, the first preset layer 110 may be the first substrate 160, in which case only the first substrate 160 may be etched to form a first via 120 formed in the first substrate 160. Alternatively, the first substrate 160 and the first device layer 170 of the first chip 100 may be etched sequentially to form the first via 120 formed in both the first substrate 160 and the first device layer 170. As another example, the first preset layer 110 may be the first wiring layer 180, in which case the first wiring layer 180 may be etched to form the first via 120 formed in the first wiring layer 180. For example, the first preset layer 110 can be the first passivation layer 190. In this case, only the first passivation layer 190 can be etched to form the first via 120 formed in the first passivation layer 190. Alternatively, the first passivation layer 190 and the first wiring layer 180 can be etched sequentially to form the first via 120 formed in the first passivation layer 190 and the first wiring layer 180.

[0086] In some embodiments, the thermally conductive material may further include a conductive material, so that while forming the thermally conductive component in the chip by depositing the thermally conductive material, the conductive portion in the chip used for circuit connections can also be formed simultaneously. In a specific example, the thermally conductive material may include a metallic material. Metallic materials typically have high thermal conductivity, and forming the corresponding thermally conductive component using a metallic material can effectively improve the chip's heat dissipation performance and reduce thermal resistance.

[0087] like Figure 7As shown, the first heat-conducting element 130 forming the first chip 100 may include one or more first wirings 132 formed on the second preset layer 140 of the first chip 100 to form the second heat-conducting portion of the first heat-conducting element 130. The one or more first wirings 132 may extend in a plane parallel to or coincident with the main plane of the first chip 100, or in other words, may extend in a plane perpendicular to the thickness direction.

[0088] Specifically, in some embodiments, a continuous thin film of thermally conductive material can be deposited on the second preset layer 140. Then, a patterned second resist layer is formed on the thermally conductive material using photolithography. The portions of the thermally conductive material not covered by the second resist layer are then etched to form one or more first wiring layers 132. Next, the remaining second resist layer can be removed to avoid affecting subsequent processes. The second resist layer can be formed solely of photoresist, or it can be formed from materials such as deposited silicon nitride. Forming the patterned second resist layer on the thermally conductive material using photolithography can, for example, involve depositing the resist material on the thermally conductive material and transferring the pattern of the mask onto the resist material using photolithography based on a mask to form the patterned second resist layer.

[0089] Alternatively, in other embodiments, a patterned photoresist layer can be formed on the second preset layer 140 of the first chip 100 using photolithography, followed by the deposition of a continuous thin film of thermally conductive material. Then, a lift-off process is used to remove the photoresist layer and the thermally conductive material thereon, thereby allowing the remaining thermally conductive material to form one or more layers of the first wiring 132. Forming the patterned photoresist layer may, for example, include depositing photoresist material on the second preset layer 140, and the pattern of the photomask can be transferred onto the photoresist material using photolithography based on a photomask, thereby forming the patterned photoresist layer.

[0090] In some embodiments, the second preset layer 140 may be, for example, as shown below. Figure 3 The first substrate 160 of the first chip 100 shown allows one or more first wiring layers 132 to be formed on the first substrate 160. Alternatively, in some embodiments, the second predetermined layer may be, for example, as shown in the figure. Figure 3 The first device layer 170 of the first chip 100 shown can be located above the first substrate 160, thus one or more first wiring layers 132 can be formed on the first device layer 170. The one or more first wiring layers 132 can serve as... Figure 3 At least a portion of the first wiring layer 180 of the first chip 100 shown.

[0091] At least a portion of one or more layers of the first wiring 132 can be used as a second thermally conductive portion of the first thermally conductive element 130 to allow for subsequent thermal communication with a second thermally conductive element of the second chip. For example, a portion of one or more layers of the first wiring 132 can be used as a second thermally conductive portion, and another portion can be used as a conductive portion for implementing circuit connections, wherein these two portions can be electrically isolated to avoid short circuits in the relevant circuits. Alternatively, all portions of one or more layers of the first wiring 132 can be used as the second thermally conductive portion.

[0092] like Figure 3 , Figure 5 and Figure 8 As shown, the method for preparing the device disclosed herein may further include:

[0093] Step S120: Form the second heat-conducting element 230 in the second chip 200.

[0094] like Figure 8 As shown in (a), the second heat-conducting element 230 forming the second chip 200 may include one or more layers of second wiring 232 formed on the third preset layer 210 of the second chip 200, wherein the one or more layers of second wiring 232 may extend in a plane parallel to or coincident with the main plane of the second chip 200, or in other words, may extend in a plane perpendicular to the thickness direction.

[0095] Specifically, in some embodiments, a continuous thin film of thermally conductive material can be deposited on the third preset layer 210. Then, a patterned third resist layer is formed on the thermally conductive material using photolithography. The portions of the thermally conductive material not covered by the third resist layer are then etched to form one or more layers of second wiring 232. Next, the remaining third resist layer can be removed to avoid affecting subsequent processes. The third resist layer can be formed solely of photoresist, or it can be formed from materials such as deposited silicon nitride. Forming the patterned third resist layer on the thermally conductive material using photolithography can, for example, involve depositing an resist material on the thermally conductive material and transferring the pattern of the mask onto the resist material using photolithography based on a mask to form the patterned third resist layer.

[0096] Alternatively, in other embodiments, a patterned photoresist layer can be formed on the third preset layer 210 of the second chip 200 using photolithography, followed by the deposition of a continuous thin film of thermally conductive material. Then, a lift-off process is used to remove the photoresist layer and the thermally conductive material thereon, thereby allowing the remaining thermally conductive material to form one or more layers of the second wiring 232. Forming the patterned photoresist layer may, for example, include depositing photoresist material on the third preset layer 210, and the pattern of the photomask can be transferred onto the photoresist material using photolithography based on a photomask, thereby forming the patterned photoresist layer.

[0097] In some embodiments, the third preset layer 210 may be, for example, as shown below. Figure 3 The second substrate 260 of the second chip 200 shown allows for the formation of one or more layers of second wiring 232. Alternatively, in some embodiments, the third preset layer 210 may be, for example, as shown in the figure. Figure 3 The second device layer 270 of the second chip 200 shown can be located above the second substrate 260, thus allowing one or more layers of second wiring 232 to be formed on the second device layer 270. The one or more layers of second wiring 232 can serve as... Figure 3 At least a portion of the second wiring layer 280 of the second chip 200 shown.

[0098] Reference Figure 3 When the first chip 100 and the second chip 200 are joined, the one or more layers of second wiring 232 formed above may be partially located in the exposed portion 420 of the second chip 200 relative to the first chip 100, so as to be partially exposed to the environment, so that the heat in the chip can be dissipated to the environment in a timely manner through the exposed portion of the one or more layers of second wiring 232.

[0099] In some embodiments, to prevent short circuits in related circuits caused by the formation of one or more layers of second wiring 232 when the first chip 100 and the second chip 200 are joined, such as... Figure 8 As shown in (b) above, the second heat-conducting element 230 forming the second chip 200 may further include:

[0100] Step S121: A second passivation layer 290 is formed on one or more layers of the second wiring.

[0101] Next, by performing localized etching on the second passivation layer 290, one or more layers of the second wiring 232 can be partially exposed to the environment when the second chip 200 is bonded to the first chip 100, thereby enabling rapid heat dissipation. Furthermore, external heat dissipation devices can be directly arranged on the exposed portions of the one or more layers of the second wiring 232, which helps to increase heat exchange efficiency and improve heat dissipation performance.

[0102] In a specific example, such as Figure 8 As shown in (c) and (d) in the figure, the second heat-conducting element 230 forming the second chip 200 may further include:

[0103] Step S122: A patterned fourth anti-etching layer 10 is formed on the second passivation layer 290;

[0104] Step S123: The second passivation layer 290 is etched under the protection of the fourth anti-etching layer 10 until at least one or more layers of the second wiring 232 are exposed.

[0105] Considering that the remaining etch resist layer may affect subsequent processes, in some embodiments, the remaining etch resist layer may be removed after step S122.

[0106] In some embodiments, after step S123, a patterned fifth etch-resistant layer can be formed on the remaining second passivation layer 290, and the second passivation layer 290 can be etched under the protection of the fifth etch-resistant layer to form a second via 220 formed in the second passivation layer 290. In this way, the second via 220 of the second passivation layer 290 and the portion of the second wiring 232 exposed to the environment can be formed respectively. Alternatively, in other embodiments, such as... Figure 8 As shown in (c) and (d), etching the second passivation layer 290 in step S123 may include forming a second via 220 in the second passivation layer 290. In this way, the location of the second via 220 in the second passivation layer 290 and the portion of the second wiring 232 that will be exposed to the environment can be taken into account to form a fourth anti-etching layer 10 with a corresponding pattern. Then, the second via 220 and the portion of the second wiring 232 exposed to the environment can be formed simultaneously by subsequent etching, thereby simplifying the process and saving manufacturing costs.

[0107] Next, as Figure 8 As shown in (d), a thermally conductive material can be filled into the second through-hole 220 to form a third thermally conductive portion 231 of the second thermally conductive element 230. One end of the third thermally conductive portion 231 can be used for thermal communication with the first thermally conductive element 130, and the other end can be used for thermal communication with one or more layers of second wiring 232. When the first chip 100 and the second chip 200 are bonded, the third thermally conductive portion 231 in the second passivation layer 290 can achieve thermal communication between the first thermally conductive element 130 and one or more layers of second wiring 232.

[0108] In some embodiments, it is also possible to, for example Figure 3A second via is formed in one or more of the second substrate 260, the second device layer 270, and the second wiring layer 280 of the second chip 200 shown. By filling the second via with a thermally conductive material, a corresponding third thermally conductive portion can be formed. The heat inside the second chip 200 can be conducted to one or more layers of the second wiring 232 through the corresponding third thermally conductive portion. This allows the heat inside the second chip 200 to be quickly dissipated to the environment through the exposed portions of the one or more layers of the second wiring 232, reducing heat accumulation inside the second chip 200, improving the heat dissipation capacity of the second chip 200, and thus improving the service life of the second chip 200.

[0109] like Figure 3 and Figure 5 As shown, the method for preparing the device disclosed herein may further include:

[0110] Step S130: Connect the first chip 100 and the second chip 200 to make the first heat-conducting element 130 and the second heat-conducting element 230 thermally connected.

[0111] The area of ​​the second chip 200 can be larger than that of the first chip 100, so that a portion of the second chip 200 forms an exposed portion 420 relative to the first chip 100 exposed to the environment. The second heat-conducting element 230 in the second chip 200 can be partially located in the exposed portion 420, thus partially exposed to the environment. In this way, the heat-conducting channel formed by the thermal connection between the first heat-conducting element 130 and the second heat-conducting element 230 can promptly conduct heat from the first chip 100 and the second chip 200 from the exposed portion 420 to the environment, reducing heat accumulation within the chip and improving heat dissipation capacity.

[0112] In some embodiments, bonding the first chip 100 and the second chip 200 may include bonding the first chip 100 to the central region of the second chip 200, so that a portion of the second chip 200 forms an exposed portion that is exposed to the environment on all sides relative to the first chip 100. This allows heat from the chip to be conducted to the environment more quickly through the exposed portion via appropriate heat-conducting components, thereby improving heat dissipation efficiency.

[0113] In some embodiments, bonding the first chip 100 and the second chip 200 may include forming a bonding layer 410 on at least one of a first side of the second chip 200 and a second side of the first chip 100, wherein the first side of the second chip 200 and the second side of the first chip 100 may be disposed face-to-face adjacent to each other, and the first thermal conductive element 130 of the first chip 100 and the second thermal conductive element 230 of the second chip 200 may be thermally connected via bonding pads 411 in the bonding layer 410. In a specific example, a hybrid bonding process may be used to bond the first chip 100 and the second chip 200 to improve the package integration of the first chip 100 and the second chip 200, and a corresponding bonding layer 410 may be formed between the first side of the second chip 200 and the second side of the first chip 100.

[0114] In some embodiments, bonding materials can be deposited on the first side of the first chip 100 and the second side of the second chip 200 respectively to form a bonding layer 410, so as to bond the first chip 100 and the second chip 200 through the bonding layer 410 on the first chip 100 and the second chip 200.

[0115] To further improve the heat dissipation effect of the semiconductor device, in some embodiments, the portion of the second heat-conducting element 230 exposed to the environment (such as...) can also be included. Figure 3 A third heat-conducting element is formed on the portion of one or more layers of the second wiring 232 exposed to the environment, which is in thermal communication with the second heat-conducting element 230. Alternatively, a corresponding heat dissipation device can be in thermal communication with the second heat-conducting element 230 to enable the second wiring 232 to conduct heat to the environment.

[0116] In some embodiments, the location of the hot spot region 430 of at least one of the first chip 100 and the second chip 200 can be determined by thermal simulation. Based on the location of the hot spot region 430, the locations of the first heat-conducting element 130 and the second heat-conducting element 230 can also be determined by thermal simulation, so that the heat-conducting channel formed by the thermal connection of the first heat-conducting element 130 and the second heat-conducting element 230 can conduct heat from the hot spot region 430, reducing heat accumulation in the hot spot region 430. For example, when the first chip 100 is used to perform computing tasks, the heat generated by the operation of the devices within the first chip 100 may be significant. In a specific example, the location of the hot spot region 430 in the first chip 100 can be determined by thermal simulation, and the location of the first heat-conducting element 130 in the first chip 100 can also be determined by thermal simulation. This allows the first heat-conducting element 130 to conduct heat from the hot spot region 430 to the second heat-conducting element 230 of the second chip 200, and then dissipate the heat from the exposed portion 420 to the environment via the second heat-conducting element 230, thereby effectively reducing heat accumulation within the first chip 100 and improving heat dissipation.

[0117] In some embodiments, the device preparation method disclosed herein may further include:

[0118] Step S210: Obtain the layout of the first chip 100 and the second chip 200;

[0119] Step S220: Determine the location of the hot spot area inside at least one of the first chip 100 and the second chip 200 through thermal simulation;

[0120] Step S230: Based on the layout of the first chip 100 and the second chip 200 and the location of the hot spot area, design a heat conduction channel for transferring the heat of the hot spot area through the exposed part, thereby determining the preset arrangement of the first heat conduction element 130 in the first chip 100 and the preset arrangement of the second heat conduction element 230 in the second chip 200.

[0121] Step S240: Insert the predetermined arrangement of the first heat-conducting component 130 and the second heat-conducting component 230 into the layout of the first chip 100 and the second chip 200, respectively.

[0122] In step S250, thermal simulation is used to determine whether the first chip 100 and the second chip 200 meet the preset thermal simulation requirements. If they do, step S260 is executed to carry out the subsequent device fabrication according to the designed heat conduction channel. Otherwise, the process returns to step S230 and the heat conduction channel is redesigned.

[0123] In this way, thermal simulation can be used to flexibly construct the corresponding heat conduction channels and determine the arrangement of heat conduction components in the corresponding chips. Furthermore, heat conduction channels can be effectively constructed under different chip stacking structures to improve the heat dissipation effect of the device.

[0124] In a specific example, thermal simulation is used to determine whether the first chip 100 and the second chip 200 meet the preset thermal simulation requirements. For example, it can be determined whether the chip temperature is less than or equal to the preset temperature.

[0125] In some embodiments, thermal channels can be designed by selecting appropriate metal components from a Process Design Kit (PDK). This allows for the efficient transfer of heat from hot spots to the environment without affecting the original chip layout. In a specific example, appropriate metal components can be pre-selected to form a preset thermal channel. Thermal simulation can then be used to predict the heat transfer within the chip under the preset thermal channel. Based on the heat transfer, the position and interconnection of the metal components can be optimized, thereby optimizing the heat conduction path and ensuring that heat from hot spots is quickly conducted to the environment, improving heat dissipation efficiency. Metal components may include, for example, at least one of through-silicon vias (TSVs), metal vias, metal wiring, thermal pads, bonding pads, package balls, and metal bumps. Metal components typically have high thermal conductivity. By constructing thermal channels using metal components, heat inside the chip can be quickly conducted to the outside, effectively reducing the temperature of hot spots, decreasing the chip's thermal resistance, and improving heat dissipation capacity. In some embodiments, at least some of the selected metal components can be configured to form... Figure 3 The first thermal conductive element 130 and / or the second thermal conductive element 230 shown are used to form corresponding thermal conductive elements to construct thermal conduction channels using metal components within the chip. This eliminates the need for additional heat dissipation equipment (such as heat sinks, fans, etc.), allowing the chip to maintain a small size and high integration design while ensuring high heat dissipation efficiency, thus meeting the stringent size and weight requirements of modern electronic devices.

[0126] Thus, based on the results of thermal simulation and in conjunction with the device fabrication methods described in some of the above embodiments, corresponding semiconductor devices (such as...) can be fabricated. Figure 3 The semiconductor device 400 shown.

[0127] In some embodiments, the hot spot area 430 of the chip can be evenly distributed by making reasonable arrangements of the first chip 100 and / or the second chip 200, for example, avoiding the concentration of working devices in the same area, so that the heat can flow rapidly between the layers of the chip, thereby reducing the thermal coupling of the chip and lowering the local maximum temperature on the chip, thereby making the temperature distribution of the chip more uniform and reducing the possibility of overheating.

[0128] Furthermore, the device fabrication method disclosed herein can also fabricate the semiconductor device 400 as described above.

[0129] In this disclosed technical solution, the heat is efficiently conducted from within the chip to the environment through a heat-conducting component in the exposed portion of the second chip relative to the first chip. This effectively reduces heat accumulation within the chip, improves heat dissipation capacity, and thus enhances chip performance stability and extends chip lifespan. Furthermore, this disclosed technical solution is compatible with existing 3D integrated manufacturing processes, can be adapted to existing 3D integrated manufacturing processes, does not require complex additional manufacturing processes, and can be easily mass-produced, exhibiting high production efficiency and feasibility.

[0130] The terms “left,” “right,” “front,” “back,” “top,” “bottom,” “upper,” “lower,” “high,” “lower,” etc., used in the specification and claims, if present, are for descriptive purposes and not necessarily for describing unchanging relative positions. It should be understood that such terms are interchangeable where appropriate, enabling embodiments of this disclosure described herein to operate, for example, in orientations different from those shown or otherwise described herein. For example, when the device in the drawings is reversed, a feature previously described as “above” other features may now be described as “below” other features. The device may also be oriented in other ways (rotated 90 degrees or in other orientations), in which case the relative spatial relationships will be interpreted accordingly.

[0131] In the specification and claims, when an element is described as being "on top of," "attached to," "connected to," "coupled to," or "in contact with" another element, the element may be directly located on top of, directly attached to, directly connected to, directly coupled to, or directly in contact with the other element, or one or more intermediate elements may be present. Conversely, when an element is described as being "directly" located on top of, directly attached to, directly connected to, directly coupled to, or directly in contact with another element, no intermediate elements are present. In the specification and claims, when a feature is arranged "adjacent" to another feature, it may mean that a feature has a portion overlapping with the adjacent feature or a portion located above or below the adjacent feature.

[0132] As used herein, the term “exemplary” means “serving as an example, instance, or illustration” and not as a “model” to be precisely copied. Any implementation described herein by example is not necessarily to be construed as preferred or advantageous over other implementations. Moreover, this disclosure is not limited to any theory expressed or implied as given in the field of art, background art, summary of invention, or detailed description.

[0133] As used herein, the term "substantially" means any minor variation resulting from design or manufacturing defects, device or component tolerances, environmental influences, and / or other factors. The term "substantially" also allows for differences from the perfect or ideal situation due to parasitic effects, noise, and other practical considerations that may exist in the actual implementation.

[0134] Furthermore, terms such as “first,” “second,” etc., may be used in this document for reference purposes only and are not intended to be limiting. For example, unless the context clearly indicates otherwise, the words “first,” “second,” and other such numerical terms relating to structures or elements do not imply order or sequence.

[0135] It should also be understood that when the term “including / contains” is used herein, it indicates the presence of the indicated feature, whole, step, operation, unit and / or component, but does not preclude the presence or addition of one or more other features, wholes, steps, operations, units and / or components and / or combinations thereof.

[0136] In this disclosure, the term “provide” is used broadly to cover all ways of obtaining an object, and therefore “provide an object” includes, but is not limited to, “purchasing,” “preparing / manufacturing,” “arranging / setting up,” “installing / assembling,” and / or “ordering” an object.

[0137] As used herein, the term “and / or” includes any and all combinations of one or more of the listed items in association. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of this disclosure. As used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise.

[0138] Those skilled in the art will recognize that the boundaries between the above operations are merely illustrative. Multiple operations may be combined into a single operation, a single operation may be distributed among additional operations, and operations may be performed with at least partial overlap in time. Moreover, alternative embodiments may include multiple instances of a particular operation, and the order of operations may be changed in various other embodiments. However, other modifications, variations, and substitutions are equally possible. Aspects and elements of all the embodiments disclosed above may be combined in any way and / or in combination with aspects or elements of other embodiments to provide multiple additional embodiments. Therefore, this specification and the accompanying drawings should be considered illustrative rather than restrictive.

[0139] While specific embodiments of this disclosure have been described in detail by way of example, those skilled in the art should understand that the examples are for illustrative purposes only and not intended to limit the scope of this disclosure. The various embodiments disclosed herein can be combined in any way without departing from the spirit and scope of this disclosure. Those skilled in the art should also understand that various modifications can be made to the embodiments without departing from the scope and spirit of this disclosure. The scope of this disclosure is defined by the appended claims.

Claims

1. A semiconductor device, characterized in that, The semiconductor device includes: A first chip, wherein a first heat-conducting element is formed in the first chip; The second chip has a second heat-conducting element that is thermally connected to the first heat-conducting element; A bonding layer, located between the first chip and the second chip and configured to bond the first chip and the second chip. The first thermal conductive element and the second thermal conductive element are thermally connected via bonding pads in the bonding layer. The first chip is bonded to a first side of the second chip. The area of ​​the second chip is larger than that of the first chip to form an exposed portion. The second thermal conductive element is partially located in the exposed portion to be partially exposed to the environment.

2. The semiconductor device according to claim 1, characterized in that, The first heat-conducting element includes a first heat-conducting portion and / or a second heat-conducting portion. The first thermally conductive portion fills the first through-hole formed in the first chip. The first chip has one or more first wirings extending in a plane perpendicular to the thickness direction, at least a portion of which is configured to serve as the second heat-conducting portion.

3. The semiconductor device according to claim 1, characterized in that, The second heat-conducting element includes one or more layers of second wiring extending in a plane perpendicular to the thickness direction, the one or more layers of second wiring being partially located in the exposed portion.

4. The semiconductor device according to claim 3, characterized in that, The second chip includes a passivation layer, a first side of which is used for bonding with the first chip, and one or more second wiring layers located on a second side of the passivation layer opposite to the first side. The second thermal conductive element further includes a third thermal conductive portion filled in a second through hole opened in the passivation layer. One end of the third thermal conductive portion is thermally connected to the first thermal conductive element, and the other end is thermally connected to the one or more layers of second wiring.

5. The semiconductor device according to claim 1, characterized in that, The semiconductor device further includes: A heat dissipation device, wherein the heat dissipation device is located on the portion of the second heat-conducting element exposed to the environment and is in thermal communication with the second heat-conducting element.

6. The semiconductor device according to claim 1, characterized in that, The semiconductor device further includes a third chip, which is bonded to a second side of the second chip opposite to the first side. The first chip is configured to perform computing tasks, the second chip is configured to perform signal transmission, or the third chip is configured to store data.

7. A method for preparing an apparatus, characterized in that, The method for preparing the device includes: Forming the first heat-conducting component in the first chip; Forming a second heat-conducting element in the second chip; and The first chip and the second chip are joined together to make the first thermally conductive element and the second thermally conductive element thermally connected. The bonding of the first chip and the second chip includes: forming a bonding layer on at least one of a first side of the second chip and a second side of the first chip, the first side of the second chip and the second side of the first chip being face-to-face adjacent to each other, the first thermal conductive element and the second thermal conductive element being thermally connected via bonding pads in the bonding layer, the area of ​​the second chip being larger than the area of ​​the first chip to form an exposed portion, and the second thermal conductive element being partially located in the exposed portion to be partially exposed to the environment.

8. The method for preparing the apparatus according to claim 7, characterized in that, The first heat-conducting element forming the first chip includes: A first through-hole is formed in a first preset layer of the first chip, and a thermally conductive material is filled into the first through-hole to form a first thermally conductive portion of the first thermally conductive element; and / or One or more first wirings are formed on the second preset layer of the first chip to form the second heat-conducting portion of the first heat-conducting component, wherein the one or more first wirings extend in a plane perpendicular to the thickness direction.

9. The method for preparing the apparatus according to claim 7, characterized in that, The second heat-conducting element forming the second chip includes: One or more second wirings are formed on the third preset layer of the second chip, extending in a plane perpendicular to the thickness direction, wherein the one or more second wirings are partially located in the exposed portion when the first chip and the second chip are joined.

10. The method for preparing the apparatus according to claim 9, characterized in that, The second heat-conducting element forming the second chip also includes: A passivation layer is formed on the one or more layers of the second wiring; A patterned anti-etching layer is formed on the passivation layer; The passivation layer is etched under the protection of the etch-resistant layer until at least partially exposing one or more layers of second wiring; and Remove the remaining anti-etching layer.

11. The method for preparing the apparatus according to claim 10, characterized in that, Etching the passivation layer under the protection of the anti-etching layer includes forming a second via in the passivation layer, wherein forming the second heat-conducting element in the second chip further includes: A thermally conductive material is filled into the second through hole to form a third thermally conductive portion of the second thermally conductive element. One end of the third thermally conductive portion is used to thermally communicate with the first thermally conductive element, and the other end is used to thermally communicate with the one or more layers of the second wiring.

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