Packaging substrate and forming method thereof, and CIS chip packaging structure and forming method thereof

Abstract

The invention provides a packaging substrate and a forming method thereof, and a CIS chip packaging structure and a forming method thereof, the packaging substrate comprises a substrate, the substrate is provided with a first surface and a second surface which are opposite to each other, the second surface of the substrate is provided with a plurality of pins, and a groove is arranged between two adjacent pins; the groove is filled with the first packaging layer; the redistribution layer is formed on the first surface of the substrate; and the metal layer covers the rewiring layer and all the pins. The packaging substrate is free of structures such as table supports and connecting ribs, the structure is simple, the universality is high, the utilization rate is high, the metal layer wraps the rewiring layer and all the pins, the binding force is high, and the reliability is improved. In the CIS chip packaging structure formed by using the packaging substrate, the cavity between the chip and the packaging substrate is small, and the binding force between the chip and the packaging substrate is improved.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and particularly to a packaging substrate and a method for forming the same, a CIS chip packaging structure and a method for forming the same. Background Art

[0002] Figure 1 It is a schematic diagram of a CIS chip packaging structure in the prior art. As Figure 1 shown, the package shell 100 is generally in a frame shape. When packaging the chip, it can be connected to the bottom surface position inside the package shell 100 through silver paste. A plurality of pads are provided at the edge positions around the surface of the chip 102. At the same time, a plurality of pins 101 are correspondingly arranged around the edge position of the inner bottom surface of the package shell 100 to surround the chip 102. The pads and the corresponding pins 101 are connected through bonding wires 103, and a glass cover plate 104 is covered on the package shell 100.

[0003] In the above packaging process, the frame has table supports, cavities, etc., and the overall bonding force is poor. The package shell for packaging the CIS chip is formed by using a ceramic substrate or a plastic substrate, and the mold opening cost of ceramic packaging and plastic packaging is relatively high, the unit price is high, and the process is relatively complex. Summary of the Invention

[0004] The purpose of the present invention is to provide a packaging substrate and a method for forming the same, a CIS chip packaging structure and a method for forming the same, so as to reduce cavities, improve bonding force and reliability.

[0005] To achieve the above purpose, the present invention provides a packaging substrate, including:

[0006] A substrate having opposite first and second surfaces, the second surface of the substrate having a plurality of pins, and a groove between two adjacent pins;

[0007] A first packaging layer filling the groove;

[0008] A redistribution layer formed on the first surface of the substrate;

[0009] A metal layer covering the redistribution layer and all the pins.

[0010] Optionally, in the packaging substrate, the material of the substrate includes copper.

[0011] Optionally, in the packaging substrate, the material of the first packaging layer is epoxy molding compound or epoxy resin adhesive.

[0012] Based on the same inventive concept, the present invention also provides a method for forming a packaging substrate, including:

[0013] Provide a substrate having opposite first and second surfaces;

[0014] Etch the second surface of the substrate to form a plurality of pins, with grooves between adjacent pins;

[0015] Form a first encapsulation layer that fills the grooves;

[0016] Etch the first surface of the substrate to form a redistribution layer; and,

[0017] Perform an electroplating process to form a metal layer that covers the redistribution layer and all the pins.

[0018] Optionally, in the method for forming the encapsulation substrate, the method for etching the second surface of the substrate to form a plurality of the pins includes:

[0019] Form a patterned photoresist layer on the second surface of the substrate, the patterned photoresist layer having a plurality of openings that expose a portion of the second surface of the substrate; and,

[0020] Use the patterned photoresist layer as a mask to etch the second surface of the substrate to form the pins.

[0021] Optionally, in the method for forming the encapsulation substrate, use a dry etching process to etch the second surface of the substrate to form the pins; use a dry etching process to etch the first surface of the substrate to form the redistribution layer.

[0022] Optionally, in the method for forming the encapsulation substrate, after etching the second surface of the substrate to form a plurality of the pins and before forming the first encapsulation layer, the method for forming the encapsulation substrate further includes:

[0023] Roughen the first surface of the substrate and the second surface having the pins.

[0024] Based on the same inventive concept, the present invention also provides a CIS chip encapsulation structure, including:

[0025] The encapsulation substrate as described above;

[0026] A chip, flip-chip fixed on the first surface of the substrate, the chip having pads that are electrically connected to the pins;

[0027] A cover plate, attached to the photosensitive area of the chip;

[0028] A second encapsulation layer, formed on the first surface of the first substrate and wrapping the chip.

[0029] Optionally, in the CIS chip packaging structure described above, the material of the second packaging layer is epoxy molding compound or epoxy resin adhesive.

[0030] Based on the same inventive concept, the present invention also provides a method for forming a CIS chip packaging structure, including:

[0031] Providing the packaging substrate as described above:

[0032] Providing a chip, and flip-chip fixing the chip on the first surface of the substrate through a flip-chip process. The chip has pads, and the pads are electrically connected to the pins;

[0033] Providing a cover plate, and attaching the cover plate to the photosensitive area of the chip; and,

[0034] Forming a second packaging layer, which is formed on the first surface of the first substrate and wraps the chip.

[0035] In the packaging substrate provided by the present invention, the packaging substrate includes a substrate. The substrate has opposite first and second surfaces. The second surface of the substrate has a plurality of pins, and there are grooves between adjacent two pins; a first packaging layer that fills the grooves; a redistribution layer formed on the first surface of the substrate; and a metal layer that covers the redistribution layer and all the pins. The packaging substrate has no structures such as pedestal supports and connecting ribs, with a simple structure, strong versatility, and high utilization rate. The metal layer wraps the redistribution layer and all the pins, with strong bonding force and improved reliability.

[0036] In the CIS chip packaging structure, the chip is flip-chip fixed on the first surface of the substrate. The chip has pads, and the pads are electrically connected to the pins; a cover plate is attached to the photosensitive area of the chip; a second packaging layer is formed on the first surface of the first substrate and wraps the chip. In this way, the cavity between the chip and the packaging substrate is smaller, improving the bonding force between the chip and the packaging substrate. Description of the Drawings

[0037] Figure 1 is a schematic diagram of a CIS chip packaging structure in the prior art;

[0038] Figure 2 is a schematic diagram of the structure of the packaging substrate provided by an embodiment of the present invention;

[0039] Figure 3 is a schematic flowchart of the method for forming the packaging substrate provided by an embodiment of the present invention;

[0040] Figures 4 to 8 is a schematic diagram of the structure formed in the method for forming the packaging substrate provided by an embodiment of the present invention;

[0041] Figure 9It is a schematic structural diagram of the CIS chip packaging structure provided by an embodiment of the present invention;

[0042] Figure 10 It is a schematic flow diagram of the method for forming the CIS chip packaging structure provided by an embodiment of the present invention;

[0043] Among them, the reference numerals are explained as follows:

[0044] 100 - Package shell; 101 - Pin; 102 - Chip; 103 - Bonding wire; 104 - Glass cover plate;

[0045] 100 - Packaging substrate; 101 - Substrate; 101a - First surface; 102b - Second surface; 110 - Pin; 110a - Groove; 120 - First packaging layer; 130 - Redistribution layer; 130a - Redistribution pattern; 140 - Metal layer.

[0046] 200 - Chip; 201 - Pad;

[0047] 300 - Cover plate;

[0048] 400 - Second packaging layer; 401 - Bonding wire; Specific embodiments

[0049] The following further elaborates on the packaging substrate and its forming method, the CIS chip packaging structure and its forming method proposed by the present invention in conjunction with the accompanying drawings and specific embodiments. According to the following description, the advantages and features of the present invention will be clearer. It should be noted that the accompanying drawings are all in a very simplified form and use non - precise scales, only for conveniently and clearly assisting in explaining the purpose of the embodiments of the present invention.

[0050] Figure 2 It is a schematic cross - sectional structure diagram of the packaging substrate provided by an embodiment of the present invention. As Figure 2 shown, this embodiment provides a packaging substrate, including a substrate 101, a first packaging layer 120, a redistribution layer 130, and a metal layer 140.

[0051] The substrate 101 is used as a carrier for encapsulating chips and can play roles such as electrical connection, protection, support, heat dissipation, and assembly. Specifically, the substrate 101 has opposite first surface 101a and second surface 101b. The second surface 101b of the substrate 101 has a plurality of pins 110, and there are grooves between two adjacent pins 110. The pins 110 are used for electrically connecting with the pads 201 of the chip 200. Among them, the shape of the pins 110 can be cylindrical, and the material of the substrate 101 includes copper. The shapes and sizes of all the pins 110 on the second surface 101b of the substrate 101 can be the same, and the widths and depths of the grooves between two adjacent pins 110 can be the same, so that the pins 110 are evenly distributed on the first surface 101a. In addition, since the second surface 101b of the substrate 101 has a plurality of pins 110, the number of formed IO (Input Output) interfaces is large, and the utilization rate of the substrate 101 is high.

[0052] In this embodiment, the first encapsulation layer 120 fills the grooves, that is, the first encapsulation layer 120 is formed on the second surface 101b of the substrate 101. Among them, the bottom surface of the first encapsulation layer 120 can be flush with the bottom surface of the pins 110. The material of the first encapsulation layer 120 can be epoxy molding compound or epoxy resin glue.

[0053] As Figure 2 shown, the redistribution layer 130 (Redistribution Layer, RDL) is formed on the first surface 101a of the substrate 101. The redistribution layer 130 includes a plurality of mutually separated redistribution patterns 130a, and the cross-sectional shape of the redistribution pattern 130a in the vertical direction can be trapezoidal. It should be noted that the redistribution layer 130 can lead the pins 110 of the substrate 101 to appropriate positions.

[0054] In this embodiment, the metal layer 140 covers the redistribution layer 130 and all the pins 110. The redistribution layer 130 and the pins 110 are wrapped by the metal layer 140, thereby preventing oxidation. The bonding force between the metal layer 140 and the redistribution layer 130 and the pins 110 is strong, improving the reliability. Among them, the material of the metal layer 140 can be nickel or gold.

[0055] In this implementation, the packaging substrate 100 has no structures such as pedestals and connecting ribs, has a simple structure and strong versatility. The metal layer 140 wraps the redistribution layer 130 and all the pins 110, has a strong bonding force and improves the reliability.

[0056] Figure 3 It is a schematic flow chart of the formation method of the packaging substrate provided by the embodiment of the present invention. As Figure 3 shown, the formation method of the packaging substrate includes:

[0057] Step S1: Provide a substrate having opposite first and second surfaces;

[0058] Step S2: Etch the second surface of the substrate to form a plurality of pins, with grooves between adjacent ones of the pins;

[0059] Step S3: Form a first encapsulation layer that fills the grooves;

[0060] Step S4: Etch the first surface of the substrate to form a redistribution layer; and,

[0061] Step S5: Perform an electroplating process to form a metal layer that covers the redistribution layer 130 and all of the pins.

[0062] Figures 4 to 8 It is a schematic diagram of the structure formed in the method for forming the encapsulation substrate 100 provided by an embodiment of the present invention. The following will be combined with Figures 4 to 8 to provide a more detailed description of the method for forming the encapsulation substrate 100 provided in this embodiment.

[0063] First, perform step S1. As Figure 4 shown, provide a substrate 101 having opposite first and second surfaces 101a and 101b. The substrate 101 is in a flat plate shape. The material of the substrate 101 includes, for example, copper.

[0064] Next, perform step S2. As Figure 5 shown, etch the second surface 101b of the substrate 101 to form a plurality of pins 110, with grooves 110a between adjacent ones of the pins 110. Specifically, the method for etching the second surface 101b of the substrate 101 to form the plurality of pins 110 includes:

[0065] First, form a patterned photoresist layer (not shown) on the second surface 101b of the substrate 101. The patterned photoresist layer has a plurality of openings that expose a part of the second surface 101b of the substrate 101; and,

[0066] Next, using the patterned photoresist layer as a mask, etch the second surface 101b of the substrate 101 to form the pins 110, that is, etch a partial thickness of the second surface 101b of the substrate 101 to form the pins 110. The encapsulation substrate 100 can be electrically connected to the chip 200 through the pins 110. Among them, the second surface 101b of the substrate 101 can be etched by a dry etching process.

[0067] As Figure 6 shown, after forming the pin 110, the first surface 101a of the substrate 101 and the second surface 101b having the pin 110 are roughened to increase the roughness of the first surface 101a of the substrate 101 and the second surface 101b having the pin 110, thereby increasing the contact area between the subsequently formed first encapsulation layer and the substrate. Among them, die stamping and pressing or plasma etching can be used for roughening treatment.

[0068] Next, step S3 is executed. As Figure 7 shown, the first encapsulation layer 120 is formed, and the first encapsulation layer 120 fills the groove 110a. The material of the first encapsulation layer 120 can be epoxy molding compound, and the first encapsulation layer 120 can be formed by an injection molding process. Alternatively, the material of the first encapsulation layer 120 can be epoxy resin glue, and the first encapsulation layer 120 can be formed by a glue coating process.

[0069] After forming the first encapsulation layer 120, the first encapsulation layer 120 can be polished to make the surface of the first encapsulation layer 120 flat, and the excess molding compound or glue can be removed to reduce the thickness of the first encapsulation layer 120 and improve heat dissipation.

[0070] Next, step S3 is executed. As Figure 8 shown, the first surface 101a of the substrate 101 is etched, that is, the first surface 101a of the substrate 101 is etched to a partial thickness to form the redistribution layer 130. The first surface 101a of the substrate 101 is etched to form the redistribution layer 130. Specifically, the method of etching the first surface 101a of the substrate 101 includes:

[0071] First, a patterned photoresist layer is formed on the first surface 101a of the substrate 101, and the patterned photoresist layer exposes a part of the first surface 101a; then, using the patterned photoresist layer as a mask, the exposed first surface 101a is etched by a dry etching process to form the redistribution layer 130. Among them, the redistribution layer 130 includes a plurality of mutually separated redistribution patterns 130a, and the cross-sectional shape of the redistribution pattern 130a in the vertical direction can be trapezoidal. An opening is provided on each side of the redistribution pattern 130a, and the shape of the opening can be an inverted trapezoid. Further, the redistribution pattern 130a can be located on the first encapsulation layer 120.

[0072] Next, step S4 is executed. As Figure 2As shown, a metal layer 140 is formed, and the metal layer 140 covers the redistribution layer 130 and all the pins 110. The material of the metal layer 140 can be nickel or gold, and the metal layer 140 can be formed by an electroplating process. The redistribution layer 130 and the pins 110 can be wrapped by the metal layer 140 to prevent oxidation. The bonding force between the metal layer 140 and the redistribution layer 130 and the pins 110 is strong, improving reliability.

[0073] Figure 9 is a schematic structural diagram of a packaging structure of a CIS chip 200 provided by an embodiment of the present invention. As Figure 9 shown, this embodiment also provides a packaging structure for a CIS chip 9, including a packaging substrate 100, a chip 200, a cover plate 300, and a second packaging layer 400.

[0074] In this embodiment, the chip 200 is flip-chip fixed on the first surface 101a of the substrate 101, that is, the chip 200 is flip-chip fixed on the redistribution layer. The chip 200 has pads 201, and the pads 201 are electrically connected to the pins 110. Among them, the pads 201 can be in one-to-one correspondence with the pins 110 and electrically connected. Further, the electrical connection between the pads 201 and the pins 110 can be achieved through bonding wires 401. The bonding wires 401 can be gold wires or aluminum wires.

[0075] As Figure 9 shown, the cover plate 300 is attached to the photosensitive area of the chip 200. Among them, the material of the cover plate 300 can be glass.

[0076] As Figure 9 shown, the second packaging layer 400 is formed on the first surface 101a of the first substrate 101 and wraps the chip 200. Among them, the material of the second packaging layer 400 can be epoxy molding compound or epoxy resin glue. For the packaging structure of the CIS chip formed by using the packaging substrate 100 provided in this embodiment, the cavity between the chip 200 and the packaging substrate 100 is small, improving the bonding force between the chip 200 and the packaging substrate 100.

[0077] Figure 10 is a schematic flowchart of a method for forming a packaging structure of a CIS chip 200 provided by an embodiment of the present invention. As Figure 10 shown, this embodiment also provides a method for forming a packaging structure of a CIS chip 200, including:

[0078] Step S10: Provide a packaging substrate 100:

[0079] Step S20: Provide the chip 200, and flip-chip fix the chip 200 on the first surface 101a of the substrate 101 through a flip-chip process. The chip 200 has pads 201, and the pads 201 are electrically connected to the pins 110. Among them, the chip 200 can be a CIS (Complementary Metal Oxide Semiconductor Image Sensor) chip.

[0080] Step S30: Provide a cover plate 300, and attach the cover plate 300 to the photosensitive area of the chip 200. Among them, the cover plate 300 can be a glass cover plate 300. And,

[0081] Step S40: Form a second encapsulation layer 400. The second encapsulation layer 400 is formed on the first surface 101a of the first substrate 101 and wraps the chip 200. The material of the second encapsulation layer 400 can be an epoxy molding compound, and the first encapsulation layer 120 can be formed through an injection molding process. Or, the material of the second encapsulation layer 400 can be an epoxy resin adhesive, and the first encapsulation layer 120 can be formed through a glue coating process.

[0082] In summary, in the CIS chip encapsulation structure and its forming method provided in the embodiments of the present invention, the chip is flip-chip fixed on the first surface of the substrate. The chip has pads, and the pads are electrically connected to the pins; the cover plate is attached to the photosensitive area of the chip; the second encapsulation layer is formed on the first surface of the first substrate and wraps the chip. In this way, the cavity between the chip and the encapsulation substrate is small, and the bonding force between the chip and the encapsulation substrate is improved.

[0083] The above description is only a description of the preferred embodiments of the present invention, and does not limit the scope of the present invention in any way. Any changes and modifications made by those of ordinary skill in the art of the present invention based on the above disclosure are within the protection scope of the claims.

Claims

1. An encapsulation substrate, characterized in that, Comprising: A substrate having opposite first and second surfaces, the second surface of the substrate having a plurality of pins, with grooves between adjacent ones of the pins; A first encapsulation layer filling the grooves; A redistribution layer formed on the first surface of the substrate; A metal layer covering the redistribution layer and all of the pins.

2. The encapsulation substrate according to claim 1, wherein The substrate is made of copper.

3. The encapsulated substrate according to claim 1, wherein The material of the first encapsulation layer is epoxy molding compound or epoxy resin adhesive.

4. A method for forming a packaging substrate, characterized in that Comprising: Providing a substrate having opposite first and second surfaces; Etching the second surface of the substrate to form a plurality of pins, with grooves between adjacent ones of the pins; Forming a first encapsulation layer filling the grooves; Etching the first surface of the substrate to form a redistribution layer; And Performing an electroplating process to form a metal layer covering the redistribution layer and all of the pins.

5. The method for forming a packaged substrate according to claim 4, wherein, The method for etching the second surface of the substrate to form a plurality of the pins includes: Forming a patterned photoresist layer on the second surface of the substrate, the patterned photoresist layer having a plurality of openings exposing a portion of the second surface of the substrate; and Using the patterned photoresist layer as a mask to etch the second surface of the substrate to form the pins.

6. The method for forming an encapsulated substrate according to claim 5, wherein Etching the second surface of the substrate using a dry etching process to form the pins; etching the first surface of the substrate using a dry etching process to form the redistribution layer.

7. The method for forming a packaged substrate according to claim 4, wherein After etching the second surface of the substrate to form a plurality of the pins and before forming the first encapsulation layer, the method for forming the packaged substrate further includes: Roughening the first surface of the substrate and the second surface having the pins.

8. A CIS chip packaging structure, characterized in that, Comprising: A packaged substrate as described in any one of claims 1 to 3; A chip flip-chip fixed on the first surface of the substrate, the chip having pads electrically connected to the pins; A cover plate attached to the photosensitive area of the chip; A second encapsulation layer formed on the first surface of the first substrate and wrapping the chip.

9. The CIS chip packaging structure according to claim 8, characterized in that, The material of the second encapsulation layer is epoxy molding compound or epoxy resin adhesive.

10. A method for forming a packaging structure of a CIS chip, characterized in that, Comprising: Providing a packaged substrate as described in any one of claims 1 to 3: Providing a chip and flip-chip fixing the chip on the first surface of the substrate through a flip-chip process, the chip having pads electrically connected to the pins; Providing a cover plate and attaching the cover plate to the photosensitive area of the chip; and Forming a second encapsulation layer, the second encapsulation layer formed on the first surface of the first substrate and wrapping the chip.

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