Chip packaging structure and electronic equipment

Abstract

The invention relates to a chip packaging structure and electronic equipment. The chip packaging structure comprises a carrier plate, and a first power chip, a double-sided substrate and a second power chip which are sequentially stacked on the carrier plate, the orthographic projection of the first power chip and the orthographic projection of the second power chip on the double-sided substrate are spaced from the edge of the double-sided substrate. The first power chip is inversely arranged on the back surface of the double-sided substrate and comprises a first grid electrode, a first drain electrode and a first source electrode; the first grid electrode is connected with the first leading-out end of the double-sided substrate, the first drain electrode is connected with the carrier plate through the exposed edge of the double-sided substrate, and the first source electrode is connected with the carrier plate; the second power chip is arranged on the front surface of the double-sided substrate and comprises a second grid electrode and a second drain electrode; the second grid electrode is connected with the second leading-out end of the double-sided substrate, and the second drain electrode is connected with the carrier plate through the exposed edge of the double-sided substrate. According to the chip packaging structure, the occupied space of the chip packaging structure can be reduced, and the storage capacity is multiplied.

Description

Technical Field

[0001] The present application relates to the field of integrated circuit technology, and particularly to a chip packaging structure and an electronic device. Background Art

[0002] With the continuous development of power devices towards integration, intelligence, and miniaturization, some advanced packaging methods such as System In Package (SiP) have been proposed for manufacturing high-power device modules.

[0003] However, the current market demand for packaging size is getting smaller and smaller, and the existing chip integration packaging solutions are gradually unable to meet the market demand for small sizes. Therefore, how to further reduce the size of the chip packaging structure is an urgent problem to be solved currently. Summary of the Invention

[0004] Based on this, the embodiments of the present application provide a chip packaging structure and an electronic device, which can reduce the occupied space of the chip packaging structure and achieve a doubling of the storage capacity.

[0005] According to some embodiments, the present application provides a chip packaging structure, including a carrier board, and a first power chip, a double-sided substrate, and a second power chip stacked in sequence on the carrier board; there are spaces between the orthographic projections of the first power chip and the second power chip on the double-sided substrate and the edges of the double-sided substrate;

[0006] The back surface of the first power chip is in contact with the back surface of the double-sided substrate, and includes a first gate, a first drain, and a first source; the first gate is connected to the first lead-out end of the double-sided substrate, the first drain is connected to the carrier board through the exposed edge of the double-sided substrate, and the first source is connected to the carrier board;

[0007] The back surface of the second power chip is in contact with the front surface of the double-sided substrate, and includes a second gate and a second drain; the second gate is connected to the second lead-out end of the double-sided substrate, and the second drain is connected to the carrier board through the exposed edge of the double-sided substrate;

[0008] Wherein, a connection circuit is provided in the double-sided substrate; both ends of the connection circuit are correspondingly connected to the first lead-out end and the second lead-out end respectively.

[0009] In some embodiments, the carrier board includes a first base island, a second base island, and a third base island arranged at intervals;

[0010] Wherein, the first source electrode is connected to the first base island, the first drain electrode is connected to the second base island via the edge exposed by the double-sided substrate, and the second drain electrode is connected to the third base island via the edge exposed by the double-sided substrate.

[0011] In some embodiments, the first power chip and the second power chip are arranged in mirror symmetry with respect to the double-sided substrate.

[0012] In some embodiments, vias are formed in the edge exposed by the double-sided substrate;

[0013] The chip packaging structure further includes a first drain lead passing through the via; the first drain electrode is connected to the second base island via the first drain lead.

[0014] In some embodiments, the chip packaging structure further includes a driving chip; the driving chip includes a first driving signal output terminal and a second driving signal output terminal;

[0015] Wherein, the first gate electrode is led out via the first lead-out end and connected to the first driving signal output terminal, and the second gate electrode is led out via the second lead-out end and connected to the second driving signal output terminal.

[0016] In some embodiments, the driving chip has a first side and a second side connected to each other;

[0017] The first base island is disposed beside the first side, and the third base island is disposed beside the second side; the second base island is disposed beside the first base island and the third base island, and is at least close to at least one side of the first base island and at least one side of the third base island.

[0018] In some embodiments, one side surface of the first power chip is attached to the first base island, so that the first source electrode is connected to the first base island.

[0019] In some embodiments, the second power chip further includes a second source electrode; the second source electrode is connected to the second base island.

[0020] In some embodiments, the double-sided substrate includes a first conductive layer, a first insulating layer, a metal layer, a second insulating layer, and a second conductive layer stacked in sequence;

[0021] Wherein, the surface of the first conductive layer away from the first insulating layer serves as the back surface of the double-sided substrate, and the surface of the second conductive layer away from the second insulating layer serves as the front surface of the double-sided substrate.

[0022] According to some embodiments, on the other hand, the present application also provides an electronic device, including the chip packaging structure provided in the foregoing some embodiments.

[0023] The chip packaging structure and the electronic device provided in the embodiments of the present application may / at least have the following advantages:

[0024] In the embodiments of the present application, the first power chip, the double-sided substrate, and the second power chip are sequentially stacked on the carrier board. Compared with the packaging method of multi-chip stacking in the same direction in the related art, in the present application, by making the back surface of the first power chip contact the back surface of the double-sided substrate, and the back surface of the second power chip contact the front surface of the double-sided substrate, the occupied space of the chip packaging structure is reduced, and the storage capacity is doubled. There is an interconnecting circuit between the two lead-out ends of the double-sided substrate, which can be used to realize the interconnection between the subsequent first power chip and the second power chip. In this way, it is beneficial to reduce the length of the lead-out wires required for electrical connection, improve the signal transmission speed, and reduce interference. In addition, in the embodiments of the present application, it is not necessary to use solder balls to connect multiple chips, so the manufacturing process is also simplified, which is beneficial to reducing the production cost.

[0025] Moreover, the edge of the double-sided substrate is exposed so that the first drain of the first power chip can be led out through the exposed edge of the double-sided substrate and connected to the carrier board, the first gate is connected to the first lead-out end of the double-sided substrate to lead out the first gate, the first source is connected to the carrier board, and it is also convenient for the second drain to be led out through the exposed edge of the double-sided substrate and connected to the carrier board, and the second gate is connected to the second lead-out end of the double-sided substrate to lead out the second gate. Compared with the packaging method in the related art where the lead-out ends do not extend outwards, in the present application, the carrier board can be used to electrically lead out the first power chip and the second power chip, which not only improves the solderability of the chip packaging structure, but also makes the first power chip and the second power chip work more stably with better effects. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the following will briefly introduce the drawings required for use in the description of the embodiments or the prior art. Obviously, the following drawings are only some embodiments of the present application. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0027] Figure 1 is a schematic side view structure diagram of the chip packaging structure provided in some embodiments of the present application;

[0028] Figure 2 is Figure 1 a schematic top view structure diagram of the shown structure;

[0029] Figure 3 is Figure 1 a schematic three - dimensional structure diagram of the structure shown;

[0030] Figure 4 In (a) of [], it is a schematic three - dimensional structure diagram when the chip packaging structure provided by some other embodiments of the present application is facing upwards; Figure 4 In (b) of [], it is Figure 4 a schematic three - dimensional structure diagram when the structure shown in (a) of [] is facing downwards;

[0031] Figure 5 is a schematic circuit diagram of the chip packaging structure provided in some embodiments of the present application.

[0032] Explanation of reference numerals:

[0033] 100a, the first power chip; 100b, the second power chip; 200, double - sided substrate; 300, carrier board; 400, driving chip; 500, lead wire; 600, sealing layer;

[0034] Ga, the first gate; Da, the first drain; Sa, the first source;

[0035] Gb, the second gate; Db, the second drain; Sb, the second source;

[0036] GND, the first base island; VS, the second base island; P, the third base island; VB, the fourth base island;

[0037] LO, the first driving signal output terminal; HO, the second driving signal output terminal. Detailed implementation manners

[0038] To facilitate the understanding of the present application, the present application will be described more comprehensively below with reference to the relevant attached drawings. The preferred embodiments of the present application are given in the drawings. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, these embodiments are provided to make the disclosure of the present application more thorough and comprehensive.

[0039] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those of ordinary skill in the technical field to which the present application belongs. The terms used in the specification of the present application herein are only for the purpose of describing specific embodiments and are not intended to limit the present application.

[0040] It should be understood that when an element or layer is referred to as "on" or "connected to" another element or layer, it can be directly on or connected to the other element or layer, or there may be intervening elements or layers. It should be understood that although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, doping types, and / or portions, these elements, components, regions, layers, doping types, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, doping type, or portion from another element, component, region, layer, doping type, or portion. Thus, without departing from the teachings of the present application, the first element, component, region, layer, doping type, or portion discussed below may be referred to as the second element, component, region, layer, or portion; for example, the first base island may be referred to as the second base island, and similarly, the second base island may be referred to as the first base island; the first base island and the second base island are different base islands.

[0041] Spatial relationship terms such as "on" can be used herein to describe the relationship of one element or feature shown in the figures to other elements or features. It should be understood that in addition to the orientations shown in the figures, spatial relationship terms also include different orientations of the device in use and operation. For example, if the device in the figures is flipped, an element or feature described as "on" will be oriented "under" other elements or features. Thus, the exemplary term "on" can include both upper and lower orientations. In addition, the device may also include additional orientations (such as rotating 90 degrees or other orientations), and the spatial descriptors used herein are accordingly interpreted.

[0042] As used herein, the singular forms "a", "an", and "the" may also include the plural forms unless the context clearly dictates otherwise. It should also be understood that when the terms "comprise" and / or "include" are used in this specification, the presence of the stated features, integers, steps, operations, elements, and / or components can be determined, but one or more other features, integers, steps, operations, elements, components, and / or groups are not excluded from being present or added. At the same time, as used herein, the term "and / or" includes any and all combinations of the related listed items.

[0043] Currently, the market demand for package size is getting smaller and smaller, and the existing chip integration packaging solutions are gradually unable to meet the market's demand for small size. Therefore, this is an urgent problem to be solved currently.

[0044] Based on this, the present application provides a chip packaging structure and an electronic device, which can reduce the occupied space of the chip packaging structure and achieve a doubling of the storage capacity. The detailed content will be elaborated in the subsequent embodiments.

[0045] According to some embodiments, the present application provides a chip packaging structure.

[0046] Please refer toFigure 1 In some embodiments, the chip packaging structure may include a carrier substrate 300, and a first power chip 100a, a double-sided substrate 200, and a second power chip 100b stacked in sequence on the carrier substrate 300. Among them, there are gaps between the orthographic projections of the first power chip 100a and the second power chip 100b on the double-sided substrate 200 and the edges of the double-sided substrate 200, thereby exposing the edges of the double-sided substrate 200.

[0047] In the chip packaging structure provided in the above embodiments, the first power chip 100a, the double-sided substrate 200, and the second power chip 100b are stacked in sequence on the carrier substrate 300. Among them, the first power chip 100a is flip-chip mounted on the back surface of the double-sided substrate 200; that is, the back surface of the first power chip 100a is in contact with the back surface of the double-sided substrate 200. The second power chip 100b is disposed on the front surface of the double-sided substrate 200; that is, the back surface of the second power chip 100b is in contact with the front surface of the double-sided substrate 200. Compared with the packaging method of multi-chip stacking in the same direction in the related art, the stacking method adopted by the above chip packaging structure can reduce the occupied space of the chip packaging structure and double the storage capacity.

[0048] The first power chip 100a is flip-chip mounted on the back surface of the double-sided substrate 200. As an example, the first power chip 100a may include a first gate Ga, a first drain Da, and a first source Sa. Among them, the first gate Ga is connected to the first lead-out end of the double-sided substrate 200, the first drain Da is connected to the carrier substrate 300 through the exposed edge of the double-sided substrate 200, and the first source Sa is connected to the carrier substrate 300. The second power chip 100b is disposed on the front surface of the double-sided substrate 200 and includes a second gate Gb and a second drain Db. Among them, the second gate Gb is connected to the second lead-out end of the double-sided substrate 200, and the second drain Db is connected to the carrier substrate 300 through the exposed edge of the double-sided substrate 200.

[0049] In the above chip packaging structure, a connection circuit may also be provided in the double-sided substrate 200; both ends of the connection circuit are correspondingly connected to the first lead-out end and the second lead-out end of the double-sided substrate 200.

[0050] The chip packaging structure provided by the above embodiments exposes the edges of the double-sided substrate 200, so that the first drain Da of the first power chip 100a can be led out through the exposed edges of the double-sided substrate 200 and connected to the carrier board 300. The first gate Ga is connected to the first lead-out end of the double-sided substrate 200 to lead out the first gate Ga, and the first source Sa is connected to the carrier board 300. And it is also convenient for the second drain Db to be led out through the exposed edges of the double-sided substrate 200 and connected to the carrier board 300. The second gate Gb is connected to the second lead-out end of the double-sided substrate 200 to lead out the second gate Gb. Compared with the packaging method in the related art where the lead-out ends do not extend outwards, the above chip packaging structure can electrically lead out the first power chip 100a and the second power chip 100b through the carrier board 300, improving the solderability of the chip packaging structure, and can also make the first power chip 100a and the second power chip 100b work more stably with better effects.

[0051] It can be understood that, as Figure 1 shown, the connection between the two described in the embodiments of the present application includes but is not limited to the electrical connection between the two through the lead wire 500. There is an interconnecting circuit between the two lead-out ends of the double-sided substrate 200 in the above chip packaging structure, which is used to realize the interconnection between the subsequent first power chip 100a and the second power chip 100b. This is beneficial to reducing the length of the lead wire 500 required for electrical connection, thereby improving the signal transmission speed and reducing interference; and there is no need to use solder balls to connect multiple chips, so the manufacturing process is also simplified, which is beneficial to reducing production costs.

[0052] As an example, the first power chip 100a and the second power chip 100b may include semiconductor chips (also called power MOS chips) installed with power MOSFETs. However, in actual embodiments, the types of the first power chip 100a and the second power chip 100b are not limited thereto.

[0053] Please continue to refer to Figure 1 , in some embodiments, the first power chip 100a and the second power chip 100b may be arranged in a mirror symmetry with respect to the double-sided substrate 200. However, in actual embodiments, the relative positional relationship between the first power chip 100a, the second power chip 100b and the double-sided substrate 200 is not limited thereto.

[0054] Please refer to Figure 2 and Figure 3 , in some embodiments, the carrier board 300 may include a first base island GND, a second base island VS and a third base island P which are arranged at intervals.

[0055] Among them, the first source electrode Sa is connected to the first base island GND, the first drain electrode Da can be connected to the second base island VS via the exposed edge of the double-sided substrate 200, and the second drain electrode Db is connected to the third base island P via the exposed edge of the double-sided substrate 200.

[0056] As an example, the first source electrode Sa can be connected to the ground voltage via the first base island GND, the first drain electrode Da can be connected to the switching voltage via the second base island VS, and the second drain electrode Db can be connected to another switching voltage via the third base island P.

[0057] In some embodiments, the second power chip 100b may further include a second source electrode Sb. Exemplarily, the second source electrode Sb can be connected to the second base island VS.

[0058] In the above chip packaging structure, the second source electrode Sb of the second power chip 100b and the first drain electrode Da of the first power chip 100a are connected to the same base island, that is, the second base island VS, reducing the complexity of the chip packaging structure and being beneficial to improving the electrical performance of the chip packaging structure.

[0059] Please continue to refer to Figure 1 , in some embodiments, one side surface of the first power chip 100a is attached to the first base island GND so that the first source electrode Sa is connected to the first base island GND.

[0060] As an example, a conductive adhesive can be used to attach one side surface of the first power chip 100a to the first base island GND.

[0061] The conductive adhesive has the function of fixing the relative positions of the first power chip 100a and the first base island GND. At the same time, it can also fill the gap between the first power chip 100a and the first base island GND, making the connection between the first power chip 100a and the first base island GND have better sealing performance, which is beneficial to improving the use reliability of the chip packaging structure.

[0062] It should be noted that the conductive adhesive is a special binder that has both viscosity and conductivity after curing. For example, the conductive adhesive may include a matrix and conductive fillers. Among them, the matrix includes epoxy resin, acrylate resin or polyurethane; the conductive fillers include carbon and metal powders, and the metal powders may include copper, silver, nickel or gold, etc.

[0063] In some embodiments, vias can be formed in the exposed edge of the double-sided substrate 200.

[0064] The above chip packaging structure may further include a first drain lead wire passing through the via. In this way, the first drain electrode Da can be connected to the second base island VS via the first drain lead wire.

[0065] Please refer to Figure 2 and Figure 3 In some embodiments, the chip package structure may further include a driving chip 400. The driving chip 400 may include a first driving signal output terminal LO and a second driving signal output terminal HO.

[0066] In the above chip package structure, the first gate Ga may be led out via a first lead-out terminal and connected to the first driving signal output terminal LO, and the second gate Gb may be led out via a second lead-out terminal and connected to the second driving signal output terminal HO.

[0067] As an example, the first driving signal output terminal LO may be a low-voltage output signal, and the second driving signal output terminal HO may be a high-voltage output signal.

[0068] As an example, as Figure 2 and Figure 3 shown, the driving chip 400 may have a connected first side and a second side.

[0069] In some embodiments, the first base island GND may be disposed beside the first side, the third base island P may be disposed beside the second side, and the second base island VS may be disposed beside the first base island GND and the third base island P, and at least close to at least one side of the first base island GND and at least one side of the third base island P.

[0070] In the chip package structure provided in the above embodiments, the first base island GND, the second base island VS, and the third base island P are arranged to be closely arranged around the driving chip 400, which is beneficial to further reducing the occupied space of the chip package structure.

[0071] In some embodiments, the double-sided substrate 200 may include a first conductive layer, a first insulating layer, a metal layer, a second insulating layer, and a second conductive layer stacked in sequence.

[0072] It should be noted that the surface of the first conductive layer away from the first insulating layer serves as the back surface of the double-sided substrate 200, and the surface of the second conductive layer away from the second insulating layer serves as the front surface of the double-sided substrate 200.

[0073] As an example, the material of the metal layer may include but is not limited to aluminum (Al). Using aluminum as the constituent material of the metal layer can make the double-sided substrate 200 have good thermal conductivity, which is beneficial to reducing the working temperature of the chip package structure, extending the service life, and improving the use reliability of the chip package structure.

[0074] As an example, as Figure 4 in the figure (a) and Figure 4As shown in Figure (b), the chip packaging structure may further include a sealing layer 600 located on one side of the carrier board 300 for sealing the first power chip 100a, the double-sided substrate 200, the second power chip 100b, and the driving chip 400. The back surface of the carrier board 300 may be exposed for external connection. For example, the pins of the carrier board 300 may be extended. In this way, it is beneficial to further improve the solderability of the chip packaging structure.

[0075] Exemplarily, please refer to Figure 5 for understanding. The carrier board 300 may include 22 pins. Pin 1 is defined as the VCC pin, pin 2 is defined as the HIN pin, pin 3 is defined as the LIN pin, pin 4 is defined as the FO pin, pin 5 is defined as the OCP pin, and pin 6 is defined as the COM pin. Pins 7 to 9 are connected together to form the third base island P. Pins 10 to 13 are connected together to form the second base island VS. Pins 14 to 19 are connected together to form the first base island GND. Pins 20 to 22 are connected together to form the fourth base island VB. The remaining pins exist independently and are not connected to each other.

[0076] As an example, the first base island GND may be connected to the ground voltage, the second base island VS may be connected to the switching voltage, the third base island P may be connected to another switching voltage, and the fourth base island VB may be connected to the power supply voltage.

[0077] The chip packaging structure in the embodiments of the present application may include, but is not limited to, a Quad Flat Non-leaded Package (QFN). Exemplarily, it may be manufactured in a size of 5×6 mm 2 .

[0078] According to some embodiments, on the other hand, the present application further provides an electronic device including the chip packaging structure provided in the foregoing some embodiments. The technical effects that can be achieved by the foregoing chip packaging structure can also be achieved by this electronic device, which will not be elaborated here.

[0079] In some embodiments, the chip packaging structure may include an Intelligent Power Module (IPM module for short). The IPM module is a highly integrated module that integrates multiple power chips, control circuits, and protection functions. It can be used in power electronic systems to provide various advantages and functions. The first power chip and the second power chip in the IPM module can be, for example, Insulated Gate Bipolar Transistors (IGBTs for short), Metal-Oxide-Semiconductor Field-Effect Transistors (MOSFETs for short), etc., but are not limited thereto. In addition, the IPM module can also integrate a drive circuit, protection functions (such as overcurrent and overtemperature protection), control circuits, and other related circuits in a chip packaging structure, making it highly compatible and easier to integrate and use in electronic systems. As an example, the IPM module can be used to provide power conversion and control functions in a half-bridge drive circuit and is widely used to drive various power devices. In addition, the IPM module can also be used to provide power conversion and control in a full-bridge drive circuit, which helps to make the full-bridge drive circuit more reliable and flexible in driving three-phase loads.

[0080] As an example, in an electronic device, an IPM module can be adopted to implement functions such as integrated undervoltage protection and / or temperature monitoring.

[0081] It should be noted that the electronic device in the embodiments of the present application includes the chip packaging structure provided in the foregoing embodiments. Therefore, the technical features between the structural embodiments and the device embodiments can be mutually replaced and supplemented without conflict, so that those skilled in the art can learn the technical content of the present application.

[0082] The technical features of the above-described embodiments can be combined arbitrarily. For the sake of brevity of description, not all possible combinations of the technical features of the above-described embodiments are described. However, as long as these combinations of technical features do not conflict, they should be considered as within the scope described in this specification.

[0083] The above-described embodiments only represent several implementation manners of the present application. Their descriptions are relatively specific and detailed, but they should not be construed as limiting the scope of the patent application. It should be pointed out that for those of ordinary skill in the art, without departing from the concept of the present application, several modifications and improvements can still be made, and these all belong to the protection scope of the present application. Therefore, the protection scope of the patent of the present application should be subject to the appended claims.

Claims

1. A chip packaging structure, characterized in that, It includes a carrier substrate, and a first power chip, a double-sided substrate, and a second power chip stacked in sequence on the carrier substrate; there are spacings between the orthographic projections of the first power chip and the second power chip on the double-sided substrate and the edges of the double-sided substrate. The back surface of the first power chip is in contact with the back surface of the double-sided substrate, and includes a first gate, a first drain, and a first source. The first gate is connected to the first lead-out end of the double-sided substrate, the first drain is connected to the carrier substrate via the exposed edge of the double-sided substrate, and the first source is connected to the carrier substrate. The back surface of the second power chip is in contact with the front surface of the double-sided substrate, and includes a second gate and a second drain; the second gate is connected to the second lead-out end of the double-sided substrate, and the second drain is connected to the carrier substrate via the exposed edge of the double-sided substrate. Wherein, a connection circuit is provided in the double-sided substrate; both ends of the connection circuit are correspondingly connected to the first lead-out end and the second lead-out end respectively.

2. The chip packaging structure according to claim 1, wherein The carrier substrate includes a first base island, a second base island, and a third base island arranged at intervals. Wherein, the first source is connected to the first base island, the first drain is connected to the second base island via the exposed edge of the double-sided substrate, and the second drain is connected to the third base island via the exposed edge of the double-sided substrate.

3. The chip packaging structure according to claim 2, wherein The first power chip and the second power chip are arranged in mirror symmetry with respect to the double-sided substrate.

4. The chip packaging structure according to claim 3, wherein Via holes are provided in the exposed edges of the double-sided substrate. The chip packaging structure further includes a first drain lead-out wire passing through the via hole; the first drain is connected to the second base island via the first drain lead-out wire.

5. The chip packaging structure according to claim 2, characterized in that, It further includes a driving chip; the driving chip includes a first driving signal output end and a second driving signal output end. Wherein, the first gate is led out via the first lead-out end and connected to the first driving signal output end, and the second gate is led out via the second lead-out end and connected to the second driving signal output end.

6. The chip packaging structure according to claim 5, characterized in that, The driving chip has a connected first side and a second side. The first base island is arranged beside the first side, and the third base island is arranged beside the second side; the second base island is arranged beside the first base island and the third base island, and at least close to at least one side of the first base island and at least one side of the third base island.

7. The chip packaging structure according to claim 2, wherein One side surface of the first power chip is attached to the first base island, so that the first source is connected to the first base island.

8. The chip packaging structure according to claim 2, wherein, The second power chip further includes a second source; the second source is connected to the second base island.

9. The chip packaging structure according to claim 1, characterized in that, The double-sided substrate includes a first conductive layer, a first insulating layer, a metal layer, a second insulating layer, and a second conductive layer stacked in sequence. Wherein, the surface of the first conductive layer away from the first insulating layer serves as the back surface of the double-sided substrate, and the surface of the second conductive layer away from the second insulating layer serves as the front surface of the double-sided substrate.

10. An electronic device, characterized in that, It includes: The chip packaging structure according to any one of claims 1 to 9.

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