Semiconductor structure including light-emitting element and manufacturing method thereof

Abstract

A semiconductor structure including a light-emitting device includes a substrate on which a display region and a bonding pad region are defined, a circuit layer formed on the substrate and located in the display region and the bonding pad region, a plurality of contact posts formed on the substrate, and a plurality of light-emitting elements disposed on the circuit layer. The circuit layer is located in the display area and the bonding pad area and electrically connected with the circuit layer, a plurality of contact columns in the display area are arranged in an array, and a plurality of light-emitting elements are located in the display area and electrically connected with the contact columns.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor manufacturing processes, and more particularly to a semiconductor structure integrating a display area and a connection pad area. Background Art

[0002] In semiconductor manufacturing processes, after electronic components and multiple circuit layers are formed on a substrate, a redistribution layer or bonding pads are often formed on the top of the stacked circuit layers to transfer these electronic components to other larger-sized pins and connect to other electronic components or voltage sources.

[0003] With the progress of semiconductor manufacturing processes, the sizes of various components are getting smaller and smaller, and more components need to be accommodated in a limited space. Therefore, structures that integrate multiple circuit areas with different functions on the same substrate have gradually been developed. Summary of the Invention

[0004] The present invention provides a semiconductor structure including light-emitting elements, comprising a substrate, on which a display area and a bonding pad area are defined, a circuit layer formed on the substrate and located in the display area and the bonding pad area, a plurality of contact posts located in the display area and the bonding pad area and electrically connected to the circuit layer, wherein the plurality of contact posts in the display area are arranged in an array, and a plurality of light-emitting elements located in the display area and electrically connected to the contact posts.

[0005] The present invention further provides a method for forming a semiconductor structure including light-emitting elements, comprising providing a substrate, on which a display area and a bonding pad area are defined, forming a circuit layer on the substrate and located in the display area and the bonding pad area, forming a plurality of contact posts located in the display area and the bonding pad area and electrically connected to the circuit layer, wherein the plurality of contact posts in the display area are arranged in an array, and forming a plurality of light-emitting elements located in the display area and electrically connected to the contact posts.

[0006] The feature of the present invention is that in order to reduce the waste of component space, the display area and the bonding pad area are integrated on the same substrate structure. Contact posts and bonding pads arranged in an array are formed in the dielectric layer near the top surface of the display area to correspond to the pixels (light-emitting elements) formed in the display area subsequently. The present invention can fabricate a high-precision pixel array, and the dielectric layer on the surface of the display area also has a flat surface, improving the display effect of the display area and the yield of the product. Description of the Drawings

[0007] To make this article easier to understand, the accompanying drawings and their detailed written descriptions can be referred to simultaneously when reading the present invention. Through the specific embodiments in this article and with reference to the corresponding accompanying drawings, the specific embodiments of the present invention will be explained in detail to expound the principle of action of the specific embodiments of the present invention. In addition, for clarity, the features in the accompanying drawings may not be drawn to actual scale, so the dimensions of some features in certain accompanying drawings may be deliberately enlarged or reduced.

[0008] Figure 1 Top view schematic diagram of the bonding pad region of the semiconductor structure according to an embodiment of the present invention;

[0009] Figure 2 Cross-sectional structure schematic diagram near the top surface of the bonding pad region of the semiconductor structure according to an embodiment of the present invention;

[0010] Figure 3 Top view schematic diagram of the display region and the bonding pad region of the semiconductor structure according to another embodiment of the present invention;

[0011] Figure 4 Cross-sectional structure schematic diagram near the top surface of the display region and the bonding pad region of the semiconductor structure according to another embodiment of the present invention.

[0012] Description of main component symbols

[0013] 10: Underlayer

[0014] 12: Dielectric layer

[0015] 12A: Dielectric layer

[0016] 12B: Dielectric layer

[0017] 14: Underlayer

[0018] 16: Underlayer

[0019] 18: Dielectric layer

[0020] 20: Dielectric layer

[0021] 22: Opening

[0022] 30: Underlayer

[0023] 32: Underlayer

[0024] 34: Top underlayer

[0025] 36: Passivation layer

[0026] 40: Light-emitting element

[0027] 42: Opening

[0028] IMD: Inter-metal dielectric layer

[0029] LM: Circuit layer

[0030] P: Bonding pad

[0031] PA: Bonding pad (first bonding pad)

[0032] PB: Bonding pad (second bonding pad)

[0033] R1: Component area

[0034] R2: Bonding pad area

[0035] R3: Display area

[0036] Sub: Substrate

[0037] S1: Pitch

[0038] S2: Distance

[0039] Via: Contact post Detailed implementation manners

[0040] To enable those of ordinary skill in the art to which the present invention pertains to further understand the present invention, the following specifically enumerate the preferred embodiments of the present invention and, in conjunction with the accompanying drawings, elaborate in detail on the composition and the intended effects of the present invention.

[0041] For the convenience of description, the accompanying drawings of the present invention are only schematic for easier understanding of the present invention, and their detailed proportions can be adjusted according to the design requirements. Regarding the up-and-down relationship of the relative components in the figures described in the text, those skilled in the art should understand that it refers to the relative positions of the objects, so they can all be flipped to present the same components, and this should all fall within the scope disclosed in this specification. First, this is hereby stated.

[0042] Although the present invention uses terms such as first, second, third, etc. to describe elements, components, regions, layers, and / or sections, it should be understood that these elements, components, regions, layers, and / or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, and / or section from another element, component, region, layer, and / or section, and they do not inherently imply or represent any previous ordinal number of the element, nor do they represent the arrangement order of one element and another element or the order in the manufacturing method. Therefore, without departing from the scope of the specific embodiments of the present invention, the first element, component, region, layer, or section discussed below can also be referred to by the term of the second element, component, region, layer, or section.

[0043] As used herein, the terms "about" or "substantially" generally mean within 20% of a given value or range, such as within 10%, or within 5%, or within 3%, or within 2%, or within 1%, or within 0.5%. It should be noted that the quantities provided in the specification are approximate quantities, that is, the meaning of "about" or "substantially" may still be implied even without specific mention of "about" or "substantially".

[0044] As used herein, the terms "coupled", "coupling", and "electrically connected" include any direct and indirect means of electrical connection. For example, if it is described in the text that the first component is coupled to the second component, it means that the first component can be directly electrically connected to the second component, or indirectly electrically connected to the second component through other devices or connection means.

[0045] Although the following describes the invention of the present invention through specific embodiments, the inventive principles of the present invention can also be applied to other embodiments. In addition, in order not to obscure the spirit of the present invention, specific details will be omitted, and the omitted details are within the knowledge scope of those of ordinary skill in the art.

[0046] Please refer to Figure 1 and Figure 2 , Figure 1 , a top view schematic diagram of the element region and the bonding pad region of a semiconductor structure showing an embodiment of the present invention, Figure 2 , a cross-sectional structure schematic diagram near the top surface of the element region and the bonding pad region of a semiconductor structure showing an embodiment of the present invention. According to an embodiment of the present invention, first, a substrate Sub is provided, and an element region R1 and a bonding pad region R2 are defined on the substrate Sub. A plurality of electronic components and circuit layers are formed within the ranges of the element region R1 and the bonding pad region R2. Here, the electronic components such as transistors, capacitors, inductors, resistors, memories, power amplifiers, or other logic circuits, etc., are located in single or multiple dielectric layers, and the present invention is not limited thereto. Then, a circuit layer is formed above the electronic components. The function of the circuit layer is to electrically connect the electronic components to other layers above, and then electrically connect to other electronic components or a voltage source, etc. through conductive pads. Usually, the circuit layer is a multi-layer stacked structure, including a horizontally extended conductive layer (commonly referred to as a metallayer) and a vertical contact pillar (commonly referred to as a Via). Other related technologies regarding electronic components and circuit layers belong to the prior art in this field and will not be elaborated herein.

[0047] After the multi-layer circuit layer is formed, usually a bonding pad is further formed on the top of the circuit layer. The function of the bonding pad is to provide a relatively large-sized pin for connecting other electronic components. As Figure 1 and Figure 2As shown, within the component region R1 and the bonding pad region R2, the conductive layer LM represents the second-to-last conductive layer among these multi-layer circuit layers (i.e., the topmost horizontal conductive layer among the multi-layer circuit layers), and the conductive layer LM is located within a metal interlayer dielectric IMD. The material of the metal interlayer dielectric IMD is, for example, silicon oxide, but is not limited thereto. The material of the conductive layer LM is, for example, a metal with good conductivity, such as tungsten, cobalt, copper, aluminum, gold, silver, etc., but is not limited thereto. There may also be a liner layer 10 outside the conductive layer LM. The material of the liner layer 10 is, for example, titanium / titanium nitride, and its function is to enhance the adhesion between the conductive layer LM and the metal interlayer dielectric IMD, enabling the conductive layer LM to be better formed within the metal interlayer dielectric IMD.

[0048] Below the conductive layer LM, there are also the above-mentioned multi-layer circuit layers and electronic components, etc. For the sake of simplicity of the drawings, these underlying circuit layers and electronic components are not shown here. Then, in order to connect these electronic components and circuit layers to other external electronic components, the circuit layers are concentrated in the bonding pad region R2, and then bonding pads P are formed within the bonding pad region R2. The bonding pad P is located within the dielectric layer 12. The dielectric layer 12 may be a single-layer or multi-layer structure. In this embodiment, a multi-layer structure is taken as an example, which includes a stacked structure of a dielectric layer 12A and a dielectric layer 12B. The material of the dielectric layer 12A is, for example, silicon nitride, and the material of the dielectric layer 12B is, for example, silicon oxide, but the present invention is not limited thereto. The bonding pad P is made of metal, such as the above-mentioned tungsten, cobalt, copper, aluminum, gold, silver, etc. In this embodiment, aluminum is taken as an example, but is not limited thereto. There may also be a liner layer 14 outside the bonding pad P. The material of the liner layer 14 may also be titanium / titanium nitride, etc., but is not limited thereto.

[0049] From the cross-sectional view structure, the above-mentioned bonding pad P is located within a groove of the dielectric layer 12, and the bonding pad P is higher than the top surface of the groove and is located above the dielectric layer 12. In the manufacturing process, a groove can be first formed in the dielectric layer 12 to expose the underlying circuit layer, and then the liner layer 14 and the bonding pad material layer (such as an aluminum layer) are formed within the groove of the dielectric layer 12. The liner layer 14 and the bonding pad P fill the groove and are located on the dielectric layer 12. Then, through a patterning step, a part of the liner layer 14 and the bonding pad material layer located on the dielectric layer 12 is removed, and the remaining bonding pad material layer is Figure 2The bonding pad P shown. Additionally, there may be another buffer layer 16, dielectric layer 18, and dielectric layer 20 above the bonding pad P. The material of the buffer layer 16 may be titanium / titanium nitride, the material of the dielectric layer 18 is, for example, phosphosilicate glass (PSG), and the material of the dielectric layer 20 is, for example, silicon nitride, but the above materials are not limited thereto. In this embodiment, the thickness of the bonding pad P above the dielectric layer 12 is about 8000 angstroms, the thickness of the dielectric layer 18 is about 4000 angstroms, and the thickness of the dielectric layer 20 is about 5000 angstroms, but the present invention is not limited thereto.

[0050] Next, openings 22 are formed in the dielectric layer 20 and the dielectric layer 18, where the openings 22 expose the bonding pad P. The function of the openings 22 is to serve as the location for subsequent connection of the bonding pad P to other electronic components or voltage sources. That is to say, other electronic components or voltage sources can be connected to the bonding pad P through the openings 22 and further connected to the underlying circuit layer and electronic components.

[0051] It should be noted that in this embodiment, although circuit layers are formed in both the component region R1 and the bonding pad region R2, and multiple electronic components are formed in the component region R1, these electronic components and the circuit layer converge into the bonding pad region R2 in the upper half of the multilayer structure and are electrically connected to external electronic components through the bonding pad P in the bonding pad region R2. In other words, from a top view ( Figure 1 ), although circuit layers and electronic components (not shown in the figure) are formed in both the component region R1 and the bonding pad region R2, only the bonding pad region R2 contains the exposed bonding pad P for connecting other external electronic components.

[0052] Therefore, in Figure 1 and Figure 2 In the illustrated embodiment, the surface of the component region R1 is covered by the dielectric layer 18 and the dielectric layer 20 without forming other components, constituting a blank area. With the progress of semiconductor manufacturing processes, more and more components are integrated on the same substrate, and manufacturers also hope to utilize the blank areas of the components, such as forming various components in the blank areas to reduce the waste of component space. For example, in currently developing virtual reality (VR) and augmented reality (AR) technologies, in wearable devices such as VR glasses or AR glasses, the circuit layer and the display device may be fabricated on the same substrate. In this development trend, Figure 1 The component region R1 can be considered to form light-emitting components to achieve a display effect.

[0053] However, if directly Figure 1 and Figure 2Forming various light-emitting elements on the surface of the element region R1 in the shown structure by means of mass transfer and the like will face several problems. First, the surface of the element region R1 is not flat enough. The reason is that when forming elements such as the bonding pad P in the bonding pad region R2, since the element region R1 is a large empty area relative to the bonding pad region R2, during the planarization step (such as chemical mechanical polishing), it is easy to generate a dishing phenomenon on the surface of the dielectric layer 20, resulting in insufficient flatness of the dielectric layer 20 on the surface of the finally formed element region R1. If no other elements (such as light-emitting elements) are formed on the surface of the element region R1, the dented situation on the surface of the element region R1 does not affect the electrical properties of the semiconductor structure. However, if light-emitting elements need to be formed on the surface of the element region R1, the dented situation on the surface of the element region R1 becomes a problem to be solved.

[0054] Another problem is that since the function of the bonding pad P is to transfer a circuit layer with a smaller size to the pins of other electronic components with a larger size, the size of the bonding pad P needs to match the pin size of the electronic component and cannot be designed too small. In the current manufacturing process, the material layer (aluminum layer) of the bonding pad P is directly filled into the groove of the dielectric layer 12, which also leads to a relatively thick thickness of the bonding pad P (about 8000 angstroms). If a circuit layer connecting the light-emitting elements is to be formed in the element region R1 during the manufacturing process of forming the bonding pad P, the thickness of the circuit layer in the element region R1 will also be relatively thick. However, an overly large thickness of the circuit layer will also cause the aspect ratio of each element to become larger, so it is also easy to cause the problem of insufficient material gap filling. If the pitch and size of the elements are increased to solve the material gap filling problem, the problem of insufficient accuracy of the circuit layer will be faced.

[0055] To solve the above problems and fabricate a structure integrating light-emitting elements and a circuit layer, the present invention proposes another embodiment. Figure 3 A top view schematic diagram of the display region and the bonding pad region of a semiconductor structure according to another embodiment of the present invention is shown. Figure 4 A cross-sectional structure schematic diagram near the top surface of the display region and the bonding pad region of a semiconductor structure according to another embodiment of the present invention is shown. As Figure 3 And Figure 4 shown, in this embodiment, an element region R1 and a bonding pad region R2 are also defined on the substrate Sub. Among them, the element region R1 is a region where a plurality of electronic components are formed, and these electronic components are integrated into the bonding pad region R2 through a circuit layer and are connected to other external electronic components or a voltage source through the bonding pad P. Here, the definitions of the element region R1 and the bonding pad region R2 are the same as those in the above-mentioned first embodiment ( Figure 1 And Figure 2 the embodiment shown), and will not be elaborated here.

[0056] It should be noted that in this embodiment, a plurality of light-emitting elements 40 are formed on the surface of the element region R1. These light-emitting elements 40 are arranged in an array and can be combined into a plurality of pixels to achieve the effect of a display screen. Since the element region R1 in this embodiment has the function of a display screen, the element region R1 can also be defined as the display region R3, and the two have the same range.

[0057] As described above, to form high-quality light-emitting elements in the display region R3, it is necessary to form a flat dielectric layer surface in the element region R1 (i.e., the display region R3), and to form a circuit layer with a sufficiently high precision in the dielectric layer under the light-emitting elements in the display region R3. As Figure 4 shown, in this embodiment, the display region R3 and the bonding pad region R2 also include a conductive layer LM in the metal interlayer dielectric IMD, and a dielectric layer 12A and a dielectric layer 12B are stacked above the metal interlayer dielectric IMD. These elements are the same as those described in the above first embodiment and will not be repeated here.

[0058] Next, contact vias Via are formed on the top of the metal interlayer dielectric IMD, and each contact via Via is located in the display region R3 and the bonding pad region R2. A liner layer 30 may be included outside the contact via Via. In this embodiment, the material of the contact via Via is, for example, tungsten, and the material of the liner layer 30 is, for example, titanium / titanium nitride, but it is not limited thereto. The difference between this embodiment and the above embodiment is that the contact via Via is located in the dielectric layer 12A and the dielectric layer 12B, and the top surface of the contact via Via is flush with the top surface of the dielectric layer 12B. In the above embodiment, the bonding pad P is not only located in the grooves of the dielectric layer 12A and the dielectric layer 12B, but also on a part of the dielectric layer 12B. In this embodiment, after filling a metal layer such as tungsten into the grooves of the dielectric layer 12, the excess tungsten metal is ground away by chemical mechanical polishing or the like to form the contact via Via. Therefore, the contact via Via is fabricated separately from the other upper circuit layers. In this way, since the height of the contact via Via is small, the size of the contact via Via can also be made smaller. In other words, a contact via Via with higher precision can be fabricated.

[0059] It should be noted that the contact via Via in this embodiment is connected to the conductive layer LM located in the bonding pad region R2 and serves as a structure for electrically connecting to the subsequent bonding pads. The contact vias Via in the display region R3 are arranged in an array and serve as a structure for electrically connecting to the subsequent light-emitting elements. Therefore, compared with the above embodiment, in this embodiment, the contact vias Via are included in the dielectric layer 12A and 12B in the display region R3 (or the element region R1), while there are no other conductive structures in the dielectric layer 12A and 12B in the element region R1 in the above first embodiment.

[0060] Next, a multi-layer conductive material layer is formed over the dielectric layer 12B, and then the excess material layer is removed by a patterning process. The remaining material layer, as shown in Figure 4 , in the display area R3 and the bonding pad area R2, on the dielectric layer 12B, there are a liner layer 32, a bonding pad P, and a top liner layer 34. These material layers are electrically connected to the underlying contact vias Via. The functions of the liner layer 32 and the top liner layer 34 here are to improve the connection quality between the bonding pad P and the contact vias Via and reduce the resistance value of the interface. However, in other embodiments, the liner layer 32 and the top liner layer 34 can be selectively omitted. In this embodiment, the liner layer 32 and the top liner layer 34 include titanium / titanium nitride, and the material of the bonding pad P includes aluminum, but the present invention is not limited thereto. Therefore, in this embodiment, the contact vias Via and the bonding pad P preferably include different materials. For example, the material of the bonding pad P includes aluminum, and the material of the contact vias Via includes tungsten, but the present invention is not limited thereto.

[0061] In addition, for the sake of clear representation, the bonding pads in the display area R3 are defined as bonding pads PA, and the bonding pads P in the connection pad area R2 are defined as bonding pads PB. However, their materials are the same and should be formed by the same process. If the bonding pad P is mentioned hereinafter, it refers to the bonding pad PA or the bonding pad PB. In this embodiment, the thickness of the bonding pad P is less than the thickness of the bonding pad P in the above Figure 2 . The thickness of the bonding pad P in this embodiment is about 1500 angstroms, but it is not limited thereto. In this way, since the thickness of the bonding pad P is relatively thin, the aspect ratio of the gap between adjacent bonding pads PA will not be too high, resulting in the problem that the subsequent material layer cannot completely fill the gap. Taking this embodiment as an example, the gap spacing S1 between adjacent bonding pads PA is about 0.4 micrometers, and the thickness of the bonding pad PA is about 1500 angstroms as described above. Under this aspect ratio, the subsequent formed material layer can fill the gap between the bonding pads PA. In addition, in this embodiment, the bonding pads PA are arranged in an array, for example. The distance from one side of a bonding pad PA to the same side of another adjacent bonding pad PA is defined as S2. Preferably, S2 is about 1.2 to 2.4 micrometers, but it is not limited thereto.

[0062] Subsequently, a passivation layer 36 is further formed to cover the dielectric layer 12B and the bonding pads P. The material of the passivation layer 36 is, for example, silicon oxide, silicon nitride, silicon oxynitride, or phosphosilicate glass. Then, a plurality of light-emitting elements 40 are formed in the display area R3 and electrically connected to the bonding pads PA in the display area R3. The light-emitting elements 40 are, for example, light-emitting diodes or other light-emitting elements, which have different colors (such as red, blue, and green) to form different pixels. The light-emitting elements 40 are arranged in the display area R3 to achieve the display function. In the actual manufacturing process, after the passivation layer 36 is completed, a plurality of openings 42 can be formed on the top surface of the passivation layer 36 by etching or other methods to expose the underlying bonding pads PB. Then, by means of mass transfer or other methods, the light-emitting elements 40 are formed in the openings in the display area R3 and electrically connected to and corresponding to the bonding pads PA in the display area R3. As for the openings 42 in the connection pad area R2, the underlying bonding pads P are also exposed to be used for connecting other electronic components or voltage sources in the future.

[0063] It should be noted that after the above-mentioned passivation layer 36 is formed, a planarization step can be additionally performed to make the surface of the passivation layer 36 flatter. Different from the above-mentioned first embodiment, in this embodiment, since a plurality of bonding pads PA are provided under the passivation layer 36, the positions of the bonding pads PA corresponding to the light-emitting elements 40 may be arranged in an array. In the planarization step, the bonding pads PA arranged in an array under the passivation layer 36 can achieve a supporting effect, avoiding the phenomenon of dishing due to the relatively large area of the passivation layer 36 in the display area R3. In other words, in this embodiment, the bonding pads PA arranged in an array not only have the function of connecting the light-emitting elements 40 but also can make the top surface of the passivation layer 36 flatter, so as to improve the display quality of the display area R3.

[0064] In this embodiment, the bonding pads PB in the connection pad area R2 and the underlying contact vias Via can also be used as the bonding pads P, that is, other electronic components or voltage sources can be connected in the future. Different from the first embodiment, the bonding pads PB in the connection pad area R2 and the underlying contact vias Via in this embodiment are separately manufactured and preferably include different materials, while the bonding pad P in the first embodiment ( Figure 2 ) is an integrally formed structure.

[0065] Based on the above description and drawings, the present invention provides a semiconductor structure including a light-emitting element, comprising a substrate Sub, a display region R3 and a bonding pad region R2 defined on the substrate, a circuit layer LM formed on the substrate Sub and located in the display region R3 and the bonding pad region R2, a plurality of contact posts Via located in the display region R3 and the bonding pad region R2 and electrically connected to the circuit layer LM, wherein the plurality of contact posts Via in the display region R3 are arranged in an array, and a plurality of light-emitting elements 40 located in the display region R3 and electrically connected to the contact posts Via.

[0066] In some embodiments of the present invention, it further includes a plurality of first bonding pads PA located in the display region R3 and between the light-emitting elements 40 and the contact posts Via.

[0067] In some embodiments of the present invention, the first bonding pads PA directly contact the contact posts Via and the light-emitting elements 40.

[0068] In some embodiments of the present invention, the plurality of light-emitting elements 40 are not located in the bonding pad region R2.

[0069] In some embodiments of the present invention, it further includes a second bonding pad PB located in the bonding pad region R2, and the second bonding pad PB is electrically connected to the contact posts Via.

[0070] In some embodiments of the present invention, the top surface of the second bonding pad PB is connected to a signal source (i.e., a voltage source or other electronic components).

[0071] In some embodiments of the present invention, it further includes a passivation layer 36 covering the first bonding pads PA and the second bonding pad PB, and the passivation layer 36 includes a plurality of openings 42. Each opening 42 exposes a part of the first bonding pad PA or the second bonding pad PB, and the light-emitting elements 40 are located in each opening 42 in the display region R1.

[0072] In some embodiments of the present invention, the first bonding pads PA and the second bonding pad PB are also located in the passivation layer 36, and the first bonding pads PA and the second bonding pad PB have the same thickness.

[0073] In some embodiments of the present invention, in the display region R3, each first bonding pad PA corresponds to each contact post Via, and the first bonding pads PA are arranged in an array.

[0074] In some embodiments of the present invention, in the display region, the distance S1 between any two adjacent first bonding pads PA is between 0.3 micrometers and 0.5 micrometers.

[0075] In some embodiments of the present invention, the first bonding pad includes a bottom layer (liner layer 32), an intermediate layer, and a top layer (top liner layer 34). The materials of the bottom layer and the top layer include titanium and titanium nitride, and the material of the intermediate layer includes aluminum.

[0076] In some embodiments of the present invention, the ratio of the area of the display region R3 to the area of the bonding pad region R2 is greater than 20.

[0077] The present invention further provides a method for forming a semiconductor structure including a light-emitting element, which includes providing a substrate Sub, defining a display region R3 and a bonding pad region R2 on the substrate Sub, forming a circuit layer LM on the substrate Sub, and the circuit layer LM is located in the display region R3 and the bonding pad region R2, forming a plurality of contact posts Via, which are located in the display region R3 and the bonding pad region R2 and are electrically connected to the circuit layer LM, wherein the plurality of contact posts vai in the display region R3 are arranged in an array, and forming a plurality of light-emitting elements 40, which are located in the display region R3 and are electrically connected to the contact posts Via.

[0078] In some embodiments of the present invention, it further includes forming a plurality of first bonding pads PA in the display region R3 and located between the light-emitting elements 40 and the contact posts Via.

[0079] In some embodiments of the present invention, in the display region R3, each first bonding pad PA corresponds to each contact post Via, and each first bonding pad PA is arranged in an array.

[0080] In some embodiments of the present invention, the first bonding pad PA directly contacts the contact post Via and the light-emitting element 40.

[0081] In some embodiments of the present invention, it further includes forming a second bonding pad PB in the bonding pad region R2, and the second bonding pad PB is electrically connected to the contact post Via.

[0082] In some embodiments of the present invention, it further includes forming a bonding pad P, performing a patterning step on the bonding pad P to remove a part of the bonding pad P, and the remaining bonding pad P located in the display region R3 is defined as the first bonding pad PA, and the remaining bonding pad P located in the bonding pad region R2 is defined as the second bonding pad PB.

[0083] In some embodiments of the present invention, it further includes forming a passivation layer 36 covering the first bonding pad PA and the second bonding pad PB.

[0084] In some embodiments of the present invention, it further includes performing a planarization step on the passivation layer 36 to make the top surface of the passivation layer 36 a flat surface.

[0085] In summary, the features of the present invention are that, in order to reduce the waste of component space, the display area and the bonding pad area are integrated on the same substrate structure. Contact columns and bonding pads arranged in an array are formed in the dielectric layer near the top surface of the display area to correspond to the pixels (light-emitting elements) formed in the display area subsequently. The present invention can fabricate a high-precision pixel array, and the dielectric layer on the surface of the display area also has a flat surface, improving the display effect of the display area and the yield of the product.

[0086] The above are only the preferred embodiments of the present invention, and all equivalent changes and modifications made according to the claims of the present invention shall fall within the scope covered by the present invention.

Claims

1. A semiconductor structure comprising a light-emitting element, characterized in that, Comprising: A substrate on which a display area and a bonding pad area are defined; A circuit layer formed on the substrate, and the circuit layer is located in the display area and the bonding pad area; A plurality of contact posts located in the display area and the bonding pad area and electrically connecting the circuit layer, wherein the plurality of contact posts in the display area are arranged in an array; and A plurality of light-emitting elements located in the display area and electrically connected to the contact posts.

2. The semiconductor structure comprising a light-emitting element according to claim 1, further comprising a plurality of first bonding pads located in the display area and between the light-emitting element and the contact posts.

3. The semiconductor structure comprising a light-emitting element according to claim 2, wherein the first bonding pad directly contacts the contact post and the light-emitting element.

4. The semiconductor structure comprising a light-emitting element according to claim 1, wherein the plurality of light-emitting elements are not located in the bonding pad area.

5. The semiconductor structure comprising a light-emitting element according to claim 2, further comprising a second bonding pad located in the bonding pad area, and the second bonding pad electrically connects the contact posts.

6. The semiconductor structure comprising a light-emitting element according to claim 5, wherein the top surface of the second bonding pad is connected to a signal source.

7. The semiconductor structure comprising a light-emitting element according to claim 5, further comprising a passivation layer covering the first bonding pad and the second bonding pad, and the passivation layer includes a plurality of openings, each opening exposing a part of the first bonding pad or the second bonding pad, and the light-emitting element is located in each of the openings in the display area.

8. The semiconductor structure comprising a light-emitting element according to claim 7, wherein the first bonding pad and the second bonding pad are also located in the passivation layer, and the first bonding pad and the second bonding pad have the same thickness.

9. The semiconductor structure comprising a light-emitting element according to claim 2, wherein in the display area, each of the first bonding pads corresponds to each of the contact posts, and the first bonding pads are arranged in an array.

10. The semiconductor structure comprising a light-emitting element according to claim 9, wherein in the display area, the distance between any two adjacent first bonding pads is between 0.3 micrometers and 0.5 micrometers.

11. The semiconductor structure comprising a light-emitting element according to claim 2, wherein the first bonding pad includes a bottom layer, an intermediate layer and a top layer, the materials of the bottom layer and the top layer include titanium and titanium nitride, and the material of the intermediate layer includes aluminum.

12. The semiconductor structure comprising a light-emitting element according to claim 1, wherein the ratio of the area of the display area to the area of the bonding pad area is greater than 20.

13. A method for forming a semiconductor structure including a light-emitting element, characterized in that, Comprising: Providing a substrate on which a display area and a bonding pad area are defined; Forming a circuit layer on the substrate, and the circuit layer is located in the display area and the bonding pad area; Forming a plurality of contact posts located in the display area and the bonding pad area and electrically connecting the circuit layer, wherein the plurality of contact posts in the display area are arranged in an array; and Forming a plurality of light-emitting elements located in the display area and electrically connected to the contact posts.

14. The method of forming a semiconductor structure including a light-emitting element as claimed in claim 13, further comprising forming a plurality of first bonding pads in the display area and located between the light-emitting element and the contact post.

15. The method of forming a semiconductor structure including a light-emitting element as claimed in claim 14, wherein in the display area, each of the first bonding pads corresponds to each of the contact posts, and the first bonding pads are arranged in an array.

16. The method of forming a semiconductor structure including a light-emitting element as claimed in claim 14, wherein the first bonding pad is in direct contact with the contact post and the light-emitting element.

17. The method of forming a semiconductor structure including a light-emitting element as claimed in claim 14, further comprising forming a second bonding pad in the bonding pad area, and the second bonding pad is electrically connected to the contact post.

18. The method of forming a semiconductor structure including a light-emitting element as claimed in claim 17, further comprising: forming a metal layer; performing a patterning step on the metal layer to remove a part of the metal layer, and the remaining metal layer in the display area is defined as the first bonding pad, and the remaining metal layer in the bonding pad area is defined as the second bonding pad.

19. The method of forming a semiconductor structure including a light-emitting element as claimed in claim 17, further comprising forming a passivation layer covering the first bonding pad and the second bonding pad.

20. The method of forming a semiconductor structure including a light-emitting element as claimed in claim 19, further comprising performing a planarization step on the passivation layer to make the top surface of the passivation layer a flat surface.

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