Method and apparatus for modulating pulse width modulation signal

Abstract

The invention discloses a modulation method of a pulse width modulation signal and equipment thereof. The modulation method of the pulse width modulation signal is applied to a three-level converter circuit. The modulation method of the pulse width modulation signal comprises the following steps: acquiring a low-frequency carrier signal based on a sinusoidal modulation wave signal; obtaining a redundancy value of a low-frequency switching tube in the three-level converter circuit, and generating a modulation ratio signal of the low-frequency switching tube based on the redundancy value and the sinusoidal modulation wave signal; and generating a pulse width modulation signal based on the modulation ratio signal of the low-frequency switching tube and the low-frequency carrier signal. Through the mode, the modulation method of the pulse width modulation signal can realize modulation of the pulse width modulation signal of the three-level converter circuit on a low-speed processor under the condition that a relatively small zero crossing dead zone is ensured, and only one switching tube of the three-level converter circuit performs switching action at each moment; therefore, the noise interference caused by the switching action of the switching tube in the three-level converter circuit is reduced.

Description

Technical Field

[0001] The present application relates to the technical field of three-level converters, and specifically relates to a modulation method and device for a pulse width modulation signal, wherein the device includes an electronic device and a computer storage medium. Background Art

[0002] With the progress of technology and the improvement of living standards, people's requirements for power quality are also constantly increasing. Multilevel converters are increasingly used in industrial and social life fields to provide higher-quality electric energy. Taking the active neutral-point-clamped (ANPC) circuit as an example, in the ANPC circuit, the ANPC circuit includes 4 low-frequency switching tubes and 2 high-frequency switches, and the low-frequency switching frequency is the same as the frequency of the modulation wave. When the duty cycle is relatively large, there may be a direct switching from a positive level to a negative level during zero-crossing switching, resulting in overvoltage of the switching tubes. Therefore, generally, zero level is inserted at the zero-crossing point as the transition level for the low-frequency switching tube to switch. However, the existing implementation of this modulation method usually uses a Field Programmable Gate Array (FPGA) for coding implementation because the operation speed of the FPGA is fast and can detect the switch state and update at a speed greater than the switching frequency. However, when the controller is a simple Microcontroller Unit (MCU), a large dead zone will be generated at the zero-crossing point when implementing this zero-level insertion modulation method at the zero-crossing point. Summary of the Invention

[0003] The present application provides a modulation method for a pulse width modulation signal, an electronic device, and a computer storage medium, aiming to solve the above problems.

[0004] To solve the above technical problems, a technical solution adopted by the present application is: providing a modulation method for a pulse width modulation signal, where the modulation method for the pulse width modulation signal is applied to a three-level converter circuit, and the modulation method for the pulse width modulation signal includes: obtaining a low-frequency carrier signal based on a sinusoidal modulation wave signal; obtaining a redundancy value of a low-frequency switching tube in the three-level converter circuit, and generating a modulation ratio signal of the low-frequency switching tube based on the redundancy value and the sinusoidal modulation wave signal; generating a pulse width modulation signal based on the modulation ratio signal of the low-frequency switching tube and the low-frequency carrier signal.

[0005] Among them, the three-level converter circuit includes an upper bridge arm composed of a first switch tube, a second switch tube, and a fifth switch tube connected in series, and a lower bridge arm composed of a third switch tube, a fourth switch tube, and a sixth switch tube connected in series. The connection point of the fifth switch tube and the sixth switch tube is connected to the midpoint of the DC bus, and the connection point of the second switch tube and the third switch tube serves as the AC output terminal of the three-level converter circuit; the low-frequency switch tubes include the first switch tube, the fourth switch tube, the fifth switch tube, and the sixth switch tube; the step of obtaining the redundancy value of the low-frequency switch tubes in the three-level converter circuit and generating a modulation ratio signal of the low-frequency switch tubes based on the redundancy value and the sine modulation wave signal includes: obtaining a first redundancy value of the first switch tube and the fourth switch tube, and generating a first modulation ratio signal of the first switch tube and a second modulation ratio signal of the fourth switch tube based on the first redundancy value and the sine modulation wave signal; obtaining a second redundancy value of the fifth switch tube and the sixth switch tube, and generating a third modulation ratio signal of the fifth switch tube and a fourth modulation ratio signal of the sixth switch tube based on the second redundancy value and the sine modulation wave signal.

[0006] Among them, the step of obtaining a first redundancy value of the first switch tube and the fourth switch tube, and generating a first modulation ratio signal of the first switch tube and a second modulation ratio signal of the fourth switch tube based on the first redundancy value and the sine modulation wave signal includes: in response to the sine modulation wave signal being greater than or equal to zero, setting the first modulation ratio signal to the sum value of a preset value and the first redundancy value; in response to the sine modulation wave signal being less than zero, setting the first modulation ratio signal to zero; in response to the sine modulation wave signal being greater than or equal to zero, setting the second modulation ratio signal to zero; in response to the sine modulation wave signal being less than zero, setting the second modulation ratio signal to the sum value of a preset value and the first redundancy value.

[0007] Among them, the step of obtaining a second redundancy value of the fifth switch tube and the sixth switch tube, and generating a third modulation ratio signal of the fifth switch tube and a fourth modulation ratio signal of the sixth switch tube based on the second redundancy value and the sine modulation wave signal includes: in response to the sine modulation wave signal being greater than or equal to zero, setting the third modulation ratio signal to the second redundancy value; in response to the sine modulation wave signal being less than zero, setting the third modulation ratio signal to a preset value; in response to the sine modulation wave signal being greater than or equal to zero, setting the fourth modulation ratio signal to a preset value; in response to the sine modulation wave signal being less than zero, setting the fourth modulation ratio signal to the second redundancy value.

[0008] Among them, the step of obtaining a first redundancy value of the first switch tube and the fourth switch tube includes: obtaining a preset delay time and a first equivalent dead time of the fifth switch tube and the first switch tube; obtaining the first redundancy value based on the preset delay time, the first equivalent dead time, and the period of the low-frequency carrier signal.

[0009] Among them, the steps of obtaining the second redundancy values of the fifth switching transistor and the sixth switching transistor include: obtaining the conduction time when the fifth switching transistor and the sixth switching transistor are conducting simultaneously; obtaining the second redundancy values based on the conduction time and the period of the low-frequency carrier signal.

[0010] Among them, the low-frequency carrier signal includes a first low-frequency carrier signal and a second low-frequency carrier signal. The steps of generating a pulse width modulation signal based on the modulation ratio signal of the low-frequency switching transistor and the low-frequency carrier signal include: generating a first pulse width modulation signal of the first switching transistor based on the first modulation ratio signal and the second low-frequency carrier signal; generating a second pulse width modulation signal of the fourth switching transistor based on the second modulation ratio signal and the second low-frequency carrier signal; generating a third pulse width modulation signal of the fifth switching transistor based on the third modulation ratio signal and the first low-frequency carrier signal; generating a fourth pulse width modulation signal of the sixth switching transistor based on the fourth modulation ratio signal and the second low-frequency carrier signal.

[0011] Among them, the steps of obtaining the low-frequency carrier signal based on the sine modulation wave signal include: in response to the sine modulation wave signal being equal to zero, setting the first low-frequency carrier signal and the second low-frequency carrier signal to zero; in response to the absolute value of the sine modulation wave signal being greater than zero, the amplitude of the first low-frequency carrier signal increases upward to a preset value in the first half cycle and decreases downward in the second half cycle to form a positive triangular wave; the amplitude of the second low-frequency carrier signal decreases downward to the opposite of the preset value in the first half cycle and increases upward in the second half cycle to form a negative triangular wave; wherein, the periods of the first low-frequency carrier signal and the second low-frequency carrier signal are half of the period of the sine modulation wave signal.

[0012] To solve the above technical problems, another technical solution adopted by this application is: to provide an electronic device, which includes a processor and a memory connected to the processor. Among them, program data is stored in the memory, and the processor executes the program data stored in the memory to execute the modulation method of the pulse width modulation signal as described in any one of the above.

[0013] To solve the above technical problems, another technical solution adopted by this application is: to provide a computer-readable storage medium, which stores program instructions internally, and the program instructions are executed by the processor to implement the modulation method of the pulse width modulation signal as described in any one of the above.

[0014] The beneficial effects of the present application are as follows: Different from the prior art, the modulation method of the pulse width modulation signal in the present application first obtains a low-frequency carrier signal based on a sine modulation wave signal, then obtains the redundancy value of each low-frequency switching tube in the three-level converter circuit, and generates a modulation ratio signal corresponding to the low-frequency switching tube based on the redundancy value and the sine modulation wave signal; finally, a pulse width modulation signal can be generated based on the modulation ratio signal of the low-frequency switching tube and the low-frequency carrier signal. In the above manner, the modulation method of the pulse width modulation signal in the present application can realize the modulation of the pulse width modulation signal of the three-level converter circuit on a low-speed processor while ensuring a small zero-crossing dead zone, and only one switching tube in the three-level converter circuit performs a switching action at each moment, thereby reducing the noise interference caused by the switching action of the switching tubes in the three-level converter circuit. Description of the Drawings

[0015] The drawings herein are incorporated into the specification and form a part of this specification. These drawings illustrate embodiments consistent with the present application and, together with the specification, are used to explain the technical solutions of the present application.

[0016] Figure 1 is a schematic circuit structure diagram of an embodiment of the ANPC circuit;

[0017] Figure 2 is a schematic diagram of the switching states of the ANPC circuit on the positive and negative half axes;

[0018] Figure 3 is a schematic waveform diagram of the pulse width modulation signal of the switching tubes of the ANPC circuit based on the existing modulation method;

[0019] Figure 4 is a schematic flowchart of the first embodiment of the modulation method of the pulse width modulation signal of the present application;

[0020] Figure 5 is Figure 4 a schematic flowchart of an embodiment of step S102 in

[0021] Figure 6 is Figure 5 a schematic flowchart of the first embodiment of step S201 in

[0022] Figure 7 is Figure 5 a schematic flowchart of the second embodiment of step S201 in

[0023] Figure 8 is a schematic waveform diagram of an embodiment of generating the pulse width modulation signal of the low-frequency switching tube based on the low-frequency carrier and the redundancy value in the present application;

[0024] Figure 9 is Figure 5 a schematic flowchart of the first embodiment of step S202 in

[0025] Figure 10 is Figure 5 The schematic flow chart of the second embodiment of step S202 in

[0026] Figure 11 is Figure 4 The schematic flow chart of one embodiment of step S103 in

[0027] Figure 12 is Figure 4 The schematic flow chart of one embodiment of step S101 in

[0028] Figure 13 It is the waveform schematic diagram of one embodiment of the pulse width modulation signal of the high-frequency switching transistor of the present application;

[0029] Figure 14 It is the waveform schematic diagram of the pulse width modulation signal of the switching transistor when the sine modulation wave frequency of the application becomes larger;

[0030] Figure 15 It is the waveform schematic diagram of the pulse width modulation signal of the switching transistor when the sine modulation wave frequency of the application becomes smaller;

[0031] Figure 16 It is the schematic structural diagram of one embodiment of the electronic device of the present application;

[0032] Figure 17 It is the schematic structural diagram of one embodiment of the computer storage medium of the present application. Detailed implementation manners

[0033] Next, embodiments of the technical solutions of the present application will be described in detail with reference to the accompanying drawings. The following embodiments are only used to illustrate the technical solutions of the present application more clearly, so they are only examples and cannot be used to limit the protection scope of the present application.

[0034] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those of ordinary skill in the technical field to which this application belongs; the terms used herein are only for the purpose of describing specific embodiments and are not intended to limit this application; the terms "including" and "having" and any variations thereof in the specification and claims of this application and the above accompanying drawing descriptions are intended to cover non-exclusive inclusion.

[0035] In the description of the embodiments of this application, technical terms such as "first" and "second" are only used to distinguish different objects and cannot be understood as indicating or implying relative importance or implicitly specifying the quantity, specific order or primary and secondary relationship of the indicated technical features. In the description of the embodiments of this application, "a plurality" means more than two unless otherwise specifically defined.

[0036] References herein to "embodiments" mean that the particular features, structures, or characteristics described in connection with the embodiments can be included in at least one embodiment of the present application. The phrase appears in various places in the specification and does not necessarily refer to the same embodiment, nor is it an independent or alternative embodiment mutually exclusive with other embodiments. Those skilled in the art will explicitly and implicitly understand that the embodiments described herein can be combined with other embodiments.

[0037] With the progress of technology and the improvement of living standards, people's requirements for power quality are also constantly increasing. Multilevel converters are increasingly used in industrial and social life fields to provide higher-quality electric energy. Taking the active neutral-point-clamped (ANPC) circuit as an example, please refer to Figure 1 , Figure 1 which is a schematic diagram of the circuit structure of an embodiment of the ANPC circuit. As Figure 1 shown, in the ANPC circuit 100, the ANPC circuit 100 includes an upper bridge arm composed of a first switching tube S1, a second switching tube S2, and a fifth switching tube Sp connected in series, and a lower bridge arm composed of a third switching tube S3, a fourth switching tube S4, and a sixth switching tube Sn connected in series. The connection point of the fifth switching tube Sp and the sixth switching tube Sn is connected to the midpoint N of the DC bus. The connection point of the second switching tube S2 and the third switching tube S3 is used as the AC output terminal of the ANPC circuit. Among them, in this embodiment, the low-frequency switching tubes include the first switching tube S1, the fourth switching tube S4, the fifth switching tube Sp, and the sixth switching tube Sn, and the high-frequency switching tubes include the second switching tube S2 and the third switching tube S3. The ANPC circuit 100 also includes a first capacitor assembly C dcp and a second capacitor assembly C dcn . The DC output terminal is connected in parallel with the first capacitor assembly C dcp and the second capacitor assembly C dcn . The first capacitor assembly C dcp and the second capacitor assembly C dcn are connected in series, and the connection point of the first capacitor assembly C dcp and the second capacitor assembly C dcn is used as the midpoint of the DC bus. In this embodiment, the frequency of the low-frequency switching tubes is the same as the frequency of the pulse width modulation signal.

[0038] Please refer to Figure 2 , Figure 2 which is a schematic diagram of the switching states of the ANPC circuit on the positive and negative half axes. The switching states of the ANPC circuit on the positive and negative half axes include positive level, positive zero level, zero level, negative zero level, and negative level. As Figure 2As shown, in the positive-level switching state, the first switching transistor S1, the second switching transistor S2, and the sixth switching transistor Sn are turned on; in the positive-zero-level switching state, the first switching transistor S1, the third switching transistor S3, and the sixth switching transistor Sn are turned on; in the zero-level switching state, the fifth switching transistor Sp and the sixth switching transistor Sn are turned on; in the negative-zero-level switching state, the second switching transistor S2, the fourth switching transistor S4, and the fifth switching transistor Sp are turned on; in the negative-level switching state, the third switching transistor S3, the fourth switching transistor S4, and the fifth switching transistor Sp are turned on.

[0039] When the duty cycle required by the ANPC circuit is relatively large, there may be a direct transition from the positive level to the negative level during the zero-crossing switching, which causes overvoltage in the conduction of the fifth switching transistor Sp and the sixth switching transistor Sn at this time. Therefore, the modulation of the ANPC circuit inserts a zero level at the zero crossing as the transition level for the switching of the low-frequency switching transistors. However, the existing implementation of this modulation method is usually carried out by encoding with a Field Programmable Gate Array (FPGA) because the operation speed of the FPGA is fast and can detect the switching state and update at a speed greater than the switching frequency. However, when the controller is a simple Microcontroller Unit (MCU), a large dead zone will be generated at the zero crossing when implementing this zero-level insertion modulation method at the zero crossing.

[0040] Please refer to Figure 3 , Figure 3 is a waveform schematic diagram of the pulse width modulation signal of the switching transistors of the ANPC circuit based on the existing modulation method. As Figure 3 shown, the size of the zero-crossing dead zone (i.e., the gray area) is at least one interruption period Ts because the processing ability of the MCU is to detect the sampling and update the duty ratio of the pulse width modulation signal once per interruption period.

[0041] To solve the above problems, the present application first proposes a modulation method for a pulse width modulation signal, and this modulation method for the pulse width modulation signal can be applied to a three-level converter circuit. Please refer to Figure 4 , Figure 4 is a flowchart of the first embodiment of the modulation method for the pulse width modulation signal of the present application. As Figure 4 shown, the modulation method for the pulse width modulation signal of this embodiment specifically includes steps S101 to S103:

[0042] Step S101: Obtain a low-frequency carrier signal based on a sinusoidal modulation wave signal.

[0043] In this embodiment, first, a sine modulation wave needs to be obtained. After obtaining the sine modulation wave, two opposite low-frequency carrier signals can be obtained based on the sine modulation wave. The method for obtaining the low-frequency carrier signals is described as follows.

[0044] Step S102: Obtain the redundancy value of the low-frequency switching tubes in the three-level converter circuit, and generate the modulation ratio signal of the low-frequency switching tubes based on the redundancy value and the sine modulation wave signal.

[0045] In this embodiment, when obtaining the pulse width modulation signal of the switching tubes, first, the redundancy value of the low-frequency switching tubes in the three-level converter circuit needs to be obtained. In this embodiment, the three-level converter circuit can take the Figure 1 ANPC circuit in

[0046] as an example. That is, when obtaining the pulse width modulation signal of the low-frequency switching tubes, a redundancy value can be set for each low-frequency switching tube, and the modulation ratio signal corresponding to the low-frequency switching tubes is generated based on the redundancy value and the sine modulation wave signal, so as to generate the equivalent dead zone of the switching tubes.

[0047] After obtaining the modulation ratio signal of the low-frequency switching tubes, the modulation ratio signal and the low-frequency carrier signal can be compared to obtain the pulse width modulation signal corresponding to the low-frequency switching tubes.

[0048] Different from the prior art, the modulation method of the pulse width modulation signal in this application first obtains the low-frequency carrier signal based on the sine modulation wave signal, then obtains the redundancy value of each low-frequency switching tube in the three-level converter circuit, and generates the modulation ratio signal corresponding to the low-frequency switching tubes based on the redundancy value and the sine modulation wave signal; finally, the pulse width modulation signal can be generated based on the modulation ratio signal of the low-frequency switching tubes and the low-frequency carrier signal. In this way, the modulation method of the pulse width modulation signal in this application can realize the modulation of the pulse width modulation signal of the three-level converter circuit on a low-speed processor while ensuring a small zero-crossing dead zone, and only one switching tube in the three-level converter circuit has a switching action at each moment, thereby reducing the noise interference caused by the switching action of the switching tubes in the three-level converter circuit.

[0049] Optionally, the method for obtaining the redundancy value of the low-frequency switching tubes in the three-level converter circuit and generating the modulation ratio signal of the low-frequency switching tubes based on the redundancy value and the sine modulation wave signal is as Figure 5 shown. Please refer to Figure 5 Figure 5 Figure 4 is the flow chart of an embodiment of step S102 in Figure 5 This embodiment can implement step S102 through the method shown in

[0050] Step S201: Obtain the first redundancy values of the first switch and the fourth switch, and generate the first modulation ratio signal of the first switch and the second modulation ratio signal of the fourth switch based on the first redundancy values and the sine modulation wave signal.

[0051] In this embodiment, the three-level converter circuit takes Figure 1 the ANPC circuit as an example. In the ANPC circuit 100, the ANPC circuit 100 includes an upper bridge arm composed of a first switch S1, a second switch S2, and a fifth switch Sp connected in series, and a lower bridge arm composed of a third switch S3, a fourth switch S4, and a sixth switch Sn connected in series. The connection point of the fifth switch Sp and the sixth switch Sn is connected to the midpoint N of the DC bus. The connection point of the second switch S2 and the third switch S3 is used as the AC output terminal of the ANPC circuit. Among them, the low-frequency switches include the first switch S1, the fourth switch S4, the fifth switch Sp, and the sixth switch Sn.

[0052] Since the first switch S1 and the fourth switch S4 are the same switches, and the fifth switch Sp and the sixth switch Sn are the same clamping tubes, only two redundancy values need to be set for the two types of switches. Then, their modulation ratio signals can be set correspondingly based on their working states in the circuit and the sine modulation wave signal.

[0053] In this embodiment, first, obtain the first redundancy values of the first switch S1 and the fourth switch S4, and generate the first modulation ratio signal of the first switch S1 and the second modulation ratio signal of the fourth switch S4 based on the first redundancy values and the sine modulation wave signal.

[0054] Step S202: Obtain the second redundancy values of the fifth switch and the sixth switch, and generate the third modulation ratio signal of the fifth switch and the fourth modulation ratio signal of the sixth switch based on the second redundancy values and the sine modulation wave signal.

[0055] Secondly, obtain the second redundancy values of the fifth switch Sp and the sixth switch Sn, and generate the third modulation ratio signal of the fifth switch Sp and the fourth modulation ratio signal of the sixth switch Sn based on the second redundancy values and the sine modulation wave signal.

[0056] Optionally, the method for generating the first modulation ratio signal of the first switch and the second modulation ratio signal of the fourth switch based on the first redundancy values and the sine modulation wave signal is as Figure 6 shown. Please refer to Figure 6 , Figure 6 which Figure 5 is the flowchart of the first embodiment of step S201 in Figure 6The steps of obtaining the first modulation ratio signal and the second modulation ratio signal in step S201 of the method shown are specifically implemented in steps including step S301 to step S302:

[0057] Step S301: In response to the sine modulation wave signal being greater than or equal to zero, the first modulation ratio signal is set to the sum of a preset value and a first redundancy value; in response to the sine modulation wave signal being less than zero, the first modulation ratio signal is set to zero.

[0058] When the sine modulation wave signal is greater than or equal to zero, the first modulation ratio signal is set to the sum of a preset value and a first redundancy value; when the sine modulation wave signal is less than zero, the first modulation ratio signal is set to zero.

[0059] Step S302: In response to the sine modulation wave signal being greater than or equal to zero, the second modulation ratio signal is set to zero; in response to the sine modulation wave signal being less than zero, the second modulation ratio signal is set to the sum of a preset value and a first redundancy value.

[0060] When the sine modulation wave signal is greater than or equal to zero, the first modulation ratio signal is set to the sum of a preset value and a first redundancy value; when the sine modulation wave signal is less than zero, the first modulation ratio signal is set to zero.

[0061] In this embodiment, the preset value is set to 1, and the first redundancy value is obtained by calculating based on the preset delay time of the switching tube, the first equivalent dead time between the fifth switching tube Sp and the first switching tube S1, and the period of the low-frequency carrier signal. The specific calculation process is described below.

[0062] Optionally, the method for obtaining the first redundancy value of the first switching tube and the fourth switching tube is as Figure 7 shown. Please refer to Figure 7 , Figure 7 which is Figure 5 the schematic flow chart of the second embodiment of step S201. This embodiment can implement the steps of obtaining the first redundancy value in step S201 through the method as Figure 7 shown. The specific implementation steps include step S401 to step S402:

[0063] Step S401: Obtain the preset delay time and the first equivalent dead time of the fifth switching tube and the first switching tube.

[0064] When obtaining the first redundancy value, it is first necessary to obtain the preset delay time of the switching tube and the first equivalent dead time of the fifth switching tube Sp and the first switching tube Sn. In this embodiment, the first equivalent dead time can be obtained through experiments or simulation tests. The preset delay time is the delay time of the switching tube. Among them, the delay time of the switching tube can be set based on the physical characteristics of the switching tube, which is not limited here.

[0065] Step S402: Obtain a first redundancy value based on a preset delay time, a first equivalent dead time, and the period of a low-frequency carrier signal.

[0066] After obtaining the preset delay time of the switching transistor, the first equivalent dead time, and the period of the low-frequency carrier signal, the first redundancy value can be calculated. The formula for calculating the first redundancy value is as follows:

[0067] A = -(Td + Th) / T (1)

[0068] Where A is the first redundancy value, Td is the delay time of the switching transistor, Th is the equivalent dead time of the fifth switching transistor Sp and the first switching transistor S1, and T is the period of the low-frequency carrier signal.

[0069] In an application scenario, please refer to Figure 8 , Figure 8 is a waveform schematic diagram of an embodiment of generating a pulse width modulation signal of a low-frequency switching transistor based on a low-frequency carrier and a redundancy value in the present application. As shown in Figure 8 , taking the ANPC circuit shown in Figure 1 as an example, for the fourth switching transistor S4, first, the second modulation ratio signal duty_S4 of the fourth switching transistor S4 needs to be set. When the sine modulation wave vb >= 0, the second modulation ratio signal duty_S4 = 0. When vb < 0, duty_S4 is not directly given the preset value 1, but a first redundancy value A is superimposed on the preset value 1. The first redundancy value A is -(Td + Th) / T. Where Th is the equivalent dead time of the fifth switching transistor Sp and the first switching transistor S1, and it is also the equivalent dead time of the sixth switching transistor Sn and the fourth switching transistor S4. At this time, the second modulation ratio signal duty_S4 of the fourth switching transistor S4 can be as shown in formula (2):

[0070]

[0071] Similarly, the first modulation ratio signal duty_S1 of the first switching transistor S1 is as shown in formula (3):

[0072]

[0073] Optionally, the method for generating the third modulation ratio signal of the fifth switching transistor and the fourth modulation ratio signal of the sixth switching transistor based on the second redundancy value and the sine modulation wave signal is as shown in Figure 9 , please refer to Figure 9 , Figure 9 is Figure 5 a flowchart of the first embodiment of step S202 in Figure 9 This embodiment can implement the steps of obtaining the third modulation ratio signal and the fourth modulation ratio signal in step S202 through the method shown in

[0074] Step S501: In response to the sine modulation wave signal being greater than or equal to zero, the third modulation ratio signal is set to the second redundant value; in response to the sine modulation wave signal being less than zero, the third modulation ratio signal is set to the preset value.

[0075] When the sine modulation wave signal is greater than or equal to zero, the third modulation ratio signal is set to the second redundant value; when the sine modulation wave signal is less than zero, the third modulation ratio signal is set to the preset value.

[0076] Step S502: In response to the sine modulation wave signal being greater than or equal to zero, the fourth modulation ratio signal is set to the preset value; in response to the sine modulation wave signal being less than zero, the fourth modulation ratio signal is set to the second redundant value.

[0077] When the sine modulation wave signal is greater than or equal to zero, the fourth modulation ratio signal is set to the preset value; when the sine modulation wave signal is less than zero, the fourth modulation ratio signal is set to the second redundant value.

[0078] In this embodiment, the preset value is set to 1, and the second redundant value is obtained by calculating the pulse width when the fifth switch tube Sp and the sixth switch tube Sn are both conducting. The specific calculation process is described below.

[0079] Optionally, the method for obtaining the second redundant value of the fifth switch tube and the sixth switch tube is as Figure 10 shown. Please refer to Figure 10 , Figure 10 which Figure 5 is the schematic flowchart of the second embodiment of step S202 in Figure 10 . This embodiment can implement the step of obtaining the second redundant value in step S202 through the method shown in

[0080] Step S601: Obtain the conduction time when the fifth switch tube and the sixth switch tube are both conducting.

[0081] When obtaining the second redundant value, it is first necessary to obtain the conduction time when the fifth switch tube Sp and the sixth switch tube Sn are both conducting. Among them, the conduction time when the fifth switch tube Sp and the sixth switch tube Sn are both conducting can be obtained through experiments or simulation tests, and there is no limitation here.

[0082] Step S602: Obtain the second redundant value based on the conduction time and the period of the low-frequency carrier signal.

[0083] After obtaining the conduction time when the fifth switch tube Sp and the sixth switch tube Sn are both conducting, the second redundant value can be calculated. The formula for calculating the second redundant value is as shown below:

[0084]

[0085] Wherein, B is the second redundancy value, 2*Td is the conduction time when the fifth switching transistor Sp and the sixth switching transistor Sn are conducting simultaneously, Td is the delay time of the switching transistor, and T is the period of the low-frequency carrier signal.

[0086] In an application scenario, such as Figure 8 As shown, when the sine modulation wave vb >= 0, the fourth modulation ratio signal duty_Sn of the sixth switching transistor Sn is set to a preset value of 1. When the sine modulation wave vb < 0, duty_Sn is not directly set to 0, but on the basis of 0, a second redundancy value B = 2*Td / T is added. That is, the fourth modulation ratio signal duty_Sn of the sixth switching transistor Sn is as shown in formula (5):

[0087]

[0088] Similarly, the third modulation ratio signal duty_Sp of the fifth switching transistor Sp is as shown in formula (6):

[0089]

[0090] Optionally, the method for generating a pulse width modulation signal based on the modulation ratio signal of the low-frequency switching transistor and the low-frequency carrier signal is as Figure 11 shown. Please refer to Figure 11 , Figure 11 which is Figure 4 a schematic flow diagram of an embodiment of step S103 in Figure 11 . In this embodiment, the low-frequency carrier signal includes a first low-frequency carrier signal and a second low-frequency carrier signal. This embodiment can implement step S103 through the method as

[0091] Step S701: Generate a first pulse width modulation signal of the first switching transistor based on the first modulation ratio signal and the second low-frequency carrier signal.

[0092] As Figure 8 shown, after obtaining the first modulation ratio signal duty_S1 of the first switching transistor S1, at this time, the first modulation ratio signal duty_S1 can be compared with the second low-frequency carrier signal carr2 as Figure 8 shown, and a first pulse width modulation signal of the first switching transistor S4 can be generated.

[0093] Step S702: Generate a second pulse width modulation signal of the fourth switching transistor based on the second modulation ratio signal and the second low-frequency carrier signal.

[0094] As Figure 8 shown, after obtaining the second modulation ratio signal duty_S4 of the fourth switching transistor S4, at this time, Figure 8As shown in the figure, by comparing the second modulation ratio signal duty_S4 with the second low-frequency carrier signal carr2, the second pulse width modulation signal of the fourth switching transistor S4 can be generated.

[0095] Step S703: Generate a third pulse width modulation signal of a fifth switching transistor based on a third modulation ratio signal and a first low-frequency carrier signal.

[0096] As Figure 8 shown, after obtaining the third modulation ratio signal duty_Sp of the fifth switching transistor Sp, at this time, as Figure 8 shown, by comparing the third modulation ratio signal duty_Sp with the first low-frequency carrier signal carr1, the third pulse width modulation signal of the fifth switching transistor Sp can be generated.

[0097] Step S704: Generate a fourth pulse width modulation signal of a sixth switching transistor based on a fourth modulation ratio signal and a second low-frequency carrier signal.

[0098] As Figure 8 shown, after obtaining the fourth modulation ratio signal duty_Sn of the sixth switching transistor Sn, at this time, as Figure 8 shown, by comparing the fourth modulation ratio signal duty_Sn with the first low-frequency carrier signal carr1, the fourth pulse width modulation signal of the sixth switching transistor Sn can be generated.

[0099] Optionally, the method for obtaining a low-frequency carrier signal based on a sine modulation wave signal is as Figure 12 shown. Please refer to Figure 12 , Figure 12 which Figure 4 is a schematic flowchart of an embodiment of step S101 in Figure 12 . In this embodiment, the low-frequency carrier signal includes a first low-frequency carrier signal and a second low-frequency carrier signal. This embodiment can implement step S101 through the method as

[0100] shown, and the specific implementation steps include steps S801 to S802:

[0101] When the sine modulation wave signal is equal to zero, the first low-frequency carrier signal and the second low-frequency carrier signal are set to zero.

[0102] Step S802: In response to the absolute value of the sine modulation wave signal being greater than zero, the amplitude of the first low-frequency carrier signal increases upward to a preset value in the first half cycle and decreases downward in the second half cycle to form a positive triangular wave; the amplitude of the second low-frequency carrier signal decreases downward to the opposite of the preset value in the first half cycle and increases upward in the second half cycle to form a negative triangular wave.

[0103] When the absolute value of the sinusoidal modulated wave signal is greater than zero, the amplitude of the first low-frequency carrier signal increases upward to a preset value in the first half cycle, and decreases downward in the second half cycle to form a positive triangle wave; the amplitude of the second low-frequency carrier signal decreases downward to the opposite number of the preset value in the first half cycle, and increases upward in the second half cycle to form a negative triangle wave. In this embodiment, the preset value is set to 1.

[0104] In this embodiment, the period of the first low-frequency carrier signal and the second low-frequency carrier signal is half of the period of the sinusoidal modulation wave signal.

[0105] In an application scenario, such as Figure 8 As shown, when a sinusoidal modulation wave vb is known, when vb=0, the first low-frequency carrier signal carr1 and the second low-frequency carrier signal carr2 are both 0 at this time. When the absolute value of vb is greater than 0, the amplitude of the first low-frequency carrier signal carr1 increases upward, and the amplitude of the second low-frequency carrier signal carr2 decreases downward. In this embodiment, the preset value is 1, that is, when the amplitude of the first low-frequency carrier signal carr1 increases to 1, it starts to decrease downward, and when the amplitude of the second low-frequency carrier signal carr2 decreases to -1, it starts to increase upward. In addition, in this embodiment, the period of the generated first low-frequency carrier signal carr1 and the second low-frequency carrier signal carr2 needs to be set to half of the period of the sinusoidal modulation wave vb. Assuming that the period of the sinusoidal modulation wave vb is 2T, the period of the first low-frequency carrier signal carr1 and the second low-frequency carrier signal carr2 is T.

[0106] Also, see Figure 13 , Figure 13 1 is a waveform diagram of a pulse width modulation signal of a high frequency switch tube of the present application. Figure 13 As shown, the pulse width modulation signals of the second switch tube S2 and the third switch tube S3 are generated by comparing the sinusoidal modulation wave vb with the carrier signal carr3 and the carrier signal carr4. The carrier signal carr3 and the carrier signal carr4 are Figure 1 The switching frequency values ​​in the ANPC circuit are shown.

[0107] See also Figure 14 , Figure 14 Schematic diagram of the waveform of the pulse width modulation signal of the switch tube when the frequency of the sinusoidal modulation wave of the present application increases. Figure 14 As shown, since the present application needs to generate the first low-frequency carrier signal carr1 and the second low-frequency carrier signal carr2 according to the comparison between the sinusoidal modulation wave vb and 0, when the frequency of the sinusoidal modulation wave vb changes, the waveform of the first low-frequency carrier signal carr1 and the second low-frequency carrier signal carr2 returning to zero will change at the zero crossing point. Figure 14It can be seen from the figure that when the frequency of the sinusoidal modulation wave vb increases, the pulse width of the fifth switch tube Sp and the sixth switch tube Sn being turned on simultaneously when passing through the zero point becomes shorter, that is, the zero level time becomes shorter, so as long as the delay time of the switch tube is set with a margin, the frequency of the usual sinusoidal modulation wave vb is the grid frequency, and generally the fluctuation range is not large, which does not affect the implementation effect of the present application.

[0108] See also Figure 15 , Figure 15 This is a waveform diagram of the pulse width modulation signal of the switch tube when the frequency of the sinusoidal modulation wave of the present application becomes smaller, such as Figure 15 As shown, it can be seen that when the frequency of the sinusoidal modulation wave vb becomes smaller, the pulse width of the fifth switch tube Sp and the sixth switch tube Sn being turned on at the same time when crossing the zero point has no effect, but it will be turned on twice, that is to say, the zero level is inserted twice at the zero point, which can also be equivalently understood as the zero level time being doubled, which also does not affect the implementation effect of the present application. Because the delay time of the switch tube is related to the physical characteristics of the switch tube, it is usually sufficient as long as it is greater than the on-off time of the switch tube, and the delay time of the switch tube is generally 1 to 2us or even ns level, so the overall increase of 2 times is still far less than the dead zone time of the existing solution at the zero point. And the frequency change of the sinusoidal modulation wave vb has no effect on the dead zone implementation effect between the first switch tube S1 and the fifth switch tube Sp and between the sixth switch tube Sn and the fourth switch tube S4.

[0109] Different from the prior art, the modulation method of the pulse width modulation signal of the present application first obtains the low-frequency carrier signal based on the sinusoidal modulation wave signal, then obtains the redundancy value of each low-frequency switch tube in the three-level converter circuit, and generates the modulation ratio signal corresponding to the low-frequency switch tube based on the redundancy value and the sinusoidal modulation wave signal; finally, the pulse width modulation signal can be generated based on the modulation ratio signal of the low-frequency switch tube and the low-frequency carrier signal. Through the above manner, the modulation method of the pulse width modulation signal of the present application can realize the modulation of the pulse width modulation signal of the three-level converter circuit on the low-speed processor while ensuring a small zero-crossing dead zone, and at each moment, the three-level converter circuit has only one switch tube switching action, thereby reducing the noise interference caused by the switching action of the switch tube in the three-level converter circuit.

[0110] In addition, the modulation method of the pulse width modulation signal of the present application can be applied not only to a single-phase three-level converter circuit, but also to a three-phase three-level converter circuit. Taking the three-phase ANPC circuit as an example, for each phase, the modulation method of the pulse width modulation signal of the present application can be applied to modulate the signal. The modulation wave signal vb of each phase is the modulation wave vbA, vbB, and vbC of each phase. In addition to being applicable to Figure 1The ANPC circuit with 2 MOS transistors and 4 IGBT transistors is also applicable to the ANPC circuit with all 6 MOS transistors.

[0111] Optionally, the present application further provides an electronic device. Please refer to Figure 16 , Figure 16 which is a schematic structural diagram of an embodiment of the electronic device of the present application. The electronic device 200 includes a processor 201 and a memory 202 connected to the processor 201.

[0112] The processor 201 may also be referred to as a CPU (Central Processing Unit). The processor 201 may be an integrated circuit chip with signal processing capabilities. The processor 201 may also be a general-purpose processor, a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components. The general-purpose processor may be a microprocessor or the processor may also be any conventional processor, etc.

[0113] The memory 202 is used to store program data required for the operation of the processor 201.

[0114] The processor 201 is further configured to execute the program data stored in the memory 202 to implement the modulation method of the pulse width modulation signal in any of the above.

[0115] Optionally, the present application further provides a computer storage medium. Please refer to Figure 17 , Figure 17 which is a schematic structural diagram of an embodiment of the computer storage medium of the present application.

[0116] The computer storage medium 300 of the embodiment of the present application stores program instructions 310 internally, and the program instructions 310 are executed to implement the modulation method of the pulse width modulation signal in any of the above.

[0117] Among them, the program instructions 310 may form a program file and be stored in the above storage medium in the form of a software product, so that an electronic device (which may be a personal computer, a server, or a network device, etc.) or a processor can execute all or part of the steps of the methods in various embodiments of the present application. The foregoing storage medium includes: various media such as a USB flash drive, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk, or an optical disc that can store program codes, or a terminal device such as a computer, a server, a mobile phone, or a tablet.

[0118] The computer storage medium 300 in this embodiment may be, but is not limited to, a USB flash drive, an SD card, a PD optical drive, a mobile hard disk, a high-capacity floppy drive, a flash memory, a multimedia memory card, a server, etc.

[0119] In one embodiment, a computer program product or a computer program is provided. The computer program product or the computer program includes computer instructions, and the computer instructions are stored in a computer storage medium. The processor of the electronic device reads the computer instructions from the computer storage medium, and the processor executes the computer instructions, so that the electronic device executes the steps in the foregoing method embodiments.

[0120] In addition, if the above functions are implemented in the form of software functions and sold or used as an independent product, they can be stored in a storage medium readable by a mobile terminal. That is, the present application also provides a storage device storing program data, and the program data can be executed to implement the methods of the foregoing embodiments. The storage device may be, for example, a USB flash drive, an optical disc, a server, etc. That is to say, the present application can be embodied in the form of a software product, which includes several instructions for causing an intelligent terminal to execute all or part of the steps of the methods of the various embodiments.

[0121] In addition, the terms “first” and “second” are only used for descriptive purposes and cannot be construed as indicating or implying relative importance or implicitly specifying the quantity of the indicated technical features. Thus, the features defined with “first” and “second” may explicitly or implicitly include at least one of the features. In the description of the present application, “a plurality of” means at least two, such as two, three, etc., unless otherwise specifically defined.

[0122] Any process or method description shown in the flowchart or described in other ways herein may be understood to represent an apparatus, segment, or portion of code including one or more executable instructions for implementing a specific logical function or process. The scope of the preferred embodiments of the present application includes additional implementations, in which the functions may be executed in a substantially simultaneous manner or in a reverse order according to the functions involved, rather than in the order shown or discussed, which should be understood by those skilled in the technical field to which the embodiments of the present application belong.

[0123] The logic and / or steps represented in the flowchart or otherwise described herein, for example, can be considered as a definitional sequence list of executable instructions for implementing logical functions, and can be embodied specifically in any computer-readable medium for use by or in connection with an instruction execution system, apparatus, or device (which can be a personal computer, a server, a network device, or other systems that can fetch instructions from the instruction execution system, apparatus, or device and execute the instructions). For the purposes of this specification, a "computer storage medium" can be any device that can contain, store, communicate, propagate, or transport a program for use by or in connection with an instruction execution system, apparatus, or device. More specific examples (a non-exhaustive list) of computer-readable media include the following: an electrical connection portion with one or more wirings (electronic device), a portable computer diskette (magnetic device), a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber device, and a portable compact disc read-only memory (CDROM). Additionally, the computer-readable medium can even be paper or other suitable media on which a program can be printed, because the program can be obtained electronically, for example, by optically scanning the paper or other media, followed by editing, interpretation, or otherwise processing as appropriate, and then stored in a computer memory.

[0124] The above are only embodiments of the present application, and do not limit the patent scope of the present application. Any equivalent structure or equivalent process transformation made by using the content of the specification and drawings of the present application, or directly or indirectly applied in other related technical fields, shall be equally included in the patent protection scope of the present application.

Claims

1. A modulation method for a pulse width modulation signal, characterized in that, Applied to a three-level converter circuit, the modulation method of the pulse width modulation signal includes: Obtaining a low-frequency carrier signal based on a sinusoidal modulation wave signal; Obtaining the redundancy value of the low-frequency switching tubes in the three-level converter circuit, and generating the modulation ratio signals of the low-frequency switching tubes based on the redundancy value and the sinusoidal modulation wave signal; Generating a pulse width modulation signal based on the modulation ratio signals of the low-frequency switching tubes and the low-frequency carrier signal.

2. The modulation method according to claim 1, characterized in that, The three-level converter circuit includes an upper bridge arm composed of a first switching tube, a second switching tube, and a fifth switching tube connected in series, and a lower bridge arm composed of a third switching tube, a fourth switching tube, and a sixth switching tube connected in series. The connection point of the fifth switching tube and the sixth switching tube is connected to the midpoint of the DC bus. The connection point of the second switching tube and the third switching tube is used as the AC output terminal of the three-level converter circuit; the low-frequency switching tubes include the first switching tube, the fourth switching tube, the fifth switching tube, and the sixth switching tube; The step of obtaining the redundancy value of the low-frequency switching tubes in the three-level converter circuit and generating the modulation ratio signals of the low-frequency switching tubes based on the redundancy value and the sinusoidal modulation wave signal includes: Obtaining the first redundancy value of the first switching tube and the fourth switching tube, and generating the first modulation ratio signal of the first switching tube and the second modulation ratio signal of the fourth switching tube based on the first redundancy value and the sinusoidal modulation wave signal; Obtaining the second redundancy value of the fifth switching tube and the sixth switching tube, and generating the third modulation ratio signal of the fifth switching tube and the fourth modulation ratio signal of the sixth switching tube based on the second redundancy value and the sinusoidal modulation wave signal.

3. The modulation method according to claim 2, characterized in that, The step of obtaining the first redundancy value of the first switching tube and the fourth switching tube, and generating the first modulation ratio signal of the first switching tube and the second modulation ratio signal of the fourth switching tube based on the first redundancy value and the sinusoidal modulation wave signal includes: In response to the sinusoidal modulation wave signal being greater than or equal to zero, the first modulation ratio signal is set to the sum value of the preset value and the first redundancy value. In response to the sinusoidal modulation wave signal being less than zero, the first modulation ratio signal is set to zero; In response to the sinusoidal modulation wave signal being greater than or equal to zero, the second modulation ratio signal is set to zero. In response to the sinusoidal modulation wave signal being less than zero, the second modulation ratio signal is set to the sum value of the preset value and the first redundancy value.

4. The modulation method according to claim 3, characterized in that The step of obtaining the second redundancy value of the fifth switching tube and the sixth switching tube, and generating the third modulation ratio signal of the fifth switching tube and the fourth modulation ratio signal of the sixth switching tube based on the second redundancy value and the sinusoidal modulation wave signal includes: In response to the sinusoidal modulation wave signal being greater than or equal to zero, the third modulation ratio signal is set to the second redundancy value. In response to the sinusoidal modulation wave signal being less than zero, the third modulation ratio signal is set to the preset value; In response to the sinusoidal modulation wave signal being greater than or equal to zero, the fourth modulation ratio signal is set to the preset value. In response to the sinusoidal modulation wave signal being less than zero, the fourth modulation ratio signal is set to the second redundancy value.

5. The modulation method according to claim 2, characterized in that, The step of obtaining the first redundancy values of the first switching transistor and the fourth switching transistor includes: Obtaining a preset delay time, a first equivalent dead time of the fifth switching transistor and the first switching transistor; Obtaining the first redundancy values based on the preset delay time, the first equivalent dead time, and the period of the low-frequency carrier signal.

6. The modulation method according to claim 2, characterized in that The step of obtaining the second redundancy values of the fifth switching transistor and the sixth switching transistor includes: Obtaining the conduction time when the fifth switching transistor and the sixth switching transistor are conducting simultaneously; Obtaining the second redundancy values based on the conduction time and the period of the low-frequency carrier signal.

7. The modulation method according to claim 4, characterized in that The low-frequency carrier signal includes a first low-frequency carrier signal and a second low-frequency carrier signal. The step of generating a pulse width modulation signal based on the modulation ratio signal of the low-frequency switching transistor and the low-frequency carrier signal includes: Generating a first pulse width modulation signal of the first switching transistor based on the first modulation ratio signal and the second low-frequency carrier signal; Generating a second pulse width modulation signal of the fourth switching transistor based on the second modulation ratio signal and the second low-frequency carrier signal; Generating a third pulse width modulation signal of the fifth switching transistor based on the third modulation ratio signal and the first low-frequency carrier signal; Generating a fourth pulse width modulation signal of the sixth switching transistor based on the fourth modulation ratio signal and the second low-frequency carrier signal.

8. The modulation method according to claim 7, wherein The step of obtaining the low-frequency carrier signal based on the sinusoidal modulation wave signal includes: In response to the sinusoidal modulation wave signal being equal to zero, setting the first low-frequency carrier signal and the second low-frequency carrier signal to zero; In response to the absolute value of the sinusoidal modulation wave signal being greater than zero, the amplitude of the first low-frequency carrier signal increases upward to the preset value in the first half cycle and decreases downward in the second half cycle to form a positive triangular wave; the amplitude of the second low-frequency carrier signal decreases downward to the opposite of the preset value in the first half cycle and increases upward in the second half cycle to form a negative triangular wave; Wherein, the periods of the first low-frequency carrier signal and the second low-frequency carrier signal are half of the period of the sinusoidal modulation wave signal.

9. An electronic device, characterized in that, The electronic device includes a processor and a memory connected to the processor. Wherein, program data is stored in the memory, and the processor executes the program data stored in the memory to execute the modulation method of the pulse width modulation signal according to any one of claims 1-8.

10. A computer storage medium, characterized in that, Program instructions are stored therein, and the program instructions are executed to implement the modulation method of the pulse width modulation signal according to any one of claims 1-8.

Images