High-parallelism polarization code encoder based on feedforward pipeline architecture

Abstract

The invention discloses a high-parallelism polarization code encoder based on a feedforward pipeline architecture. The high-parallelism polarization code encoder comprises K encoding matrixes and K-1 core encoding modules, the coding matrixes are transversely arranged at intervals, and one core coding module is arranged between every two adjacent coding matrixes; the polar code encoding process of the high-parallelism polar code encoder is divided into K stages; each stage corresponds to one coding matrix; the coding matrix and the core coding module are continuously multiplexed, so that the construction of the whole high-parallelism polar code encoder can be completed; according to the invention, the parallel stage number of the encoder and the encoding stage number of the encoder can be autonomously selected as preset encoder parameters according to specific encoding requirements so as to adapt to different resource requirements, rate requirements and encoding code length requirements; compared with the existing encoder, the high-parallelism polar code encoder provided by the invention can effectively reduce the hardware complexity and improve the encoding speed.

Description

Technical Field

[0001] The present invention belongs to the field of communication technologies, and particularly relates to a high-parallelism polar code encoder based on a feed-forward pipeline architecture. Background Art

[0002] Polar codes are a class of linear block codes based on the channel polarization phenomenon. It is the first coding scheme that can be strictly proven to achieve the Shannon limit under a binary-input discrete memoryless channel (BI-DMC), and it has currently been used as one of the standard coding schemes for the fifth-generation mobile communication system. In practical applications, the implementation of a coding scheme not only depends on the performance of the algorithm itself but also needs to consider many aspects of circuit design.

[0003] Resource consumption is one of the key considerations, including chip area, power consumption, and memory usage, which are directly related to cost and energy efficiency. Design complexity affects the development cycle and cost. A simple and efficient design can speed up the product's time to market and reduce production costs. Therefore, the circuit design of encoding and decoding algorithms needs to seek a balance among performance, resources, flexibility, modularity, and complexity to achieve an optimal system solution.

[0004] Currently, for the design of polar code encoders, only some independent encoder architecture design schemes are given. Existing polar encoders have problems such as excessive hardware area, low processing frequency, and high algorithm complexity. Summary of the Invention

[0005] To solve the above problems existing in the prior art, the present invention provides a high-parallelism polar code encoder based on a feed-forward pipeline architecture. The technical problems to be solved by the present invention are achieved through the following technical solutions:

[0006] The present invention provides a high-parallelism polar code encoder based on a feed-forward pipeline architecture, including:

[0007] K coding matrices and K - 1 core coding modules, where K ≥ 2; among them,

[0008] Each coding matrix is arranged horizontally at intervals, and 1 core coding module is set between adjacent coding matrices; the polar code encoding process of the high-parallelism polar code encoder is divided into K stages; each stage corresponds to a coding matrix;

[0009] In each stage, the coding matrix performs an operation on the received input data and its corresponding generating matrix according to the preset encoder parameters and Kronecker product, based on the polar code factor graph corresponding to the current stage, to obtain the encoded sequence;

[0010] The core encoding module controls its own commutation module according to an external control signal to perform transposition processing on the encoded sequence it receives, obtaining a transposed encoded sequence; and transmits the transposed encoded sequence to the corresponding encoding matrix in the next stage connected thereto, so that the transposed encoded sequence performs an operation with the generation matrix corresponding to the next stage according to the data flow direction in the polar code factor graph.

[0011] The sequence to be encoded is the input data of the first encoding matrix, and the encoded sequence output by the Kth encoding matrix is the encoding result of the high-parallelism polar code encoder.

[0012] In an embodiment of the present invention, the preset encoder parameters include:

[0013] The number of parallel stages M of the encoder, the number of encoding stages K of the encoder, and the code length N of the encoder encoding; where M is an integer power of 2.

[0014] In an embodiment of the present invention, the expression of the code length of the encoder encoding is as follows:

[0015] N = M K ;

[0016] where M represents the number of parallel stages of the encoder, and K represents the number of encoding stages of the encoder.

[0017] In an embodiment of the present invention, the encoding matrix is an M-order encoding matrix, and the expression of the generation matrix corresponding to the encoding matrix is as follows:

[0018]

[0019] where, represents the Kronecker power, m = log2M, M represents the number of parallel stages of the encoder,

[0020] In an embodiment of the present invention, the encoding matrix is an M-order encoding matrix, and each M-order encoding matrix includes XOR gates; where M represents the number of parallel stages of the encoder.

[0021] In an embodiment of the present invention, the core encoding module includes:

[0022] The left D flip-flop group, the commutation module, and the right D flip-flop group; where the number of parallel stages of the commutation module is M.

[0023] In an embodiment of the present invention, the total number of D flip-flops in each path of the left D flip-flop group and the right D flip-flop group is (M - 1) × M k-1 ; where,

[0024] In the left D flip-flop group, the number of D flip-flops from the first path to the Nth path forms an arithmetic sequence with the first term being 0 and the common difference being M k-1 ;

[0025] In the right D flip-flop group, the number of D flip-flops from the first path to the Nth path forms an arithmetic sequence with the first term being (M - 1)×M k-1 , and the common difference being -M k-1 ; k represents the configuration parameter of the core coding module.

[0026] In an embodiment of the present invention, the total number of D flip-flops in the high-parallelism polar code encoder is M K -M; where M represents the parallel level of the encoder, and K represents the coding level of the encoder.

[0027] Advantages of the present invention:

[0028] In the solution provided by the present invention, by continuously reusing the coding matrix and the core coding module, the construction of the entire high-parallelism polar code encoder can be completed; the present invention can independently select the parallel level of the encoder and the coding level of the encoder as the preset encoder parameters according to specific coding requirements to adapt to different resource requirements, rate requirements, and coding length requirements; compared with the existing encoders, the high-parallelism polar code encoder proposed by the present invention can effectively reduce the hardware complexity and improve the coding speed. Description of the Drawings

[0029] Figure 1 is a schematic structural diagram of a high-parallelism polar code encoder based on a feed-forward pipeline architecture provided by an embodiment of the present invention;

[0030] Figure 2 is a schematic structural diagram of a core coding module in a high-parallelism polar code encoder based on a feed-forward pipeline architecture provided by an embodiment of the present invention;

[0031] Figure 3 is a schematic structural diagram of a high-parallelism polar code encoder based on a feed-forward pipeline architecture when the coding level K of the encoder is 3 and the parallel level M of the encoder is 4 provided by an embodiment of the present invention;

[0032] Figure 4 is a schematic diagram of the splitting process of the polar code factor graph at each stage in a high-parallelism polar code encoder based on a feed-forward pipeline architecture when the coding level K of the encoder is 3 and the parallel level M of the encoder is 4 provided by an embodiment of the present invention. Detailed Embodiments

[0033] The following further describes the present invention in detail with specific embodiments, but the implementation manners of the present invention are not limited thereto.

[0034] An embodiment of the present invention provides a high-parallelism polar code encoder based on a feed-forward pipeline architecture, as Figure 1 shown, which may include:

[0035] K encoding matrices and K-1 core encoding modules, where K≥2; among them,

[0036] Each encoding matrix is arranged horizontally at intervals, and 1 core encoding module is arranged between adjacent encoding matrices; the polar code encoding process of the high-parallelism polar code encoder is divided into K stages; each stage corresponds to an encoding matrix;

[0037] In each stage, the encoding matrix performs an operation on the received input data and its corresponding generating matrix according to the preset encoder parameters and Kronecker product, based on the polar code factor graph corresponding to the current stage, to obtain an encoded sequence;

[0038] The core encoding module controls its commutation module according to an external control signal to perform a transposition process on the received encoded sequence to obtain a transposed encoded sequence; the transposed encoded sequence is transmitted to the encoding matrix corresponding to the next stage connected thereto, so that the transposed encoded sequence performs an operation with the generating matrix corresponding to the next stage according to the data flow in the polar code factor graph;

[0039] The sequence to be encoded is the input data of the first encoding matrix, and the encoded sequence output by the Kth encoding matrix is the encoding result of the high-parallelism polar code encoder.

[0040] The high-parallelism polar code encoder based on the feed-forward pipeline architecture proposed by the embodiment of the present invention aims at the problems that the existing encoder has a long critical path and low resource utilization rate. Based on the nested characteristics of the polar code encoding matrix, the encoding circuit is split and processed, and through vertical parallelism and horizontal pipeline hierarchical processing, the polar code encoding is completed.

[0041] The preset encoder parameters may include:

[0042] The parallel level M of the encoder, the encoding level K of the encoder, and the code length N of the encoder encoding; among them, M is an integer power of 2.

[0043] The expression of the code length of the encoder encoding is as follows:

[0044] N = M K ;

[0045] Among them, M represents the parallel level of the encoder, and K represents the encoding level of the encoder.

[0046] From Figure 1It can be seen that the input of the high-parallelism polar code encoder is M parallel lines, which are sequentially denoted as the 1st line to the Mth line from top to bottom. The sequence to be encoded is The input of the encoder needs to occupy T in = N / M system clocks. The input of the 1st line is sequentially input within T in system clocks The input of the 2nd line is sequentially input within T in system clocks The input of the ith line is sequentially input within T in system clocks The input of the Mth line is sequentially input within T in system clocks

[0047]

[0048] The encoding matrix is an M-order encoding matrix, and its polar code encoding function Among them, the encoding matrix is an M-order encoding matrix, and the expression of the generating matrix corresponding to the encoding matrix is as follows:

[0049]

[0050] Among them, represents the Kronecker power, m = log2M, M represents the encoder parallel level, The generating matrix G corresponding to the M-order encoding matrix M can be obtained by replacing the modulo-2 addition units in the M-order encoding factor graph with XOR gates, and then the encoding circuit diagram can be obtained.

[0051] The encoding matrix can be an M-order encoding matrix, and each M-order encoding matrix includes XOR gates; among them, M represents the encoder parallel level.

[0052] The core encoding module, as Figure 2 shown, may include:

[0053] The left D flip-flop group, the commutation module, and the right D flip-flop group; among them, the parallel level of the commutation module is M.

[0054] From Figure 2 it can be seen that the total number of D flip-flops in each path of the left D flip-flop group and the right D flip-flop group is (M - 1) × M k-1 ; among them,

[0055] In the left D flip-flop group, the number of D flip-flops from the 1st path to the Nth path forms an arithmetic sequence with the first term being 0 and the common difference being M k-1 ;

[0056] In the right D flip-flop bank, the number of D flip-flops from the first path to the Nth path forms an arithmetic sequence with the first term being (M - 1)×M k-1 , and the common difference being -M k-1 ; k represents the configuration parameter of the core coding module.

[0057] The total number of D flip-flops in the high-parallelism polar code encoder is M K - M; where M represents the parallel level of the encoder, and K represents the coding level of the encoder.

[0058] Each core coding module includes a commutation module. Each commutation module requires an external control signal with a bit width of m, where m = log2M. The expression of this external control signal is v1 K-1 = {v1, v2,..., v K-1}; where v1 is the external control signal corresponding to the commutation module in the core coding module with the rightmost configuration parameter k = 1, and v K-1 is the external control signal corresponding to the commutation module in the core coding module with the leftmost configuration parameter k = K - 1. The rest of the external control signals in this expression follow by analogy. The setting of the external control signal is as follows: v1 K-1 = {v1, v2,…, v K-1} forms a sequence with a length of K - 1 and a radix of M. The left side of this sequence is the least significant bit, and the right side is the most significant bit. The least significant bit of this sequence increases by 1 every clock. Whenever the least significant bit changes to M - 1, the least significant bit becomes 0 in the next clock, and the adjacent higher bit increases by 1. When the value of each bit in this sequence is M - 1, the sequence returns to the all-0 sequence in the next clock.

[0059] The input of the commutation module is an input signal with a bit width of M, denoted as i0 M-1 = {i0, i1,…, i M-1}; The output of the commutation module is an output signal with a bit width of M, denoted as o0 M-1 = {o0, o1,…, o M-1}; The commutation module also has an external control signal with a bit width of m = log2M, denoted as v. The commutation module performs the following functions:

[0060]

[0061] The detailed change method of the sequence of the external control signal in the commutation module will be illustrated with specific examples below.

[0062] When the high-parallelism polar code encoder is encoding, the sequence to be encoded is input to the left input end of the encoder and waits for M K-1After - 1 clock, the encoder output starts to output the encoded sequence. At the first clock when the sequence to be encoded is input, the sequence in the external control signal is set to all 0, and then it increases by 1 at each subsequent clock. The encoded sequence can be x0 N-1 ={x0, x1,..., x N-2 , x N-1}, and the output of the encoder takes T out =N / M system clocks. At the first output clock, the M - way outputs sequentially output x0, x1,......, x M-1 , at the second output clock, the M - way outputs sequentially output x M , x M+1 ,......, x 2M-1 , …, at the i - th output clock, the M - way outputs sequentially output x (i-1)M , x (i-1)M+1 ,......, x iM-1 , …, at the T out -th output clock, the M - way outputs sequentially output x N-M , x N-M+1 ,......, x N-1 . The total processing delay of the entire encoding is

[0063] For ease of understanding, taking the parallel level of the encoder M = 4, the encoding level of the encoder K = 3, and the code length of the encoder N = M K =64 as an example, the high - parallel - degree polar code encoder based on the feed - forward pipeline architecture when K = 3 is described in detail below.

[0064] A schematic structural diagram of a high - parallel - degree polar code encoder based on the feed - forward pipeline architecture when K = 3 is shown as Figure 3 . The high - parallel - degree polar code encoder is used to complete the functions corresponding to the operations of the encoding formula, and the encoding formula is as follows:

[0065]

[0066] Among them, is the Kronecker power, 6 = log264, the sequence to be encoded is u0 63 ={u0, u1,..., u 62 , u 63}, and the encoded sequence is x0 63 ={x0, x1,..., x 62 , x 63}.

[0067] The input sequence of the encoder is as Figure 3As shown, the input of the encoder is 4 parallel lines, which are denoted as the 1st line - the 4th line from top to bottom. The input of the encoder needs to occupy T in = N / M = 16 system clocks. The 1st input is sequentially input with u0 within 15 system clocks 15 = {u0, u1,..., u 15}, the 2nd input is sequentially input with u 16 31 = {u 16 , u 17 ,..., u 31} within 15 system clocks, the 3rd input is sequentially input with u 32 47 = {u 32 , u 33 ,..., u 47} within 15 system clocks, and the 4th input is sequentially input with u 48 63 = {u 48 , u 49 ,..., u 63}.

[0068] It can be seen from Figure 3 that the encoder consists of 5 horizontal modules, which can include: 2 core encoding modules and 3 fourth-order encoding matrices. The 3 fourth-order encoding matrices are arranged horizontally at intervals, with 1 core encoding module interspersed between each two. The configuration parameters of the core encoding modules are 2 and 1 from left to right in sequence.

[0069] Since the encoding level K of the encoder is 3, the configuration parameters of the 2 core encoding modules in the encoder are 2 and 1 from left to right respectively.

[0070] The core encoding module with a configuration parameter of 2, as Figure 3 shown, can include:

[0071] The commutation module in the middle and the D flip-flop groups on the left and right sides of the commutation module. The parallel level of the commutation module is 4, and the total number of D flip-flops in each path is the same, all 12. The number of D flip-flops in each path of the left D flip-flop group forms an increasing arithmetic progression from top to bottom, which are 0, 4, 8, 12 in sequence from the first path to the fourth path; the number of D flip-flops in each path of the right D flip-flop group forms a decreasing arithmetic progression from top to bottom, which are 12, 8, 4, 0 in sequence from the first path to the fourth path. The processing delay of each path of the core encoding module with configuration parameter 2 is 12, and the total number of D flip-flops is 48. The core encoding module with configuration parameter 1 may include: the commutation module in the middle and the D flip-flop groups on the left and right sides of the commutation module. Among them, the parallel level of the commutation module is 4, and the total number of D flip-flops in each path is the same, all 3. The number of D flip-flops in each path of the left D flip-flop group forms an increasing arithmetic progression from top to bottom, which are 0, 1, 2, 3 in sequence from the first path to the fourth path; the number of D flip-flops in each path of the right D flip-flop group forms a decreasing arithmetic progression from top to bottom, which are 3, 2, 1, 0 in sequence from the first path to the fourth path. The processing delay of each path of the core encoding module with configuration parameter 1 is 3, and the total number of D flip-flops is 12.

[0072] Specifically, the input of the commutation module is an input signal with a bit width of 4, denoted as i0 3 ={i0, i1, i2, i3}; the output of the commutation module is an output signal with a bit width of 4, denoted as o0 3 ={o0, o1, o2, o3}; the commutation module also has an external control signal with a bit width of 2, denoted as v. The commutation module performs the following functions:

[0073]

[0074] It can be understood that each core encoding module contains a commutation module, and each commutation module requires an external control signal with a bit width of 2, denoted as v1 2 ={v1, v2}, where v1 is the external control signal corresponding to the rightmost core encoding module with configuration parameter k = 1, and v2 is the external control signal corresponding to the leftmost core encoding module with configuration parameter k = 2. The external control signal is set as follows:

[0075] v1 2 ={v1, v2} forms a sequence with a length of 2 and a base of 4. The left side of the sequence is the least significant bit, and the right side is the most significant bit. Each clock, the least significant bit of this sequence increases by 1. Whenever the least significant bit changes to 3, in the next clock, the least significant bit becomes 0, and the adjacent higher bit increases by 1; when the value of each bit in the sequence is 3, in the next clock, the sequence returns to the all-0 sequence. Specifically, v1 2 ={v1, v2} actually changes as follows:

[0076]

[0077] This sequence changes cyclically as shown in the above actual transformation method.

[0078] When performing specific encoding processing, the sequence to be encoded is input to the input end on the left side of the encoder. After waiting for 15 clocks, the output end of the encoder starts to output the encoded sequence. While the sequence to be encoded is being input, the control sequence changes according to the above actual transformation method by the clock. Among them, at the first clock when the sequence to be encoded is input, the sequence is set to all 0, and then it increases by 1 every clock. The encoded sequence is x0 63 ={x0, x1,..., x 62 , x 63}, and the output of the encoder takes T out =N / M = 16 system clocks. At the first output clock, the 4-way output outputs x0, x1, x2, x3 from top to bottom in sequence. At the second output clock, the 4-way output outputs x4, x5, x6, x7 from top to bottom in sequence,..., at the i-th output clock, the 4-way output outputs x 4i-4 , x 4i-3 , x 4i-2 , x 4i-1 , …, at the 16th output clock, the 4-way output outputs x 60 , x 61 , x 62 , x 63 , and the encoding is completed. The total processing delay of the encoding is 31, and the throughput is approximately 2 bit / cycle, where bit / cycle represents bits per cycle.

[0079] Specifically, for a schematic diagram of the splitting process of the polarization code factor graph in each stage of a high-parallel polarization code encoder based on a feed-forward pipeline architecture with K = 3 provided in an embodiment of the present invention, please refer to Figure 4 shown. It can be seen from Figure 4 the splitting process of the polarization code factor graph with m = 2, K = 3, and N = 64. The polarization code encoding with N = 64 can be decomposed into 3 stages, namely stages 1 to 3 shown in the figure. Each stage can be completed by the generation matrix G4 represented by the gray dashed box. By reasonably planning the data flow path and reusing the generation matrix, the entire encoding process can be completed using 3 generation matrices.

[0080] Figure 4 shows the splitting situation of the encoder factor graph. Figure 3 The leftmost 4th-order encoding matrix in Figure 4 completes the encoding work in stage 1 of 16 , u 32 , u48 ,{u1,u 17 ,u 33 ,u 49},...,{u 15 ,u 31 ,u 47 ,u 63}; Figure 3 The middle 4-order coding matrix has completed Figure 4 the coding work in the second stage of the middle stage. The bits participating in the operation are grouped in fours and are, in order, Figure 3 The rightmost 4-order coding matrix in the middle has completed Figure 4 the coding work in the third stage of the middle stage. The bits participating in the operation are grouped in fours and are, in order, {u0, u1, u2, u3}, {u4, u5, u6, u7},..., {u 60 ,u 61 ,u 62 ,u 63}. The core coding module with configuration parameter k = 2 has completed the control of the data flow transformation between stage 1 and stage 2, and the core coding module with configuration parameter k = 1 has completed the control of the data flow transformation between stage 2 and stage 3.

[0081] In the embodiment of the present invention, by continuously reusing the coding matrix and the core coding module, the construction of the entire high-parallelism polar code encoder can be completed; the present invention can independently select the parallel level of the encoder and the coding level of the encoder as preset encoder parameters according to specific coding requirements to adapt to different resource requirements, rate requirements, and coding length requirements; compared with the existing encoders, the high-parallelism polar code encoder proposed in the embodiment of the present invention can effectively reduce the hardware complexity and improve the coding speed.

[0082] It should be noted that in the description of the present invention, it should be understood that the terms "first" and "second" are only used for descriptive purposes and cannot be construed as indicating or implying relative importance or implicitly specifying the quantity of the indicated technical features. Thus, the features defined with "first" and "second" may explicitly or implicitly include one or more of such features. In the description of the present invention, "a plurality" means two or more unless otherwise specifically defined.

[0083] The above are only the preferred embodiments of the present invention and are not intended to limit the protection scope of the present invention. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principle of the present invention are included in the protection scope of the present invention.

Claims

1. A high-parallelism polar code encoder based on a feedforward pipeline architecture, characterized in that: include: K encoding matrices and K-1 core encoding modules, K ≥ 2; where, Each coding matrix is ​​arranged horizontally at intervals, and a core coding module is set between adjacent coding matrices; the polar code encoding process of the high parallel polar code encoder is divided into K stages; each stage corresponds to a coding matrix; In each stage, the coding matrix operates on the received input data and its corresponding generator matrix based on the preset encoder parameters and the Kronecker product according to the polar code factor graph corresponding to the current stage to obtain a coded sequence; The core coding module controls its own commutation module to perform transposition processing on the coded sequence received by itself according to the external control signal to obtain the commutated coded sequence; transmits the commutated coded sequence to the coding matrix corresponding to the next connected stage, so that the commutated coded sequence is operated according to the data flow direction in the polar code factor diagram and the generation matrix corresponding to the next stage; The sequence to be encoded is input data of the first encoding matrix, and the encoded sequence output by the Kth encoding matrix is ​​the encoding result of the high parallelism polar code encoder.

2. The high-parallelism polar code encoder based on a feedforward pipeline architecture according to claim 1, characterized in that: The preset encoder parameters include: The number of parallel encoder stages M, the number of stages encoded by the encoder K and the code length encoded by the encoder N; wherein M is an integer power of 2.

3. The high-parallelism polar code encoder based on a feedforward pipeline architecture according to claim 2, characterized in that: The expression of the code length encoded by the encoder is as follows: N=M K ; Wherein, M represents the number of parallel encoder stages, and K represents the number of encoder encoding stages.

4. The high-parallelism polar code encoder based on a feedforward pipeline architecture according to claim 2, characterized in that: The encoding matrix is ​​an M-order encoding matrix, and the expression of the generator matrix corresponding to the encoding matrix is ​​as follows: in, represents the Kronecker power, m = log2M, M represents the number of parallel encoder levels, 5. The high-parallelism polar code encoder based on a feedforward pipeline architecture according to claim 2, characterized in that: The coding matrix is ​​an M-order coding matrix, and each M-order coding matrix includes XOR gates; where M represents the number of parallel encoder stages.

6. The high-parallelism polar code encoder based on a feedforward pipeline architecture according to claim 2, characterized in that: The core encoding module includes: A left D flip-flop group, a switching module and a right D flip-flop group; wherein the parallel level number of the switching module is M.

7. The high-parallelism polar code encoder based on a feedforward pipeline architecture according to claim 6, characterized in that: The total number of D flip-flops in each of the left D flip-flop group and the right D flip-flop group is (M-1)×M k-1 ;in, In the left D flip-flop group, the number of D flip-flops from the 1st to the Nth is 0 for the first item and M for the tolerance. k-1 The arithmetic progression of ; In the right D flip-flop group, the number of D flip-flops from the 1st to the Nth is the first term (M-1)×M k-1 , tolerance is -M k-1 An arithmetic progression; k represents the configuration parameters of the core encoding module.

8. The high-parallelism polar code encoder based on a feedforward pipeline architecture according to claim 2, characterized in that: The total number of D flip-flops in the high parallel polar code encoder is M K -M; where M represents the number of parallel encoder levels, and K represents the number of encoder encoding levels.

Images