Data processing method, communication node and storage medium

Abstract

The invention discloses a data processing method, a communication node and a storage medium. The data processing method comprises the following steps: acquiring a first bit sequence, a first modulation order, a second modulation order and a modulation symbol number, wherein the first bit sequence comprises a first subsequence and a second subsequence; performing shaping coding on the first sub-sequence according to the first modulation order to obtain a second bit sequence; performing channel coding on the second sub-sequence and the second bit sequence to obtain a third bit sequence; performing rate matching on the second sub-sequence, the second bit sequence and the third bit sequence based on the first modulation order and the second modulation order to obtain a fourth bit sequence; performing modulation mapping on the fourth bit sequence according to the second modulation order to obtain a modulation symbol sequence, and sending a signal comprising the modulation symbol sequence to the second communication node; wherein the first modulation order is not equal to the second modulation order, and the length of the modulation symbol sequence is equal to the number of modulation symbols.

Description

Technical Field

[0001] This application relates to the field of communication technologies, and for example, relates to a data processing method, a communication node, and a storage medium. Background Art

[0002] In the fifth-generation (5G) mobile communication system of the 3rd Generation Partnership Project (3GPP), in order to achieve the same transmission spectral efficiency, Quadrature Amplitude Modulation (QAM) needs to increase the additional signal-to-noise ratio (up to 1.53 dB at most) compared with the optimal Gaussian signal. Currently, the most effective and least complex transmission scheme for approximating Gaussian signals is the Probabilistic Amplitude Shaping (PAS) scheme based on unequal probability QAM constellations. The PAS scheme adds a shaping encoder before channel coding to achieve unequal probability transmission of QAM constellation points. The shaping encoder can be a distribution matcher or a structure based on block codes. No matter which type of shaping encoder it is, in the case of retransmission, in order to adapt to channel changes, there will be a problem that the modulation order of the modulation mapper is different from the modulation order of the shaping coding in the first transmission. The current solution is usually to perform low code rate coding at the first transmission, and at the retransmission, continuously select some bits of the first transmission coding starting from a certain starting index for transmission. However, for the PAS scheme, using the current solution is not only not applicable to the scenario where the modulation order of the retransmission modulation mapper is different from the modulation order of the shaping encoder in the first transmission, but also causes the distribution of the modulated constellation points to tend to be equally probable, losing the gain of probability shaping. Summary of the Invention

[0003] An embodiment of this application provides a data processing method, which is applied to a first communication node. The method includes:

[0004] Obtain a first bit sequence, a first modulation order, a second modulation order, and the number of modulation symbols. The first bit sequence includes a first subsequence and a second subsequence;

[0005] Perform shaping coding on the first subsequence according to the first modulation order to obtain a second bit sequence;

[0006] Perform channel coding on the second subsequence and the second bit sequence to obtain a third bit sequence;

[0007] Perform rate matching on the second subsequence, the second bit sequence, and the third bit sequence based on the first modulation order and the second modulation order to obtain a fourth bit sequence;

[0008] Modulate and map the fourth bit sequence according to the second modulation order to obtain a modulation symbol sequence, and send a signal including the modulation symbol sequence to a second communication node;

[0009] Wherein, the first modulation order and the second modulation order are not equal, the length of the modulation symbol sequence is equal to the number of modulation symbols, and each symbol in the modulation symbol sequence is a constellation point in the modulation constellation corresponding to the second modulation order.

[0010] An embodiment of the present application provides a data processing method, which is applied to a second communication node. The method includes:

[0011] Receive a signal including a modulation symbol sequence sent by a first communication node, and obtain a first modulation order, a second modulation order, and the number of modulation symbols;

[0012] Demodulate the signal based on the second modulation order to obtain soft information of the fourth bit sequence;

[0013] Perform rate dematching according to the first modulation order, the second modulation order, and the soft information of the fourth bit sequence to obtain the soft information corresponding to the third bit sequence, the second bit sequence, and the second subsequence respectively;

[0014] Perform channel decoding on the soft information corresponding to the third bit sequence, the second bit sequence, and the second subsequence respectively to obtain an estimate of the second subsequence and an estimate of the second bit sequence;

[0015] Perform shaping decoding on the estimate of the second bit sequence according to the first modulation order to obtain an estimate of the first subsequence;

[0016] Determine an estimate of the first bit sequence from the estimate of the first subsequence and the estimate of the second subsequence;

[0017] Wherein, the first modulation order and the second modulation order are not equal, the length of the modulation symbol sequence is equal to the number of modulation symbols, each symbol in the modulation symbol sequence is a constellation point in the modulation constellation corresponding to the second modulation order, and the soft information is a log-likelihood ratio or a probability value.

[0018] An embodiment of the present application provides a communication node, including: a processor; the processor is used to implement the data processing method of any embodiment when executing a computer program.

[0019] An embodiment of the application further provides a computer-readable storage medium, storing a computer program, and when the computer program is executed by a processor, the data processing method of any embodiment is implemented.

[0020] More descriptions are provided in the accompanying drawings, the detailed implementation manners, and the claims regarding the above embodiments and other aspects of the present application and their implementation manners. Description of the Drawings

[0021] Figure 1 It is a schematic diagram of the networking of a wireless communication system provided by an embodiment of the present application;

[0022] Figure 2 It is a block diagram of a transmitter link with probability amplitude shaping provided by some embodiments of the present application;

[0023] Figure 3 It is a block diagram of a shaping encoder including shaping block segmentation provided by an embodiment of the present application;

[0024] Figure 4 It is a block diagram of a low-density parity-check coding chain provided by an embodiment of the present application;

[0025] Figure 5 It is a block diagram of a shaping encoder provided by an embodiment of the present application;

[0026] Figure 6 It is a block diagram of a shaping encoder link based on a block code provided by an embodiment of the present application;

[0027] Figure 7 It is a block diagram of a shaping encoder based on a block code including shaping block segmentation provided by an embodiment of the present application;

[0028] Figure 8 It is a first flowchart of a data processing method provided by an embodiment of the present application;

[0029] Figure 9 It is a second flowchart of a data processing method provided by an embodiment of the present application;

[0030] Figure 10 It is a first structural diagram of a data processing device provided by an embodiment of the present application;

[0031] Figure 11 It is a second structural diagram of a data processing device provided by an embodiment of the present application;

[0032] Figure 12 It is a structural diagram of a BS provided by an embodiment of the present application;

[0033] Figure 13 It is a structural diagram of a UE provided by an embodiment of the present application. Detailed Implementation Manner

[0034] It should be understood that the specific embodiments described herein are merely used to explain the present application and are not used to limit the present application. The embodiments of the present application will be described in detail below with reference to the accompanying drawings.

[0035] The communication method provided by the embodiments of the present application can be applied to systems of various communication standards. For example, the systems to which the communication method provided by the embodiments of the present application can be applied include, but are not limited to, long term evolution (LTE) systems, various versions evolved from LTE, fifth generation mobile communication technology (5G) systems, future mobile communication networks (such as sixth generation 6G mobile communication networks (6th generation mobile communication network, 6G), seventh generation 7G mobile communication networks (7th generation mobile communication network, 7G)), or various communication convergence systems, etc. In addition, the communication method provided by the embodiments of the present application can also be applied to future-oriented communication systems, etc.

[0036] In the description of the present disclosure, mod(x,y) represents the remainder operation, that is, the remainder of x divided by y. Or floor(x) represents the floor function, that is, the largest integer less than or equal to x. Or ceil(x) represents the ceiling function, that is, the smallest integer greater than or equal to x. The notations S(n)~S(p) and the notation [S(n),…,S(p)] are equivalent and interchangeable, both representing a sequence containing p - n + 1 elements. The number of elements p - n + 1 contained in the sequence S(n)~S(p) is also referred to as the length or size of the sequence. Without causing ambiguity, the sequence [S(n),…,S(p)] can also be referred to by the letter S. For two sequences S1 = [S1(n1),…,S1(p1)] and S2 = [S2(n2),…,S2(p2)], [S1,S2] represents the sequence [S1(n1),…,S1(p1),S2(n2),…,S2(p2)] of length p1 - n1 + p2 - n2 + 2 formed by splicing the sequences S1 = [S1(n1),…,S1(p1)] and S2 = [S2(n2),…,S2(p2)].

[0037] Figure 1 is a schematic diagram of the networking of a wireless communication system provided by the embodiments of the present application. As Figure 1As shown, the wireless communication system includes, but is not limited to, a first communication node 10 and a second communication node 20, and wireless signals can be transmitted, received, and related interactions can occur between the first communication node 10 and the second communication node 20.

[0038] In some embodiments, the first communication node 10 and the second communication node 20 satisfy one of the following: the first communication node 10 is a base station and the second communication node 20 is a terminal; the first communication node 10 is a terminal and the second communication node 20 is a base station; the first communication node 10 is a terminal and the second communication node 20 is a terminal.

[0039] In some examples, a terminal can be a device with wireless transceiver capabilities that can be deployed on land, including indoor or outdoor, handheld, wearable, or vehicle-mounted; it can also be deployed on water (such as on a ship, etc.); it can also be deployed in the air (such as on an airplane, balloon, satellite, etc.). A terminal can be a mobile phone, a tablet computer, a computer with wireless transceiver capabilities, a virtual reality (VR) terminal, an augmented reality (AR) terminal, a wireless terminal in industrial control, a wireless terminal in unmanned driving, a wireless terminal in remote medical care, a wireless terminal in a smart grid), a wireless terminal in transportation safety, a wireless terminal in a smart city, a wireless terminal in a smart home, and so on. The embodiments of the present application do not limit the application scenarios. A terminal can sometimes also be referred to as a user, a user equipment (UE), an access terminal, a UE unit, a UE station, a mobile station, a mobile unit, a remote station, a remote terminal, a mobile device, a UE terminal, a wireless communication device, a UE agent, or a UE device, etc., and the embodiments of the present application do not limit this.

[0040] In some examples, a base station can be a base station (BS) or an evolved node B (eNB or eNodeB) in long term evolution (LTE), long term evolution advanced (LTEA), a base station device in a 5G network, or a base station in a future communication system, etc. For example, a gNB, gNodeB, hNB, hNodeB, iNB, or iNodeB. A base station can include various macro base stations, micro base stations, home base stations, wireless remote radio heads, reconfigurable intelligent surfaces (RISs), routers, wireless fidelity (WIFI) devices, or various network-side devices such as a primary cell and a cooperating cell.

[0041] It should be noted thatFigure 1 This is only an exemplary framework diagram, Figure 1 The number of devices included and the names of each device are not limited.

[0042] To make the objectives, technical solutions, and advantages of the embodiments of the present application clearer, the following will clearly and completely describe the technical solutions in the embodiments of the present application with reference to the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the scope of protection of the present application.

[0043] It should be noted that the terms "first", "second", etc. in the description and claims of the present application and the above-mentioned drawings are used to distinguish similar objects, and do not necessarily need to describe a specific order or sequence. It should be understood that such used data can be interchanged under appropriate circumstances so that the embodiments of the present application described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "include", "have" and any variations thereof are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or device that includes a series of steps or units does not necessarily have to be limited to those steps or units clearly listed, but may include other steps or units not clearly listed or inherent to these processes, methods, products, or devices.

[0044] The embodiments of the present application provide a data processing method. Implementing this method can bring the following beneficial effects: For the PAS scheme, in a scenario where the modulation order of the modulation mapper applicable to retransmission is different from the modulation order of the shaping encoder for the first transmission, the distribution of the modulated constellation points is still non-equiprobable, maintaining the characteristics of probability shaping.

[0045] Before introducing the data processing method of the present application, the existing PAS scheme will be introduced first:

[0046] Figure 2 The block diagram of a transmitter link for probability amplitude shaping provided by some embodiments of the present application includes a splitter 201, a shaping encoder 202, a channel encoder 203, and a modulation mapper 204. Among them, the splitter 201 is used to split, divide, or separate the first bit sequence into a first subsequence and a second subsequence.

[0047] The first bit sequence can be a bit sequence b(0) to b(K-1) including K bits. The first subsequence is a bit sequence [b1(0), …, b1(K1-1)] including K1 bits, and the second subsequence is a bit sequence [b2(0), …, b2(K2-1)] including K2 bits, where K1 and K2 are non-negative integers, and K, K1, and K2 satisfy K = K1 + K2.

[0048] The shaping encoder 202 is used to obtain a shaping encoded output bit sequence c(0) to c(N1-1) of length N1 from the K1 bits of the input first subsequence b1(0) to b1(K1-1) according to a specified non-uniform probability distribution.

[0049] In some embodiments, the ratio K1 / N1 of the number of bits K1 of the first subsequence b1(0) to b1(K1-1) to the number of bits N1 of the shaping encoded output bit sequence c(0) to c(N1-1) is called the shaping code rate. In this application, the shaping code rate is denoted as R sh . Therefore, there is R sh = K1 / N1.

[0050] In some embodiments, the first subsequence b1(0) to b1(K1-1) is divided into multiple blocks and then respectively subjected to shaping encoding to obtain bit sequences c of multiple shaping blocks r . The bit sequences c of multiple shaping blocks r are concatenated to obtain a shaping encoded output bit sequence c(0) to c(N1-1). As Figure 3 is a block diagram of a shaping encoder including shaping block splitting provided by an embodiment of this application, including shaping block splitting 601, distribution matcher 602, shaping block concatenation 603, and amplitude-to-bit mapper 604.

[0051] The channel encoder 203 takes the second subsequence b2(0) to b2(K2-1) output by the splitter 201 and the shaping encoded output bit sequence c(0) to c(N1-1) output by the shaping encoder 202 as inputs. The channel encoder 203 encodes the inputs to obtain a channel encoder output bit sequence g(0) to g(Ng-1) of length Ng corresponding to multiple shaping blocks. Where Ng is a positive integer.

[0052] In some embodiments, the channel encoder output bit sequence g(0) to g(Ng-1) is called the codeword of the channel encoder.

[0053] In some embodiments, the channel encoder output bit sequence g(0) to g(Ng-1) is called the parity bit sequence of the channel encoder.

[0054] In some embodiments, the output bit sequence g(0) to g(Ng-1) of the channel encoder includes all the bits of the shaping-coded output bit sequence c(0) to c(N1-1) output by the shaping encoder 202.

[0055] In some embodiments, the output bit sequence g(0) to g(Ng-1) of the channel encoder includes some bits of the second subsequence b2(0) to b2(K2-1) output by the splitter 201.

[0056] In some embodiments, the output bit sequence g(0) to g(Ng-1) of the channel encoder includes all the bits of the second subsequence b2(0) to b2(K2-1) output by the splitter 201.

[0057] In some embodiments, the output bit sequence g(0) to g(Ng-1) of the channel encoder includes Np parity bits.

[0058] In some embodiments, the channel encoder 203 is generally implemented by a binary forward error correction (FEC) code.

[0059] In some embodiments, the forward error correction code can be one of the following: polar code, low density parity check coding (LDPC), convolutional code, turbo code, Reed-Muller code, Reed-Solomon code, Bose-Chaudhuri-Hocquenghem code, concatenated code, cyclic code, block code, Hamming code, Golay code, repetition code, single parity check code.

[0060] In some embodiments, the channel encoder 203 may include at least one of the following operations: cyclic redundancy check (CRC) bit attachment, code block segmentation, code block CRC attachment, forward error correction coding, low density parity check coding, polar coding, rate matching, bit selection, bit interleaving, code block concatenation. As Figure 4 The block diagram of a channel encoder 203 based on low density parity check coding provided by an embodiment of the present application is shown, including transport block (TB) CRC bit attachment 501, code block segmentation and code block CRC attachment 502, LDPC coding 503, rate matching 504, code block concatenation 505.

[0061] A specific method for rate matching 504 is introduced in detail below.

[0062] Rate matching 504 is used to obtain the LDPC-coded bit sequence d output from LDPC coding 503 rDetermine the output bit sequence of rate matching, where r is the index of the segmented code block in code block segmentation and code block CRC attachment 502.

[0063] In some embodiments, rate matching 504 determines the output bit sequence of rate matching from the LDPC-encoded bit sequence d based on the following parameters r Determine the output bit sequence of rate matching: cyclic buffer length Ncb, number of transport layers N layer , modulation order Qm, number of code blocks C, total number of encoded bits Ng, redundancy version number rv id , redundancy version start position k0.

[0064] In some embodiments, rate matching 504 includes two modules: bit selection 5041 and bit interleaving 5042.

[0065] Among them, for the code block with index r, bit selection 5041 determines the bit selection sequence e from the LDPC-encoded bit sequence d according to the following parameters r Determine the bit selection sequence e r : cyclic buffer length Ncb, number of transport layers N layer , lifting value Z, modulation order Qm, number of code blocks C, total number of encoded bits Ng, redundancy version number rv id , redundancy version start position k0.

[0066] In some embodiments, the cyclic buffer length Ncb is determined by a high-layer parameter.

[0067] In some embodiments, the number of transport layers N layer is determined by a high-layer parameter.

[0068] In some embodiments, the lifting value Z is the lifting value used to determine the LDPC encoding check matrix in LDPC encoding 503.

[0069] In some embodiments, the modulation order Qm is the modulation order of the modulation constellation used by the modulation mapper 204 in the transmitter link of probability amplitude shaping.

[0070] In some embodiments, the number of code blocks C is the number of code blocks determined by code block segmentation and code block CRC attachment 502 in the LDPC encoding chain.

[0071] In some embodiments, the total number of encoded bits Ng is the total number of encoded bits available for the transmission of the transport block, which is obtained by multiplying the number of resource elements Nre available for data transmission, determined by a high-layer parameter, the number of transport layers N layer , and the modulation order Qm, that is, G = N layer ×Nre×Qm.

[0072] In some embodiments, the redundancy version number rv idDetermined by high-level parameters.

[0073] In some embodiments, the redundancy version number rv id is obtained from the downlink control information.

[0074] In some embodiments, the redundancy version number rv id is obtained from the uplink control information.

[0075] In some embodiments, the redundancy version starting position k0 is determined by the base graph used in the LDPC encoding 503, the redundancy version number rv id , the cyclic buffer length Ncb, and the lifting value Z.

[0076] Exemplarily, Table 1 shows the starting positions k0 of different redundancy versions.

[0077] Table 1

[0078]

[0079] The specific operations of the bit selection 5041 include:

[0080] Step 1: Set the length E r of the bit selection sequence e r for the code block with index r. When the code block index r is less than or equal to Set Otherwise, set

[0081] Step 2: Determine the redundancy version starting position k0 from Table 1 according to the base graph used in the LDPC code, the redundancy version number rv id , the cyclic buffer length Ncb, and the lifting value Z.

[0082] Step 3: For the code block with index r, starting from the bit with index k0 in the LDPC-encoded bit sequence d r , select E r non-padding bits in a cycle with the cyclic buffer length Ncb to obtain the bit selection sequence e r .

[0083] The bit interleaving 5042 determines the bit interleaving sequence f r based on the bit selection sequence e r with length E for the code block with index r. r .

[0084] In some embodiments, the bit interleaving 5042 determines the bit interleaving sequence f r based on the following parameters for the code block with index r from the bit selection sequence e r with length E.r : Bit selection sequence e r , Bit selection sequence e r 's length E r , Modulation order Qm.

[0085] In some embodiments, the modulation order Qm is the modulation order of the modulation constellation used by the modulation mapper 204 in the transmitter link of probability amplitude shaping.

[0086] In some embodiments, the specific operation of bit interleaving 5042 includes: for the bit selection sequence e of index r r , write the bit selection sequence e r row by row and then column by column into a buffer matrix of Qm rows and E r / Qm columns, and then read it out column by column and then row by row into a bit interleaved sequence f r of the same length E r , that is, for r = 0, 1,..., C - 1, j = 0, 1,..., E r / Qm - 1, i = 0, 1,..., Qm - 1, set f r (i + j·Qm) = e r (i·E r / Qm + j).

[0087] In some embodiments, the C bit interleaved sequences f0, f1,..., f output by bit interleaving 5042 C-1 are also the output bit sequences of rate matching 504 in the LDPC coding chain.

[0088] In some embodiments, the C bit interleaved sequences f0, f1,..., f output by bit interleaving 5042 C-1 are concatenated to obtain the channel encoder output bit sequence g(0) ~ g(Ng - 1).

[0089] The modulation mapper 204 takes the encoded channel encoder output bit sequence g(0) ~ g(Ng - 1) as input. The modulation mapper 204 is configured to map the channel encoder output bit sequence (g) to constellation symbols (such as QAM symbols, amplitude - shift keying (ASK) symbols) of modulation order Qm, and finally obtain the shaped symbol sequence X(0) ~ X(Nx - 1), where Nx is the length of the shaped symbol sequence.

[0090] In some embodiments, Nx = Ng / Qm, where Nx is the length of the shaped symbol sequence, the length of the channel encoder output bit sequence g, and Qm is the modulation order of the modulation constellation used by the modulation mapper 204.

[0091] In some embodiments, the transmitter link further includes a transmitter. The shaped symbol sequence can be transmitted through the transmitter over a wireless channel.

[0092] As Figure 5 Shown is a block diagram of a shaping encoder 202 provided by an embodiment of the present application, including a distribution matcher 301 and an amplitude-to-bit mapper 302. Among them, the distribution matcher 301 is used to map K1 bits of the first subsequence into an amplitude symbol sequence A(0) to A(NA-1) with a specified non-uniform probability distribution, where NA is a positive integer.

[0093] In some embodiments, each element A(j) in the amplitude symbol sequence takes values from the set {1, 3, 5,...,(2 Qm / 2 - 3),(2 Qm / 2 - 1)}, that is, A(j) ∈ {1, 3, 5,...,(2 Qm / 2 - 3),(2 Qm / 2 - 1)}, where Qm is the modulation order of the quadrature amplitude modulation constellation used by the modulation mapper 204 in the transmitter link.

[0094] In some embodiments, each element A(j) in the amplitude symbol sequence takes values from the amplitude set {1, 3, 5,...,(2 Qm - 3),(2 Qm - 1)}, where Qm is the modulation order of the amplitude shift keying modulation used by the modulation mapper 204 in the transmitter link. Hereinafter, the set {1, 3, 5,...,(2 Qm / 2 - 3),(2 Qm / 2 - 1)} or {1, 3, 5,...,(2 Qm - 3),(2 Qm - 1)} is referred to as the amplitude set.

[0095] The amplitude-to-bit mapper 302 takes the amplitude symbol sequence A(0) to A(NA-1) output by the distribution matcher 301 as input; the amplitude-to-bit mapper 302 can output an ordered bit sequence c(0) to c(N1-1).

[0096] In some embodiments, the amplitude-to-bit mapper 302 converts each amplitude A(j) in the amplitude symbol sequence into Qm / 2 - 1 bits c(j·(Qm / 2 - 1)), c(j·(Qm / 2 - 1)+1), …, c(j·(Qm / 2 - 1)+Qm / 2 - 2) according to a preset mapping method, and then concatenates them into an ordered bit sequence c(0) to c(N1 - 1), where the length N1 of the ordered bit sequence c(0) to c(N1 - 1) is equal to NA×(Qm / 2 - 1), and Qm is the modulation order of the quadrature amplitude modulation constellation used by the modulation mapper 204 in the transmitter link.

[0097] In some embodiments, the amplitude-to-bit mapper 302 converts each amplitude A(j) in the amplitude symbol sequence into Qm - 1 bits c(j·(Qm - 1)), c(j·(Qm - 1)+1), …, c(j·(Qm - 1)+Qm - 2) according to a preset mapping method, and then concatenates them into an ordered bit sequence c(0) to c(N1 - 1), where the length N1 of the ordered bit sequence c(0) to c(N1 - 1) is equal to NA×(Qm - 1), and Qm is the modulation order of the amplitude shift keying modulation used by the modulation mapper 204 in the transmitter link.

[0098] Exemplarily, Table 2 shows the amplitude-to-bit mapping methods of the quadrature amplitude modulation constellations with modulation orders Qm = 4, 6, 8, 10, and also the amplitude-to-bit mapping methods of the amplitude shift keying modulations corresponding to modulation orders Qm = 2, 3, 4, 5 respectively.

[0099] Table 2

[0100]

[0101] Among them, the bit strings mapped by the amplitude in the case of different values of Qm are shown, and N / A means not applicable.

[0102] It should be noted that the distribution matcher 301 is the key of the PAS architecture and is the earliest shaping encoder implementation method in the PAS architecture. The transmitter with the PAS architecture can provide modulation symbols with non-uniform (i.e., shaped) probabilities for the constellation diagram through the distribution matcher. Relying on the PAS technology, the distribution matcher 301 can take a sequence containing K1 independent bits as input and provide a sequence of amplitude symbols (containing NA) with non-uniform probabilities as output, where the amplitude symbol sequence is used to represent the message of the first subsequence b1(0) to b1(K1 - 1).

[0103] In some embodiments, the distribution matcher can use any one of a variety of suitable algorithms and any one of a variety of suitable configurations.

[0104] In some embodiments, the distribution matcher 301 can be one of the following: constant-composition distribution matcher (CCDM), bit-level distribution matcher (BL-DM), product distribution matcher (PDM), multi-composition distribution matcher (MCDM), multiset-partition distribution matcher (MPDM), partition-based distribution matcher, parallel magnitude distribution matcher based on subset sorting, streaming distribution matcher, prefix code distribution matcher, shell mapping, enumerative sphere shaping (ESS), approximate enumerative sphere shaping (AESS), partial enumerative sphere shaping (PESS), Huffman-coded sphere shaping (HCSS), framing of variable-length distribution matcher output to fixed-length code blocks, distribution matcher with flag ratio control, hierarchical distribution matcher, distribution matcher based on parallel dichotomy, polarization coding distribution matcher.

[0105] It should be noted that the above-listed distribution matcher technologies are different from each other. However, the general purpose of the distribution matcher is to generate a probabilistic deterministic symbol sequence for constructing a shaped signal, for example, an ASK signal or a QAM signal.

[0106] Figure 6 A block diagram of a shaping encoder link based on a block code is given, including a log-likelihood ratio generator 401, a channel decoder 402, a channel encoder 403, a bit mask 404, and a multiplexer 405. Among them, the shaping encoder link can obtain a group of information bits, for example, the bit sequence b1(0)~b1(K1-1) of the first subsequence output by the splitter 201, that is, u = b1.

[0107] In some embodiments, the group of information bits may be uniformly distributed and may be a bit-level sequence u = [u0, u1, u2, …, u m-1, where m is the modulation order of amplitude shift keying modulation used by the modulation mapper in the transmitter link or m is half of the modulation order Qm of quadrature amplitude modulation used by the modulation mapper in the transmitter link.

[0108] Exemplarily, assume that the transmitter link uses a 64-QAM constellation or equivalently an 8-ASK constellation, and the number of bits carried by each amplitude symbol is or m = log28 = 3. At this time, u = [u0, u1, u2]. The information bit group may be input to the log-likelihood ratio generator 401 in the shaping encoder link. The log-likelihood ratio generator 401 is configured to generate a set of log-likelihood ratios (Log-Likelihood Ratio, LLR) LLR(0) to LLR(NL-1) corresponding to the information bit group.

[0109] In some embodiments, the log-likelihood ratio generator 401 also divides the log-likelihood ratio group into multiple shaping blocks according to the length of the shaping block based on at least a part of the log-likelihood ratio group for the channel decoder 402 to perform decoding. As Figure 7 shown is a block diagram of a shaping encoder including shaping block segmentation provided by an embodiment of the present application, including: a log-likelihood ratio generator 701, a shaping block segmentation 702, a channel decoder 703, a channel encoder 704, a shaping block concatenation 705, a bit mask and concatenation 706.

[0110] In some embodiments, the goal of probability amplitude shaping is to generate a covering code to maximize power savings after bit mask processing. Therefore, the log-likelihood ratio generator 401 can be configured to generate log-likelihood ratios LLR(0) to LLR(NL-1) for the information bit group according to the power savings caused by bit flipping.

[0111] Exemplarily, assume that (u0, u1) in the amplitude symbol sequence u corresponding to the information bit group is equal to (1, 1). Inverting or masking u0 will result in whose associated power change is 16. In this case, the corresponding log-likelihood ratio LLR is denoted as "16".

[0112] Exemplarily, Table 3 shows examples of bit flipping, log-likelihood ratio LLR values, and power savings.

[0113] Table 3

[0114]

[0115] In some embodiments, dividing the log-likelihood ratio group LLR(0) to LLR(NL-1) into multiple shaping blocks can be based on one or more parameters. For example, these parameters may include the number of shaping blocks (Cs), which can be defined as Nre is the number of resource elements (REs) for transmitting information bit groups, and Nsmax is the maximum shaping block length. In some cases, Nsmax can be a fixed value in a wireless communication standard, such as 512 (i.e., 2^9). The shaping block length (Ns) can be defined as If the length NL of the log-likelihood ratio group LLR(0) to LLR(NL - 1) or the input symbol length Nin (e.g., it may be defined as NL = Nin = 2 × Nre) is greater than the shaping block length (Ns), then multiple shaping blocks can be generated by splitting.

[0116] In some embodiments, after splitting the log-likelihood ratio group LLR(0) to LLR(NL - 1) into multiple shaping blocks, the shaping blocks can be sent to the channel decoder 402.

[0117] The channel decoder 402 is configured to decode multiple shaping blocks using a linear code or a forward error correction code to obtain shaping bits (s(0) to s(Ks - 1)).

[0118] Exemplarily, the channel decoder 402 can decode multiple shaping blocks according to the shaping code rate (R sh ), and the shaping code rate can be defined as R sh = Ks / Ns, where Ks is the number of shaping bits (s), and Ns is the codeword length output by the channel encoder 403 (i.e., the shaping block length).

[0119] Exemplarily, the channel decoder 402 can decode multiple shaping blocks according to the shaping code rate (R sh ), and the shaping code rate can be defined as R sh = Ns / Ks, where Ks is the number of shaping bits (s), and Ns is the codeword length output by the channel encoder 403 (i.e., the shaping block length).

[0120] In some embodiments, the linear code or FEC code can be determined depending on the shaping code rate R sh and the shaping block length Ns.

[0121] In some embodiments, the generator matrix (G) of the linear code or FEC code can be constructed based on the shaping code rate R sh and the shaping block length Ns.

[0122] In some embodiments, the linear code or FEC code can be one of the following: polar code, low-density parity-check code, convolutional code, turbo code, Reed-Muller code, Reed-Solomon code, Bose-Chaudhuri-Hocquenghem code, concatenated code, cyclic code, block code, Hamming code, Golay code, repetition code, single parity-check code.

[0123] In some embodiments, the shaping block length (Ns) can be determined based on the "rate distortion bound" and the decoding process of linear codes or FEC codes.

[0124] The channel encoder 403 takes the shaped bit sequence (s) as input. And it can re-encode the shaped bit sequence according to the shaping code rate and generate shaped codewords v(0) to v(Nv-1) using a linear code or an FEC code.

[0125] Exemplarily, to obtain the shaped codeword v, the channel encoder 403 can multiply the shaped bit sequence (s) by the generator matrix (G) of the linear code or FEC code according to v = s × G, where the multiplication is performed in the Galois field.

[0126] The bit mask module 404 can perform a shaping operation on a subset of the information bit group u to generate a shaped information bit sequence

[0127] It should be noted that the goal of shaping is to maximize power savings. Therefore, to maximize power savings, the bit mask module 404 can be configured to apply the shaped codeword v to the bit layer of the amplitude symbol that has the greatest impact on the signal power, such as the most-significant bit (MSB) u0.

[0128] Exemplarily, the most-significant bit MSB can be the leftmost bit in the bit string of Table 2.

[0129] Exemplarily, the bit mask module 404 may perform a shaping operation on the MSB and according to apply it to the shaped codeword v, where represents bitwise modulo-2 addition.

[0130] The multiplexer 405 takes the shaped information bit sequence (e.g., ), the remaining unshaped subset in the information bit group u (e.g., u1, u2,..., u m-1 ) and the shaped bit sequence (s) as inputs. And based on the inputs, it generates the shaped encoder output bit sequence c(0) to c(N1-1). In this application, the shaped information bit sequence (e.g., ) and the remaining unshaped subset in the information bit group u (e.g., u1, u2,..., u m-1 ) are collectively referred to as the bit mask bit sequence, i.e., the sequence is the bit mask bit sequence.

[0131] In some embodiments, the multiplexer 405 combines the shaped information bit sequence, the remaining unshaped subset u1, u2,..., u in the information bit group u m-1and the integer bit sequence(s) are combined into the output bit sequence c(0) to c(N1-1) of the integer encoder.

[0132] Exemplarily,

[0133] In some other embodiments,

[0134] In still some other embodiments,

[0135] In still some other embodiments,

[0136] In some embodiments, u in the unshaped remaining subset of the information bit group u j is a sequence of length Nx, where Nx is the length of the modulation symbol sequence output by the modulation mapper 204 in the transmitter link and the modulation mapper 204 uses amplitude shift keying modulation.

[0137] In some embodiments, u in the unshaped remaining subset of the information bit group u j is a sequence of length 2×Nx, where Nx is the length of the modulation symbol sequence output by the modulation mapper 204 in the transmitter link and the modulation mapper 204 uses quadrature amplitude modulation.

[0138] Next, the data processing method of the present application and its technical effects will be described.

[0139] Figure 8 is the first process schematic diagram of a data processing method provided by an embodiment of the present application. As Figure 8 shown, the method provided in this embodiment is applicable to a first communication node (which may also be referred to as a first communication node device, or a first node, or a first device). The method includes the following steps.

[0140] S110. Obtain a first bit sequence, a first modulation order, a second modulation order, and the number of modulation symbols.

[0141] In some embodiments, the first modulation order is used for transmission when the new data indication signaling remains unchanged.

[0142] In some embodiments, the first modulation order is used for the first transmission of the first bit sequence.

[0143] In some embodiments, the second modulation order is used for the retransmission of the first bit sequence.

[0144] In some embodiments, the first modulation order (denoted as Qm1) and the second modulation order (denoted as Qm2) are not equal.

[0145] In some embodiments, the first bit sequence (denoted as b) includes a first subsequence (denoted as b1) and a second subsequence (denoted as b2).

[0146] In some embodiments, the first modulation order is not equal to the second modulation order. It may be that the first modulation order is greater than the second modulation order. It may also be that the first modulation order is less than the second modulation order.

[0147] In some embodiments, the first modulation order is equal to the second modulation order.

[0148] In some embodiments, the first bit sequence may be referred to as an information bit sequence, a payload bit sequence, a transport block, a transport block bit sequence, a code block, or a code block bit sequence.

[0149] In some embodiments, the first bit sequence may be a bit sequence b(0) to b(K - 1) including K bits. The first subsequence is a bit sequence [b1(0), …, b1(K1 - 1)] including K1 bits, and the second subsequence is a bit sequence [b2(0), …, b2(K2 - 1)] including K2 bits, where K1 and K2 are non-negative integers, and K, K1, and K2 satisfy K = K1 + K2.

[0150] In some embodiments, it may be b = [b1, b2], or it may also be b = [b2, b1].

[0151] In some embodiments, the first bit sequence may be a sequence composed of the bits of a transport block, where the length or the number of bits K of the bit sequence b(0) to b(K - 1) is the transport block size. The first bit sequence may also be a sequence obtained by concatenating the bits of the transport block and the cyclic redundancy check bits calculated from the bits of the transport block, where the length or the number of bits K of the bit sequence b(0) to b(K - 1) is the sum of the number of bits of the transport block and the number of cyclic redundancy check bits calculated from the bits of the transport block.

[0152] In some embodiments, the length K1 of the first subsequence b1 may be a multiple of Qm1 / 2 - 1. The length K1 of the first subsequence b1 may also be a multiple of Qm1 - 1.

[0153] In a specific example, K1 = Nx × (Qm1 - 1), where Nx is the number of modulation symbols. In another specific example, K1 = Cs × Ns × (Qm1 - 1), where is the number of shaping blocks, is the shaping block length, Nx is the number of modulation symbols, and Nsmax is the maximum shaping block length. In yet another specific example, K1 = 2 × Nx × (Qm1 / 2 - 1), where Nx is the number of modulation symbols. In still another specific example, K1 = Cs × Ns × (Qm1 / 2 - 1), where is the number of shaping blocks, is the shaping block length, Nx is the number of modulation symbols, and Nsmax is the maximum shaping block length.

[0154] In some embodiments, the first communication node may obtain the first bit sequence from a higher layer.

[0155] In some embodiments, the first communication node may obtain the first modulation order by obtaining it from a higher layer, by determining it according to control information, or by determining it according to downlink control information.

[0156] In some embodiments, the first communication node may obtain the second modulation order by obtaining it from a higher layer, by determining it according to control information, or by determining it according to downlink control information.

[0157] In some embodiments, the first communication node may obtain the number of modulation symbols by obtaining it from a higher layer, by determining it according to control information, or by determining it according to downlink control information.

[0158] S120. Perform shaping encoding on the first subsequence according to the first modulation order to obtain a second bit sequence.

[0159] In some embodiments, the second bit sequence (denoted as c) is the output bit sequence of the shaping encoder, the output bit sequence of the amplitude-to-bit mapper, or the output bit sequence of the multiplexer.

[0160] In some embodiments, the second bit sequence includes a part of the bits of the first subsequence or the shaping bit sequence output by the channel decoder.

[0161] In one embodiment, in shaping encoding, a distribution matcher is used (a specific example is as Figure 3 shown, and another specific example is as Figure 5In the case shown); perform shaping encoding on the first subsequence according to the first modulation order to obtain a second bit sequence, including: encoding the first subsequence using a distribution matcher according to the first modulation order to obtain an amplitude symbol sequence with a non-uniform probability distribution, denoted as A(0)~A(NA-1); converting each element A(j) in the amplitude symbol sequence into Qm1 / 2-1 bits according to a preset mapping method, such as: c(j·(Qm1 / 2-1)), c(j·(Qm1 / 2-1)+1), …, c(j·(Qm1 / 2-1)+Qm1 / 2-2); concatenating the Qm1 / 2-1 bits into a second bit sequence c(0)~c(N1-1); where each element A(j) in the amplitude symbol sequence takes values from the amplitude set {1, 3, 5, ..., (2 Qm1 / 2 -3), (2 Qm1 / 2 -1)}, the length of the amplitude symbol sequence is NA, NA = 2×Nx, the length of the second bit sequence is N1, N1 = NA×(Qm1 / 2-1) or N1 = Nx×(Qm1-2), Nx is the number of modulation symbols, and Qm1 is the first modulation order.

[0162] In a specific example, Qm1 = 8, the amplitude set is {1, 3, 5, 7, 9, 11, 13, 15}, the amplitude-to-bit mapping method is shown in Table 4, and the corresponding relationship between each consecutive (Qm1 / 2-1) = (8 / 2-1) = 3 bits c(3j), c(3j+1), c(3j+2) of the second bit sequence c(0)~c(N1-1) and the amplitude A(j).

[0163] Table 4

[0164]

[0165] In one embodiment, when the shaping encoder uses a shaping encoder based on a block code (a specific example is as shown in Figure 6 shown, another specific example is as shown in Figure 7 shown); perform shaping encoding on the first subsequence according to the first modulation order to obtain a second bit sequence, including: encoding the first subsequence using the Figure 7 shown shaping encoder based on a block code according to the first modulation order to obtain a second bit sequence.

[0166] In a specific example, the second bit sequence c is obtained by concatenating a bit mask bit sequence of length K1 determined by a bit mask and a shaping bit sequence s of length Ks, that is, the length N1 of the second bit sequence c = K1 + Ks, the second bit sequence Or Or Among them, the bit mask bit sequence Consecutive Qm1-1 bits two Qm1-1 combinations satisfy the unequal probability distribution. In a specific example, Qm1 = 3, and the bit mask bit sequence for Qm1 - 1 = 2 consecutive bits The probability distributions of the four combinations are shown in Table 5.

[0167] Table 5

[0168]

[0169] S130. Perform channel coding on the second subsequence and the second bit sequence to obtain a third bit sequence.

[0170] In one embodiment, the third bit sequence (denoted as d) includes at least one of the following: a part of the bits of the second subsequence; a part of the bits of the shaping bit sequence in the second bit sequence; all the bits of the second bit sequence; all the bits of the second bit sequence except the shaping bit sequence; padding bits; parity bits generated by the channel encoder; all the bits of the bit mask bit sequence in the second bit sequence.

[0171] The first communication node multiplexes the second subsequence b2(0) to b2(K2 - 1) and the second bit sequence c(0) to c(N1 - 1) into a bit sequence of length K2 + N1 as information bits for channel coding, obtaining a third bit sequence d(0) to d(Nd - 1) of length Nd.

[0172] In one embodiment, the third bit sequence d(0) to d(Nd - 1) includes all the bits of the second bit sequence c(0) to c(N1 - 1).

[0173] In one embodiment, the third bit sequence d(0) to d(Nd - 1) includes at least one of the following: all the bits of the bit mask bit sequence of length K1 in the second bit sequence c ; a subsequence of length Ks' of the shaping bit sequence s of length Ks in the second bit sequence c; a subsequence of length K2' of the second subsequence b2 of length K2; padding bits or empty bits f of length Nfb b ; p of the Np parity bits generated by channel coding fec =[p fec (0), …, p fec (Np - 1)], where 0 ≤ Ks' ≤ Ks, 0 ≤ K2' ≤ K2, 0 ≤ Nfb, 0 ≤ Np.

[0174] S140. Perform rate matching on the second subsequence, the second bit sequence, and the third bit sequence based on the first modulation order and the second modulation order to obtain a fourth bit sequence.

[0175] In one embodiment, rate matching is performed on the second subsequence, the second bit sequence, and the third bit sequence based on the first modulation order and the second modulation order to obtain a fourth bit sequence, including: dividing the second subsequence, the second bit sequence, and the third bit sequence into amplitude bit sequences (denoted as d a ) with a length of Nda and non-amplitude bit sequences (denoted as d na ) with a length of Ndna; determining an interleaving matrix (denoted as H IL ) based on the first modulation order, the second modulation order, the amplitude bit sequence, and the non-amplitude bit sequence; and taking Ng bits from the interleaving matrix column by column and then row by row as the fourth bit sequence (denoted as g).

[0176] In one embodiment, the length of the amplitude bit sequence is equal to the length of the second bit sequence c, that is, Nda = N1. The amplitude bit sequence includes and only includes all the bits of the second bit sequence c. The length of the non-amplitude bit sequence Ndna is Nd - N1, including all the bits of the second subsequence b2 and the third bit sequence d except for the second bit sequence c.

[0177] In one embodiment, the length of the amplitude bit sequence is equal to the length of the second bit sequence c, that is, Nda = N1. The amplitude bit sequence includes and only includes all the bits of the second bit sequence c. The length of the non-amplitude bit sequence Ndna is K2 - Pb + Nd, including a part of the second subsequence b2 and all the bits of the third bit sequence d.

[0178] In one embodiment, the length of the amplitude bit sequence is equal to the length of the second bit sequence c, that is, Nda = N1. The amplitude bit sequence includes and only includes all the bits of the second bit sequence c. The length of the non-amplitude bit sequence Ndna is K2 - Pb + Nd + Ks, including a part of the second subsequence b2, all the bits of the third bit sequence, and all the bits of the shaping bit sequence in the second bit sequence c.

[0179] Combined with step S120, it can be seen that the consecutive Qm1 / 2 - 1 bits d a in the amplitude bit sequence d with indexes j·(Qm1 / 2 - 1), j·(Qm1 / 2 - 1)+1, …, j·(Qm1 / 2 - 1)+Qm1 / 2 - 2, namely d a (j·(Qm1 / 2 - 1)), d a (j·(Qm1 / 2 - 1)+1), …, d a (j·(Qm1 / 2 - 1)+Qm1 / 2 - 2) correspond to the amplitude A(j).

[0180] In a specific example, the second subsequence b2, the second bit sequence c, and the third bit sequence d satisfy the relationship: d = [c(0), …, c(N1 - 1), b2(Pb), …, b2(K2 - 1), p fec (0), …, p fec (Np - 1)], where Nd = N1 + K2 - Pb + Np, 0 ≤ Pb ≤ K2, p fec (0), …, p fec (Np - 1) are Np check bits generated by channel coding. The amplitude bit sequence is the second bit sequence c of length N1, that is, d a = c, and the non - amplitude bit sequence is d na = [b2(Pb), …, b2(K2 - 1), p fec (0), …, p fec (Np - 1)].

[0181] In another specific example, the second subsequence b2, the second bit sequence c, and the third bit sequence d satisfy the relationship: d = [b2(Pb), …, b2(K2 - 1), c(0), …, c(N1 - 1), p fec (0), …, p fec (Np - 1)], where Nd = N1 + K2 - Pb + Np, 0 ≤ Pb ≤ K2, p fec (0), …, p fec (Np - 1) are Np check bits generated by channel coding. The amplitude bit sequence is the second bit sequence c of length N1, that is, d a = c, and the non - amplitude bit sequence is d na = [b2(Pb), …, b2(K2 - 1), p fec (0), …, p fec (Np - 1)].

[0182] In yet another specific example, the second subsequence b2, the second bit sequence c, and the third bit sequence d satisfy the relationship: d = [c(0), …, c(N1 - 1), p fec (0), …, p fec (Np - 1)], where Nd = N1 + Np, p fec (0), …, p fec (Np - 1) are Np check bits generated by channel coding. The channel - coding output bit sequence d does not include the second subsequence b2. The amplitude bit sequence is the second bit sequence c of length N1, that is, d a = c, and the non - amplitude bit sequence is d na = [p fec (0), …, p fec (Np - 1)].

[0183] In yet another specific example, the second subsequence b2, the second bit sequence c, and the third bit sequence d satisfy the relationship: d = [b2(Nb1), …, b2(Nb2), c, b2(Nb3), …, b2(K2 - 1), p fec , where c = [c(0), …, c(N1 - 1)], p fec = [p fec (0), …, p fec (Np - 1)] are Np check bits generated by channel coding, Nd = Nb2 - Nb1 + 1 + N1 + K2 - Nb3 + Np, 0 ≤ Nb1 ≤ Nb2 < Nb3 ≤ K2, the third bit sequence d does not include the second subsequence b2, the amplitude bit sequence is the second bit sequence c of length N1, that is, d a = c, and the non - amplitude bit sequence is d na = [b2(Nb1), …, b2(Nb2), p fec (0), …, p fec (Np - 1)].

[0184] In yet another specific example, the second subsequence b2, the second bit sequence c, and the third bit sequence d satisfy the relationship: d = [b2(Nb1), …, b2(Nb2), c, b2(Nb3), …, b2(K2 - 1), f b , p fec , where c = [c(0), …, c(N1 - 1)], p fec = [p fec (0), …, p fec (Np - 1)] are Np check bits generated by the channel encoder 203, f b is a padding bit or a null bit and has a length of Nfb, Nd = Nb2 - Nb1 + 1 + N1 + Nfb + K2 - Nb3 + Np, 0 ≤ Nb1 ≤ Nb2 < Nb3 ≤ K2, the amplitude bit sequence is the second bit sequence c of length N1, that is, d a = c, and the non - amplitude bit sequence is d na = [b2(Nb1), …, b2(Nb2), b2(Nb3), …, b2(K2 - 1), f b , p fec .

[0185] In yet another specific example, the second subsequence b2, the second bit sequence c, the third bit sequence d, the amplitude bit sequence d a and the non - amplitude bit sequence d na satisfy the relationship: d a = [c(0), …, c(N1 - 1)], d na= [b2(Pb), …, b2(K2 - 1), d(0), …, d(Nd - 1)], where Ndna = Nd + K2 - Pb, 0 ≤ Pb ≤ K2.

[0186] In yet another specific example, the second subsequence b2, the second bit sequence c, the third bit sequence d, the amplitude bit sequence d a and the non - amplitude bit sequence d na satisfy the relationship: d a = [c(0), …, c(N1 - 1)], d na = [d(0), …, d(Nd - 1)], where Nda = N1, Ndna = Nd.

[0187] In still another specific example, the second subsequence b2, the second bit sequence c, the third bit sequence d, the amplitude bit sequence d a and the non - amplitude bit sequence d na satisfy the relationship: d a = [c(0), …, c(N1 - 1)], d na = [b2(Nb1), …, b2(Nb2), b2(Nb3), …, b2(K2 - 1), d(0), …, d(Nd - 1)], where Nda = N1, Ndna = Nb2 - Nb1 + 1 + K2 - Nb3 + Nd.

[0188] In one embodiment, the length of the amplitude bit sequence is equal to the length of the bit - mask bit sequence in the second bit sequence c , that is, Nda = K1, and the amplitude bit sequence includes and only includes all the bits of the bit - mask bit sequence in the second bit sequence c , and the length of the non - amplitude bit sequence Ndna is Nd - Nda = Nd - K1, including all the bits in the third bit sequence d except the bit - mask bit sequence in the second bit sequence c other than that.

[0189] Combined with step S120, it can be seen that for the amplitude bit sequence d a the consecutive Qm1 - 1 bits d at indices j·(Qm1 - 1), j·(Qm1 - 1)+1, …, j·(Qm1 - 1)+Qm1 - 2 in it a (j·(Qm1 - 1)), d a (j·(Qm1 - 1)+1), …, d a (j·(Qm1 - 1)+Qm1 - 2) correspond to the consecutive Qm1 - 1 bits of the bit - mask bit sequence Therefore, for the amplitude bit sequence d a the consecutive Qm1 - 1 bits d in it​a (j·(Qm1 - 1)), d a (j·(Qm1 - 1)+1), …, d a (j·(Qm1 - 1)+Qm1 - 2) of 2 Qm1-1 combinations satisfy the unequal probability distribution.

[0190] The following gives several specific examples to illustrate the relationship between the third bit sequence d of length Nd, the second subsequence b2 of length K2, and the bit mask bit sequence of length K1 in the second bit sequence c the integer bit sequence s of length Ks in the second bit sequence c, the padding bit or empty bit f of length Nfb b , the amplitude bit sequence d of length Nda a and the non - amplitude bit sequence d of length Ndna na :

[0191] (1) d na = [bs(Pb), …, bs(K2 + Ks - 1), f b , p fec ;

[0192] (2) d na = [bs(Pb), …, bs(K2 + Ks - 1), f b , p fec ;

[0193] (3) d na = [bs(Nbs1), …, bs(Nbs2), bs(Nbs3), …, bs(Nbs4), f b , p fec ,

[0194] where Nd = K1 + K2 + Ks + Nfp + Np - Pb, 0 ≤ Pb ≤ K2 + Ks or Pb = K2 + Ks - (Nbs2 - Nbs1 + 1)-(Nbs4 - Nbs3 + 1), bs = [b2, s] or bs = [s, b2], 0 ≤ Nbs1 ≤ Nbs2 ≤ Nbs3 ≤ Nbs4 < K2 + Ks.

[0195] The following introduces the determination method of the interleaving matrix in different cases:

[0196] In one embodiment, when the first modulation order is greater than the second modulation order, the interleaving matrix is determined based on the first modulation order, the second modulation order, the amplitude bit sequence, and the non - amplitude bit sequence, including: The first step, from the non - amplitude bit sequence d naThe bit d of the second starting index k2 na (k2) starts to select the first bit other than 2×Ng / Qm2 padding bits with the second cyclic buffer size Ncb2, and the first bits form the first 2 rows of the interleaving matrix. Second step, from the amplitude bit sequence d a The first starting index k1·(Qm1 / 2 - 1) in or the bit d a (k1·(Qm1 / 2 - 1)) starts to select the second bit other than (Qm1 - 2)×Ng / Qm2 padding bits with the first cyclic buffer size Ncb1, and the second bits form the last Qm1 - 2 rows of the interleaving matrix; wherein, the interleaving matrix is Qm1 rows and Ng / Qm2 columns, Ng is the length of the fourth bit sequence, Qm1 is the first modulation order, Qm2 is the second modulation order, and k1 and k2 are integers.

[0197] In a specific example, Nx = Ng / Qm2, k1 = 0, k2 = 0, and the interleaving matrix H IL is:

[0198]

[0199] In another specific example, Qm1 = 8, Qm2 = 6, Ng = 60, Ncb1 = N1 = 60, Ncb2 = Nd - N1 = 800 - 60 = 740, the number of padding bits Nfb = 65, and the interleaving matrix H IL is:

[0200]

[0201] In one embodiment, when the first modulation order is less than the second modulation order, determining the interleaving matrix based on the first modulation order, the second modulation order, the amplitude bit sequence, and the non - amplitude bit sequence includes: First step, from the amplitude bit sequence d a The first starting index k1·(Qm1 - 1) in or the bit d a (k1·(Qm1 - 1)) starts to select the third bit other than (Qm1 - 1)×Ng / Qm2 padding bits with the first cyclic buffer size Ncb1, and the third bits form a row vector whose row index of the interleaving matrix is greater than 0 and less than Qm1. In a specific example, the element H IL in the interleaving matrix H with column index j and row index i is set to the amplitude bit d IL (i,j) of index k1·(Qm1 - 1)+j·(Qm1 - 1)+i - 1 a (k1·(Qm1 - 1)+j·(Qm1 - 1)+i - 1). Second step, from the non - amplitude bit sequence d na The bit d of the second starting index k2 na(k2) starts to select the fourth bits other than (Qm2 - Qm1 + 1) × Ng / Qm2 padding bits with the second cyclic buffer size Ncb2. The row index of the row vector composed of the fourth bits is 0 or not less than Qm1. Among them, the interleaving matrix is a matrix with Qm2 rows and Ng / Qm2 columns, Ng is the length of the fourth bit sequence, Qm1 is the first modulation order, Qm2 is the second modulation order, and k1 and k2 are integers.

[0202] In a specific example, for the interleaving matrix H IL the element H IL (i, j) at column index j and row index i satisfies the following formula:

[0203]

[0204] In another specific example, for the interleaving matrix H IL the element H IL (i, j) at column index j and row index i satisfies the following formula:

[0205]

[0206] In another embodiment for determining the fourth bit sequence, this step S140 may be: rate matching the third bit sequence based on the first modulation order and the second modulation order to obtain the fourth bit sequence; correspondingly, the method for determining the amplitude bit sequence and the non - amplitude bit sequence is: dividing the third bit sequence into an amplitude bit sequence and a non - amplitude bit sequence.

[0207] In one embodiment, the fourth bit sequence includes at least one of the following: a part of the bits of the amplitude bit sequence; a part of the bits of the non - amplitude bit sequence.

[0208] In one embodiment, the amplitude bit sequence includes at least one of the following: a part of the bits of the second bit sequence; all the bits of the second bit sequence; a part of the bits of the bits of the second bit sequence except for the shaping bit sequence, where the shaping bit sequence is the bits output by the channel decoder; all the bits of the second bit sequence except for the shaping bit sequence.

[0209] In one embodiment, the non - amplitude bit sequence includes at least one of the following: a part of the bits of the second subsequence; a part of the bits of the shaping bit sequence in the second bit sequence; padding bits; parity bits generated by the channel encoder.

[0210] In one embodiment, for the fourth bit sequence g, the bit g(j) corresponding to the remainder of the index j divided by Qm2 being not less than 0 and not greater than 1 is the bit e in the non - amplitude bit sequence na(k); that is, when 0 ≤ mod(j, Qm2) ≤ 1, or when j = i·Qm2 + r and 0 ≤ r ≤ 1, g(j) = e na (k).

[0211] In one embodiment, for the fourth bit sequence g, when the remainder of the index number j divided by Qm2 is not less than Qm1 and less than Qm2, the corresponding bit g(j) is a bit e in the non-amplitude bit sequence na (k); that is, when Qm1 ≤ mod(j, Qm2) < Qm2, or when j = i·Qm2 + r and Qm1 ≤ r < Qm2, g(j) = e na (k).

[0212] In one embodiment, when the first modulation order is greater than the second modulation order, for the fourth bit sequence g, when the remainder of the index number j divided by Qm2 is greater than 1 and less than Qm2, the corresponding bit g(j) is a bit e in the amplitude bit sequence a (k); that is, when 1 < mod(j, Qm2) < Qm2, or when j = i·Qm2 + r and 1 < r < Qm2, g(j) = e a (k).

[0213] In one embodiment, when the first modulation order is less than the second modulation order, for the fourth bit sequence g, when the remainder of the index number j divided by Qm2 is greater than 1 and less than Qm1, the corresponding bit g(j) is a bit e in the amplitude bit sequence a (k); that is, when 1 < mod(j, Qm2) < Qm1, or when j = i·Qm2 + r and 1 < r < Qm1, g(j) = e a (k).

[0214] In one embodiment, for the fourth bit sequence g, when the remainder of the index number j divided by Qm2 is greater than 1 and less than Qm′, the corresponding bit g(j) is a bit e in the amplitude bit sequence a (k); that is, when 1 < mod(j, Qm2) < Qm′ = min(Qm1, Qm2), or when j = i·Qm2 + r and 1 < r < Qm′ = min(Qm1, Qm2), g(j) = e a (k).

[0215] Wherein, Qm1 is the first modulation order, Qm2 is the second modulation order, and Qm′ is the smaller value of the first modulation order and the second modulation order.

[0216] S150. Modulate and map the fourth bit sequence according to the second modulation order to obtain a modulation symbol sequence, and send a signal including the modulation symbol sequence to the second communication node.

[0217] Among them, the length of the modulation symbol sequence is equal to the number of modulation symbols, and each symbol in the modulation symbol sequence is a constellation point in the modulation constellation corresponding to the second modulation order.

[0218] In one embodiment, when the modulation mapping adopts quadrature amplitude modulation, the first communication node inputs the fourth bit sequence g with a length of Ng into the modulation mapper for quadrature amplitude modulation with a modulation order of the second modulation order Qm2, and obtains a modulation symbol sequence (denoted as X) with a length of Nx. Among them, Nx is the number of modulation symbols, and the j-th symbol X(j) of the modulation symbol sequence X is determined by Qm2 consecutive bits g(j·Qm2), g(j·Qm2 + 1), …, g(j·Qm2 + Qm2 - 1) with indexes j·Qm2, j·Qm2 + 1, …, j·Qm2 + Qm2 - 1 in the fourth bit sequence g according to a preset mapping rule.

[0219] In a specific example, when Qm2 = 4, 6, 8, 10, the relationship between Qm2 consecutive bits g(j·Qm2), g(j·Qm2 + 1), …, g(j·Qm2 + Qm2 - 1) and the j-th symbol X(j) is shown in Table 6 and Table 7. Among them, Table 6 shows the relationship between the real part of the j-th symbol X(j) and Qm2 / 2 bits g(j·Qm2), g(j·Qm2 + 2), …, g(j·Qm2 + Qm2 - 2) with indexes divided by Qm2 and the remainder being even. In the table, the indexes of the bits from left to right increase in sequence. Among them, the bit g(j·Qm2) determines the positive or negative sign of the real part of the j-th symbol X(j), and the remaining Qm2 / 2 - 1 bits determine the absolute value or amplitude of the real part of the symbol X(j); Table 7 shows the relationship between the imaginary part of the j-th symbol X(j) and Qm2 / 2 bits g(j·Qm2 + 1), g(j·Qm2 + 3), …, g(j·Qm2 + Qm2 - 1) with indexes divided by Qm2 and the remainder being odd. In the table, the indexes of the bits from left to right increase in sequence. Among them, the bit g(j·Qm2 + 1) determines the positive or negative sign of the imaginary part of the j-th symbol X(j), and the remaining Qm2 / 2 - 1 bits determine the absolute value or amplitude of the imaginary part of the symbol X(j).

[0220] Table 6

[0221]

[0222]

[0223] Table 7

[0224]

[0225]

[0226] In one embodiment, when amplitude shift keying (ASK) modulation is used for modulation mapping, the first communication node inputs a fourth bit sequence g of length Ng into a modulation mapper for ASK modulation with a second modulation order Qm2, obtaining a modulation symbol sequence X of length Nx. Here, Nx is the number of modulation symbols. The j-th symbol X(j) of the modulation symbol sequence X is determined by Qm2 consecutive bits g(j·Qm2), g(j·Qm2 + 1), …, g(j·Qm2 + Qm2 - 1) in the fourth bit sequence g according to a preset mapping rule. Among them, the bit in the fourth bit sequence g whose index has a remainder of 0 when divided by Qm2 determines the sign of the modulation symbol sequence X, and the bits in the fourth bit sequence g whose indices have non-zero remainders when divided by Qm2 determine the absolute value or amplitude of the modulation symbol sequence X. It can be seen that the Qm2 consecutive bits g(j·Qm2), g(j·Qm2 + 1), …, g(j·Qm2 + Qm2 - 1) are the elements on the column with column index j in the interleaving matrix H. IL The elements on the column with column index j in

[0227] In a specific example, when Qm2 = 2, 3, 4, 5, the relationship between the Qm2 consecutive bits g(j·Qm2), g(j·Qm2 + 1), …, g(j·Qm2 + Qm2 - 1) and the j-th symbol X(j) is shown in Table 8.

[0228] Table 8

[0229]

[0230]

[0231] The beneficial effects of the technical solution of the present application in different situations are analyzed as follows:

[0232] When the first modulation order is greater than the second modulation order, according to step S140, it can be known that the 0-th row and the 1-st row of the j-th column of the interleaving matrix H IL are two non-amplitude bit sequences d na in the bits d na (k′) and d na (k″). The bits in the 2-nd row and the Qm1 - 1-st row of the j-th column of the interleaving matrix H IL are Qm1 - 2 consecutive bits d a in the amplitude bit sequence d a (k1·(Qm1 / 2 - 1) + j·(Qm1 - 2)), d a (k1·(Qm1 / 2 - 1) + j·(Qm1 - 2) + 1), …, d a (k1·

[0233] (Qm1 / 2 - 1)+j·(Qm1 - 2)+Qm1 - 3), i.e., d a (k″′), d a (k″′ + 1), …, d a (k″′ + Qm1 - 3), where k″′ = (k1 + 2j)·(Qm1 / 2 - 1).

[0234] Qm1 / 2 - 1 bits d a (k″′), d a (k″′ + 1), …, d a (k″′ + Qm1 / 2 - 2) correspond to the amplitude A(k1 + 2j); Qm1 / 2 - 1 bits d a (k″′ + Qm1 / 2 - 1), d a (k″′ + Qm1 / 2), …, d a (k″′ + Qm1 - 3) correspond to the amplitude A(k1 + 2j + 1).

[0235] In summary, in the j - th column of the interleaving matrix H IL the bits in ascending order of row index can be: d na (k′), d na (k″), d a (k″′), d a (k″′ + Qm1 / 2 - 1), d a (k″′ + 1), d a (k″′ + Qm1 / 2), …, d a (k″′ +

[0236] Qm1 / 2 - 2), d a (k″′ + Qm1 - 3).

[0237] The bits at indices j·Qm2, j·Qm2 + 1, …, j·Qm2 + Qm2 - 1 in the fourth bit sequence g are respectively set to the bits of the j - th column of the interleaving matrix H IL H IL (i, 0), H IL (i, 1), …, H IL (i, Qm2 - 1). The bits at indices j·Qm2, j·Qm2 + 1, …, j·Qm2 + Qm2 - 1 in the fourth bit sequence g are respectively the bits d na (k′), d na (k″), d a (k″′), d a (k″′ + Qm1 / 2 - 1), d a (k″′ + 1), d a (k″′ + Qm1 / 2), …, d a (k″′ +

[0238] Qm2 / 2 - 2), d a (k″′ + Qm1 / 2 - 1 + Qm2 / 2 - 2). That is, the bits at indices j·Qm2, j·Qm2 + 1, …, j·Qm2 + Qm2 - 1 in the fourth bit sequence g include two non - amplitude bits d na (k′), d na (k″), the first Qm2 / 2 - 1 bits of the amplitude A(k1 + 2j) and the first Qm2 / 2 - 1 bits of the amplitude A(k1 + 2j + 1).

[0239] According to step S150, it can be known that among the Qm2 consecutive bits in the fourth bit sequence g, the Qm2 / 2 bits g(j·Qm2), g(j·Qm2 + 2), …, g(j·Qm2)+Qm2 - 2 whose indices have an even remainder when divided by Qm2 are mapped to the real part of the j - th symbol X(j). Among them, the bit g(j·Qm2) determines the sign of the real part of the j - th symbol X(j), and the remaining Qm2 / 2 - 1 bits determine the absolute value or amplitude of the real part of the symbol X(j); the bit g(j·Qm2) is a non - amplitude bit d na (k′), among the Qm2 consecutive bits in the fourth bit sequence g, the Qm2 / 2 bits whose indices have an even remainder when divided by Qm2 correspond to the first Qm2 / 2 - 1 bits of the amplitude A(k1 + 2j). Therefore, the non - amplitude bit d na (k′) determines the sign of the real part of the symbol X(j), and the first Qm2 / 2 - 1 bits of the amplitude A(k1 + 2j) determine the amplitude of the real part of the symbol X(j). Similarly, the non - amplitude bit d na (k″) determines the sign of the imaginary part of the symbol X(j), and the first Qm2 / 2 - 1 bits of the amplitude A(k1 + 2j + 1) determine the amplitude of the imaginary part of the symbol X(j).

[0240] Taking Table 4 as an example, assuming Qm1 = 8, Qm2 = 6, the probabilities of the first Qm2 / 2 - 1 = 2 bits of the amplitude A(k1 + 2j) or A(k1 + 2j + 1) are as follows:

[0241] The probability that c(3j)=0 and c(3j + 1)=1 is equal to the sum of the amplitudes "1" and "3", that is, 0.1710 + 0.1654 = 0.3364.

[0242] The probability that c(3j)=0 and c(3j + 1)=0 is equal to the sum of the amplitudes "5" and "7", that is, 0.1546 + 0.1395 = 0.2941.

[0243] The probability that c(3j)=1 and c(3j + 1)=0 is equal to the sum of the amplitudes "9" and "11", that is, 0.1215 + 0.1020 = 0.2235.

[0244] The probability that c(3j) = 1 and c(3j + 1) = 1 is equal to the sum of the amplitudes "13" and "15", i.e., 0.0823 + 0.0637 = 0.1460.

[0245] According to the existing literature, the bits in the non - amplitude bit sequence d na are equally - probable distributed. The amplitudes of the real and imaginary parts of X(j) maintain the characteristic of unequal probability and maintain the shaping effect.

[0246] In summary, in the case where the first modulation order Qm1 is greater than the second modulation order Qm2, the modulation mapping amplitude probability is still unequal - probable, maintaining the shaping effect.

[0247] In the case where the first modulation order is less than the second modulation order, in a specific example, Qm1 = 3, Qm2 = 4, the bit - mask bit sequence For the 4 combinations of consecutive Qm1 - 1 = 2 bits the probability distribution is shown in Table 9. Determine the symbol X(j) from the fourth - bit sequence g according to the fourth column of Table 8. Table 10 gives the relationship between the bit - mask bit sequence the amplitude bit sequence d a the non - amplitude bit sequence d na and the probability of the symbol X(j), where k1 = k2 = 0. The bits with indices 4j and 4j + 3 in the fourth - bit sequence g come from the non - amplitude bit sequence d na and the bits with indices 4j + 1 and 4j + 2 come from the amplitude bit sequence d a . The probability distribution of the non - amplitude bit sequence d na is equally - probable. Since each symbol X(j) contains 2 bits of the non - amplitude bit sequence d na , the probability of the symbol X(j) is equal to one - quarter of the probability of the combination of the bits . It can be seen that the symbols in the modulation symbol sequence X still have the characteristic of unequal probability, and the probability of the symbol with a larger amplitude is smaller, maintaining the shaping characteristic.

[0248] Table 9

[0249]

[0250] Table 10

[0251]

[0252] Figure 9 is the second process schematic diagram of an information configuration method provided by an embodiment of the present application. As Figure 9As shown, the method provided in this embodiment is applicable to a second communication node (which may also be referred to as a second communication node device, or a second node, or a second device). The method includes the following steps.

[0253] S210. Receive a signal including a modulated symbol sequence sent by a first communication node, and obtain a first modulation order, a second modulation order, and the number of modulation symbols.

[0254] In some embodiments, the first modulation order is used for transmission when the new data indication signaling remains unchanged.

[0255] In some embodiments, the first modulation order is used for the first transmission of a first bit sequence.

[0256] In some embodiments, the second modulation order is used for the retransmission of the first bit sequence.

[0257] The length of the modulated symbol sequence (denoted as X) is equal to the number of modulation symbols, and each symbol in the modulated symbol sequence is a constellation point in the modulation constellation of the second modulation order.

[0258] In some embodiments, the first modulation order is not equal to the second modulation order. It may be that the first modulation order is greater than the second modulation order. It may also be that the first modulation order is less than the second modulation order. It may also be that the first modulation order is equal to the second modulation order.

[0259] In some embodiments, the manner in which the second communication node obtains the first modulation order may be to obtain it from a higher layer, may be determined according to control information, or may also be determined according to downlink control information.

[0260] In some embodiments, the manner in which the second communication node obtains the second modulation order may be to obtain it from a higher layer, may be determined according to control information, or may also be determined according to downlink control information.

[0261] In some embodiments, the manner in which the second communication node obtains the number of modulation symbols may be to obtain it from a higher layer, may be determined according to control information, or may also be determined according to downlink control information.

[0262] S220. Demodulate the signal based on the second modulation order to obtain the soft information of a fourth bit sequence.

[0263] In one embodiment, the soft information is a log-likelihood ratio or a probability value.

[0264] Taking the soft information as the log-likelihood ratio as an example, the second communication node demodulates the signal including the modulation symbol sequence X with the modulation order of the second modulation order Qm2, and obtains the log-likelihood ratio sequence LLRg(0) to LLRg(Ng-1) with the length of Ng corresponding to the fourth bit sequence g, where LLRg(j) is the log-likelihood ratio corresponding to the bit g(j) in the fourth bit sequence g.

[0265] In one embodiment, the fourth bit sequence includes at least one of the following: a part of the bits of the amplitude bit sequence; a part of the bits of the non-amplitude bit sequence.

[0266] In one embodiment, the amplitude bit sequence includes at least one of the following: a part of the bits of the second bit sequence; all the bits of the second bit sequence; a part of the bits of the bits of the second bit sequence except the shaping bit sequence, and the shaping bit sequence is the bit output by the channel decoder; all the bits of the second bit sequence except the shaping bit sequence.

[0267] In one embodiment, the non-amplitude bit sequence includes at least one of the following: a part of the bits of the second subsequence; a part of the bits of the shaping bit sequence in the second bit sequence; padding bits; parity bits generated by the channel encoder.

[0268] In one embodiment, for the bit g(j) in the fourth bit sequence g where the remainder of the index j divided by Qm2 is not less than 0 and not greater than 1, it is the bit e na (k); that is, when 0≤mod(j,Qm2)≤1, or when j = i·Qm2 + r and 0≤r≤1, g(j) = e na (k).

[0269] In one embodiment, for the bit g(j) in the fourth bit sequence g where the remainder of the index j divided by Qm2 is not less than Qm1 and less than Qm2, it is the bit e na (k); that is, when Qm1≤mod(j,Qm2)<Qm2, or when j = i·Qm2 + r and Qm1≤r<Qm2, g(j) = e na (k).

[0270] In one embodiment, when the first modulation order is greater than the second modulation order, for the bit g(j) in the fourth bit sequence g where the remainder of the index j divided by Qm2 is greater than 1 and less than Qm2, it is the bit e a (k); that is, when 1<mod(j,Qm2)<Qm2, or when j = i·Qm2 + r and 1<r<Qm2, g(j) = e a (k).

[0271] In one embodiment, when the first modulation order is less than the second modulation order, for the bit g(j) in the fourth bit sequence g where the remainder of the index j divided by Qm2 is greater than 1 and less than Qm1, it is the bit e a (k) in the amplitude bit sequence; that is, when 1 < mod(j, Qm2) < Qm1, or when j = i·Qm2 + r and 1 < r < Qm1, g(j) = e a (k).

[0272] In one embodiment, for the bit g(j) in the fourth bit sequence g where the remainder of the index j divided by Qm2 is greater than 1 and less than Qm′, it is the bit e a (k) in the amplitude bit sequence; that is, when 1 < mod(j, Qm2) < Qm′, or when j = i·Qm2 + r and 1 < r < Qm′, g(j) = e a (k).

[0273] Here, Qm1 is the first modulation order, Qm2 is the second modulation order, and Qm′ is the smaller value of the first modulation order and the second modulation order.

[0274] S230. Perform rate dematching based on the soft information of the first modulation order, the second modulation order, and the fourth bit sequence to obtain the soft information corresponding to the third bit sequence, the second bit sequence, and the second subsequence respectively.

[0275] Here, the second bit sequence is the output bit sequence of the shaping encoder, the output bit sequence of the amplitude-to-bit mapper, or the output bit sequence of the multiplexer, and the second bit sequence includes a part of the bits of the first subsequence or the shaping bit sequence output by the channel decoder.

[0276] In one embodiment, the third bit sequence includes at least one of the following: a part of the bits of the second subsequence; a part of the bits of the shaping bit sequence in the second bit sequence; all the bits of the second bit sequence; all the bits of the second bit sequence except the shaping bit sequence; padding bits; parity bits generated by the channel encoder; all the bits of the bit mask bit sequence in the second bit sequence.

[0277] In another embodiment of rate dematching for the fourth bit sequence, this step S230 may be: perform rate dematching based on the soft information of the first modulation order, the second modulation order, and the fourth bit sequence to obtain the soft information corresponding to the third bit sequence, which specifically includes the following three steps:

[0278] First step. The second communication node first places the log-likelihood ratio sequence LLRg of the fourth bit sequence g with a length of Ng in a column-first and row-second manner into the log-likelihood ratio interleaving matrix H LLR,IL with Qm2 rows and Ng / Qm2 columns, where H LLR,ILThe element H with row index i and column index j LLR,IL (i, j) is set to the element at index j×Qm2 + i in the log-likelihood ratio sequence LLRg, i.e., H LLR,IL (i, j) = LLRg(j×Qm2 + i), where Qm2 is the second modulation order.

[0279] Step 2: The second communication node interleaves the log-likelihood ratio matrix H LLR,IL The log-likelihood ratios with row indices greater than 1 and less than Qm1 in the matrix H are placed column by column and then row by row into the amplitude bit log-likelihood ratio sequence LLRa(0) to LLRa(Na - 1) with a length of Na = (Qm1 - 2)×Ng / Qm2, and the log-likelihood ratios with row indices less than 2 and greater than or equal to Qm1 in the matrix H LLR,IL are placed column by column and then row by row into the non-amplitude bit log-likelihood ratio sequence LLRna(0) to LLRna(Nna - 1) with a length of Nna = (Qm2 - Qm1 + 2)×Ng / Qm2.

[0280] In a specific example,

[0281]

[0282] where i = mod(k, Qm1 - 2),

[0283]

[0284] where i = mod(k, Qm2 - Qm1 + 2),

[0285] Step 3: The second communication node initializes the log-likelihood ratio sequence LLRd(0) to LLRd(Nd - 1) corresponding to the third bit sequence d with a length of Nd to an all-zero sequence. The second node sets the log-likelihood ratio values at indices greater than or equal to N1 + K2 and less than Kb×Z in the log-likelihood ratio sequence LLRd(0) to LLRd(Nd - 1) to the maximum value, where Kb is the number of systematic columns of the matrix of the base graph of the LDPC code, Z is the lifting value, N1 is the length of the second bit sequence, and K2 is the length of the second subsequence. The second node uses the amplitude bit log-likelihood ratio sequence LLRa with a length of Na = (Qm1 - 2)×Ng / Qm2 to set the log-likelihood ratios at indices greater than or equal to Pb and less than N1 + Pb in the log-likelihood ratio sequence LLRd, and the second node uses the non-amplitude bit log-likelihood ratio sequence LLRna with a length of Nna to set the log-likelihood ratios at indices greater than or equal to Pb + N1 and less than N1 + K2 or at indices greater than or equal to Kb×Z in the log-likelihood ratio sequence LLRd.

[0286] S240. Perform channel decoding on the soft information corresponding to the third bit sequence, the second bit sequence, and the second subsequence respectively to obtain an estimate of the second subsequence and an estimate of the second bit sequence.

[0287] In an embodiment of the present application, the second communication node performs LDPC code channel decoding on the log-likelihood ratio sequence LLRd of length Nd to obtain an estimate of the second subsequence b2 and an estimate of the second bit sequence c.

[0288] S250. Perform shaping decoding on the estimate of the second bit sequence according to the first modulation order to obtain an estimate of the first subsequence.

[0289] In an embodiment of the present application, the second communication node performs de-distribution matching on the estimate of the second bit sequence c according to the first modulation order Qm1 to obtain an estimate of the first subsequence b1.

[0290] In some embodiments, the length K1 of the first subsequence b1 may be a multiple of Qm1 / 2 - 1. The length K1 of the first subsequence b1 may also be a multiple of Qm1 - 1, where Qm1 is the first modulation order.

[0291] In a specific example, K1 = Nx × (Qm1 - 1), where Nx is the number of modulation symbols. In another example, K1 = Cs × Ns × (Qm1 - 1), where is the number of shaping blocks, is the shaping block length, Nx is the number of modulation symbols, and Nsmax is the maximum shaping block length.

[0292] S260. Determine an estimate of the first bit sequence from the estimate of the first subsequence and the estimate of the second subsequence.

[0293] In an embodiment of the present application, the second communication node determines an estimate of the first bit sequence b from the estimate of the first subsequence b1 and the estimate of the second subsequence b2.

[0294] Figure 10 is a schematic structural diagram of a data processing device provided by an embodiment of the present application. The device may be configured in the first communication node, such as Figure 10 shown, the device 300 includes: a data acquisition module 310, a shaping encoding module 320, a channel encoding module 330, a rate matching module 340, and a modulation mapping module 350.

[0295] The data acquisition module 310 is configured to acquire a first bit sequence, a first modulation order, a second modulation order, and the number of modulation symbols, where the first bit sequence includes a first subsequence and a second subsequence;

[0296] The shaping encoding module 320 is configured to perform shaping encoding on the first subsequence according to the first modulation order to obtain a second bit sequence;

[0297] The channel encoding module 330 is configured to perform channel encoding on the second subsequence and the second bit sequence to obtain a third bit sequence;

[0298] The rate matching module 340 is configured to perform rate matching on the second subsequence, the second bit sequence, and the third bit sequence based on the first modulation order and the second modulation order to obtain a fourth bit sequence;

[0299] The modulation mapping module 350 is configured to perform modulation mapping on the fourth bit sequence according to the second modulation order to obtain a modulation symbol sequence, and send a signal including the modulation symbol sequence to a second communication node;

[0300] In one embodiment, the first modulation order and the second modulation order are not equal.

[0301] In one embodiment, the first modulation order and the second modulation order are equal.

[0302] In one embodiment, the length of the modulation symbol sequence is equal to the number of modulation symbols, and each symbol in the modulation symbol sequence is a constellation point in the modulation constellation corresponding to the second modulation order.

[0303] In one embodiment, the length of the first subsequence is a multiple of Qm1 / 2 - 1 or a multiple of Qm1 - 1, where Qm1 is the first modulation order.

[0304] In one embodiment, the second bit sequence is the output bit sequence of a shaping encoder, the output bit sequence of an amplitude-to-bit mapper, or the output bit sequence of a multiplexer, and the second bit sequence includes a part of the bits of the first subsequence or a shaping bit sequence output by a channel decoder.

[0305] In one embodiment, the third bit sequence includes at least one of the following: a part of the bits of the second subsequence; a part of the bits of the shaping bit sequence in the second bit sequence; all the bits of the second bit sequence; all the bits of the second bit sequence except the shaping bit sequence; padding bits; parity bits generated by a channel encoder; all the bits of the bit mask bit sequence in the second bit sequence.

[0306] In one embodiment, when the shaping coding uses a distribution matcher; the shaping coding module 320 is further configured to use the distribution matcher to encode the first subsequence according to the first modulation order, so as to obtain an amplitude symbol sequence with a non-uniform probability distribution; convert each element in the amplitude symbol sequence into Qm1 / 2 - 1 bits according to a preset mapping method; splice the Qm1 / 2 - 1 bits into the second bit sequence; wherein, each element in the amplitude symbol sequence takes values from the amplitude set {1, 3, 5,..., (2 Qm1 / 2 - 3), (2 Qm1 / 2 - 1)}, the length of the amplitude symbol sequence is NA, NA = 2 × Nx, and the length of the second bit sequence is N1, N1 = NA × (Qm1 / 2 - 1) or N1 = Nx × (Qm1 - 2), where Nx is the number of modulation symbols and Qm1 is the first modulation order.

[0307] In one embodiment, when the shaping coding uses a shaping encoder based on a block code; the shaping coding module 320 is further configured to use the shaping encoder to encode the first subsequence according to the first modulation order, so as to obtain the second bit sequence.

[0308] In one embodiment, the rate matching module 340 is further configured to divide the second subsequence, the second bit sequence, and the third bit sequence into an amplitude bit sequence and a non-amplitude bit sequence; determine an interleaving matrix based on the first modulation order, the second modulation order, the non-amplitude bit sequence, and the non-amplitude bit sequence; and take Ng bits from the interleaving matrix as the fourth bit sequence.

[0309] In one embodiment, when the first modulation order is greater than the second modulation order, the rate matching module 340 is further configured to select first bits other than 2 × Ng / Qm2 padding bits from the non-amplitude bit sequence, and form the first 2 rows of the interleaving matrix with the first bits; select second bits other than (Qm1 - 2) × Ng / Qm2 padding bits from the amplitude bit sequence, and form the last Qm1 - 2 rows of the interleaving matrix with the second bits; wherein, the interleaving matrix is Qm1 rows and Ng / Qm2 columns, Ng is the length of the fourth bit sequence, Qm1 is the first modulation order, and Qm2 is the second modulation order.

[0310] In one embodiment, when the first modulation order is less than the second modulation order, the rate matching module 340 is further configured to select third bits other than (Qm1 - 1)×Ng / Qm2 padding bits from the amplitude bit sequence, and form a row vector with row indices of the interleaving matrix greater than 0 and less than Qm1 from the third bits; select fourth bits other than (Qm2 - Qm1 + 1)×Ng / Qm2 padding bits from the non-amplitude bit sequence, and form a row vector with row index 0 or row indices not less than Qm1 of the interleaving matrix from the fourth bits; where the interleaving matrix is Qm2 rows by Ng / Qm2 columns, Ng is the length of the fourth bit sequence, Qm1 is the first modulation order, and Qm2 is the second modulation order.

[0311] In one embodiment, the rate matching module 340 is further configured to perform rate matching on the third bit sequence based on the first modulation order and the second modulation order to obtain a fourth bit sequence; correspondingly, divide the third bit sequence into an amplitude bit sequence and a non-amplitude bit sequence.

[0312] In one embodiment, the fourth bit sequence includes at least one of the following: a part of the bits of the amplitude bit sequence; a part of the bits of the non-amplitude bit sequence.

[0313] In one embodiment, the bits corresponding to the remainder of the index number in the fourth bit sequence divided by Qm2 being not less than 0 and not greater than 1 belong to the bits in the non-amplitude bit sequence; the bits corresponding to the remainder of the index number in the fourth bit sequence divided by Qm2 being not less than Qm1 and less than Qm2 are the bits in the non-amplitude bit sequence.

[0314] In one embodiment, when the first modulation order is greater than the second modulation order, the bits corresponding to the remainder of the index number in the fourth bit sequence divided by Qm2 being greater than 1 and less than Qm2 are the bits in the amplitude bit sequence.

[0315] In one embodiment, when the first modulation order is less than the second modulation order, the bits corresponding to the remainder of the index number in the fourth bit sequence divided by Qm2 being greater than 1 and less than Qm1 are the bits in the amplitude bit sequence.

[0316] In one embodiment, the bits corresponding to the remainder of the index number in the fourth bit sequence divided by Qm2 being greater than 1 and less than Qm′ are the bits in the amplitude bit sequence.

[0317] Where Qm1 is the first modulation order, Qm2 is the second modulation order, and Qm′ is the smaller value of the first modulation order and the second modulation order.

[0318] In one embodiment, the amplitude bit sequence includes at least one of the following: a part of the bits of the second bit sequence; all the bits of the second bit sequence; a part of the bits of the bits of the second bit sequence other than the shaping bit sequence, where the shaping bit sequence is the bits output by the channel decoder; all the bits of the second bit sequence other than the shaping bit sequence.

[0319] In one embodiment, the non-amplitude bit sequence includes at least one of the following: a part of the bits of the second subsequence; a part of the bits of the shaping bit sequence in the second bit sequence; padding bits; parity bits generated by the channel encoder.

[0320] The data processing device provided in this embodiment is applicable to Figure 8 the data processing method of the embodiment shown. The implementation principle of the data processing device provided in this embodiment is similar to that of the above embodiment, and has corresponding functions and beneficial effects.

[0321] Figure 11 It is a schematic structural diagram of a data processing device provided by an embodiment of the present application. The device can be configured in a second communication node, such as Figure 11 as shown, the device 400 includes: a data receiving module 410, a signal demodulating module 420, a rate dematching module 430, a channel decoding module 440, a shaping decoding module 450, and a sequence determining module 460.

[0322] The data receiving module 410 is configured to receive a signal including a modulation symbol sequence sent by a first communication node, and obtain a first modulation order, a second modulation order, and the number of modulation symbols;

[0323] The signal demodulating module 420 is configured to demodulate the signal based on the second modulation order to obtain the soft information of the fourth bit sequence;

[0324] The rate dematching module 430 is configured to perform rate dematching according to the first modulation order, the second modulation order, and the soft information of the fourth bit sequence to obtain the soft information corresponding to the third bit sequence, the second bit sequence, and the second subsequence respectively;

[0325] The channel decoding module 440 is configured to perform channel decoding on the soft information corresponding to the third bit sequence, the second bit sequence, and the second subsequence respectively to obtain the estimation of the second subsequence and the estimation of the second bit sequence;

[0326] The shaping decoding module 450 is configured to perform shaping decoding on the estimation of the second bit sequence according to the first modulation order to obtain the estimation of the first subsequence;

[0327] A sequence determination module 460, configured to determine an estimate of a first bit sequence from the estimate of the first subsequence and the estimate of the second subsequence;

[0328] In one embodiment, the first modulation order and the second modulation order are not equal.

[0329] In one embodiment, the first modulation order and the second modulation order are equal.

[0330] In one embodiment, the length of the modulation symbol sequence is equal to the number of modulation symbols, and each symbol in the modulation symbol sequence is a constellation point in the modulation constellation corresponding to the second modulation order.

[0331] In one embodiment, the soft information is a log-likelihood ratio or a probability value.

[0332] In one embodiment, the length of the first subsequence is a multiple of Qm1 / 2 - 1 or a multiple of Qm1 - 1, where Qm1 is the first modulation order.

[0333] In one embodiment, the second bit sequence is an output bit sequence of a shaping encoder, an output bit sequence of an amplitude-to-bit mapper, or an output bit sequence of a multiplexer, and the second bit sequence includes a part of the bits of the first subsequence or a shaping bit sequence output by a channel decoder.

[0334] In one embodiment, the third bit sequence includes at least one of the following: a part of the bits of the second subsequence; a part of the bits of the shaping bit sequence in the second bit sequence; all the bits of the second bit sequence; all the bits of the second bit sequence except the shaping bit sequence; padding bits; parity bits generated by a channel encoder; all the bits of the bit mask bit sequence in the second bit sequence.

[0335] In one embodiment, the fourth bit sequence includes at least one of the following: a part of the bits of the amplitude bit sequence; a part of the bits of the non-amplitude bit sequence.

[0336] In one embodiment, the bits in the fourth bit sequence whose remainder of the index number divided by Qm2 is not less than 0 and not greater than 1 are the bits in the non-amplitude bit sequence.

[0337] In one embodiment, the bits in the fourth bit sequence whose remainder of the index number divided by Qm2 is not less than Qm1 and less than Qm2 are the bits in the non-amplitude bit sequence.

[0338] In one embodiment, when the first modulation order is greater than the second modulation order, the bits in the amplitude bit sequence are the bits in the fourth bit sequence whose index number divided by Qm2 has a remainder greater than 1 and less than Qm2.

[0339] In one embodiment, when the first modulation order is less than the second modulation order, the bits in the amplitude bit sequence are the bits in the fourth bit sequence whose index number divided by Qm2 has a remainder greater than 1 and less than Qm1.

[0340] In one embodiment, the bits in the amplitude bit sequence are the bits in the fourth bit sequence whose index number divided by Qm2 has a remainder greater than 1 and less than Qm'.

[0341] Wherein, Qm1 is the first modulation order, Qm2 is the second modulation order, and Qm' is the smaller value of the first modulation order and the second modulation order.

[0342] In one embodiment, the amplitude bit sequence includes at least one of the following: a part of the bits of the second bit sequence; all the bits of the second bit sequence; a part of the bits of the second bit sequence except for the shaping bit sequence, where the shaping bit sequence is the bits output by the channel decoder; all the bits of the second bit sequence except for the shaping bit sequence.

[0343] In one embodiment, the non-amplitude bit sequence includes at least one of the following: a part of the bits of the second subsequence; a part of the bits of the shaping bit sequence in the second bit sequence; padding bits; parity bits generated by the channel encoder.

[0344] The data processing device provided in this embodiment is applicable to Figure 9 the data processing method of the illustrated embodiment. The implementation principle of the data processing device provided in this embodiment is similar to that of the above embodiment, and has corresponding functions and beneficial effects.

[0345] An embodiment of the present application also provides a communication node, including: a processor, which is used to implement the method provided in any embodiment of the present application when executing a computer program. Specifically, the communication node can be the first communication node or the second communication node. Exemplarily, the following embodiments respectively provide a schematic structural diagram of a communication node as a BS and a UE.

[0346] Figure 12 is a schematic structural diagram of a BS provided in an embodiment of the present application. As Figure 12 shown, the BS includes a processor 60, a memory 61, and a communication interface 62; the number of processors 60 in the BS can be one or more. Figure 12Taking a processor 60 in the BS as an example; the processor 60, the memory 61, and the communication interface 62 in the BS can be connected through a bus or other means. Figure 10 Taking the connection through a bus as an example. The bus represents one or more of several types of bus structures, including a memory bus or a memory controller, a peripheral bus, a graphics acceleration port, a processor, or a local bus using any bus structure in a variety of bus structures.

[0347] The memory 61, as a computer-readable storage medium, can be set to store software programs, computer-executable programs, and modules, such as the program instructions / modules corresponding to the methods in the embodiments of the present application. The processor 60 executes at least one functional application and data processing of the BS by running the software programs, instructions, and modules stored in the memory 61, that is, implementing the above methods.

[0348] The memory 61 can include a program storage area and a data storage area. Among them, the program storage area can store an operating system and application programs required for at least one function; the data storage area can store data created according to the use of the terminal, etc. In addition, the memory 61 can include a high-speed random access memory, and can also include a non-volatile memory, such as at least one magnetic disk storage device, a flash memory device, or other non-volatile solid-state storage devices. In some instances, the memory 61 can include a memory remotely set relative to the processor 60, and these remote memories can be connected to the BS through a network. Examples of the above networks include, but are not limited to, the Internet, an enterprise intranet, a network, a mobile communication network, and combinations thereof.

[0349] The communication interface 62 can be set to receive and send data.

[0350] Figure 13 It is a schematic structural diagram of a UE provided by an embodiment of the present application. The UE can be implemented in various forms. The UE in the present application can include, but is not limited to, mobile terminal devices such as mobile phones, smart phones, laptop computers, digital broadcast receivers, PDAs, tablet computers (Portable Device, PAD), portable multimedia players (Portable Media Player, PMP), navigation devices, in-vehicle terminal devices, in-vehicle display terminals, in-vehicle electronic rearview mirrors, etc., and fixed terminal devices such as digital televisions (television, TV), desktop computers, etc.

[0351] Such as Figure 13 As shown, the UE 50 can include a wireless communication unit 51, an audio / video (Audio / Video, A / V) input unit 52, a user input unit 53, a sensing unit 54, an output unit 55, a memory 56, an interface unit 57, a processor 58, a power supply unit 59, and so on.Figure 11 A UE including various components is shown, but it should be understood that it is not required to implement all the shown components. More or fewer components may be implemented alternatively.

[0352] In this embodiment, the wireless communication unit 51 allows radio communication between the UE 50 and a BS or a network. The A / V input unit 52 is arranged to receive an audio or video signal. The user input unit 53 may generate key input data according to a command input by a user to control various operations of the UE 50. The sensing unit 54 detects the current state of the UE 50, the location of the UE 50, the presence or absence of a touch input by the user to the UE 50, the orientation of the UE 50, the acceleration or deceleration movement and direction of the UE 50, etc., and generates a command or signal for controlling the operation of the UE 50. The interface unit 57 serves as an interface through which at least one external device can be connected to the UE 50. The output unit 55 is configured to provide an output signal in a visual, audio, and / or tactile manner. The memory 56 may store software programs for processing and control operations executed by the processor 58, etc., or may temporarily store data that has been output or is to be output. The memory 56 may include at least one type of storage medium. Moreover, the UE 50 may cooperate with a network storage device that performs the storage function of the memory 56 through a network connection. The processor 58 generally controls the overall operation of the UE 50. The power supply unit 59 receives external power or internal power under the control of the processor 58 and provides appropriate power required to operate various elements and components.

[0353] The processor 58 executes at least one functional application and data processing by running a program stored in the memory 56, for example, implementing the method provided in the embodiments of the present application.

[0354] The embodiments of the present application also provide a computer-readable storage medium, on which a computer program is stored. When the computer program is executed by a processor, the method provided in any embodiment of the present application is implemented.

[0355] The computer storage medium of the embodiments of the present application may adopt any combination of one or more computer-readable media. The computer-readable media may be computer-readable signal media or computer-readable storage media. The computer-readable storage media may be, for example, but not limited to, an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any combination of the above. The computer-readable storage media includes (a non-exhaustive list): an electrical connection having one or more wires, a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an electrically erasable, programmable read-only memory (EPROM), a flash memory, an optical fiber, a portable compact disc read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the above. In the present application, the computer-readable storage media may be any tangible medium that contains or stores a program that can be used by or in conjunction with an instruction execution system, apparatus, or device.

[0356] The computer-readable signal media may include a data signal propagated in a baseband or as part of a carrier wave, in which the computer-readable program code is carried. Such a propagated data signal may take various forms, including but not limited to an electromagnetic signal, an optical signal, or any suitable combination of the above. The computer-readable signal media may also be any computer-readable media other than the computer-readable storage media, which can send, propagate, or transmit a program for use by or in conjunction with an instruction execution system, apparatus, or device.

[0357] The program code contained on the computer-readable media may be transmitted by any appropriate medium, including but not limited to wireless, wire, optical fiber, radio frequency (RF), etc., or any suitable combination of the above.

[0358] The computer program code for performing the operations of the present disclosure may be written in one or more programming languages or a combination of multiple programming languages. The programming languages include object-oriented programming languages (such as Java, Smalltalk, C++, Ruby, Go), and also include conventional procedural programming languages (such as the "C" language or similar programming languages). The program code may be executed entirely on the user's computer, partially on the user's computer, executed as a stand-alone software package, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In the case of a remote computer, the remote computer may be connected to the user's computer through any type of network (including a Local Area Network (LAN) or a Wide Area Network (WAN)), or may be connected to an external computer (for example, by connecting through the Internet using an Internet service provider).

[0359] An embodiment of the present invention also provides a computer program product, including a computer program which, when executed by a processor, implements the method provided in any embodiment of the present invention.

[0360] In the process of implementing the computer program product, the computer program code for performing the operations of the present invention may be written in one or more programming languages or a combination thereof. The programming languages include object-oriented programming languages, such as Java, Smalltalk, C++, and also include conventional procedural programming languages, such as the "C" language or similar programming languages. The program code may be executed entirely on the user's computer, partially on the user's computer, executed as a stand-alone software package, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In the case of a remote computer, the remote computer may be connected to the user's computer through any type of network - including a Local Area Network (LAN) or a Wide Area Network (WAN) - or may be connected to an external computer (for example, by connecting through the Internet using an Internet service provider).

[0361] Those skilled in the art should understand that the term user terminal covers any suitable type of wireless user equipment, such as a mobile phone, a portable data processing device, a portable network browser, or a vehicle-mounted mobile station.

[0362] Generally speaking, various embodiments of the present application may be implemented in hardware or dedicated circuits, software, logic, or any combination thereof. For example, some aspects may be implemented in hardware, while other aspects may be implemented in firmware or software that can be executed by a controller, a microprocessor, or other computing devices, although the present application is not limited thereto.

[0363] Embodiments of the present application can be implemented by a data processor of a mobile device executing computer program instructions, for example, in a processor entity, or by hardware, or by a combination of software and hardware. The computer program instructions can be assembly instructions, Instruction Set Architecture (ISA) instructions, machine instructions, machine-related instructions, microcode, firmware instructions, status setting data, or source code or object code written in any combination of one or more programming languages.

[0364] Any block diagram of a logical process in the accompanying drawings of the present application can represent program steps, or can represent interconnected logical circuits, modules and functions, or can represent a combination of program steps and logical circuits, modules and functions. The computer program can be stored in a memory. The memory can be of any type suitable for the local technical environment and can be implemented using any suitable data storage technology, such as but not limited to read-only memory (ROM), random access memory (RAM), optical memory devices and systems (Digital Versatile Disc DVD or CD disc), etc. The computer-readable medium can include a non-transitory storage medium. The data processor can be of any type suitable for the local technical environment, such as but not limited to a general-purpose computer, a special-purpose computer, a microprocessor, a Digital Signal Processing (DSP), an Application Specific Integrated Circuit (ASIC), a Field-Programmable Gate Array (FPGA), and a processor based on a multi-core processor architecture.

Claims

1. A data processing method, characterized in that: Applied to a first communication node, the method comprises: Acquire a first bit sequence, a first modulation order, a second modulation order, and a number of modulation symbols, wherein the first bit sequence includes a first subsequence and a second subsequence; Performing shaping encoding on the first subsequence according to the first modulation order to obtain a second bit sequence; performing channel coding on the second subsequence and the second bit sequence to obtain a third bit sequence; performing rate matching on the second subsequence, the second bit sequence, and the third bit sequence based on the first modulation order and the second modulation order to obtain a fourth bit sequence; Modulate and map the fourth bit sequence according to the second modulation order to obtain a modulation symbol sequence, and send a signal including the modulation symbol sequence to the second communication node; The first modulation order and the second modulation order are not equal, the length of the modulation symbol sequence is equal to the number of modulation symbols, and each symbol in the modulation symbol sequence is a constellation point in the modulation constellation corresponding to the second modulation order.

2. The method according to claim 1, characterized in that The length of the first subsequence is a multiple of Qm1 / 2-1 or a multiple of Qm1-1, where Qm1 is a first modulation order.

3. The method according to claim 1, characterized in that The second bit sequence is an output bit sequence of a shaping encoder, an output bit sequence of an amplitude-to-bit mapper or an output bit sequence of a multiplexer, and the second bit sequence includes a portion of bits of the first subsequence or a shaping bit sequence output by a channel decoder.

4. The method according to claim 1, characterized in that The third bit sequence includes at least one of the following: a portion of bits of the second subsequence; a portion of bits of the shaped bit sequence in the second bit sequence; all bits of the second bit sequence; all bits in the second bit sequence except the shaped bit sequence; Padding bits; Check bits generated by the channel encoder; All bits of the bit mask bit sequence in the second bit sequence.

5. The method according to claim 1, characterized in that In the case where the shaping coding adopts a distribution matcher; Performing shaping encoding on the first subsequence according to the first modulation order to obtain a second bit sequence includes: Encoding the first subsequence using the distribution matcher according to the first modulation order to obtain an amplitude symbol sequence with a non-uniform probability distribution; Convert each element in the amplitude symbol sequence into Qm1 / 2-1 bits according to a preset mapping method; splicing the Qm1 / 2-1 bits into the second bit sequence; Each element in the amplitude symbol sequence takes a value from the amplitude set {1,3,5,...,(2 Qm1 / 2 -3),(2 Qm1 / 2 -1)}, the length of the amplitude symbol sequence is NA, NA=2×Nx, the length of the second bit sequence is N1, N1=NA×(Qm1 / 2-1) or N1=Nx×(Qm1-2), Nx is the number of modulation symbols, and Qm1 is the first modulation order.

6. The method according to claim 1, characterized in that In the case where the shaping coding adopts a shaping encoder based on a block code; Performing shaping encoding on the first subsequence according to the first modulation order to obtain a second bit sequence includes: The first subsequence is encoded using the shaping encoder according to the first modulation order to obtain the second bit sequence.

7. The method according to claim 1, characterized in that performing rate matching on the second subsequence, the second bit sequence, and the third bit sequence based on the first modulation order and the second modulation order to obtain a fourth bit sequence, comprising: dividing the second subsequence, the second bit sequence and the third bit sequence into amplitude bit sequences and non-amplitude bit sequences; determining an interleaving matrix based on the first modulation order, the second modulation order, the amplitude bit sequence, and the non-amplitude bit sequence; Ng bits are taken from the interleaving matrix as the fourth bit sequence.

8. The method according to claim 7, characterized in that In a case where the first modulation order is greater than the second modulation order, determining an interleaving matrix based on the first modulation order, the second modulation order, the amplitude bit sequence, and the non-amplitude bit sequence includes: Selecting a first bit other than 2×Ng / Qm2 padding bits from the non-amplitude bit sequence, and forming first two rows of the interleaving matrix with the first bit; Selecting second bits other than (Qm1-2)×Ng / Qm2 padding bits from the amplitude bit sequence, and forming the last Qm1-2 rows of the interleaving matrix with the second bits; The interleaving matrix has Qm1 rows and Ng / Qm2 columns, Ng is the length of the fourth bit sequence, Qm1 is the first modulation order, and Qm2 is the second modulation order.

9. The method according to claim 7, characterized in that: In a case where the first modulation order is less than the second modulation order, determining an interleaving matrix based on the first modulation order, the second modulation order, the amplitude bit sequence, and the non-amplitude bit sequence includes: Select a third bit other than (Qm1-1)×Ng / Qm2 padding bits from the amplitude bit sequence, and use the third bit to form a row vector of the interleaving matrix whose row index is greater than 0 and less than Qm1; Select a fourth bit other than (Qm2-Qm1+1)×Ng / Qm2 padding bits from the non-amplitude bit sequence, and form a row vector of the interleaving matrix whose row index is 0 or whose row index is not less than Qm1 by the fourth bit; The interleaving matrix is ​​Qm2 rows and Ng / Qm2 columns, Ng is the length of the fourth bit sequence, Qm1 is the first modulation order, and Qm2 is the second modulation order.

10. The method according to claim 7, characterized in that Before performing modulation mapping on the fourth bit sequence according to the second modulation order to obtain a modulation symbol sequence, the method further includes: performing rate matching on the third bit sequence based on the first modulation order and the second modulation order to obtain a fourth bit sequence; Accordingly, dividing the second subsequence, the second bit sequence and the third bit sequence into an amplitude bit sequence and a non-amplitude bit sequence includes: The third bit sequence is divided into an amplitude bit sequence and a non-amplitude bit sequence.

11. The method according to claim 1, characterized in that: The fourth bit sequence includes at least one of the following: A portion of the bits in the amplitude bit sequence; A portion of the bits in a non-amplitude bit sequence.

12. The method according to claim 11, characterized in that The bit corresponding to the remainder of the index number in the fourth bit sequence divided by Qm2 being not less than 0 and not greater than 1 is the bit in the non-amplitude bit sequence; The bit corresponding to the remainder of the index number in the fourth bit sequence divided by Qm2 is not less than Qm1 and less than Qm2 is the bit in the non-amplitude bit sequence; In the case where the first modulation order is greater than the second modulation order, the bit corresponding to the index number in the fourth bit sequence divided by Qm2 with a remainder greater than 1 and less than Qm2 is the bit in the amplitude bit sequence; In the case where the first modulation order is smaller than the second modulation order, the bit corresponding to the index number in the fourth bit sequence divided by Qm2 with a remainder greater than 1 and less than Qm1 is the bit in the amplitude bit sequence; The bit corresponding to the remainder of the index number divided by Qm2 in the fourth bit sequence being greater than 1 and less than Qm′ is the bit in the amplitude bit sequence; Among them, Qm1 is the first modulation order, Qm2 is the second modulation order, and Qm′ is the smaller value between the first modulation order and the second modulation order.

13. The method according to claim 7 or 10, characterized in that: The amplitude bit sequence includes at least one of the following: a portion of bits of the second bit sequence; all bits of the second bit sequence; a portion of bits in the second bit sequence excluding a shaped bit sequence, wherein the shaped bit sequence is bits output by a channel decoder; All bits in the second bit sequence except the shaping bit sequence.

14. The method according to claim 7 or 10, characterized in that: The non-amplitude bit sequence includes at least one of the following: a portion of bits of the second subsequence; a portion of bits of the shaped bit sequence in the second bit sequence; Padding bits; Parity bits generated by the channel encoder.

15. A data processing method, characterized in that: Applied to a second communication node, the method comprises: Receiving a signal including a modulation symbol sequence sent by a first communication node, and acquiring a first modulation order, a second modulation order, and a number of modulation symbols; Demodulating the signal based on the second modulation order to obtain soft information of a fourth bit sequence; Performing rate matching according to the first modulation order, the second modulation order, and the soft information of the fourth bit sequence to obtain soft information corresponding to the third bit sequence, the second bit sequence, and the second subsequence; performing channel decoding on the soft information corresponding to the third bit sequence, the second bit sequence, and the second subsequence, respectively, to obtain an estimate of the second subsequence and an estimate of the second bit sequence; Performing shaping and decoding on the estimate of the second bit sequence according to the first modulation order to obtain an estimate of the first subsequence; determining an estimate of a first bit sequence from the estimate of the first subsequence and the estimate of the second subsequence; The first modulation order and the second modulation order are not equal, the length of the modulation symbol sequence is equal to the number of modulation symbols, each symbol in the modulation symbol sequence is a constellation point in the modulation constellation corresponding to the second modulation order, and the soft information is a log-likelihood ratio or a probability value.

16. The method according to claim 15, characterized in that The length of the first subsequence is a multiple of Qm1 / 2-1 or a multiple of Qm1-1, where Qm1 is a first modulation order.

17. The method according to claim 15, characterized in that The second bit sequence is an output bit sequence of a shaping encoder, an output bit sequence of an amplitude-to-bit mapper or an output bit sequence of a multiplexer, and the second bit sequence includes a portion of bits of the first subsequence or a shaping bit sequence output by a channel decoder.

18. The method according to claim 15, characterized in that The third bit sequence includes at least one of the following: a portion of bits of the second subsequence; a portion of bits of the shaped bit sequence in the second bit sequence; all bits of the second bit sequence; all bits in the second bit sequence except the shaped bit sequence; Padding bits; Check bits generated by the channel encoder; All bits of the bit mask bit sequence in the second bit sequence.

19. The method according to claim 15, characterized in that The fourth bit sequence includes at least one of the following: A portion of the bits in the amplitude bit sequence; A portion of the bits in a non-amplitude bit sequence.

20. The method according to claim 19, characterized in that The bit corresponding to the remainder of the index number in the fourth bit sequence divided by Qm2 being not less than 0 and not greater than 1 is the bit in the non-amplitude bit sequence; The bit corresponding to the remainder of the index number in the fourth bit sequence divided by Qm2 is not less than Qm1 and less than Qm2 is the bit in the non-amplitude bit sequence; In the case where the first modulation order is greater than the second modulation order, the bit corresponding to the index number in the fourth bit sequence divided by Qm2 with a remainder greater than 1 and less than Qm2 is the bit in the amplitude bit sequence; In the case where the first modulation order is smaller than the second modulation order, the bit corresponding to the index number in the fourth bit sequence divided by Qm2 with a remainder greater than 1 and less than Qm1 is the bit in the amplitude bit sequence; The bit corresponding to the remainder of the index number divided by Qm2 in the fourth bit sequence being greater than 1 and less than Qm′ is the bit in the amplitude bit sequence; Among them, Qm1 is the first modulation order, Qm2 is the second modulation order, and Qm′ is the smaller value between the first modulation order and the second modulation order.

21. The method according to claim 19, characterized in that The amplitude bit sequence includes at least one of the following: a portion of bits of the second bit sequence; all bits of the second bit sequence; a portion of bits in the second bit sequence excluding a shaped bit sequence, wherein the shaped bit sequence is bits output by a channel decoder; All bits in the second bit sequence except the shaping bit sequence.

22. The method according to claim 19, characterized in that The non-amplitude bit sequence includes at least one of the following: a portion of bits of the second subsequence; a portion of bits of the shaped bit sequence in the second bit sequence; Padding bits; Parity bits generated by the channel encoder.

23. A communication node, characterized in that: include: processor; The processor is used to implement the data processing method as described in any one of claims 1-14 or claims 15-22 when executing the computer program.

24. A computer-readable storage medium storing a computer program, characterized in that: When the computer program is executed by a processor, the data processing method according to any one of claims 1 to 14 or claims 15 to 22 is implemented.

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