Method and system for improving error correction efficiency

Abstract

The invention provides a method and system for improving error correction efficiency, and the method comprises the steps: calculating the real error rate of a secret key in an error correction process, and determining the next error correction segment length according to the calculated real error rate when each error correction is successful; the error correction segment length is determined according to the pre-analyzed relationship among the segment length, the real error rate and the error rate. According to the method, through modeling, the corresponding appropriate segment length is selected to complete error correction according to the keys with different code lengths and bit error rate ranges, so that the error correction efficiency of the system is effectively improved.

Description

Technical Field

[0001] The present invention belongs to the technical field of quantum key distribution, and particularly relates to a method and system for improving error correction efficiency. Background Technique

[0002] The statements in this part only provide background technical information related to the present invention, and do not necessarily constitute prior art.

[0003] Quantum Key Distribution (QKD) utilizes the fundamental physical properties of quantum to achieve secure key distribution. The sender prepares the key information to be distributed as photons in different quantum states. By using the basic principles of quantum mechanics, it is ensured that eavesdropping and deciphering during the information transmission process can be perceived and processed by the receiver, thus providing a more reliable key distribution method. As Figure 1 shown, it is the complete QKD implementation process.

[0004] During the quantum key distribution process, the purpose of error correction is to correct the sifted keys with certain differences at both ends by publicly disclosing part of the information to ensure that the keys at both ends can be kept consistent.

[0005] Currently, there are mainly two algorithms for error correction in the quantum key extraction process: the winnow algorithm and the LDPC algorithm. The winnow algorithm has low resource consumption and is simple to implement, but its error correction efficiency is poor; the LDPC algorithm has a complex implementation process and a high algorithm complexity, resulting in a low error correction processing bandwidth, but its error correction efficiency is high. The winnow error correction uses parity-check codes to detect errors and Hamming codes to correct single-bit errors. After multiple rounds of interleaving and iteration, the original keys at both ends are made consistent. When the parity check is consistent in each round, it is considered that the error correction is completed, and the hash value or CRC value of the keys at both ends is calculated. If the hash value or CRC value is different, the batch of keys is discarded; if the hash value or CRC value is the same, the error-corrected keys are output. The main interaction process is as Figure 2 shown.

[0006] During the error correction process, the code length n includes information bits and parity-check bits. If the information bits are k, then the parity-check bits are m = n - k, and the code rate is R = k / n. The error correction efficiency is a parameter used to measure the error correction performance, also known as the F factor. The physical meaning of the error correction efficiency is the ratio of the redundant information amount I Redundancy brought by error correction to the information amount I Lose lost due to the channel transition probability, that is:

[0007]

[0008] In general, F > 1. Only in the ideal case, F = 1, that is, the redundant information brought by error correction exactly compensates for the information loss caused by the channel transition probability.

[0009] Assume that the code elements 0 and 1 in the GF(2) field are equally probable, the original message sequence is C with a length of k, and the channel transition probability is e; the sequence P leaked during the error correction process has a length of n - k. The redundant information brought by error correction is the sequence P. Therefore, we have:

[0010] I Redundancy = n - k

[0011] If we define system A as follows: both C and P are transmitted through a BSC channel with a channel transition probability of e, then the information loss of system A is expressed as follows:

[0012] I Lose = [-e log2e - (1 - e) log2(1 - e)] n

[0013] At this time, the following equation holds:

[0014]

[0015]

[0016] The calculation formula for the F factor of system A can be obtained as follows:

[0017]

[0018] If we define system B as follows: C is transmitted through a BSC channel with a channel transition probability of e, and P is transmitted through a noiseless channel, then the information loss of system B is expressed as follows:

[0019] I Lose = [-e log2e - (1 - e) log2(1 - e)] k

[0020] At this time, the following equation holds:

[0021]

[0022] The calculation formula for the F factor of system B can be obtained as follows:

[0023]

[0024] The error correction for the QKD system has some differences from traditional error correction. Traditional error correction only focuses on whether the original message sequence C can be correctly corrected after reaching the destination during transmission through the BSC channel. The error correction for the QKD system is used to correct the symmetric keys generated at both ends of the key distribution device. The key verification sequence at one end is transmitted to the other end through the BSC channel or an error-free channel to complete error correction. Since the QKD system model is constructed based on the error loss of the error-corrected key, it is calculated according to System A.

[0025] As Figure 3 shown in the figure of the measured efficiency and the corresponding bit error rate relationship of the currently adopted error correction algorithm, it can be seen that when the bit error rate is <2%, the error correction efficiency even reaches above 4.0, which is very different from the target error correction efficiency F of about 1.5. The poor error correction efficiency affects the privacy amplification factor, thereby affecting the final key generation amount. Summary of the Invention

[0026] In order to solve the above problems, the present invention proposes a method and system for improving error correction efficiency. The present invention completes error correction by modeling and selecting the corresponding appropriate segment length according to the keys with different code lengths and bit error rate ranges, thereby effectively improving the error correction efficiency of the system.

[0027] According to some embodiments, the present invention adopts the following technical solutions:

[0028] A method for improving error correction efficiency, comprising the following steps:

[0029] During error correction, calculate the true error rate of the key, and determine the next error correction segment length according to the calculated true error rate when each error correction is successful;

[0030] The error correction segment length is determined according to the relationship between the pre-analyzed segment length, true error rate and bit error rate.

[0031] As an alternative implementation, when the screened key is generated after the first basis, it is processed according to the original error correction segment length.

[0032] As an alternative implementation, when a certain error correction is successful, select the next error correction segment length processing method according to the true error rate. When a certain error correction fails, select the segment length according to the maximum bit error rate range for the next error correction.

[0033] As an alternative implementation, calculate the total number of segments, the amount of leaked key after each error correction, the code rate after each error correction, the probability of successful error correction, and the error rate of the total key after each error correction according to the requirements of the code length, error rate and segmentation strategy.

[0034] As an alternative embodiment, when the error rate is less than or equal to the set value, a graph of different error rate intervals, selected segment lengths, iteration probabilities, and corresponding error correction efficiencies is plotted, and the error correction segment length is determined based on the graph.

[0035] As a further embodiment, among all the segmentation strategies, select the segmentation strategy that can complete error correction and has the best error correction efficiency.

[0036] As a further embodiment, select a segment length whose error rate after error correction is lower than the initial error rate and that can take into account the amount of key leakage.

[0037] As an alternative embodiment, when the error rate is greater than the set value, after increasing the segment length, a graph of different error rate intervals, selected segment lengths, iteration probabilities, and corresponding error correction efficiencies is plotted, and the error correction segment length is determined based on the graph.

[0038] As an alternative embodiment, the error correction segment length is pre-configured and dynamically adjusted.

[0039] A system for improving error correction efficiency, comprising:

[0040] A selection module, configured to calculate the true error rate of the key during the error correction process, and determine the next error correction segment length according to the calculated true error rate each time the error correction is successful;

[0041] A storage module, configured to store the relationship between the error correction segment length, the true error rate, and the error code rate.

[0042] A computer-readable storage medium for storing computer instructions, which, when executed by a processor, complete the steps in the above method.

[0043] An electronic device, comprising a memory, a processor, and computer instructions stored on the memory and running on the processor, which, when the computer instructions are run by the processor, complete the steps in the above method.

[0044] Compared with the prior art, the beneficial effects of the present invention are:

[0045] The present invention uses a mathematical modeling method to determine the error correction segment length that should be used under different error code rates, and thus selects an appropriate segment length according to the error code rate to complete error correction, effectively improving the error correction efficiency of the system.

[0046] The error correction segment length of the present invention can be pre-set or configured by software, and dynamically adjusted to achieve the optimal algorithm.

[0047] The present invention can theoretically assist in improving the error correction efficiency by reducing the error correction code length and allowing a certain probability of error correction failure. For a quantum key distribution system, the first error correction can select the segment length according to the maximum bit error rate range. During the error correction process, the real error rate information is statistically analyzed, and the real error rate information obtained each time is used to guide the selection of the next error correction segment length. When the current error correction fails, the segment length is immediately selected according to the maximum bit error rate range, and the subsequent real error rate information is still used to guide the selection of the next error correction segment length.

[0048] To make the above objects, features, and advantages of the present invention more apparent and understandable, the following specific embodiments are given in detail in conjunction with the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0049] The accompanying drawings forming a part of this specification are used to provide a further understanding of the present invention. The schematic embodiments and descriptions thereof of the present invention are used to explain the present invention and do not constitute an improper limitation of the present invention.

[0050] Figure 1 is a schematic diagram of the implementation process of the existing quantum key distribution;

[0051] Figure 2 is a schematic diagram of the existing error correction process;

[0052] Figure 3 is a measured relationship diagram of the error correction efficiency and the bit error rate of the winnow algorithm in the QKD system;

[0053] Figure 4 is a relationship diagram of the error rate after one error correction and the initial error rate under different segment lengths in this embodiment;

[0054] Figure 5 is a diagram of the error correction efficiency corresponding to different bit error rates in the original intervals of this embodiment;

[0055] Figure 6 is a diagram of the error correction efficiency corresponding to different bit error rates in each interval of this embodiment;

[0056] Figure 7 is a diagram of the error correction efficiency when the bit error rate exceeds 3.5%. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0057] The present invention will be further described below in conjunction with the drawings and embodiments.

[0058] It should be noted that the following detailed descriptions are all illustrative and are intended to provide further explanations of the present invention. Unless otherwise specified, all technical and scientific terms used herein have the same meaning as commonly understood by those of ordinary skill in the technical field to which the present invention belongs.

[0059] It should be noted that the terms used herein are only for describing specific embodiments and are not intended to limit the exemplary embodiments according to the present invention. As used herein, unless the context clearly indicates otherwise, the singular forms are also intended to include the plural forms. In addition, it should be understood that when the terms "comprising" and / or "including" are used in this specification, they specify the presence of features, steps, operations, devices, components, and / or combinations thereof.

[0060] Embodiment 1

[0061] Necessary descriptions are given first, such as Figure 2 As shown, the following are the key steps in the error correction process:

[0062] 1) Segment the key and calculate the corresponding parity check code (simply perform modulo-2 addition on each bit in the segment to obtain a 1-bit modulo-2 addition result as the parity check code), and compare whether the parity check codes at both ends are the same. In each round of error correction process, the segmentation rule is as follows:

[0063] Table 1

[0064]

[0065] Table 1 shows the segmented length of the Shifted key corresponding to the respective error correction rounds, in units of bits, and the maximum number of error correction iterations is 8 rounds.

[0066] 2) Encode the key with inconsistent parity using the Hamming matrix to obtain the Hamming code of the key in the corresponding segment area. The Hamming matrices for the corresponding segment areas are T4*15, T5*31, T6*63, T7*127, T8*255, T9*511, T10*1023, T11*2047. Taking T4*15 as an example:

[0067]

[0068] Its structure is regular. In each column of the matrix, from right to left, are the binary values of 1 to 15. The same is true for T5*31, T6*63, T7*127, and T8*255. In each column of the matrix, from right to left, are the binary values of 1 to N (N is the number of columns of the matrix), which will not be elaborated here. By comparing the Hamming codes at both ends, the corresponding key error can be found. During the error correction process, just flip the key. Here, the principle of Hamming error correction is illustrated by an example. Suppose the original key at the Alice end = [0 0 1 1 0 1 0 1 1 0 1 0 1 1 1], and suppose the original key at the Bob end = [0 0 0 1 0 1 0 1 1 0 1 0 1 1 1]. Through parity check, the parity of Alice = ^[0 0 11 0 1 0 1 1 0 10 1 1 1] = 1, and the parity of Bob = ^[0 0 0 1 0 1 0 1 1 0 1 0 1 1 1] = 0. An error is found through the fact that the parity of Alice ≠ the parity of Bob. Perform Hamming encoding on the Alice end and the Bob end respectively:

[0069]

[0070]

[0071] The Hamming code at the Alice end = [0 0 0 1], and the Hamming code at the Bob end = [1 1 0 1]. By comparing the Hamming codes at both ends, the position information of the bits that are inconsistent is found. [0 0 0 1]^[1 1 0 1] = [1 1 0 1]. It can be seen that the hexadecimal [1 1 0 1] is 13. It can be seen that the 13th bit of the keys corresponding to Alice and Bob among the 1 to 15 bits is inconsistent. At this time, flip the 13th bit key at the Alice end to complete the error correction of the keys at both the Alice and Bob ends;

[0072] 3) Since the Hamming code can only correct 1 bit error in the corresponding section, after each round of error correction, data permutation processing is performed on the key. The maximum length of the Sifted Key processed by the error correction module is 1020 Kbits. The pseudo-random sequence M sequence generated by the primitive polynomial constructing the LFSR can generate at most 2^20–1 pseudo-random addresses, which can cover each bit of the Sifted Key. After each round of parity check and Hamming error correction, data permutation is performed except for the 8th round;

[0073] 4) According to the Hamming code error correction, the true error rate corresponding to the key is statistically calculated;

[0074] 5) When the parity check codes are consistent, the key is output for hash value or CRC value calculation, and the calculation results are compared. If the results are consistent, it is determined that the error correction is successful and the keys are consistent; if the results are inconsistent, it is determined that the error correction fails and the keys for this error correction are discarded;

[0075] 6) After the error correction ends, this algorithm gives a flag indicating whether the error correction is successful or failed, and the key amount before and after the error correction is the same.

[0076] To solve the problem in the prior art that when the bit error rate meets the conditions, the error correction efficiency does not meet the requirements, and the poor error correction efficiency affects the privacy amplification factor, thus affecting the final key generation amount.

[0077] This embodiment proposes a method for improving the winnow error correction efficiency in the process of quantum key distribution. By means of mathematical modeling, according to the keys with different code lengths and bit error rate ranges, the corresponding appropriate segment lengths are selected to complete the error correction. The specific process is as follows:

[0078] For keys with a code length of M and an error rate of e, the segmentation strategy is N (meaning that each segment has N bits). If the bit errors in each segment follow a binomial distribution, then after one parity check, the number of segments S with different parity checks between the two parties is:

[0079]

[0080] There are a total of M / N segments, and the situation of each segment is the same.

[0081] There is 1 parity check error:

[0082] There are 3 parity check errors:

[0083] Other parity check errors are similar to the above.

[0084] For each winnow error correction, the leaked key amount is:

[0085]

[0086] M / N is the total number of segments, the information announced by the parity check;

[0087] S log2N is the number of bits announced after the Hamming interaction.

[0088] Therefore, after E error corrections, the code rate: R = d / M.

[0089]

[0090]

[0091]

[0092] The error correction leakage amount is related to the number of error correction iterations, and the F factor is as follows:

[0093]

[0094] Let e1 be defined as the probability that there is only one error in each segment during one error correction. Then the probability of successful error correction is expressed as:

[0095]

[0096] Each segment has N bits, 2n + 1 bits are in error, and N - (2n + 1) bits are correct. So after one error correction, the number of successfully corrected keys is Se1, and the probability of introducing key errors is The probability of randomly correcting 1 bit out of multiple bit errors is After one error correction, the error rate e in the total key n is:

[0097]

[0098]

[0099]

[0100]

[0101]

[0102]

[0103]

[0104] As can be obtained as Figure 4 shown, the relationship diagram of the error rate after one error correction and the initial error rate under different segment lengths. It can be seen that the longer the segment length is selected, the less the key leakage amount is, but the error rate after error correction is also higher, and sometimes even higher than the initial error rate. Therefore, on the premise of ensuring that the keys at both ends of AB are consistent after 8 rounds of error correction, the key leakage amount should be considered comprehensively.

[0105] If there is only one error left after the first 7 rounds of error correction, then the error will surely be corrected successfully in the 8th round. So all the segmentation strategies with only one error left after 7 rounds of error correction can be calculated first, and then the strategy with the best error correction efficiency can be selected from them. In the 7th round of error correction, in the case of a code length of 1 Mbit, control the probability of correcting 1 bit error in the 7th round to be lower than

[0106] The original algorithm model (taking the upper limit calculation) is shown in Table 2:

[0107] Table 2

[0108]

[0109] The error correction efficiency corresponding to different bit error rates in each interval of the original algorithm is as follows Figure 5 shown

[0110] When the error rate exceeds 3.5%, the theoretical probability of the last error correction required is 1.6*10 -5 , higher than 10 -6 . There is still a relatively high risk of failure. The algorithm bottleneck is between 3.5% and 4%. As can be seen from the above table, the error correction efficiency is relatively high when 3.5% < e < 4%, but at the same time, it reaches the algorithm bottleneck. Therefore, different segment lengths are selected according to different bit error rate intervals to optimize the algorithm

[0111] Based on the original winnow error correction code length, the segment length is selected for error correction according to different bit error rate intervals. Through the above calculation of each round of error correction iteration convergence, assuming a certain error correction failure rate is allowed, such as the error correction is controlled within 4 rounds, and the iteration probability is controlled at 10 -4 (assuming that before the segment length reaches 1023, the average error rate is 10 -4 ), the convergence of each selection of different segment lengths can be evaluated according to the above formula

[0112] For example, for an error rate within 0.5%, the segment length is selected as 63 for the first time, and the convergence probability is 1.4*10^-3. The segment length is selected as 255 for the second time, and the convergence probability is 4.3*10^-4... and so on to evaluate the situation of each round of iteration, and determine that the iteration probability in the last round is less than 10 -4 . According to the above method, the calculation is shown in Table 3

[0113] Table 3

[0114]

[0115]

[0116] Accordingly, the error correction efficiency diagram corresponding to different bit error rates in each interval is drawn, as shown in Figure 6 shown

[0117] When the bit error rate exceeds 3.5%, the above algorithm has basically reached the bottleneck and cannot correct errors normally. Therefore, the segment length 7 is increased to solve the situation where the bit error rate exceeds 3.5% (see Table 4), as shown in Figure 7 shown

[0118] Table 4

[0119]

[0120] For the bit error rate range of each error correction and the error correction code length used, the convergence can be evaluated through the error correction iteration probability of each round. The optimal selection can be completed through the above modeling

[0121] In actual application, the error correction segment length can be selected as any value. What is described in this embodiment is only for the convenience of data reading and writing in the actual use process.

[0122] Embodiment 2

[0123] In the actual post-processing error correction process, the following steps can be adopted to improve the error correction efficiency.

[0124] When the first Shifted Key is sent, it is still processed according to the original error correction segment length processing method, that is, the error correction segment length per round is processed as shown in Table 5.

[0125] Table 5

[0126]

[0127] During the error correction process, the true error rate of the key is statistically calculated. When the first error correction is successful, the next error correction segment length processing method is selected according to the statistically calculated true error rate. When the first error correction fails, the next error correction is still carried out as the first time;

[0128] Adjust the segment length strategy according to the error code rate statistically calculated last time. Before error correction, select an appropriate segment length for error correction according to different error code rate intervals. The error correction segment length is evaluated according to the method provided in Embodiment 1 to select the optimal efficiency. The segment length can be preset or configured and changed by software, and dynamically adjusted to achieve the optimal algorithm. For the winnow error correction proposed in this proposal, the segment length selection is carried out according to Table 6 each time.

[0129] Table 6

[0130]

[0131]

[0132] When a certain error correction fails in the middle, the next time it is processed according to the first error correction processing method. Under the condition of allowing a certain number of error corrections to fail, keep carrying out according to the above strategy to ensure the optimal error correction efficiency each time.

[0133] Those skilled in the art should understand that the embodiments of the present invention can be provided as a method, a system, or a computer program product. Therefore, the present invention can take the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware aspects. Moreover, the present invention can take the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk memory, CD-ROM, optical memory, etc.) containing computer-usable program code.

[0134] The present invention is described with reference to the flowcharts and / or block diagrams of methods, apparatuses (systems), and computer program products according to embodiments of the present invention. It should be understood that each flow and / or block in the flowchart and / or block diagram, and the combinations of flows and / or blocks in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to the processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing devices to generate a machine, such that the instructions executed by the processor of the computer or other programmable data processing devices produce a means for implementing the functions specified in the Figure 1 one or more flows and / or blocks Figure 1 one or more blocks.

[0135] These computer program instructions can also be stored in a computer-readable memory that can direct a computer or other programmable data processing device to work in a specific manner, such that the instructions stored in the computer-readable memory produce a manufactured article including an instruction means that implements the functions specified in the Figure 1 one or more flows and / or blocks Figure 1 one or more blocks.

[0136] These computer program instructions can also be loaded onto a computer or other programmable data processing device, such that a series of operation steps are executed on the computer or other programmable device to generate a computer-implemented process, and thus the instructions executed on the computer or other programmable device provide steps for implementing the functions specified in the Figure 1 one or more flows and / or blocks Figure 1 one or more blocks.

[0137] The above are only the preferred embodiments of the present invention and are not used to limit the present invention. For those skilled in the art, the present invention can have various changes and modifications. Any modifications, equivalent replacements, improvements, etc. made by those skilled in the art without creative efforts within the spirit and principle of the present invention shall be included in the protection scope of the present invention.

Claims

1. A method for improving error correction efficiency, characterized in that, Including the following steps: During the error correction process, calculate the true error rate of the key. When each error correction is successful, determine the next error correction segment length according to the calculated true error rate; The error correction segment length is determined according to the relationship between the segment length, the true error rate, and the bit error rate analyzed in advance.

2. The method for improving error correction efficiency according to claim 1, characterized in that, When the screened key is generated for the first time after the basis, it is processed according to the original error correction segment length.

3. The method for improving error correction efficiency according to claim 1, characterized in that, When a certain error correction is successful, select the next error correction segment length processing method according to the true error rate. When a certain error correction fails, select the segment length within the maximum bit error rate range for the next error correction.

4. A method for improving error correction efficiency according to claim 1, characterized in that, According to the requirements of the code length, error rate, and segmentation strategy, calculate the total number of segments, the amount of leaked key after each error correction, the code rate after each error correction, the probability of successful error correction, and the error rate of the total key after each error correction.

5. A method for improving error correction efficiency as described in claim 1, characterized in that, in When the error rate is less than or equal to the set value, draw a chart of different bit error rate intervals, selected segment lengths, iteration probabilities, and corresponding error correction efficiencies, and determine the error correction segment length based on the chart.

6. A method for improving error correction efficiency as described in claim 5, characterized in that, Select the segmentation strategy that can complete error correction and has the best error correction efficiency among all segmentation strategies.

7. The method for improving error correction efficiency according to claim 5, characterized in that, Select the segment length whose error rate after error correction is lower than the initial error rate and can take into account the key leakage amount.

8. A method for improving error correction efficiency according to claim 1, characterized in that, When the error rate is greater than the set value, after increasing the segment length, draw a chart of different bit error rate intervals, selected segment lengths, iteration probabilities, and corresponding error correction efficiencies, and determine the error correction segment length based on the chart.

9. The method for improving error correction efficiency according to claim 1, characterized in that The error correction segment length is pre-configured and dynamically adjusted.

10. A system for improving error correction efficiency, characterized in that, Including: A selection module configured to calculate the true error rate of the key during the error correction process and determine the next error correction segment length according to the calculated true error rate when each error correction is successful; A storage module configured to store the error correction segment length and the relationship between the true error rate and the bit error rate.

11. A computer-readable storage medium, characterized in that, For storing computer instructions, when the computer instructions are executed by a processor, the steps in the method described in any one of claims 1-9 are completed.

12. An electronic device, characterized in that, Including a memory, a processor, and computer instructions stored on the memory and running on the processor. When the computer instructions are run by the processor, the steps in the method described in any one of claims 1-9 are completed.

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