Key generation system of physical unclonable function based on alternating current detection

Abstract

The invention provides a key generation system of a physical unclonable function based on alternating current detection, and belongs to the technical field of physical unclonable functions, the system comprises a PUF module used for converting an externally input alternating current voltage signal and outputting a digital signal, and a control logic module electrically connected with the PUF module and used for generating a key according to the digital signal, wherein the PUF module comprises two capacitance-resistance circuits which are symmetrically arranged and a sensitive amplifier, an alternating current voltage signal passes through the two capacitance-resistance circuits which are symmetrically arranged to obtain a first voltage and a second voltage, and a digital signal is output after the first voltage and the second voltage are subtracted through the sensitive amplifier. And the voltage difference signal is further amplified by utilizing the voltage division characteristics of capacitive reactance and impedance under the alternating current signal through the two symmetrically arranged capacitance resistance circuits, so that the sensitivity of the key generation system is improved.

Description

Technical Field

[0001] The present invention relates to the technical field of physical unclonable functions, and particularly to a key generation system of a physical unclonable function based on AC detection. Background Art

[0002] The PUF is scientifically named as physical unclonable function, which mainly utilizes the deep sub-micron variations occurring naturally during the semiconductor physical production process and endows each transistor with slightly random electrical characteristics. These unique characteristics form the basis of the unique identity of the chip.

[0003] The SC PUF circuit is composed of four modules: a switched-capacitor circuit, a latch-style sense amplifier (LSSA), a register (REG), and a control logic (CTL). When the enable signal of the control logic module is valid and the select signal of the control logic module is logic low, the upper and lower plates of the capacitors C 1P , C 2P , C 1N and C 2N are both connected to the ground wire, and the switched-capacitor circuit operates in a discharge state and stores no charge. When the select signal of the control logic module is logic high, the deviation in the ratio of the sampling capacitors C 1P and C 2P during the manufacturing process will be converted into a voltage deviation. The latch-style sense amplifier amplifies the voltage difference and converts it into a digital output. The register stores the digital outputs of all PUF cells, and the control logic module is used to generate control signals αCLK_REG (clock signal), αEN, and αSEL and drive each module to work orderly based on the control signals. The physical unclonable function circuit based on the switched-capacitor circuit mainly relies on the random capacitance errors generated during the manufacturing process to generate a unique identification function. After the capacitance ratio mismatch is converted into a voltage difference value, it is amplified by the latch-style sense amplifier and then converted into a digital output. Considering that the latch-style sense amplifier will generate an offset voltage due to the matching of MOS transistors during the manufacturing process, the effective deviation voltage finally determining the output of the latch-style sense amplifier is the voltage difference value plus the offset voltage. The polarity of the effective deviation voltage determines whether the latch-style sense amplifier outputs a digital 0 or a digital 1. Moreover, the absolute value of the deviation voltage in the PUF cell determines the output reliability of the PUF cell. The larger the absolute value of the deviation voltage, the lower the probability that the deviation voltage changes its polarity due to the power supply voltage and temperature, and the higher the reliability. The deviation voltage is mainly determined by the process deviation that is difficult to avoid during the chip manufacturing process, so it cannot be determined during the design.

[0004] However, the SC PUF circuit has a technical problem of low sensitivity. The main reason is that the tiny error of the capacitor is usually only at the micron level, and the change in the capacitance of the capacitor itself is extremely small, resulting in a low voltage difference that cannot be detected by subsequent circuits. Secondly, as the process scale decreases, the leakage current of the SC PUF circuit gradually increases, and the key quantization method based on the principle of charge conservation gradually becomes ineffective. The process size of integrated circuits is generally at the micron level, and there will be errors in the process of quantizing capacitors using the principle of charge conservation during production. Therefore, there is a technical problem in the prior art that the sensitivity of the physical unclonable function key generation system is not high. Summary of the invention

[0005] In view of this, it is necessary to provide a key generation system based on a physical unclonable function of AC detection to solve the technical problem of low sensitivity of the physical unclonable function key generation system of the switched capacitor in the prior art.

[0006] In order to solve the above technical problems, the present invention provides a key generation system based on a physical unclonable function of AC detection, comprising: The PUF module is used to convert the external input AC voltage signal and output a digital signal; A control logic module, electrically connected to the PUF module, for generating a key according to the digital signal; Among them, the PUF module includes two symmetrically arranged capacitor-resistor circuits and a sensitive amplifier; the AC voltage signal obtains a first voltage and a second voltage through the two symmetrically arranged capacitor-resistor circuits, and the first voltage and the second voltage are differentiated through the sensitive amplifier to output a digital signal.

[0007] In a possible implementation, the symmetrically arranged two-way capacitor-resistance circuit includes: A first capacitor, a second capacitor, a first resistor, a second resistor, a first switch, and a second switch; One end of the first capacitor is grounded, the other end of the first capacitor is electrically connected to one end of the first resistor, the sensitive amplifier and the control logic module, and the other end of the first resistor is electrically connected to the first switch; One end of the second capacitor is grounded, the other end of the second capacitor is electrically connected to one end of the second resistor, the sensitive amplifier and the control logic module, and the other end of the second resistor is electrically connected to the second switch.

[0008] In a possible implementation, the sense amplifier includes: a first MOS tube, a second MOS tube, a third MOS tube, a fourth MOS tube, a fifth MOS tube and a sixth MOS tube; The source of the first MOS transistor is electrically connected to an external voltage source. The drain of the first MOS transistor is electrically connected to the sources of the second MOS transistor and the third MOS transistor respectively. The drain of the second MOS transistor is electrically connected to the source of the fourth MOS transistor. The gate of the second MOS transistor is electrically connected to the gate of the fourth MOS transistor. The drain of the third MOS transistor is electrically connected to the source of the fifth MOS transistor. The gate of the third MOS transistor is electrically connected to the gate of the fifth MOS transistor. The source of the sixth MOS transistor is electrically connected to the drain of the fourth MOS transistor and the gate of the fifth MOS transistor respectively. The drain of the sixth MOS transistor is grounded; The common terminal of the first capacitor and the first resistor is electrically connected to the drain of the second MOS transistor, the source of the fourth MOS transistor, the gate of the third MOS transistor, the gate of the fourth MOS transistor, and the control logic module; The common terminal of the second capacitor and the second resistor is electrically connected to the gate of the second MOS transistor, the gate of the fourth MOS transistor, the drain of the third MOS transistor, the source of the fifth MOS transistor, and the control logic module.

[0009] In a possible implementation, the PUF module further includes: an amplification module and a rectification module; The first voltage and the second voltage are amplified by the amplification module to obtain the amplified first voltage and second voltage. The amplified first voltage and second voltage are rectified by the rectification module to output the first DC voltage and the second DC voltage. The first DC voltage and the second DC voltage are differentiated by a sense amplifier to output a digital signal.

[0010] In a possible implementation, the amplification module includes: a first amplifier and a second amplifier; The first voltage is amplified by the first amplifier to obtain the amplified first voltage. The second voltage is amplified by the second amplifier to obtain the amplified second voltage.

[0011] In a possible implementation, the rectification module includes: a first rectifier and a second rectifier; The amplified first voltage is rectified by the first rectifier to obtain the first DC voltage. The amplified second voltage is rectified by the second rectifier to obtain the second DC voltage.

[0012] In a possible implementation, the system further includes: a register; The register is electrically connected to the PUF module, and is configured to receive the digital signal and store the digital signal to obtain stored data; The control logic module is further communicatively connected to the register, and is configured to generate a key according to the stored data.

[0013] In a possible implementation, The control logic module is also electrically connected to the first switch and the second switch, and is configured to generate a first control signal, and respectively control the opening or closing of the first switch and the second switch based on the first control signal.

[0014] In a possible implementation manner, The control logic module is also electrically connected to the gate of the first MOS transistor and the gate of the sixth MOS transistor, and is configured to generate a second control signal, and respectively control the on / off states of the first MOS transistor and the sixth MOS transistor based on the second control signal.

[0015] In a possible implementation manner, the number of the PUF modules is n, where n is an integer greater than 2.

[0016] The beneficial effects of the present invention are as follows: The present invention provides a key generation system based on an alternating current detection-based physical unclonable function. Compared with the existing key generation system based on direct current sampling based on the principle of charge conservation in a physical unclonable function, there is a problem of low sensitivity when extracting keys. The key generation system proposed by the present invention mainly consists of a PUF module and a control logic module. Among them, the capacitive resistor circuit symmetrically arranged in the PUF module mainly consists of two paths of resistors and capacitors connected in series compared with the traditional capacitive switch circuit. The capacitive resistor circuit mainly uses the voltage division characteristics of capacitive reactance and impedance under an alternating current signal to extract the voltage difference signal. Because the voltage division phases of the capacitor and the resistor are inconsistent, the voltage in the capacitor lags behind the current by 90 degrees in phase, while the voltage and current in the resistor are in the same phase. Therefore, there is a 90-degree phase difference between the voltage divisions obtained by the resistor and the capacitor in the capacitive resistor circuit. Compared with a pure capacitive circuit, it brings a preliminary amplification effect to the voltage difference caused by the random capacitance error generated during the manufacturing process of the circuit. The capacitive resistor circuit has no strict timing restrictions compared with a pure capacitive circuit, and it is not based on the principle of charge conservation, so it will not be affected by the charge stray and feedthrough errors in the circuit, thus improving the sensitivity of the circuit. Secondly, the control logic module controls the PUF module accordingly to generate accurate random keys. Description of the Drawings

[0017] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following will briefly introduce the drawings required for the description of the embodiments. Obviously, the following drawings are only some embodiments of the present invention. For those skilled in the art, without creative efforts, other drawings can be obtained based on these drawings.

[0018] Figure 1 It is a schematic structural diagram of an embodiment of the key generation system based on an alternating current detection-based physical unclonable function provided by the present invention; Figure 2Key generation framework diagram of an embodiment of the key generation system for physical unclonable functions based on AC detection provided by the present invention; Figure 3 Series capacitance-resistance circuit diagram of an embodiment of the key generation system for physical unclonable functions based on AC detection provided by the present invention; Figure 4 Phase difference diagram of the first divided voltage and the second divided voltage of an embodiment of the key generation system for physical unclonable functions based on AC detection provided by the present invention; Figure 5 ΔV in the series capacitance-resistance circuit of an embodiment of the key generation system for physical unclonable functions based on AC detection provided by the present invention and Function diagram; Figure 6 Model simulation diagram of the series capacitance-resistance circuit of an embodiment of the key generation system for physical unclonable functions based on AC detection provided by the present invention; Figure 7 LSSA output digital signal diagram of an embodiment of the key generation system for physical unclonable functions based on AC detection provided by the present invention; Figure 8 Monte Carlo data histogram of an embodiment of the key generation system for physical unclonable functions based on AC detection provided by the present invention; Figure 9 Basic structure diagram of the unit of the existing physical unclonable function of an embodiment of the key generation system for physical unclonable functions based on AC detection provided by the present invention; Figure 10 Pure capacitance circuit diagram of an embodiment of the key generation system for physical unclonable functions based on AC detection provided by the present invention; Figure 11 ΔV in the pure capacitance circuit of an embodiment of the key generation system for physical unclonable functions based on AC detection provided by the present invention and Function diagram; Figure 12 |ΔV| and σ function diagram in the pure capacitance circuit of an embodiment of the key generation system for physical unclonable functions based on AC detection provided by the present invention; Figure 13 Model simulation diagram of the switched capacitor circuit of an embodiment of the key generation system for physical unclonable functions based on AC detection provided by the present invention. Detailed implementation manners

[0019] The following will clearly and completely describe the technical solutions in the embodiments of the present invention with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without creative efforts belong to the scope of protection of the present invention.

[0020] In the description of the embodiments of the present application, unless otherwise specified, the meaning of "a plurality of" is two or more.

[0021] In the embodiments of the present invention, the terms "include" and "have" and any variations thereof are intended to cover non-exclusive inclusion. For example, a process, method, device, product or equipment that includes a series of steps or modules does not necessarily have to be limited to those steps or modules clearly listed, but may include other steps or modules that are not clearly listed or are inherent to these processes, methods, products or equipment.

[0022] In the embodiments of the present invention, the naming or numbering of steps does not mean that the steps in the method flow must be executed in the time / logical order indicated by the naming or numbering. The named or numbered process steps can be changed in the execution order according to the technical purpose to be achieved, as long as the same or similar technical effects can be achieved.

[0023] Referring to "embodiments" in this article means that the specific features, structures or characteristics described in connection with the embodiments may be included in at least one embodiment of the present invention. The phrase appears in various positions in the specification does not necessarily refer to the same embodiment, nor is it an independent or alternative embodiment mutually exclusive with other embodiments. Those skilled in the art explicitly and implicitly understand that the embodiments described herein can be combined with other embodiments.

[0024] The following nouns are supplemented and explained: Symmetric setting means that the model sizes of the capacitors and resistors involved in the two-capacitor-resistor circuits are exactly the same.

[0025] The present invention provides a key generation system for a physical unclonable function based on AC detection, which will be described separately below.

[0026] Figure 1 FIG. is a schematic structural diagram of an embodiment of the key generation system for a physical unclonable function based on AC detection provided by the present invention. The system includes: A PUF (Physical Unclonable Function) module 110, which is used to convert an externally input AC voltage signal and output a digital signal; A control logic module 120, electrically connected to the PUF module 110, is configured to generate a key according to a digital signal; Among them, the PUF module 110 includes two symmetrically arranged capacitive-resistive circuits 111 and a sense amplifier 112; an AC voltage signal obtains a first voltage and a second voltage through the two symmetrically arranged capacitive-resistive circuits 111, and the sense amplifier 112 subtracts the first voltage and the second voltage and then outputs a digital signal.

[0027] It can be understood that the present invention provides a key generation system based on an AC-detection physical unclonable function. Compared with the existing key generation system based on DC sampling of the charge conservation principle in the physical unclonable function, the problem of low sensitivity exists when extracting keys. The key generation system proposed by the present invention mainly consists of a PUF module 110 and a control logic module 120. Among them, the symmetrically arranged capacitive-resistive circuit 111 in the PUF module 110, compared with the traditional capacitive-switching circuit, is mainly composed of two resistors and capacitors in series. The capacitive-resistive circuit mainly uses the voltage division characteristics of capacitive reactance and impedance under an AC signal to extract a voltage difference signal. Because the voltage division phases of the capacitor and the resistor are inconsistent, the voltage in the capacitor lags behind the current by 90 degrees in phase, while the voltage in the resistor is in phase with the current. Therefore, there is a 90-degree phase difference in the voltage division obtained by the resistor and the capacitor in the capacitive-resistive circuit 111. Compared with a pure capacitive circuit, it brings a preliminary amplification effect to the voltage difference caused by the random capacitance error generated during the manufacturing process of the circuit. The capacitive-resistive circuit 111 has no strict timing restrictions compared with a pure capacitive circuit, and it is not based on the charge conservation principle, so it will not be affected by the charge stray and feedthrough errors in the circuit, thus improving the sensitivity of the circuit. Secondly, the control logic module 120 controls the PUF module accordingly to generate an accurate random key.

[0028] It needs to be further explained that the change in the capacitance value of the capacitor in the capacitive-resistive circuit 111 will cause a change in the phase of the self-voltage division of the capacitor. For a switched-capacitor circuit, the mis-touch caused by the capacitance value does not affect the voltage phase output by the capacitor. Therefore, no matter what kind of error the capacitor has, |ΔV| is always equal to |V1| - |V2|. For the capacitive-resistive circuit 111, when the capacitance value of the capacitor changes, it will cause a change in the phase of the capacitor voltage division. The |ΔV| after the change in the capacitor voltage division phase will definitely be greater than |V1| - |V2|, thus achieving a greater proportion of amplification effect.

[0029] Figure 2 This is a key generation framework diagram of an embodiment of the key generation system based on an AC-detection physical unclonable function provided by the present invention. The system includes: The number of PUF modules 110 is n, and n is an integer greater than 2.

[0030] It can be understood that Figure 2 For a complete key generation framework diagram, n PUF modules 110 are designed in the chip, and the digital signals output by each PUF module 110 are input into the control logic module 120. The control logic module 120 is used to generate corresponding keys according to the n digital signals, where n is an integer greater than 2. The following listed embodiments can be used to supplement the corresponding content in this embodiment.

[0031] It can be further understood that a circuit model built by a key quantization method of a physical unclonable function based on AC detection. The input AC excitation is an AC signal with an amplitude swinging within 0~1.8V and a frequency of 10M.

[0032] The capacitance values of the capacitors in the switched-capacitor circuit and the capacitor resistor circuit 110 are set to 100fF, and the error capacitance value is set as variable A. It is considered that the capacitance fluctuation caused by process dimension error is within ±5%.

[0033] In the actual working principle, since the size data of each internal component in the chip manufacturing process is not completely ideal, there is a certain degree of process error, and this error is random. The circuit in this article uses a resistor-capacitor series RC circuit. When there is a process error in the capacitor, the voltage divided by the capacitor will change, resulting in the appearance of ΔV. The error capacitance variable can be controlled within 5% for transient simulation.

[0034] Figure 3 A series circuit diagram of a capacitor and a resistor for an embodiment of a key generation system of a physical unclonable function based on AC detection provided by the present invention Figure 4 A phase difference diagram of the first divided voltage and the second divided voltage for an embodiment of a key generation system of a physical unclonable function based on AC detection provided by the present invention Figure 5 For an embodiment of a key generation system of a physical unclonable function based on AC detection provided by the present invention, ΔV in the series circuit of a capacitor and a resistor and Function diagram and Figure 6 A simulation diagram of a series circuit model of a capacitor and a resistor for an embodiment of a key generation system of a physical unclonable function based on AC detection provided by the present invention.

[0035] In some embodiments of the present invention, the two symmetrically arranged capacitor resistor circuits include: A first capacitor, a second capacitor, a first resistor, a second resistor, a first switch and a second switch; One end of the first capacitor is grounded, and the other end of the first capacitor is electrically connected to one end of the first resistor, the sense amplifier, and the control logic module. The other end of the first resistor is electrically connected to the first switch; One end of the second capacitor is grounded, and the other end of the second capacitor is electrically connected to one end of the second resistor, the sense amplifier, and the control logic module. The other end of the second resistor is electrically connected to the second switch.

[0036] It can be further understood that Figure 4 For the convenience of calculation, let the capacitance value of the capacitor close to the excitation in the circuit be set as C, and the capacitance value of the capacitor close to the zero potential point be C' and σ C' (0.95 < σ < 1.05, thereby simulating the random error of the capacitance value).

[0037] It can be further understood that Figure 5 At this time, |ΔV| is a function of fRC and σ. The figure shows the relationship between |ΔV| and the variable fRC when the error is ±2.5% and ±5%. It can be seen that the function reaches an extreme value when fRC is approximately 1. According to the function image data, when the error is ±2.5%, |ΔV| is approximately 0.012 Vin; when the error is ±5%, |ΔV| is approximately 0.024 Vin. At this time, compared with the original pure capacitor circuit, the ΔV voltage difference brought by the same capacitance value error has increased by approximately 100%, reflecting an excellent amplification function.

[0038] Considering that the phase of the voltage changes after the capacitance changes, at this time, V1, V2, and ΔV are:

[0039] In the formula: V1 is the output first voltage, V2 is the output second voltage, f is the frequency of the excitation signal VDD, 10M is used in the subsequent simulation, σ is the error coefficient, and the error coefficients ±2.5% and ±5% mentioned above correspond to the two cases of = 0.975, 1.025 and 0.95, 1.05. R is the resistance value, C is the capacitance value, and Vin is the power supply VDD.

[0040] Finally, in the switched-capacitor RUF circuit, due to process errors during actual manufacturing, the size of the capacitor fluctuates slightly, affecting the output of the voltage value. When using the sampling capacitor for charging and discharging, a relatively large process error fluctuation is required to generate a stable detectable voltage difference, and there are relatively strict restrictions on the timing. However, using the capacitance-resistance AC voltage division scheme in this article, a smaller process size error of the capacitor is required to generate a stable detectable voltage difference, greatly improving the stability of the physical unclonable function.

[0041] It can be further understood that Figure 6 In a series-connected capacitor-resistor circuit structure, the simulation waveforms of capacitor C2 with errors of ±2.5% and ±5% respectively. (Among them, the red line is the voltage value of V1 - V2 with an error of 5%, the yellow line is the voltage value of V1 - V2 with an error of 2.5%, the green line is the voltage value of V1 - V2 with an error of -2.5%, and the blue line is the voltage value of V1 - V2 with an error of -5%). According to the simulation results, in a pure capacitor circuit structure, when VSIN is an AC voltage of 1.8V, when the error of capacitor C2 is ±2.5%, the peak value of ΔV obtained is about 11mV; when the error of capacitor C2 is ±5%, the peak value of ΔV obtained is about 22mV.

[0042] It can be seen that under the same dimensional error, the peak value of ΔV provided by the capacitor-resistor circuit 111 using the series voltage division principle is increased by about 300% compared with the switched capacitor, which can fully reflect that the series-connected capacitor-resistor circuit model can effectively improve the sensitivity and stability of the PUF.

[0043] Figure 7 This is the LSSA output digital signal diagram of an embodiment of the key generation system of the physical unclonable function based on AC detection provided by the present invention. Among them, the red line is the voltage value of the output first voltage V1, and the green line is the voltage value of the output second voltage V2.

[0044] In some embodiments of the present invention, the sense amplifier includes: a first MOS (Metal-Oxide-Semiconductor Field-Effect Transistor) transistor, a second MOS transistor, a third MOS transistor, a fourth MOS transistor, a fifth MOS transistor, and a sixth MOS transistor; The source of the first MOS transistor is electrically connected to the external voltage source VDD. The drain of the first MOS transistor is electrically connected to the sources of the second MOS transistor and the third MOS transistor respectively. The drain of the second MOS transistor is electrically connected to the source of the fourth MOS transistor. The gate of the second MOS transistor is electrically connected to the gate of the fourth MOS transistor. The drain of the third MOS transistor is electrically connected to the source of the fifth MOS transistor. The gate of the third MOS transistor is electrically connected to the gate of the fifth MOS transistor. The source of the sixth MOS transistor is electrically connected to the drains of the fourth MOS transistor and the gate of the fifth MOS transistor respectively. The drain of the sixth MOS transistor is grounded; The common terminal of the first capacitor and the first resistor is electrically connected to the drain of the second MOS transistor, the source of the fourth MOS transistor, the gate of the third MOS transistor, the gate of the fourth MOS transistor, and the control logic module; The common terminal of the second capacitor and the second resistor is electrically connected to the gate of the second MOS transistor, the gate of the fourth MOS transistor, the drain of the third MOS transistor, the source of the fifth MOS transistor, and the control logic module.

[0045] It can be further understood that the source of the first MOS transistor is electrically connected to the external voltage source VDD for the first MOS transistor to obtain the externally input voltage.

[0046] In some embodiments of the present invention, the PUF module 110 further includes: an amplification module and a rectification module; The first voltage and the second voltage are amplified by the amplification module to obtain the amplified first voltage and second voltage. The amplified first voltage and second voltage are rectified by the rectification module to output the first DC voltage and the second DC voltage. The first DC voltage and the second DC voltage are subtracted by the sense amplifier 112 to output a digital signal.

[0047] It can be further understood that during the actual operation process, first, a fixed-frequency AC signal is used to excite the RC series circuit, and a DC power supply is used to supply power to the subsequent amplification module and the sense amplifier. After obtaining the two voltage values of V1 and V2, first, V1 and V2 are connected to the amplification module to obtain the amplified AC voltage signal. The amplified voltage signal is connected to the rectification circuit to obtain the DC signals V1_1 and V2_1. Finally, the DC signals V1_1 and V2_1 are input into the sense amplifier to obtain the digital output signal.

[0048] In some embodiments of the present invention, the amplification module includes: A first amplifier and a second amplifier; the first voltage is amplified by the first amplifier to obtain the amplified first voltage, and the second voltage is amplified by the second amplifier to obtain the amplified second voltage.

[0049] It can be further understood that during the actual operation process, first, a fixed-frequency AC signal is used to excite the RC series circuit, and a DC power supply is used to supply power to the subsequent amplification module and the sense amplifier. After obtaining the two voltage values of V1 and V2, first, V1 and V2 are connected to the amplification module to obtain the amplified AC voltage signal. The amplified voltage signal is connected to the rectification circuit to obtain the DC signals V1_1 and V2_1. Finally, the DC signals V1_1 and V2_1 are input into the sense amplifier to obtain the digital output signal.

[0050] In some embodiments of the present invention, the rectification module includes: a first rectifier and a second rectifier; The amplified first voltage is rectified by the first rectifier to obtain the first DC voltage, and the amplified second voltage is rectified by the second rectifier to obtain the second DC voltage.

[0051] It can be further understood that during the actual operation process, first, a fixed-frequency AC signal is used to excite the RC series circuit, and a DC power supply is used to supply power to the subsequent amplification module and the sensitive amplifier. After obtaining the two voltage values V1 and V2, first, V1 and V2 are connected to the amplification module to obtain an amplified AC voltage signal, and the amplified voltage signal is connected to the rectification circuit to obtain DC signals V1_1 and V2_1. Finally, the DC signals V1_1 and V2_1 are input into the sensitive amplifier to obtain a digital output signal.

[0052] Figure 8 This is a Monte Carlo data histogram of an embodiment of the key generation system based on AC detection physical unclonable function provided by the present invention, including: The register is electrically connected to the PUF module 110, and is used to receive digital signals and store the digital signals to obtain stored data. The control logic module 120 is communicatively connected to the register and is used to generate a key according to the stored data.

[0053] It can be further understood that finally, a Monte Carlo simulation with a sample number of 10,000 is performed, and the obtained data is input into Matlab to generate a histogram, and the generated image is as Figure 8 shown. It can be seen that the final key result conforms to the normal distribution and meets the requirements of key randomness.

[0054] In some embodiments of the present invention, The control logic module 120 is also electrically connected to the first switch and the second switch, and is used to generate a first control signal and respectively control the opening or closing of the first switch and the second switch based on the first control signal.

[0055] Figure 9 This is a basic structure diagram of an existing physical unclonable function unit of an embodiment of the key generation system based on AC detection physical unclonable function provided by the present invention, including: The control logic module 120 is also electrically connected to the gate of the first MOS transistor and the gate of the sixth MOS transistor, and is used to generate a second control signal and respectively control the on / off of the first MOS transistor and the sixth MOS transistor based on the second control signal.

[0056] It can be understood that the basic structure of the switched-capacitor PUF is as Figure 9 shown, and it is composed of four modules: a switched-capacitor circuit, a sensitive amplifier 114 (latch-style sense amplifier, LSSA), a register (register, REG), and a control logic (control logic, CTL). When the enable signal α EN is valid, the selection signal α SELWhen it is logic low, capacitor C 1P , C 2P , C 1N and C 2N 's upper and lower plates are both connected to the ground wire GND. The SC circuit operates in a discharge state and no charge is stored. When α SEL becomes logic high, the upper plates of the sampling capacitors C 1P and C 1N are both connected to the power supply potential VDD. The capacitor circuit will operate in a charge redistribution state. At this time, the ratio of the sampling capacitors C 1N , C 2N , C 1P and C 2P in the manufacturing process will be converted into a voltage deviation. LSSA amplifies this voltage difference and converts it into a digital output. REG stores the digital outputs of all PUF units, and the control logic is used to generate control signals α CLK _ REG (clock signal), α EN and α SEL to drive each module to work orderly.

[0057] The circuit of the switch-capacitor based Physically Unclonable Function (PUF) mainly relies on the random capacitance errors generated during the manufacturing process to generate unique identification functions. After the capacitance ratio mismatch is converted into a voltage difference ΔVPN, it is amplified by LSSA and then converted into a digital output. Considering that LSSA will generate an offset voltage VOFFSET due to the mismatch of MOS transistors during the manufacturing process, the effective deviation voltage that finally determines the LSSA output is ΔV = ΔVPN + VOFFSET. The polarity of ΔV determines whether LSSA outputs digital 0 or digital 1. Moreover, the absolute value of the deviation voltage ΔV in the PUF unit determines the output reliability of the PUF unit. The larger |ΔV| is, the lower the probability that the deviation voltage ΔV changes its polarity due to the influence of the power supply voltage and temperature, and the higher the reliability. ΔV is mainly determined by the process deviations that are difficult to avoid during the chip manufacturing process, so it cannot be determined during the design.

[0058] The switch-capacitor based Physically Unclonable Function has the following disadvantages: First, the sensitivity is insufficient. The tiny errors of the capacitors are usually only at the micron level, and the change in the capacitance value of the capacitor itself is extremely small, resulting in a low voltage difference and cannot be detected by the subsequent circuit; Second, as the process scale decreases, the leakage current gradually increases, and the key quantization method based on the principle of charge conservation gradually fails (the reliability decreases). And the process size of integrated circuits is generally at the micron level, and there will be errors in quantifying the process errors of capacitors through the principle of charge conservation.

[0059] Figure 10The pure capacitance circuit diagram of an embodiment of the key generation system based on AC detection physical unclonable function provided by the present invention and Figure 11 In the pure capacitance circuit of an embodiment of the key generation system based on AC detection physical unclonable function provided by the present invention, ΔV and Function graph, including: It can be understood that Figure 10 The function images of and |ΔV| under the conditions of error values of ±2.5% and ±5% are shown in According to the result of the monotonicity of the function image, when the error range is within ±5%, Extreme value is obtained when it is about 1, and |ΔV| is about 0.006 Vin when the error is ±2.5%; |ΔV| is about 0.012 Vin when the error is ±5%.

[0060] It can be understood that Figure 11 The principle of is the DC sampling of the charge conservation principle to extract the voltage difference. The calculation formula of its ΔV is as follows:

[0061] In the formula: C Is the capacitance value of the capacitor close to the excitation in the circuit, And Are the capacitance value close to the zero potential point and |ΔV| is And σ Function of.

[0062] Figure 12 In the pure capacitance circuit of an embodiment of the key generation system based on AC detection physical unclonable function provided by the present invention, |ΔV| and σ Function graph, including: It can be understood that Figure 12 Shows the function image of |ΔV| and σ In the figure, the abscissa is σ And the ordinate is |ΔV|. It can be seen that as the capacitance deviation increases, the voltage difference will also increase.

[0063] Figure 13 The simulation diagram of the switched capacitor circuit model of an embodiment of the key generation system based on AC detection physical unclonable function provided by the present invention, including: It can be understood that the simulation waveforms of the capacitor with errors of ±2.5% and ±5% respectively (where the red line is the voltage value of V1 - V2 with an error of 5%, the yellow line is the voltage value of V1 - V2 with an error of 2.5%, the green line is the voltage value of V1 - V2 with an error of -2.5%, and the blue line is the voltage value of V1 - V2 with an error of -5%). According to the simulation results, in the switched-capacitor circuit structure, when VDD is a 1.8V DC voltage, when the capacitor error is ±2.5%, the obtained ΔV is approximately 3.6mV; when the error of capacitor C10 is ±5%, the obtained ΔV is approximately 7.2mV. It can be seen that obtaining a voltage difference using the principle of capacitor charge and discharge requires a relatively high capacitance value, while the capacitance value in the simulation environment in this paper is the size of a conventional chip capacitor, fluctuating around 100fF, and the small capacitance value results in the value of ΔV being lower than the theoretically calculated value.

[0064] The above has introduced in detail the key generation system of the physical unclonable function based on AC detection provided by the present invention. Specific examples are used in this paper to elaborate on the principle and implementation manner of the present invention. The description of the above embodiments is only used to help understand the method and its core idea of the present invention; at the same time, for those skilled in the art, according to the idea of the present invention, there will be changes in the specific implementation manner and application scope. In summary, the content of this specification should not be construed as a limitation to the present invention.

Claims

1. A key generation system for a physical unclonable function based on AC detection, characterized in that Comprising: A PUF module for converting an externally input AC voltage signal and outputting a digital signal; A control logic module electrically connected to the PUF module for generating a key according to the digital signal; Wherein, the PUF module includes two symmetrically arranged capacitor-resistor circuits and a sense amplifier; the AC voltage signal obtains a first voltage and a second voltage through the two symmetrically arranged capacitor-resistor circuits, and the sense amplifier subtracts the first voltage and the second voltage and then outputs a digital signal.

2. The key generation system of the physical unclonable function based on AC detection according to claim 1, characterized in that The two symmetrically arranged capacitor-resistor circuits include: A first capacitor, a second capacitor, a first resistor, a second resistor, a first switch and a second switch; One end of the first capacitor is grounded, the other end of the first capacitor is electrically connected to one end of the first resistor, the sense amplifier and the control logic module, and the other end of the first resistor is electrically connected to the first switch; One end of the second capacitor is grounded, the other end of the second capacitor is electrically connected to one end of the second resistor, the sense amplifier and the control logic module, and the other end of the second resistor is electrically connected to the second switch.

3. The key generation system of the physical unclonable function based on AC detection according to claim 2, characterized in that, The sense amplifier includes: a first MOS transistor, a second MOS transistor, a third MOS transistor, a fourth MOS transistor, a fifth MOS transistor and a sixth MOS transistor; The source of the first MOS transistor is electrically connected to an external voltage source, the drain of the first MOS transistor is electrically connected to the sources of the second MOS transistor and the third MOS transistor respectively, the drain of the second MOS transistor is electrically connected to the source of the fourth MOS transistor, the gate of the second MOS transistor is electrically connected to the gate of the fourth MOS transistor, the drain of the third MOS transistor is electrically connected to the source of the fifth MOS transistor, the gate of the third MOS transistor is electrically connected to the gate of the fifth MOS transistor, the source of the sixth MOS transistor is electrically connected to the drains of the fourth MOS transistor and the gate of the fifth MOS transistor respectively, and the drain of the sixth MOS transistor is grounded; The common end of the first capacitor and the first resistor is electrically connected to the drain of the second MOS transistor, the source of the fourth MOS transistor, the gate of the third MOS transistor, the gate of the fourth MOS transistor and the control logic module; The common end of the second capacitor and the second resistor is electrically connected to the gate of the second MOS transistor, the gate of the fourth MOS transistor, the drain of the third MOS transistor, the source of the fifth MOS transistor and the control logic module.

4. The key generation system of the physical unclonable function based on AC detection according to claim 1, characterized in that, The PUF module further includes: an amplification module and a rectification module; The first voltage and the second voltage obtain amplified first voltage and second voltage through the amplification module, the amplified first voltage and second voltage are rectified through the rectification module to output a first DC voltage and a second DC voltage, and the first DC voltage and the second DC voltage are subtracted by the sense amplifier to output a digital signal.

5. The key generation system of the physical unclonable function based on AC detection according to claim 4, characterized in that, The amplification module includes: a first amplifier and a second amplifier; The first voltage obtains an amplified first voltage through the first amplifier, and the second voltage obtains an amplified second voltage through the second amplifier.

6. The key generation system of the physical unclonable function based on AC detection according to claim 4, wherein The rectification module includes: a first rectifier and a second rectifier; The amplified first voltage is rectified by the first rectifier to obtain a first DC voltage, and the amplified second voltage is rectified by the second rectifier to obtain a second DC voltage.

7. The key generation system of the physical unclonable function based on AC detection according to claim 1, characterized in that, The system further includes a register; The register is electrically connected to the PUF module, and is used to receive digital signals and store the digital signals to obtain stored data; The control logic module is also communicatively connected to the register, and is used to generate a key according to the stored data.

8. The key generation system of the physical unclonable function based on AC detection according to claim 7, wherein: The control logic module is also electrically connected to the first switch and the second switch, and is used to generate a first control signal and respectively control the opening or closing of the first switch and the second switch based on the first control signal.

9. The key generation system of the physical unclonable function based on AC detection according to claim 8, wherein: The control logic module is also electrically connected to the gates of the first MOS transistor and the sixth MOS transistor, and is used to generate a second control signal and respectively control the on / off states of the first MOS transistor and the sixth MOS transistor based on the second control signal.

10. The key generation system of the physical unclonable function based on AC detection according to any one of claims 1-9, characterized in that, The number of the PUF modules is n, where n is an integer greater than 2.

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