A key generation system based on physical unclonable function of AC detection

Abstract

The present invention provides a key generation system for a physical unclonable function (PUF) based on AC detection, belonging to the technical field of physical unclonable functions. The system includes a PUF module for converting an externally input AC voltage signal to output a digital signal, and a control logic module electrically connected to the PUF module for generating a key based on the digital signal. The PUF module includes two symmetrically arranged capacitor-resistor circuits and a sensitive amplifier. The AC voltage signal is passed through the two symmetrically arranged capacitor-resistor circuits to obtain a first voltage and a second voltage. The sensitive amplifier then takes the difference between the first and second voltages and outputs a digital signal. The two symmetrically arranged capacitor-resistor circuits utilize the voltage-dividing characteristics of capacitive reactance and impedance under AC signals to further amplify the voltage difference signal, thereby improving the sensitivity of the key generation system.

Description

Technical Field

[0001] The present invention relates to the technical field of physical unclonable functions, and in particular to a key generation system of a physical unclonable function based on alternating current detection. Background Art

[0002] PUF, or Physically Unclonable Function, leverages the deep submicron variations that naturally occur during semiconductor physics production to impart slightly random electrical characteristics to each transistor. These unique characteristics form the basis of a chip's unique identity.

[0003] The SC PUF circuit consists of four modules: a switched capacitor circuit, a latch-style senseamplifier (LSSA), a register (REG), and a control logic (CTL). When the enable signal of the control logic module is valid and the selection signal of the control logic module is logic low, the capacitor C 1P , C 2P , C 1N and C 2N The upper and lower plates of the switch capacitor are connected to the ground, and the switch capacitor circuit works in the discharge state and does not store charge. When the selection signal of the control logic module is logic high, the sampling capacitor C 1P and C 2P The deviation in the ratio of capacitance to capacitance during the manufacturing process is converted into a voltage deviation. A latch-type sense amplifier amplifies this voltage difference and converts it into a digital output. Registers store the digital outputs of all PUF units, while the control logic module generates control signals αCLK_REG (clock signal), αEN, and αSEL, and drives the modules to operate in an orderly manner based on these control signals. Physically unclonable function circuits based on switched capacitor circuits rely primarily on random capacitance errors generated during the manufacturing process to generate unique identification functions. Capacitor ratio mismatch is converted into a voltage difference, which is then amplified by a latch-type sense amplifier and converted into a digital output. Considering that latch-type sense amplifiers may generate an offset voltage due to MOS transistor adaptation during the manufacturing process, the effective offset voltage output by the latch-type sense amplifier is the voltage difference plus the offset voltage. The polarity of the effective offset voltage determines whether the latch-type sense amplifier outputs a digital 0 or a digital 1. Furthermore, the absolute value of the offset voltage in a PUF unit determines the output reliability of the PUF unit. A larger absolute value of the offset voltage indicates a lower probability of the offset voltage changing polarity due to power supply voltage and temperature, and thus higher reliability. The deviation voltage is mainly determined by the process deviation that is difficult to avoid during the chip manufacturing process, so it cannot be determined during the design.

[0004] However, SC PUF circuits suffer from a low sensitivity. This is primarily due to the fact that minute errors in capacitance are typically only at the micron level, causing minimal changes in the capacitance itself. This results in a low voltage difference, making it undetectable by subsequent circuitry. Furthermore, as process scale decreases, the leakage current in SC PUF circuits increases, making key quantization methods based on the principle of charge conservation increasingly ineffective. Since integrated circuit process sizes are generally at the micron level, the manufacturing process for quantizing capacitance based on the principle of charge conservation will incur errors. Therefore, existing technologies suffer from a low sensitivity for physically unclonable function key generation systems. Summary of the Invention

[0005] In view of this, it is necessary to provide a key generation system based on a physical unclonable function of AC detection to solve the technical problem of low sensitivity of the physical unclonable function key generation system of the switched capacitor in the prior art.

[0006] In order to solve the above technical problems, the present invention provides a key generation system based on a physical unclonable function with AC detection, comprising:

[0007] The PUF module is used to convert the external input AC voltage signal and output a digital signal;

[0008] A control logic module, electrically connected to the PUF module, for generating a key based on the digital signal;

[0009] Among them, the PUF module includes two symmetrically arranged capacitor-resistor circuits and a sensitive amplifier; the AC voltage signal is converted into a first voltage and a second voltage through the two symmetrically arranged capacitor-resistor circuits, and the first voltage and the second voltage are subtracted by the sensitive amplifier to output a digital signal.

[0010] In a possible implementation, the symmetrically arranged two-way capacitor-resistor circuit includes:

[0011] A first capacitor, a second capacitor, a first resistor, a second resistor, a first switch, and a second switch;

[0012] One end of the first capacitor is grounded, the other end of the first capacitor is electrically connected to one end of the first resistor, the sense amplifier and the control logic module, and the other end of the first resistor is electrically connected to the first switch;

[0013] One end of the second capacitor is grounded, the other end of the second capacitor is electrically connected to one end of the second resistor, the sense amplifier and the control logic module, and the other end of the second resistor is electrically connected to the second switch.

[0014] In a possible implementation, the sense amplifier includes: a first MOS transistor, a second MOS transistor, a third MOS transistor, a fourth MOS transistor, a fifth MOS transistor, and a sixth MOS transistor;

[0015] The source of the first MOS transistor is electrically connected to the external voltage source, the drain of the first MOS transistor is electrically connected to the source of the second MOS transistor and the source of the third MOS transistor respectively, the drain of the second MOS transistor is electrically connected to the source of the fourth MOS transistor, the gate of the second MOS transistor is electrically connected to the gate of the fourth MOS transistor, the drain of the third MOS transistor is electrically connected to the source of the fifth MOS transistor, the gate of the third MOS transistor is electrically connected to the gate of the fifth MOS transistor, the source of the sixth MOS transistor is electrically connected to the drain of the fourth MOS transistor and the gate of the fifth MOS transistor respectively, and the drain of the sixth MOS transistor is grounded;

[0016] The common end of the first capacitor and the first resistor is electrically connected to the drain of the second MOS transistor, the source of the fourth MOS transistor, the gate of the third MOS transistor, the gate of the fourth MOS transistor, and the control logic module;

[0017] The common end of the second capacitor and the second resistor is electrically connected to the gate of the second MOS transistor, the gate of the fourth MOS transistor, the drain of the third MOS transistor, the source of the fifth MOS transistor and the control logic module.

[0018] In a possible implementation, the PUF module further includes: an amplification module and a rectification module;

[0019] The first voltage and the second voltage are amplified by the amplification module to obtain the amplified first voltage and the second voltage, the amplified first voltage and the second voltage are rectified by the rectification module to output the first DC voltage and the second DC voltage, and the first DC voltage and the second DC voltage are differentiated by the sensitive amplifier to output a digital signal.

[0020] In a possible implementation, the amplification module includes: a first amplifier and a second amplifier;

[0021] The first voltage is amplified by the first amplifier to obtain the first voltage, and the second voltage is amplified by the second amplifier to obtain the second voltage.

[0022] In a possible implementation, the rectifier module includes: a first rectifier and a second rectifier;

[0023] The amplified first voltage is rectified by a first rectifier to obtain a first DC voltage, and the amplified second voltage is rectified by a second rectifier to obtain a second DC voltage.

[0024] In a possible implementation, the system further includes: a register;

[0025] The register is electrically connected to the PUF module, and is used to receive the digital signal and store the digital signal to obtain stored data;

[0026] The control logic module is also connected to the register for communication and is used to generate a key according to the stored data.

[0027] In one possible implementation,

[0028] The control logic module is also electrically connected to the first switch and the second switch, and is used to generate a first control signal and control the opening or closing of the first switch and the second switch respectively based on the first control signal.

[0029] In one possible implementation,

[0030] The control logic module is also electrically connected to the gate of the first MOS transistor and the gate of the sixth MOS transistor, and is used to generate a second control signal and control the on and off of the first MOS transistor and the sixth MOS transistor respectively based on the second control signal.

[0031] In a possible implementation, the number of the PUF modules is n, where n is an integer greater than 2.

[0032] The present invention has the beneficial effect of providing a key generation system based on a physical unclonable function (PUF) with AC detection. Compared to existing PUF key generation systems that suffer from low sensitivity when extracting keys using DC sampling based on the principle of charge conservation, the present invention proposes a key generation system primarily composed of a PUF module and a control logic module. The symmetrically arranged capacitor-resistor circuit in the PUF module, compared to a traditional capacitive switch circuit, primarily consists of two resistors and a capacitor in series. The capacitor-resistor circuit primarily utilizes the voltage-dividing characteristics of capacitive reactance and impedance under AC signals to extract a voltage difference signal. Because the voltage division phases of the capacitor and resistor are out of phase, the voltage in the capacitor lags 90 degrees behind the current, while the voltage in the resistor is in phase with the current. Therefore, the resulting voltage division in the capacitor-resistor circuit has a 90-degree phase difference, providing a preliminary amplification effect on voltage differences caused by random capacitance errors during the circuit manufacturing process, compared to pure capacitive circuits. Compared to pure capacitive circuits, the capacitor-resistor circuit does not have strict timing constraints and is not based on the principle of charge conservation. Therefore, it is not affected by charge stray and feedthrough errors in the circuit, thereby improving the circuit's sensitivity. Secondly, the PUF module is controlled accordingly through the control logic module to generate an accurate random key. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative work.

[0034] Figure 1 A schematic structural diagram of an embodiment of a key generation system based on a physical unclonable function using AC detection provided by the present invention;

[0035] Figure 2 A key generation framework diagram of an embodiment of a key generation system based on a physical unclonable function of AC detection provided by the present invention;

[0036] Figure 3 A capacitor-resistor series circuit diagram of an embodiment of a key generation system based on an AC detection physical unclonable function provided by the present invention;

[0037] Figure 4 A phase difference diagram of a first divided voltage and a second divided voltage of an embodiment of a key generation system based on a physical unclonable function with AC detection provided by the present invention;

[0038] Figure 5 The ΔV and ΔV in the capacitor-resistor series circuit of an embodiment of the key generation system based on the physical unclonable function of AC detection provided by the present invention are Function graphs;

[0039] Figure 6 A simulation diagram of a capacitor-resistor series circuit model of an embodiment of a key generation system based on a physical unclonable function using AC detection provided by the present invention;

[0040] Figure 7 This is a diagram of the LSSA output digital signal of an embodiment of the key generation system based on the AC detection physical unclonable function provided by the present invention;

[0041] Figure 8 A Monte Carlo data histogram of an embodiment of a key generation system based on a physical unclonable function of AC detection provided by the present invention;

[0042] Figure 9 A basic structural diagram of a conventional physical unclonable function unit of an embodiment of a key generation system of a physical unclonable function based on AC detection provided by the present invention;

[0043] Figure 10A pure capacitance circuit diagram of an embodiment of a key generation system based on a physical unclonable function of AC detection provided by the present invention;

[0044] Figure 11 The ΔV and the ΔV in the pure capacitance circuit of an embodiment of the key generation system based on the physical unclonable function of AC detection provided by the present invention are Function graphs;

[0045] Figure 12 A graph showing the |ΔV| and σ functions in a pure capacitive circuit of an embodiment of the key generation system based on the physical unclonable function of AC detection provided by the present invention;

[0046] Figure 13 This is a simulation diagram of a switched capacitor circuit model of an embodiment of a key generation system based on a physical unclonable function with AC detection provided by the present invention. DETAILED DESCRIPTION

[0047] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without making any creative efforts shall fall within the scope of protection of the present invention.

[0048] In the description of the embodiments of the present application, unless otherwise specified, “plurality” means two or more.

[0049] The terms "including" and "having" and any variations thereof in the embodiments of the present invention are intended to cover non-exclusive inclusions. For example, a process, method, apparatus, product or device comprising a series of steps or modules is not necessarily limited to those steps or modules explicitly listed, but may include other steps or modules not explicitly listed or inherent to these processes, methods, products or devices.

[0050] The naming or numbering of the steps in the embodiments of the present invention does not mean that the steps in the method flow must be executed in the time / logical sequence indicated by the naming or numbering. The execution order of the named or numbered process steps can be changed according to the technical purpose to be achieved, as long as the same or similar technical effects can be achieved.

[0051] References herein to "embodiments" mean that a particular feature, structure, or characteristic described in connection with the embodiments may be included in at least one embodiment of the present invention. The appearance of this phrase in various places in the specification does not necessarily refer to the same embodiment, nor does it constitute a separate or alternative embodiment that is mutually exclusive of other embodiments. It is understood, both explicitly and implicitly, by those skilled in the art that the embodiments described herein may be combined with other embodiments.

[0052] Provide additional explanations for the following terms:

[0053] The symmetrical setting is: the capacitors and resistors involved in the two capacitor-resistor circuits are exactly the same in size.

[0054] The present invention provides a key generation system based on a physical unclonable function of AC detection, which is described below.

[0055] Figure 1 This is a schematic structural diagram of an embodiment of a key generation system based on a physical unclonable function using AC detection provided by the present invention. The system includes:

[0056] PUF (Physical Unclonable Function) module 110, used to convert external input AC voltage signals and output digital signals;

[0057] a control logic module 120 , electrically connected to the PUF module 110 , configured to generate a key based on the digital signal;

[0058] Among them, the PUF module 110 includes two symmetrically arranged capacitor-resistor circuits 111 and a sensitive amplifier 112; the AC voltage signal obtains a first voltage and a second voltage through the two symmetrically arranged capacitor-resistor circuits 111, and the first voltage and the second voltage are subtracted through the sensitive amplifier 112 to output a digital signal.

[0059] It can be understood that the present invention provides a key generation system based on a physical unclonable function with AC detection. Compared with the existing physical unclonable function key generation system, which uses a DC sampling method based on the principle of charge conservation to extract keys, the present invention proposes a key generation system mainly composed of a PUF module 110 and a control logic module 120. The symmetrically arranged capacitor-resistor circuit 111 in the PUF module 110 is mainly composed of two resistors and a capacitor in series, compared to the traditional capacitor switch circuit. The capacitor-resistor circuit mainly uses the voltage divider characteristics of capacitive reactance and impedance under AC signals to extract the key. The voltage difference signal, because the voltage division phase of the capacitor and resistor is inconsistent, the voltage in the capacitor lags 90 degrees behind the phase of the current, while the voltage in the resistor is consistent with the phase of the current. Therefore, the voltage division of the resistor and capacitor in the capacitor-resistor circuit 111 has a 90-degree phase difference. Compared with a pure capacitor circuit, it has a preliminary amplification effect on the voltage difference caused by random capacitance errors generated during the circuit manufacturing process. Compared with a pure capacitor circuit, the capacitor-resistor circuit 111 does not have strict timing constraints and is not based on the principle of charge conservation. Therefore, it is not affected by the charge stray and feedthrough errors in the circuit, thereby improving the circuit sensitivity. Secondly, the PUF module is controlled accordingly by the control logic module 120 to generate an accurate random key.

[0060] It should be further explained that a change in the capacitance value of the capacitor in the capacitor-resistor circuit 111 will cause the phase of the capacitor's own voltage divider to change. However, for a switched capacitor circuit, a false touch caused by the capacitance value does not affect the voltage phase of the capacitor output. Therefore, regardless of the capacitance error, |ΔV| is always equal to |V1|-|V2|. For the capacitor-resistor circuit 111, when the capacitance value changes, it will cause the phase of the capacitor voltage divider to change. After the capacitor voltage divider phase changes, |ΔV| will definitely be greater than |V1|-|V2|, thus achieving a larger amplification effect.

[0061] Figure 2 This is a key generation framework diagram of an embodiment of a key generation system based on a physical unclonable function with AC detection provided by the present invention. The system includes:

[0062] The number of PUF modules 110 is n, where n is an integer greater than 2.

[0063] It is understandable that Figure 2This is a diagram of a complete key generation framework. A chip is designed with n PUF modules 110. The digital signal output by each PUF module 110 is input into a control logic module 120. The control logic module 120 is configured to generate a corresponding key based on the n digital signals, where n is an integer greater than 2. The following embodiments can be used to supplement the corresponding contents of this embodiment.

[0064] It can be further understood that the circuit model of the key quantization method based on the physical unclonable function of AC detection is constructed with an AC excitation input of an AC signal with an amplitude ranging from 0 to 1.8V and a frequency of 10MHz.

[0065] The capacitance of the switched capacitor circuit and the capacitor-resistor circuit 110 is set to 100 fF, and the capacitance error is set to variable A. It is assumed that the capacitance fluctuation caused by the process dimension error is within ±5%.

[0066] In actual operation, the dimensions of the chip's internal components aren't ideal during manufacturing, leading to a certain degree of process error. This error is random. The circuit in this article uses a series resistor-capacitor RC circuit. When process error exists in the capacitor, the voltage divided by the capacitor will vary, resulting in ΔV. The error capacitance variation can be controlled to within 5% for transient simulation.

[0067] Figure 3 A capacitor and resistor series circuit diagram of an embodiment of a key generation system based on an AC detection physical unclonable function provided by the present invention, Figure 4 A phase difference diagram of the first divided voltage and the second divided voltage of an embodiment of a key generation system based on a physical unclonable function of AC detection provided by the present invention, Figure 5 The ΔV and ΔV in the capacitor-resistor series circuit of an embodiment of the key generation system based on the physical unclonable function of AC detection provided by the present invention are Function graph and Figure 6 This is a simulation diagram of a capacitor-resistor series circuit model of an embodiment of a key generation system based on a physical unclonable function with AC detection provided by the present invention.

[0068] In some embodiments of the present invention, the symmetrically arranged two-way capacitor-resistor circuit includes:

[0069] A first capacitor, a second capacitor, a first resistor, a second resistor, a first switch, and a second switch;

[0070] One end of the first capacitor is grounded, the other end of the first capacitor is electrically connected to one end of the first resistor, the sense amplifier and the control logic module, and the other end of the first resistor is electrically connected to the first switch;

[0071] One end of the second capacitor is grounded, the other end of the second capacitor is electrically connected to one end of the second resistor, the sense amplifier and the control logic module, and the other end of the second resistor is electrically connected to the second switch.

[0072] It can be further understood that Figure 4 For the convenience of calculation, let the capacitance value of the capacitor close to the excitation in the circuit be C, the capacitance value of the capacitor close to the zero potential point be C' and σ C' (0.95<σ<1.05, used to simulate the random error of capacitor value).

[0073] It can be further understood that Figure 5 In this case, |ΔV| is a function of fRC and σ. The figure shows the relationship between |ΔV| and the variable fRC when the error is ±2.5% and ±5%. It can be seen that when fRC is approximately 1, the function reaches its extreme value. According to the function graph data, when the error is ±2.5%, the maximum value of |ΔV| is approximately 0.012 Vin; when the error is ±5%, the maximum |ΔV| is about 0.024 Compared to the original pure capacitance circuit, the ΔV voltage difference caused by the same capacitance value error is increased by about 100%, demonstrating excellent amplification function.

[0074] Considering that the phase of the voltage changes due to the change in capacitance, V1, V2, and ΔV are:

[0075]

[0076] Where: V1 is the first output voltage, V2 is the second output voltage, f is the frequency of the excitation signal VDD, the subsequent simulation uses 10M, σ is the error coefficient, the error coefficients mentioned above are ±2.5% and ±5%, which correspond to =0.975, 1.025 and 0.95, 1.05, R is the resistance value, C is the capacitance value and Vin is the power supply VDD.

[0077] Finally, the switched-capacitor RUF circuit utilizes process tolerances during the actual manufacturing process, which can lead to slight fluctuations in capacitor dimensions and affect the output voltage. When charging and discharging the sampling capacitor, generating a stable, detectable voltage difference requires relatively large process tolerances and places relatively strict constraints on timing. However, using this article's capacitor-resistor AC voltage divider solution, generating a stable, detectable voltage difference requires even smaller process tolerances, significantly improving the stability of the physically unclonable function.

[0078] It can be further understood that Figure 6The following are simulated waveforms for capacitor C2 in a capacitor-resistor series circuit structure with errors of ±2.5% and ±5%, respectively (the red line represents the voltage value of V1-V2 with an error of 5%, the yellow line represents the voltage value of V1-V2 with an error of 2.5%, the green line represents the voltage value of V1-V2 with an error of -2.5%, and the blue line represents the voltage value of V1-V2 with an error of -5%). The simulation results show that in a purely capacitive circuit structure, when VSIN is an AC voltage of 1.8V, the peak ΔV value obtained when the capacitance error of C2 is ±2.5% is approximately 11mV; when the capacitance error of C2 is ±5%, the peak ΔV value obtained is approximately 22mV.

[0079] It can be seen that under the same dimensional error, the ΔV peak provided by the capacitor-resistor circuit 111 using the series voltage divider principle is increased by about 300% compared to the switched capacitor, which fully demonstrates that the capacitor-resistor series circuit model can effectively improve the sensitivity and stability of the PUF.

[0080] Figure 7 This is a diagram of the LSSA output digital signal of an embodiment of the key generation system based on AC detection and physical unclonable function provided by the present invention. The red line represents the voltage value of the output first voltage V1, and the green line represents the voltage value of the output second voltage V2.

[0081] In some embodiments of the present invention, the sense amplifier includes: a first MOS (Metal-Oxide-Semiconductor Field-Effect Transistor) transistor, a second MOS transistor, a third MOS transistor, a fourth MOS transistor, a fifth MOS transistor, and a sixth MOS transistor;

[0082] The source of the first MOS transistor is electrically connected to the external voltage source VDD, the drain of the first MOS transistor is electrically connected to the source of the second MOS transistor and the source of the third MOS transistor respectively, the drain of the second MOS transistor is electrically connected to the source of the fourth MOS transistor, the gate of the second MOS transistor is electrically connected to the gate of the fourth MOS transistor, the drain of the third MOS transistor is electrically connected to the source of the fifth MOS transistor, the gate of the third MOS transistor is electrically connected to the gate of the fifth MOS transistor, the source of the sixth MOS transistor is electrically connected to the drain of the fourth MOS transistor and the gate of the fifth MOS transistor respectively, and the drain of the sixth MOS transistor is grounded;

[0083] The common end of the first capacitor and the first resistor is electrically connected to the drain of the second MOS transistor, the source of the fourth MOS transistor, the gate of the third MOS transistor, the gate of the fourth MOS transistor, and the control logic module;

[0084] The common end of the second capacitor and the second resistor is electrically connected to the gate of the second MOS transistor, the gate of the fourth MOS transistor, the drain of the third MOS transistor, the source of the fifth MOS transistor and the control logic module.

[0085] It can be further understood that the source of the first MOS transistor is electrically connected to the external voltage source VDD, so that the first MOS transistor can obtain the external input voltage.

[0086] In some embodiments of the present invention, the PUF module 110 further includes: an amplification module and a rectification module;

[0087] The first voltage and the second voltage are amplified by the amplification module to obtain the amplified first voltage and the second voltage. The amplified first voltage and the second voltage are rectified by the rectification module to output the first DC voltage and the second DC voltage. The first DC voltage and the second DC voltage are subtracted by the sensitive amplifier 112 to output a digital signal.

[0088] It can be further understood that in actual operation, a fixed-frequency AC signal is first used to excite the RC series circuit, and a DC power supply is used to power the subsequent amplification module and sense amplifier. After obtaining the two voltage values V1 and V2, V1 and V2 are first connected to the amplification module to obtain the amplified AC voltage signal. The amplified voltage signal is then connected to the rectifier circuit to obtain DC signals V1_1 and V2_1. Finally, the DC signals V1_1 and V2_1 are input into the sense amplifier to obtain the digital output signal.

[0089] In some embodiments of the present invention, the amplification module includes:

[0090] A first amplifier and a second amplifier; the first voltage is amplified by the first amplifier to obtain a first voltage, and the second voltage is amplified by the second amplifier to obtain a second voltage.

[0091] It can be further understood that in actual operation, a fixed-frequency AC signal is first used to excite the RC series circuit, and a DC power supply is used to power the subsequent amplification module and sense amplifier. After obtaining the two voltage values V1 and V2, V1 and V2 are first connected to the amplification module to obtain the amplified AC voltage signal. The amplified voltage signal is then connected to the rectifier circuit to obtain DC signals V1_1 and V2_1. Finally, the DC signals V1_1 and V2_1 are input into the sense amplifier to obtain the digital output signal.

[0092] In some embodiments of the present invention, a rectifier module includes: a first rectifier and a second rectifier;

[0093] The amplified first voltage is rectified by a first rectifier to obtain a first DC voltage, and the amplified second voltage is rectified by a second rectifier to obtain a second DC voltage.

[0094] It can be further understood that in actual operation, a fixed-frequency AC signal is first used to excite the RC series circuit, and a DC power supply is used to power the subsequent amplification module and sense amplifier. After obtaining the two voltage values V1 and V2, V1 and V2 are first connected to the amplification module to obtain the amplified AC voltage signal. The amplified voltage signal is then connected to the rectifier circuit to obtain DC signals V1_1 and V2_1. Finally, the DC signals V1_1 and V2_1 are input into the sense amplifier to obtain the digital output signal.

[0095] Figure 8 The Monte Carlo data histogram of an embodiment of the key generation system of the physical unclonable function based on AC detection provided by the present invention includes:

[0096] The register is electrically connected to the PUF module 110 and is used to receive the digital signal and store the digital signal to obtain stored data;

[0097] The control logic module 120 is in communication with the register and is configured to generate a key according to the stored data.

[0098] It can be further understood that the Monte Carlo simulation with a sample number of 10,000 is finally performed, and the obtained data is input into MATLAB to generate a histogram, and the generated image is as follows Figure 8 As shown, it can be seen that the final key result conforms to the normal distribution and meets the key randomness requirements.

[0099] In some embodiments of the present invention,

[0100] The control logic module 120 is also electrically connected to the first switch and the second switch, and is configured to generate a first control signal and control the opening or closing of the first switch and the second switch respectively based on the first control signal.

[0101] Figure 9 The basic structure diagram of the existing physical unclonable function unit of one embodiment of the key generation system of the physical unclonable function based on AC detection provided by the present invention includes:

[0102] The control logic module 120 is also electrically connected to the gate of the first MOS transistor and the gate of the sixth MOS transistor, and is used to generate a second control signal and control the on and off of the first MOS transistor and the sixth MOS transistor respectively based on the second control signal.

[0103] It is understandable that the basic structure of the switched capacitor PUF is as follows Figure 9As shown, it consists of four modules: switch capacitor circuit, latch-style senseamplifier 114 (LSSA), register (REG) and control logic (CTL). EN Valid, select signal α SEL When the logic is low, the capacitor C 1P , C 2P , C 1N and C 2N The upper and lower plates of the SC are connected to the ground GND, and the SC circuit works in the discharge state without storing any charge. SEL When the sampling capacitor C 1P and C 1N The upper plates of the capacitors are connected to the power supply potential VDD, and the capacitor circuit will work in the charge redistribution state. At this time, the sampling capacitor C 1N , C 2N , C 1P and C 2P The deviation of the ratio during the manufacturing process is converted into a voltage deviation. LSSA amplifies the voltage difference and converts it into a digital output. REG stores the digital output of all PUF units, and the control logic is used to generate the control signal α CLK _ REG (clock signal), α EN and α SEL Drive each module to work in order.

[0104] Switched-capacitor (SVC)-based physically unclonable functions (PUFs) rely primarily on random capacitance errors introduced during the manufacturing process to generate unique identification features. Capacitor ratio mismatch is converted into a voltage difference ΔVPN, which is then amplified by the LSSA and converted into a digital output. Considering that offset voltage VOFFSET is generated during the LSSA manufacturing process due to MOS transistor mismatch, the effective offset voltage at the LSSA output is ΔV = ΔVPN + VOFFSET. The polarity of ΔV determines whether the LSSA outputs a digital 0 or a digital 1. Furthermore, the absolute value of the offset voltage ΔV within the PUF unit determines the output reliability of the unit. A larger |ΔV| indicates a lower probability of the offset voltage ΔV changing polarity due to power supply voltage and temperature, and thus higher reliability. ΔV is primarily determined by inevitable process variations during chip manufacturing and cannot be determined during design.

[0105] The physical unclonable function based on switched capacitors has the following disadvantages:

[0106] First, the sensitivity is not enough. The tiny error of the capacitor is usually only at the micron level, which has a very small change in the capacitance of the capacitor itself, resulting in a low voltage difference that cannot be detected by subsequent circuits.

[0107] Second, as the process scale decreases, the leakage current gradually increases, and the key quantization method based on the principle of charge conservation gradually becomes ineffective (reliability decreases). However, the process size of integrated circuits is generally at the micron level, and there will be errors in the process errors of quantizing capacitors using the principle of charge conservation during production.

[0108] Figure 10 A pure capacitance circuit diagram of an embodiment of a key generation system based on a physical unclonable function of AC detection provided by the present invention and Figure 11 The ΔV and the ΔV in the pure capacitance circuit of an embodiment of the key generation system based on the physical unclonable function of AC detection provided by the present invention are Function graphs, including:

[0109] It is understandable that Figure 10 The error values are shown in the table below: ±2.5% and ±5% The function graph of |ΔV|. According to the monotonicity of the function graph, when the error range is within ±5%, The extreme value is about 1, and the error is ±2.5% when |ΔV| is about 0.006 Vin; when the error is ±5%, |ΔV| is approximately 0.012 Vin.

[0110] It is understandable that Figure 11 The principle is to extract the voltage difference by DC sampling based on the principle of charge conservation. The ΔV calculation formula is as follows:

[0111]

[0112] Where: C is the capacitance value of the capacitor close to the excitation in the circuit, and is the capacitance value close to the zero potential point and |ΔV| is and σ function.

[0113] Figure 12 In a pure capacitance circuit, |ΔV| and |ΔV| are related to one embodiment of a key generation system based on a physical unclonable function of an AC detection provided by the present invention. σ Function graphs, including:

[0114] It is understandable that Figure 12 Shows the relationship between |ΔV| and σ Function graph, the horizontal axis is σThe vertical axis is |ΔV|. It can be seen that as the capacitance deviation increases, the voltage difference also increases.

[0115] Figure 13 A switched capacitor circuit model simulation diagram of an embodiment of a key generation system based on an AC detection physical unclonable function provided by the present invention includes:

[0116] It can be understood that the simulation waveforms with capacitance errors of ±2.5% and ±5% are respectively (where the red line is the voltage value of V1-V2 with an error of 5%, the yellow line is the voltage value of V1-V2 with an error of 2.5%, the green line is the voltage value of V1-V2 with an error of -2.5%, and the blue line is the voltage value of V1-V2 with an error of -5%). According to the simulation results, in the switched capacitor circuit structure, when VDD is a 1.8V DC voltage, when the capacitance error is ±2.5%, the obtained ΔV is approximately 3.6mV; when the C10 capacitance error is ±5%, the obtained ΔV is approximately 7.2mV. It can be seen that using the capacitor charging and discharging principle to obtain a voltage difference requires a higher capacitance value, and the capacitance value of the simulation environment in this article is the capacitance value of conventional chip capacitors, fluctuating around 100fF. The smaller capacitance value causes the ΔV value to be lower than the theoretical calculated value.

[0117] The above is a detailed introduction to the key generation system of the physical unclonable function based on AC detection provided by the present invention. Specific examples are used herein to illustrate the principles and implementation methods of the present invention. The description of the above embodiments is only used to help understand the method of the present invention and its core ideas. At the same time, for those skilled in the art, according to the ideas of the present invention, there may be changes in the specific implementation methods and application scopes. In summary, the content of this specification should not be understood as limiting the present invention.

Claims

1. A key generation system based on a physical unclonable function with AC detection, characterized in that: include: The PUF module is used to convert the external input AC voltage signal and output a digital signal; A control logic module, electrically connected to the PUF module, for generating a key based on the digital signal; The PUF module includes two symmetrically arranged capacitor-resistor circuits and a sensitive amplifier. An AC voltage signal is passed through the two symmetrically arranged capacitor-resistor circuits to obtain a first voltage and a second voltage. The sensitive amplifier then takes the difference between the first and second voltages and outputs a digital signal. The symmetrically arranged two-way capacitor-resistor circuit includes: A first capacitor, a second capacitor, a first resistor, a second resistor, a first switch, and a second switch; One end of the first capacitor is grounded, the other end of the first capacitor is electrically connected to one end of the first resistor, the sense amplifier and the control logic module, and the other end of the first resistor is electrically connected to the first switch; One end of the second capacitor is grounded, the other end of the second capacitor is electrically connected to one end of the second resistor, the sense amplifier and the control logic module, and the other end of the second resistor is electrically connected to the second switch; The sensitive amplifier includes: a first MOS tube, a second MOS tube, a third MOS tube, a fourth MOS tube, a fifth MOS tube and a sixth MOS tube; The source of the first MOS transistor is electrically connected to the external voltage source, the drain of the first MOS transistor is electrically connected to the source of the second MOS transistor and the source of the third MOS transistor respectively, the drain of the second MOS transistor is electrically connected to the source of the fourth MOS transistor, the gate of the second MOS transistor is electrically connected to the gate of the fourth MOS transistor, the drain of the third MOS transistor is electrically connected to the source of the fifth MOS transistor, the gate of the third MOS transistor is electrically connected to the gate of the fifth MOS transistor, the source of the sixth MOS transistor is electrically connected to the drain of the fourth MOS transistor and the gate of the fifth MOS transistor respectively, and the drain of the sixth MOS transistor is grounded; The common end of the first capacitor and the first resistor is electrically connected to the drain of the second MOS transistor, the source of the fourth MOS transistor, the gate of the third MOS transistor, the gate of the fourth MOS transistor, and the control logic module; The common end of the second capacitor and the second resistor is electrically connected to the gate of the second MOS transistor, the gate of the fourth MOS transistor, the drain of the third MOS transistor, the source of the fifth MOS transistor and the control logic module.

2. The key generation system based on AC detection physical unclonable function according to claim 1, characterized in that: The PUF module also includes: an amplification module and a rectification module; The first voltage and the second voltage are amplified by the amplification module to obtain the amplified first voltage and the second voltage, the amplified first voltage and the second voltage are rectified by the rectification module to output the first DC voltage and the second DC voltage, and the first DC voltage and the second DC voltage are differentiated by the sensitive amplifier to output a digital signal.

3. The key generation system based on AC detection physical unclonable function according to claim 2, characterized in that: The amplification module includes: a first amplifier and a second amplifier; The first voltage is amplified by the first amplifier to obtain the first voltage, and the second voltage is amplified by the second amplifier to obtain the second voltage.

4. The key generation system based on AC detection physical unclonable function according to claim 2, characterized in that: The rectifier module includes: a first rectifier and a second rectifier; The amplified first voltage is rectified by a first rectifier to obtain a first DC voltage, and the amplified second voltage is rectified by a second rectifier to obtain a second DC voltage.

5. The key generation system based on AC detection physical unclonable function according to claim 1, characterized in that: The system further includes a register; The register is electrically connected to the PUF module, and is used to receive the digital signal and store the digital signal to obtain stored data; The control logic module is also in communication with the register and is used to generate a key according to the stored data.

6. The key generation system based on AC detection physical unclonable function according to claim 5, characterized in that: The control logic module is also electrically connected to the first switch and the second switch, and is used to generate a first control signal and control the opening or closing of the first switch and the second switch respectively based on the first control signal.

7. The key generation system based on AC detection physical unclonable function according to claim 6, characterized in that: The control logic module is also electrically connected to the gate of the first MOS transistor and the gate of the sixth MOS transistor, and is used to generate a second control signal and control the on and off of the first MOS transistor and the sixth MOS transistor respectively based on the second control signal.

8. The key generation system based on a physical unclonable function with AC detection according to any one of claims 1 to 7, characterized in that: The number of the PUF modules is n, where n is an integer greater than 2.

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