Image processing apparatus and method performed by image processing apparatus

Abstract

An image processing apparatus and a method performed by the image processing apparatus are provided. The image processing apparatus includes: a channel interface including a data channel, a vertical sync line, a horizontal sync line, and a data enable line; and a combiner configured to convert N pieces of first image data (where N is a positive integer greater than or equal to 2) into second image data having a different image format, time-divide and output the second image data to the data channel, output N vertical synchronization signals for the second image data to the vertical synchronization line, and output N vertical synchronization signals for the second image data to the vertical synchronization line. And outputs N data enable signals for second image data to the horizontal synchronization line and the data enable line.

Description

[0001] This application claims priority to Korean Patent Application No. 10-2023-0195613, filed with the Korean Intellectual Property Office on December 28, 2023, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0002] Example embodiments relate to an image processing apparatus and method. Background Art

[0003] In the past, a video output device (such as a TV) only served as a display for watching broadcasts. However, the role of the video output device has gradually expanded over time. For example, now a video output device is required to combine the Internet and applications to provide content for home entertainment (such as games and workouts). To provide various content, the video output device needs to receive digital data from broadcasts, the Internet, or other sources, and generate and process video data from the received digital data.

[0004] The video output device may include an image processing device for generating and processing video data. The image processing device may include a plurality of unit modules for performing various functions, and it may need to use an existing channel interface between the unit modules to transmit and receive a larger number of video data. Summary of the Invention

[0005] Example embodiments provide an image processing apparatus and method for transmitting and receiving a larger number of image data using a channel interface without increasing the number of bit lines in the channel interface. According to at least some example embodiments, when the RGB format is converted to the YCbCr 422 format and 16-bit (= 8 bits × 2) data instead of the existing 24-bit (= 8 bits × 3) data is transmitted, 8-bit spare data may be generated, and the 8-bit may be used to implement a larger number of video channels than allowed by the conventional system.

[0006] According to an example embodiment, an image processing apparatus includes: a channel interface including a data channel, a vertical synchronization line, a horizontal synchronization line, and a data enable line; and a combiner configured to: convert N first image data (where N is a positive integer greater than or equal to 2) into second image data having a different image format, time-division multiplex and output the second image data to the data channel, output N vertical synchronization signals for the second image data to the vertical synchronization line, and output N data enable signals for the second image data to the horizontal synchronization line and the data enable line.

[0007] According to an exemplary embodiment, an image processing apparatus includes: a channel interface including a data channel, a vertical synchronization line, a horizontal synchronization line, and a data enable line; a combiner configured to: convert N pieces of first image data (where N is a positive integer greater than or equal to 2) into second image data having different image formats, perform time division multiplexing on the second image data and output the result to the data channel, output N vertical synchronization signals for the second image data to the vertical synchronization line, and output N data enable signals for the second image data to the horizontal synchronization line and the data enable line; and a separator configured to: receive the second image data through the data channel, receive the N vertical synchronization signals through the vertical synchronization line, and receive the N data enable signals through the horizontal synchronization line and the data enable line.

[0008] According to an exemplary embodiment, a method performed by an image processing apparatus includes: converting N pieces of first image data (where N is a positive integer greater than or equal to 2) into second image data having different image formats; performing time division multiplexing on the second image data and outputting the result to the data channel; outputting N vertical synchronization signals for the second image data to the vertical synchronization line; and outputting N data enable signals for the second image data to the horizontal synchronization line and the data enable line. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] The above and other aspects, features, and advantages of the present disclosure will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings.

[0010] Figure 1 is a diagram showing an image processing apparatus according to some exemplary embodiments.

[0011] Figure 2 is a diagram showing more specifically an image processing apparatus according to some exemplary embodiments.

[0012] Figure 3 is a diagram showing waveforms of signals transmitted through a channel interface according to some exemplary embodiments.

[0013] Figure 4 is a diagram showing an example of second image data output using two data enable signals.

[0014] Figure 5 and Figure 6 is a diagram showing waveforms of vertical synchronization signals according to some exemplary embodiments.

[0015] Figure 7 is a diagram showing a decoding operation of an image processing apparatus according to some exemplary embodiments.

[0016] Figure 8 is a diagram showing more specifically an image processing apparatus according to some exemplary embodiments.

[0017] Figure 9 is a diagram that more specifically shows an image processing apparatus and a data channel according to some example embodiments.

[0018] Figure 10 is a diagram that more specifically shows an image processing apparatus and a data channel according to some example embodiments.

[0019] Figure 11 is a diagram showing a combiner that processes image data having an exemplary format.

[0020] Figure 12 is a diagram showing an image processing apparatus including a plurality of channel interfaces according to some example embodiments.

[0021] Figure 13 is a diagram showing an image processing apparatus including a plurality of channel interfaces and a plurality of combiners according to some example embodiments.

[0022] Figure 14 is a flowchart showing a method of operating an image processing apparatus according to some example embodiments.

[0023] Figure 15 is a diagram showing an image processing apparatus including an asynchronous buffer according to some example embodiments.

[0024] Figure 16 and Figure 17 is a diagram showing the operation of an image processing apparatus based on an Figure 15 asynchronous buffer according to some example embodiments.

[0025] Figure 18 is a diagram showing a display device according to some example embodiments. Detailed Description

[0026] Hereinafter, example embodiments will be described with reference to the accompanying drawings.

[0027] Figure 1 is a diagram showing an image processing apparatus according to some example embodiments.

[0028] Referring to Figure 1 , the image processing apparatus 100 may be configured to perform all image processing operations on image data. The image processing apparatus 100 may be implemented in hardware or a combination of hardware and software.

[0029] According to some example embodiments, the image processing apparatus 100 may be implemented as various types of processors (such as a central processing unit (CPU), a graphics processing unit (GPU), a microprocessor, a multimedia processor, or an application processor). Optionally, the display controller may be implemented as an integrated circuit (IC) or a system on a chip (SoC).

[0030] The image processing apparatus 100 may include a plurality of unit modules UM1 and UM2. The unit modules UM1 and UM2 may transmit and receive image data to and from each other or process the transmitted and received image data, and may be implemented in hardware or a combination of hardware and software. For example, each of the unit modules UM1 and UM2 may decode digital data received via a high-definition multimedia interface (HDMI), a universal serial bus (USB), the Internet, or a broadcast (not shown) to generate image data, process the image data, or perform an operation to improve the picture quality (PQ) of the image data or an operation to output the image data.

[0031] At least a portion of the unit modules UM1 and UM2 may include at least one of a combiner 110 and / or a splitter 120. For example, in Figure 1 the first unit module UM1 is shown to include a combiner 110, and the second unit module UM2 is shown to include a splitter 120. The combiner 110 and the splitter 120 may be connected to each other via a channel interface CHI.

[0032] The combiner 110 may convert or combine multiple pieces of image data received by the first unit module UM1 into a single piece of image data and output the converted data via the channel interface CHI. For example, the combiner 110 may be used to transmit the image data processed in each of the unit modules UM1 and UM2. The splitter 120 may receive the converted image data via the channel interface CHI and convert the received image data back into multiple pieces of original image data. For example, the splitter 120 may be used to receive the image data to be processed in each of the unit modules UM1 and UM2.

[0033] According to an example embodiment, a unit module that does not need to transmit and receive image data may not include the combiner 110 and the splitter 120.

[0034] Figure 2 is a diagram showing in more detail an image processing apparatus according to some example embodiments.

[0035] Referring to Figure 2, according to some example embodiments, the combiner 210 can receive various types of data through the input data channels IDCH0 to IDCHN-1 (or IDCH(N-1)), the input vertical sync lines IVSL0 to IVSLN-1 (or IVSL(N-1)), the input horizontal sync lines IHSL0 to IHSLN-1 (or IHSL(N-1)), and the input data enable lines IDEL0 to IDELN-1 (or IDEL(N-1)). For example, the input data channels IDCH0 to IDCHN-1, the input vertical sync lines IVSL0 to IVSLN-1, the input horizontal sync lines IHSL0 to IHSLN-1, and the input data enable lines IDEL0 to IDELN-1 can be connected to other unit modules or external devices (not shown). Although not shown, each combiner 210 and each separator 220 can be provided with pins (not shown) for each of the input data channels IDCH0 to IDCHN-1, the input vertical sync lines IVSL0 to IVSLN-1, the input horizontal sync lines IHSL0 to IHSLN-1, and the input data enable lines IDEL0 to IDELN-1.

[0036] The combiner 210 can receive N first image data DAT0 to DATN-1 (or DAT(N-1)) from N input data channels IDCH0 to IDCHN-1, where N is a positive integer greater than or equal to 2. The N first image data DAT0 to DATN-1 can have the same image format, but can be processed separately in the image processing apparatus 200. For example, each of the N first image data DAT0 to DATN-1 can be defined such that the views output through the display panel are different from each other.

[0037] To process the N first image data DAT0 to DATN-1, the combiner 210 can receive N input vertical sync signals ivsync0 to ivsyncN-1 (or ivsync(N-1)) through the N input vertical sync lines IVSL0 to IVSLN-1 and receive N input horizontal sync signals hsync0 to hsyncN-1 (or hsync(N-1)) through the N input horizontal sync lines IHSL0 to IHSLN-1. In an example embodiment, the vertical sync signal can be an image control signal for matching the frame sync of the image data, and can indicate the timing (e.g., start timing) of each frame period. The horizontal sync signal can be a video control signal for matching the horizontal sync within the same frame of the image data, and can indicate the timing (e.g., start timing) of each horizontal time within the frame.

[0038] In addition, the combiner 210 may receive N input data enable signals IDE0 to IDEN-1 (or IDE(N-1)) for N first image data DAT0 to DATN-1 through N input data enable lines IDEL0 to IDEN-1. In an exemplary embodiment, the data enable signal may include a valid period or a valid interval for a frame. For example, the data enable signal may indicate the start or end of a valid period of any image data.

[0039] The combiner 210 may combine N first image data DAT0 to DATN-1 and convert the combined data into second image data FDAT having a different image format. For example, the combiner 210 may convert the combined data into second image data FDAT having a size smaller than the size of the first image data DAT0 to DATN-1. The second image data FDAT may have a size smaller than the transmissible size of the data channels DCH included in the channel interface CHI based on the converted image format. The N first image data DAT0 to DATN-1 may be combined and converted into second image data FDAT based on the conversion of the image format.

[0040] The combiner 210 may time-divide the second image data FDAT having the converted image format and output the time-divided data to the data channel DCH. For example, the converted second image data FDAT may include regions corresponding to each of the N first image data DAT0 to DATN-1. The combiner 210 may time-divide each region through the data channel DCH and sequentially output the time-divided regions. Thus, different from the first image data DAT0 to DATN-1 received through the plurality of input data channels IDCH0 to IDCHN-1, the combiner 210 may output the second image data FDAT without using N data channels DCH.

[0041] In order to later convert the second image data FDAT back into N first image data DAT0 to DATN-1 that can be identified from each other by the separator 220, the combiner 210 may output N vertical synchronization signals vsync0 to vsyncN-1 (or vsync(N-1)) and N data enable signals DEa, DEb, and RDE through the channel interface CHI.

[0042] According to some example embodiments, the combiner 210 may generate and output individually recognizable vertical synchronization signals vsync0 to vsync(N - 1) from the input vertical synchronization signals ivsync0 to ivsync(N - 1) for the converted second image data (FDAT). Optionally, when the input vertical synchronization signals ivsync0 to ivsyncN - 1 input to the combiner 210 are already configured to be recognizable from each other, the combiner 210 may also output the same vertical synchronization signals vsync0 to vsyncN - 1 as the input vertical synchronization signals ivsync0 to ivsyncN - 1.

[0043] According to some example embodiments, the combiner 210 may output N vertical synchronization signals vsync0 to vsyncN - 1 for the second image data FDAT to the vertical synchronization line VSL. For example, the combiner 210 may output N vertical synchronization signals vsync0 to vsyncN - 1 through a single vertical synchronization line VSL included in the channel interface CHI, rather than outputting the N vertical synchronization signals vsync0 to vsyncN - 1 to different vertical synchronization lines VSL. The combiner 210 may output the N vertical synchronization signals vsync0 to vsyncN - 1 output through the vertical synchronization line VSL such that the output vertical synchronization signals vsync0 to vsyncN - 1 are recognizable from each other by the separator 220.

[0044] According to some example embodiments, for the time - division output of the converted second image data FDAT, the combiner 210 may generate and output data enable signals DEa, DEb, and RDE for the time - division output from the input data enable signals IDE0 to IDEN - 1. Optionally, when the input data enable signals IDE0 to IDEN - 1 input to the combiner 210 are already configured for time - division, the combiner 210 may also output the same data enable signals DEa, DEb, and RDE as the input data enable signals IDE0 to IDEN - 1.

[0045] According to some example embodiments, the combiner 210 may output N data enable signals DEa, DEb, and RDE for the second image data FDAT to the horizontal synchronization line HSL and the data enable line DEL included in the channel interface CHI. For example, the combiner 210 may output a first data enable signal DEa corresponding to one of the N data enable signals DEa, DEb, and RDE to the horizontal synchronization line HSL and omit the output of the horizontal synchronization signals hsync0 to hsyncN - 1. In addition, the combiner 210 may output a second data enable signal Deb different from the first data enable signal DEa to the data enable line DEL for the data enable signal.

[0046] The combiner 210 can output the first data enable signal DEa and the second data enable signal DEb to the horizontal sync line HSL and the data enable line DEL, and the remaining data enable signal RDE among the N data enable signals can be output to the data channel DCH. The data channel DCH can be configured to transmit multiple pieces of data, and the combiner 210 can output the second image data FDAT and the remaining data enable signal RDE together through the data channel DCH.

[0047] As a result, the combiner 210 can time-division multiplex and output multiple pieces of first image data DAT0 to DATN-1 to a single data channel DCH to output the multiple pieces of first image data DAT0 to DATN-1 to the separator 220 through a single channel interface CHI. In addition, the combiner 210 can output multiple individually recognizable vertical sync signals vsync0 to vsyncN-1 required to transmit the multiple pieces of first image data DAT0 to DATN-1. To output the multiple data enable signals DEa, DEb, and RDE required to transmit the multiple pieces of first image data DAT0 to DATN-1, the combiner 210 can output one of the data enable signals to the horizontal sync line HSL without outputting the horizontal sync signals hsync0 to hsyncN-1 on the horizontal sync line HSL (e.g., by omitting the horizontal sync signals hsync0 to hsyncN-1). In addition, the combiner 210 can output the remaining data enable signal RDE through the data channel DCH.

[0048] According to the above embodiment, the combiner 210 can output the second image data FDAT and related control signals (e.g., the vertical sync signals vsync0 to vsync(N-1) and the data enable signals) corresponding to the multiple pieces of first image data DAT0 to DATN-1 through a single channel interface CHI including the data channel DCH, the vertical sync line VSL, the horizontal sync line HSL, and the data enable line DEL without any additional lines, channels, or interfaces between the combiner 210 and the separator 220.

[0049] No additional lines, channels, or interfaces are needed, such that a greater number of data can be transmitted without increasing the number of pins (not shown) connected between the unit modules. An increase in the number of pins may cause difficulties in connecting the unit modules and an increase in the size of the image processing apparatus 200, but problems such as connection difficulties or size increases can be prevented according to the exemplary embodiment.

[0050] The separator 220 may receive second image data FDAT, multiple vertical synchronization signals vsync0 to vsyncN-1, and multiple data enable signals DEa, DEb, and RDE from the combiner 210 through a channel interface CHI. For example, the separator 220 may receive the second image data FDAT converted into different image formats from N first image data DAT0 to DATN-1 (where N is a positive integer greater than or equal to 2) through a data channel DCH, receive N vertical synchronization signals vsync0 to vsyncN-1 for the second image data FDAT through a vertical synchronization line VSL, and receive N data enable signals DEa, DEb, and RDE for the second image data FDAT through the data channel DCH, a horizontal synchronization line HSL, and a data enable line DEL.

[0051] The separator 220 may decode the second image data FDAT based on the vertical synchronization signals vsync0 to vsyncN-1 and the data enable signals to obtain N first image data DAT0 to DATN-1.

[0052] The separator 220 may output N first image data DAT0 to DATN-1 through multiple output data channels ODCH0 to ODCHN-1 (or ODCH(N-1)).

[0053] Similar to the combiner 210, the separator 220 may receive and decode N first image data DAT0 to DATN-1 through a single channel interface CHI.

[0054] A clock signal CLK may be commonly applied to the combiner 210 and the separator 220. The combiner 210 may convert or output the first image data DAT0 to DATN-1 into the second image data FDAT based on the clock signal CLK. Similarly, the separator 220 may receive the second image data FDAT or decode the second image data FDAT into the first image data DAT0 to DATN-1 based on the clock signal CLK.

[0055] Figure 3 is a diagram showing waveforms of signals transmitted through a channel interface according to some example embodiments. In Figure 3 two first image data (e.g., N = 2) are shown as being input to the combiner, but the example embodiments are not limited thereto.

[0056] Refer to Figure 3, the first vertical synchronization signal vsync0 and the second vertical synchronization signal vsync1 required to send two first image data can be sent through the vertical synchronization line. As described above, the combiner can output multiple vertical synchronization signals on a single vertical synchronization line VSL, but can output synchronization signals that can be recognized. For example, as shown in the accompanying drawings, the first vertical synchronization signal vsync0 can have a single pulse and the second vertical synchronization signal vsync1 can have two pulses, so that the first vertical synchronization signal vsync0 and the second vertical synchronization signal vsync1 can be distinguished from each other.

[0057] In addition, a first data enable signal DEa having multiple pulses can be output, and a second data enable signal Deb having multiple pulses can be output in the same manner after the start of the first data enable signal DEa in the time domain. In some embodiments, the interval in which each data enable signal has a specific value (e.g., logic high) can correspond to the above-mentioned valid interval. For example, specific image data can be valid in the valid interval of a specific data enable signal. For example, as shown in the accompanying drawings, the combiner can output the time-divisioned first data enable signal DEa and the second data enable signal Deb.

[0058] In addition, the converted second image data FDAT0 and FDAT1 of multiple first image data can be output through the data channel DCH. The second image data FDAT0 and FDAT1 can include the 2-1 image data FDAT0 corresponding to one first image data and the 2-2 image data FDAT1 corresponding to the other first image data. The 2-1 image data FDAT0 can correspond to the first vertical synchronization signal vsync0 and the first data enable signal DEa, and the 2-2 image data FDAT1 can correspond to the second vertical synchronization signal vsync1 and the second data enable signal Deb. For example, one of the time-divisioned 2-1 image data FDAT0 and 2-2 image data FDAT1 can be an even signal, and the other can be an odd signal.

[0059] The combiner can output the 2-1 image data FDAT0 in the valid interval of the first data enable signal DEa and output the 2-2 image data FDAT1 in the valid interval of the second data enable signal Deb. In some embodiments, the combiner can time-division the 2-1 image data FDAT0 and the 2-2 image data on a single data channel DCH and output them. Therefore, in Figure 3 cases, the 2-1 image data FDAT0 and the 2-2 image data FDAT1 can be alternately output in a specific interval in the time domain.

[0060] As a result, the combiner may time-divide and transmit the 2-1st image data FDAT0 and the 2-2nd image data FDAT1 based on the first data enable signal DEa transmitted through the horizontal synchronization line HSL and the second data enable signal DEb transmitted through the data enable line DEL.

[0061] Figure 4 is a diagram illustrating an example of second image data output using two data enable signals.

[0062] Reference Figure 4 , and wherein the valid intervals of the first data enable signal DEa and the second data enable signal DEb do not overlap with each other Figure 3 Differently, the first data enable signal DEa and the second data enable signal DEb may have overlapping valid intervals. Therefore, when the valid intervals of the first data enable signal DEa and the second data enable signal DEb are defined as logic high and the remaining intervals are defined as logic low, the combination of the first data enable signal DEa and the second data enable signal DEb may represent a total of four logic states.

[0063] According to some example embodiments, when N data enable signals are used, the data enable signals may have 2N logic states. Except for an interval in which all data enable signals are logic low, the combiner may output 2N-1 pieces of first image data converted into the second image data FDAT through the N data enable signals.

[0064] In such Figure 4 In the case of N=2 shown in , the combiner can output the second image data FDAT0 to FDAT2 corresponding to the three first image data via the data channel DCH through two data enable signals. For example, the combiner can time-divided and output the second image data FDAT0 to FDAT2 on a single data channel DCH, so that the 2-1st image data FDAT0, the 2-2nd image data FDAT1, and the 2-3rd image data FDAT2 can be sequentially output. Each image data can correspond to any one of the logic states. For example, in Figure 4 , the 2-1st image data FDAT0 may correspond to a logic state (1, 0), the 2-2nd image data FDAT1 may correspond to a logic state (0, 1), and the 2-3rd image data FDAT2 may correspond to a logic state (1, 1).

[0065] As a result, according to example embodiments, the combiner may output a plurality of data enable signals using the data channel DCH, the horizontal synchronization line, and the data enable line included in the channel interface to output a plurality of pieces of first image data converted into the second image data FDAT0 to FDAT2.

[0066] Figure 5 andFigure 6 is a diagram showing waveforms of vertical synchronization signals according to some example embodiments. In Figure 5 , t represents time.

[0067] Referring to Figure 5 , according to some example embodiments, N vertical synchronization signals may have different numbers of pulses according to the above embodiments.

[0068] For example, in order to send multiple vertical synchronization signals to a single vertical synchronization line VSL, a combiner may process the vertical synchronization signals such that each vertical synchronization signal has a different number of pulses (or unit waveforms). For example, as shown in Figure 5 , the combiner may process the vertical synchronization signals such that the first vertical synchronization signal vsync0 has a single pulse and the second vertical synchronization signal vsync1 has two pulses.

[0069] Optionally, each vertical synchronization signal may be set and generated to have a different number of waveforms, and the combiner may receive the corresponding vertical synchronization signals through input vertical synchronization lines.

[0070] Referring to Figure 6 , when multiple vertical synchronization signals are simultaneously input through input vertical synchronization lines (for example, when two of the N vertical synchronization signals overlap each other), the combiner may delay one of the vertical synchronization signals by a predetermined amount of time. In some embodiments, the predetermined amount of time for the delay may be preset, or may be set by the combiner, a unit module, an image processing device, or a host (not shown) of the image processing device connected to Figure 1 .

[0071] For example, when the first vertical synchronization signal vsync0 and the second vertical synchronization signal vsync1 are simultaneously input at time point t1, the combiner may delay the second vertical synchronization signal vsync1_prev from time point t1 to time point t2. For example, the combiner may delay the start time of the effective interval of the first pulse of the second vertical synchronization signal vsync1_prev to time point t2. Thus, the effective interval of the first pulse of the second vertical synchronization signal vsync1_delay delayed to time point t2 may start.

[0072] In addition to the above embodiments, N vertical synchronization signals may be output to be recognizable from each other through a single vertical synchronization line VSL according to various examples.

[0073] The image processing device according to the above embodiments may send multiple vertical synchronization signals through a single vertical synchronization line when multiple vertical synchronization signals are needed to send multiple image data.

[0074] Figure 7It is a diagram showing the decoding operation of an image processing apparatus according to some example embodiments.

[0075] Referring to Figure 7 , a vertical synchronization signal vsync, a horizontal synchronization signal hsync, and a data enable signal DE can be transmitted through a channel interface (see Figure 1 and Figure 2 ), and a clock signal CLK for the operation of a combiner and a separator can be transmitted. In some embodiments, the horizontal synchronization signal hsync can have a pulse at each specific time point.

[0076] According to some example embodiments, the data enable signal DE can have both an active interval and a remaining interval (e.g., an inactive interval) within an interval in which the horizontal synchronization signal hsync has a pulse (e.g., a single cycle of the horizontal synchronization signal hsync). For example, the data enable signal DE can allow a pulse of the horizontal synchronization signal hsync to appear in the remaining interval of the data enable signal DE.

[0077] In some embodiments, a combiner or a separator can identify a timing (e.g., the start timing of each horizontal time (e.g., a pulse of the horizontal synchronization signal hsync)) by identifying the remaining intervals between the active intervals of the data enable signal DE based on the clock signal. For example, a combiner or a separator can identify the timing of each horizontal time without the horizontal synchronization signal hsync. For example, when a specific number of clock signal (CLK) pulses are input during the remaining interval of the data enable signal DE, a combiner or a separator can identify the start of the timing of each horizontal time.

[0078] As a result, even when the transmission of the horizontal synchronization signal hsync through the horizontal synchronization line HSL included in the channel interface CHI is omitted, the image processing apparatus can identify the timing of the horizontal time of the image data. Therefore, according to an example embodiment, the horizontal synchronization line HSL included in the channel interface CHI can be used as a line for the transmission of the data enable signal DE.

[0079] Figure 8 It is a diagram showing more details of an image processing apparatus according to some example embodiments. Hereinafter, redundant descriptions thereof will be omitted.

[0080] Referring to Figure 8 , different from the description provided in Figure 2 , the combiner 310 included in the image processing apparatus 300 may not receive a plurality of horizontal synchronization signals. For example, Figure 2 the input horizontal synchronization lines IHSL0 to IHSLN-1 may be omitted or deactivated.

[0081] As described above, the combiner 310 or the separator 320 may not require a horizontal synchronization signal for combining or decoding image data. Different from the description provided in Figure 2 where the horizontal synchronization signal is first received by the combiner 310, Figure 8 the combiner 310 of

[0082] Figure 2 Figure 2 may omit the reception of the horizontal synchronization signal. Except that the horizontal synchronization signal is not input to the combiner 310, the combiner 310 and the separator 320 may operate in the same manner as in

[0083]

[0084]

[0085] Figure 9

[0086] Figure 9 Figure 9 Figure 9 Figure 9 Figure 9 The combiner 310 may output N first image data DAT0 to DATN-1 received through the input data channels IDCH0 to IDCHN-1 through the data channel DCH, output N vertical synchronization signals vsync0 to vsync(N-1) corresponding to the N input vertical synchronization signals ivsync0 to ivsync(N-1) received through the input vertical synchronization lines IVSL0 to IVSL(N-1) through a single vertical synchronization line VSL, and output N data enable signals DEa, DEb, and RDE corresponding to the N input data enable signals IDE0 to IDE(N-1) received through the input data enable lines IDEL0 to IDEL(N-1) through the horizontal synchronization line HSL, the data enable line DEL, and the data channel DCH. For example, the combiner 310 may output a single data enable signal DEa through the horizontal synchronization line HSL instead of the horizontal synchronization signal whose reception is omitted.

[0083] The separator 320 may receive each signal through the channel interface CHI, decode the second image data FDAT based on the clock signal, and output the obtained N first image data DAT0 to DATN-1 through the N output data channels ODCH0 to ODCHN-1.

[0084] The image processing apparatus according to the above embodiment may reduce the interfaces required for transmitting and receiving the horizontal synchronization signal by omitting the transmission and reception of the horizontal synchronization signal, and may use the horizontal synchronization line to transmit additional signals (e.g., data enable signals).

[0085] Figure 9 is a diagram showing more details of an image processing apparatus and data channels according to some example embodiments.

[0086] Refer to Figure 9, the data channel DCH connected between the combiner 410 and the separator 420 included in the image processing device 400 according to some example embodiments may include a plurality of data lines. For example, the data channel DCH may include m data lines (where m is a positive integer), and m may be defined as the size of the first image data. For example, when the size of each first image data is 24 bits, the data channel DCH may include 24 data lines.

[0087] A part of the plurality of data lines may be allocated for the output of the second image data FDAT, and the remaining data lines may be allocated for the data enable signal. For example, the combiner 410 may output the second image data FDAT to the user data lines UDL which are n data lines among the m data lines (where n is a positive integer), and n may be defined as the size of the second image data FDAT. For example, when the second image data FDAT with the converted format has a size of n bits, n data lines may be allocated as the user data lines UDL.

[0088] The remaining data lines RDL (the remaining data lines among the m data lines other than the user data lines UDL) may be allocated for the data enable signal. The combiner 410 may output one or more data enable signals among the N data enable signals to the remaining data lines among the m data lines.

[0089] For example, the combiner 410 may output the first data enable signal DEa through the horizontal sync line HSL and output the second data enable signal DEb through the data enable line DEL. Then, the remaining data enable signals DEc to DEN-1 among the N data enable signals may be reserved. The combiner 410 may output the remaining data enable signals DEc to DEN-1 through the remaining data lines RDL. In addition, the combiner 410 may output a plurality of vertical sync signals vsync0 to vsyncN-1 through the vertical sync line VSL.

[0090] As a result, according to the example embodiments, when the data lines having the size of the data required to transmit the converted second image data FDAT are allocated for the second image data FDAT, the remaining remaining data lines RDL may be used to transmit the data enable signal. Therefore, according to the example embodiments, a plurality of first image data DAT0 to DATN-1 may be transmitted without additional lines, channels or interfaces.

[0091] Figure 10 is a diagram showing in more detail an image processing apparatus and a data channel according to some example embodiments.

[0092] Refer to Figure 10 , similar to Figure 9The description provided in, including the multiple data lines in the data channel DCH between the combiner 510 and the separator 520 connected to the image processing apparatus 500 according to some example embodiments, may include user data lines UDL and remaining data lines RDL. The user data lines UDL are assigned to the second image data FDAT, and the remaining data lines RDL may be assigned to the data enable signals DEd to DEN-1 and / or the vertical synchronization signals vsync0 to vsyncN-1. For example, as described above Figure 9 As described in, the remaining data lines RDL may be used to output not only the data enable signals but also the vertical synchronization signals vsync0 to vsyncN-1.

[0093] According to some example embodiments, all of the N vertical synchronization signals vsync0 to vsyncN-1 may be assigned to the remaining data lines RDL as shown in the drawings, or a part of the N vertical synchronization signals vsync0 to vsyncN-1 may be assigned to the remaining data lines RDL. When all of the vertical synchronization signals vsync0 to vsyncN-1 are assigned to the remaining data lines RDL, the vertical synchronization line VSL may be assigned to the data enable signal.

[0094] For example, the combiner 510 may output the first data enable signal DEa through the vertical synchronization line VSL. In addition, the combiner 510 may output the second data enable signal DEb through the horizontal synchronization line HSL and output the third data enable signal through the data enable line DEL. Then, the remaining data enable signals DEd to DEN-1 among the N data enable signals may be left. The combiner 510 may output the remaining data enable signals DEd to DEN-1 through the remaining data lines RDL.

[0095] As described in the above embodiments, the vertical synchronization signals vsync0 to vsyncN-1 and the data enable signals may be output through various lines included in the channel interface CHI.

[0096] Figure 11 is a diagram showing a combiner that processes image data having an exemplary format.

[0097] Referring to Figure 11, for example, the first image data in Red - Green - Blue (RGB) format including RGB0[23:0] and RGB1[23:0] may have the RGB format, and the second image data YCbCr[15:0] may have the YCbCr format, where "Y" represents luminance, "Cb" represents blue chrominance difference, and "Cr" represents red chrominance difference. For example, the first image data RGB0[23:0] and RGB1[23:0] having the RGB format may have a size of 24 bits, and the second image data YCbCr[15:0] having the YCbCr format may have a size of 16 bits.

[0098] The combiner 600 may receive the first image data RGB0[23:0] and RGB1[23:0] through the first input data channels IDCH0 and IDCH1. Each of the input data channels IDCH0 and IDCH1 may have a size of 24 bits.

[0099] The combiner 600 may convert the two first image data RGB0[23:0] and RGB1[23:0] into the second image data YCbCr[15:0] having the YCbCr format, and may output the second image data YCbCr[15:0] through the user data line UDL of the data channel DCH. For example, the combiner 600 may convert the first image data RGB0[23:0] and RGB1[23:0] into the second image data YCbCr[15:0] having the YCbCr 422 format. In some embodiments, the converted second image data YCbCr[15:0] may include YCb data and YCr data corresponding to the YCbCr format. Each of the YCb data and YCr data may have a size of 16 bits. When the size of the user data line UDL is 16 bits, the user data line UDL may transmit a single YCb data or a single YCr data. For example, the combiner 600 may alternately output the YCb data and YCr data to the data channel DCH in the time domain.

[0100] Therefore, the combiner 600 may time - division multiplex and output the second - 1 image data FDAT0 corresponding to the 1 - 1 image data, the second - 2 image data FDAT1 corresponding to the 1 - 2 image data, the YCb data and YCr data YCb0 and YCr0 included in the second - 1 image data FDAT0, and the YCb data and YCr data YCb1 and YCr1 included in the second - 2 image data FDAT1 through the user data line UDL.

[0101] For example, the combiner 600 may time - division multiplex and output the second - 1 image data FDAT0 and the second - 2 image data FDAT1, but the unit data (YCb data and YCr data) of each image data may also be output as time - division multiplexed.

[0102] As a result, according to the exemplary embodiment, by time-division multiplexing the second image data YCbCr[15:0] based on data types (e.g., the 2-1 image data FDAT0 and the 2-2 image data FDAT1) and units (e.g., YCb data and YCr data), the transmission of the second image data YCbCr[15:0] can be performed through the user data line UDL that allows 16-bit data to be transmitted at a time.

[0103] In a data channel DCH having a size of 24 bits, in addition to the 16 bits of the user data line UDL for transmitting the second image data YCbCr[15:0], the remaining 8 bits of the remaining data line RDL can be allocated to the data enable signal DE and / or the vertical synchronization signal vsync.

[0104] Figure 12 It is a diagram showing an image processing apparatus including a plurality of channel interfaces according to some exemplary embodiments.

[0105] Referring to Figure 12 , the image processing apparatus 700 may include a plurality of channel interfaces CHI0 and CHI1. Each of the channel interfaces CHI0 and CHI1 may include a data channel DCH0 or DCH1, a vertical synchronization line VSL0 or VSL1, a horizontal synchronization line HSL0 or HSL1, and a data enable line DEL0 or DEL1.

[0106] Each of the channel interfaces CHI0 and CHI1 may output the second image data FDAT (data converted from a plurality of first image data DAT0 to DAT3) from the combiner 710 to the separator 720. For example, the first channel interface CHI0 may include a first data channel DCH0 for outputting the second image data FDAT0 and FDAT1 converted from a plurality of first image data (e.g., the 1-1 image data DAT0 and the 1-2 image data DAT1), a first vertical synchronization line VSL0 for outputting the vertical synchronization signals vsync0 and vsync1 corresponding to the plurality of first image data, and a first horizontal synchronization line HSL0 and a first data enable line DEL0 for outputting a first data enable signal DEa and a second data enable signal DEb for the plurality of first image data.

[0107] For example, the second channel interface CHI1 may include a second data channel DCH1 for outputting second image data FDAT2 and FDAT3 converted from a plurality of first image data (e.g., the 1st - 3rd image data DAT2 and the 1st - 4th image data DAT3), a second vertical sync line VSL1 for outputting vertical sync signals vsync2 and vsync3 corresponding to the plurality of first image data, and a second horizontal sync line HSL1 and a second data enable line DEL1 for outputting a third data enable signal DEc and a fourth data enable signal DEd for the plurality of first image data.

[0108] Considering the maximum data size that can be transmitted by each of the channel interfaces CHI0 and CHI1, the combiner 710 may convert, combine, and output the second image data FDAT0 to FDAT3. For example, when the data channels DCH0 of the channel interface CHI0 and the data channel DCH1 of the channel interface CHI1 can both transmit the second image data FDAT0 to FDAT3 converted from two first image data as shown in the drawings, the combiner 710 may allocate and output each of the second image data FDAT0 to FDAT3 and the control signals (two vertical sync signals and two data enable signals) associated with the second image data FDAT0 to FDAT3 to the channel interfaces CHI0 and CHI1 respectively.

[0109] The example embodiments are not limited to Figure 12 . Therefore, when multiple channel interfaces are provided, the size of the second image data that can be transmitted through each channel interface, the number of vertical sync signals, and the number of data enable signals can be further extended according to the implementation of the channel interface. When the number of required data enable signals increases as the size of the second image data FDAT that can be transmitted increases, additional data enable signals other than the data enable signals shown in the drawings can be transmitted through the remaining data lines according to the above embodiments.

[0110] Figure 13 is a diagram showing an image processing apparatus including a plurality of channel interfaces and a plurality of combiners according to some example embodiments.

[0111] Referring to Figure 13 , according to some example embodiments, a plurality of combiners 811 and 812 and / or splitters 821 and 822 may be provided. For example, the combiners 811 and 812 and / or the splitters 821 and 822 may be provided in the same number as the number of channel interfaces CHI.

[0112] A plurality of combiners 811 and 812 may be provided in a single unit module (e.g., the first unit module UM1), and a plurality of separators 821 and 822 may be provided in a single unit module (e.g., the second unit module UM2). According to an example embodiment, the first unit module UM1 may include a single combiner 811 or 812, and the second unit module UM2 may include a plurality of separators 821 and 822. Optionally, the first unit module UM1 may include a plurality of combiners 811 and 812, and the second unit module UM2 may include a single separator 821 or 822.

[0113] Each of the combiners 811 and 812 may be connected to a single separator 821 or 822 through a single channel interface CHI, and may perform operations such as receiving first image data and a control signal, format conversion and combination of the first image data, and output of second image data and a control signal.

[0114] Figure 14 is a flowchart showing a method of operating an image processing apparatus according to some example embodiments.

[0115] Referring to Figure 14 , in operation S110, the image processing apparatus may convert N pieces of first image data into second image data having different image formats. For example, the image processing apparatus may convert first image data having an RGB format into second image data having a YCbCr format. The N pieces of first image data may be combined with each other to be converted into second image data based on the conversion of the image format.

[0116] In operation S120, the image processing apparatus may output the converted second image data to a data channel based on time division. According to time division, second image data different from each other may be alternately output through a single data channel.

[0117] According to some example embodiments, the method of operating an image processing apparatus may further include an operation of receiving second image data and an operation of decoding the second image data to obtain N pieces of first image data.

[0118] Figure 15 is a diagram showing an image processing apparatus including an asynchronous buffer according to some example embodiments.

[0119] Referring to Figure 15 , according to some example embodiments, the image processing apparatus 900 may include a plurality of asynchronous buffers 911 and 912. For example, the asynchronous buffers 911 and 912 may be provided in the same number as the number of N pieces of first image data DAT0 and DAT1. Each of the asynchronous buffers 911 and 912 may be connected to an input terminal of the combiner 920. For ease of description, Figure 15 shows the case where N = 2, but the example embodiments are not limited thereto.

[0120] The asynchronous buffers 911 and 912 can receive the input vertical synchronization signals ivsync0 and ivsync1, the first image data DAT0 and DAT1, the input data enable signals IDE0 and IDE1, the first clock signal assigned to the first image data DAT0 and DAT1, and the second clock signal CLK_0_1 assigned to the second image data FDAT from the unit modules within the image processing device 900 or a host (not shown) connected to the image processing device 900.

[0121] The asynchronous buffers 911 and 912 can be de-aligned (e.g., de-synchronized) based on the timing of the first clock signal, synchronizing the timing of the input vertical synchronization signals ivsync0 and ivsync1, the first image data DAT0 and DAT1, and the input data enable signals IDE0 and IDE1 with the timing of the second clock signal CLK_0_1. The asynchronous buffers 911 and 912 can output the synchronized vertical synchronization signals S_vsync0 and S_vsync1, the synchronized first image data S_DAT0 and S_DAT1, and the synchronized input data enable signals S_IDE0 and S_IDE1 to the combiner 920.

[0122] The combiner 920 can receive the synchronized vertical synchronization signals S_vsync0 and S_vsync1, the synchronized first image data S_DAT0 and S_DAT1, and the synchronized input data enable signals S_IDE0 and S_IDE1 from the asynchronous buffers 911 and 912, and can receive the second clock signal CLK_0_1 from the unit modules within the image processing device 900 or a host (not shown) connected to the image processing device 900. The combiner 920 can combine and convert the synchronized first image data S_DAT0, S_DAT1 received from each of the asynchronous buffers 911 and 912 into the second image data FDAT based on the second clock signal CLK_0_1. In addition, the combiner 920 can convert the synchronized input data enable signals S_IDE0 and S_IDE1 into data enable signals DEa and DEb for the second image data FDAT and output the data enable signals DEa and DEb. In addition, the combiner 920 can combine the synchronized vertical synchronization signals S_vsync0 and S_vsync1 to output the combined vertical synchronization signals vsync0 and vsync1.

[0123] Figure 16 and Figure 17 is a diagram showing the operation of an image processing device based on an Figure 15 asynchronous buffer according to some example embodiments.

[0124] Referring to Figure 15 andFigure 16 The timing of the 1st - 2 clock signal CLK_1, the 1st - 2 image data DAT1, and the second input data enable signal IDE1 input to the second asynchronous buffer 912 may be asynchronous with the timing of the 1st - 1 clock signal CLK_0, the 1st - 1 image data DAT0, and the first input data enable signal IDE0 input to the first asynchronous buffer 911. In one exemplary embodiment, the 1st - 1 clock signal CLK_0 and the 1st - 2 clock signal CLK_1 may have a frequency of f1 (where f1 is a real number greater than 0).

[0125] When the timing of the 1st - 1 clock signal CLK_0 is normal, it may be necessary to synchronize the timing of other clock signals, related data (first image data), and input data enable signals that are abnormal.

[0126] The second clock signal CLK_0_1 may be input to the asynchronous buffer to perform the synchronization process of the asynchronous buffer. The second clock signal CLK_0_1 may have a frequency corresponding to the product of k (where k represents the number of first clock signals and is a positive integer) and f1. For example, when there are two asynchronous buffers as shown in Figure 15 and Figure 17 , the second clock signal CLK_0_1 may have a frequency of 2f1. The second clock signal CLK_0_1 can be used as a reference clock signal for synchronization.

[0127] As a result, the frequency of the second clock signal CLK_0_1 may have a k:1 relationship with the frequency of the first clock signal. As described above, this is because the combiner is allowed to perform time - division of the second image data FDAT and output it to a single data channel DCH.

[0128] The second asynchronous buffer 912 may synchronize the timing of the 1st - 2 clock signal CLK_1, the 1st - 2 image data, and the second input data enable signal based on the 1st - 1 clock signal CLK_0 and the second clock signal CLK_0_1. For example, at any time point ta, the second asynchronous buffer 912 may process the 1st - 2 clock signal CLK_1 based on the second clock signal CLK_0_1 such that the 1st - 2 clock signal CLK_1 matches the 1st - 1 clock signal CLK_0 in the time domain. Along with the processing of the 1st - 2 clock signal CLK_1, the timing of the 1st - 2 image data and the second data enable signal DEb may also be synchronized. Therefore, the timing of the synchronized 1st - 2 image data S_DAT1 and the second input data enable signal S_IDE1 may be synchronized with the timing of the 1st - 1 image data DAT0 and the first input data enable signal IDE0.

[0129] Referring to Figure 15 and Figure 17, the combiner can combine and convert the first - 1 image data and the first - 2 image data into second image data FDAT based on the second clock signal CLK_0_1. The second image data FDAT can have time - division - multiplexed regions corresponding to each of the first image data (e.g., the second image data) FDAT0 and FDAT1. In addition, the combiner can output a first data enable signal DEa and a second data enable signal DEb corresponding to each time - division - multiplexed region.

[0130] When the input first image data is not aligned with the timing of the control signal and the clock signal for the first image data, the image processing apparatus according to the above - mentioned embodiments can synchronize the asynchrony through an asynchronous buffer.

[0131] Figure 18 is a diagram showing a display device according to some example embodiments.

[0132] Referring to Figure 18 , the display device 1000 may include a display controller 1100 and a display panel 1200.

[0133] The display controller 1100 can control the overall operation of the display device 1000. The display controller 1100 can generate input image data to be displayed on the display panel 1200 and control commands for controlling the display device 1000. For example, the control commands may include setting information regarding brightness, gamma, frame rate, operation mode of the display driving circuit, etc. The display controller 1100 can process the input image data based on a clock signal and / or various synchronization signals. The input image data may include frame data corresponding to each of a plurality of frames.

[0134] In some example embodiments, the display controller 1100 can be implemented as various types of processors (such as a central processing unit (CPU), a graphics processing unit (GPU), a microprocessor, a multimedia processor, or an application processor). Optionally, the display controller 1100 can be implemented as an integrated circuit (IC) or a system - on - chip (SoC).

[0135] The display controller 1100 may include a first unit module UM1 and a second unit module UM2. The first unit module UM1 includes a combiner according to the above - mentioned some example embodiments, and the second unit module UM2 includes a separator. According to the above - mentioned some example embodiments, the first unit module UM1 and the second unit module UM2 can be connected to each other through a channel interface CHI. Each unit module can perform various functions to process the input image data.

[0136] According to some example embodiments, each unit module may exchange image data with other unit modules through a channel interface CHI to process input image data. According to the above embodiments, the channel interface CHI may include a data channel, a vertical synchronization line, a horizontal synchronization line, and a data enable line to output image data. A combiner included in the first unit module may convert N pieces of first image data into second image data having a different image format, and time-division multiplex the second image data and output it to the channel interface. A separator included in the second unit module may receive and decode the second image data.

[0137] The display controller 1100 may convert input image data into an analog signal for driving the display panel 1200, and provide the converted analog signal to the display panel 1200.

[0138] The display panel 1200 may be a display unit on which an actual image is displayed, and may be one of display devices (such as a thin film transistor liquid crystal display (TFT-LCD), an organic light emitting diode (OLED) display, a field emission display, or a plasma display panel (PDP)) that receive an electrically transmitted image signal and display a two-dimensional image.

[0139] As described above, an image processing apparatus and method for transmitting and receiving a larger number of image data using a channel interface may be provided.

[0140] The example embodiments have been described above by means of method steps showing the execution of specified functions and their relationships. For ease of description, the boundaries and sequences of these functional building blocks and method steps have been defined herein. As long as the specified functions and relationships are appropriately executed, alternative boundaries and sequences may be defined. Therefore, any such alternative boundaries or sequences are within the scope and spirit of the claims.

[0141] As used herein, expressions such as "at least one of..." when following a list of elements modify the entire list of elements, rather than modifying individual elements of the list. Thus, for example, both "at least one of A, B, or C" and "at least one of A, B, and C" represent any combination of A, B, C, or two or more of A, B, and C. Similarly, A and / or B represents A, B, or A and B.

[0142] Any functional block shown in the accompanying drawings and described above can be implemented in a processing circuit, such as hardware including logic circuits, a hardware / software combination (such as a processor executing software), or a combination thereof. For example, the processing circuit can more specifically include, but is not limited to, a central processing unit (CPU), an arithmetic logic unit (ALU), a digital signal processor, a microcomputer, a field programmable gate array (FPGA), a system on a chip (SoC), a programmable logic unit, a microprocessor, an application specific integrated circuit (ASIC), etc.

[0143] The units and / or modules described herein can be implemented using hardware components or a combination of software components and hardware components. For example, the hardware components can include a microcontroller, a memory module, a sensor, an amplifier, a bandpass filter, an analog-to-digital converter, and a processing device, etc. The processing device can be implemented using one or more hardware devices configured to execute and / or perform program code by performing arithmetic, logical, and input / output operations. The (one or more) processing devices can include a processor, a controller, and an arithmetic logic unit, a digital signal processor, a microcomputer, a field programmable array, a programmable logic unit, a microprocessor, or any other device capable of responding and executing instructions in a defined manner. The processor can be a hardware processor (such as a central processing unit (CPU), a multiprocessor, a distributed processing system, an application specific integrated circuit (ASIC), and / or a suitable hardware processing unit). The (one or more) processing devices can run an operating system (OS) and one or more software applications running on the OS. The processing device can also access, store, manipulate, process, and create data in response to the execution of software. For simplicity, the description of the processing device is used as singular; however, those skilled in the art will understand that the processing device can include multiple processing elements and multiple types of processing elements. For example, the processing device can include multiple processors, or a processor and a controller. In addition, different processing configurations of a dedicated computer (such as a parallel processor, a multi-core processor, a distributed processing, etc.) that configures the processing device to control one or more of its operations when executing instructions according to firmware or software are feasible.

[0144] The software can include a computer program, a fragment of code, an instruction, or some combination thereof for independently or jointly instructing and / or configuring the processing device to operate as desired, thereby transforming the processing device into a dedicated processor. The software and data can be permanently or temporarily embodied in any type of machine, component, physical or virtual device, and / or computer storage medium or device. The software can also be distributed over a networked computer system such that the software is stored and executed in a distributed manner. The software and data can be stored by one or more computer-readable recording media.

[0145] While the example embodiments have been shown and described above, it will be clear to those skilled in the art that modifications and variations can be made without departing from the scope of the inventive concept defined by the appended claims.

Claims

1. An image processing device, comprising: Channel interface, including data channel, vertical synchronization line, horizontal synchronization line and data enable line; as well as The combiner is bound to the channel interface and is configured to: converting N pieces of first image data into second image data having a different image format, wherein N is a positive integer greater than or equal to 2, The second image data is time-divided and output to the data channel, outputting N vertical synchronization signals for the second image data to the vertical synchronization lines, and N data enable signals for the second image data are output to the horizontal synchronization line and the data enable line.

2. The image processing device according to claim 1, wherein: The second image data has an image format having a size smaller than that of the first image data.

3. The image processing apparatus according to claim 1, wherein: The combiner is configured to output a first data enable signal among the N data enable signals to a horizontal synchronization line, and output a second data enable signal among the N data enable signals to a data enable line.

4. The image processing apparatus according to claim 1, wherein: The data channel includes m data lines, where m is a positive integer, and The size of a single one of the N pieces of first image data is m bits.

5. The image processing apparatus according to claim 4, wherein: The combiner is configured to: output the second image data to n data lines among the m data lines, wherein n is a positive integer less than m, and The size of a single piece of second image data is n bits.

6. The image processing apparatus according to claim 5, wherein: The combiner is configured to output at least one of the N data enable signals to at least one remaining data line among the m data lines.

7. The image processing apparatus according to claim 1, wherein: The N vertical synchronization signals have different numbers of pulses.

8. The image processing apparatus according to claim 1, wherein: The combiner is configured to delay one of the two vertical synchronization signals by a predetermined amount of time based on two vertical synchronization signals overlapping each other among the N vertical synchronization signals.

9. The image processing apparatus according to claim 1, wherein: The first image data has an RGB format, and the second image data has a YCbCr format.

10. The image processing apparatus according to claim 9, wherein: The second image data includes YCb data and YCr data corresponding to a YCbCr format, and The combiner is configured to alternately output the YCb data and the YCr data to the data channel in the time domain.

11. The image processing apparatus according to any one of claims 1 to 10, further comprising: An asynchronous buffer is connected to the input of the combiner and is configured to: receive the first image data, a first clock signal assigned to the first image data and a second clock signal assigned to the second image data, and synchronize the first image data with the second clock signal based on the first clock signal being desynchronized.

12. The image processing apparatus according to claim 11, wherein: The number of asynchronous buffers is set to N.

13. An image processing device, comprising: Channel interface, including data channel, vertical synchronization line, horizontal synchronization line and data enable line; a combiner coupled to the channel interface and configured to: convert N pieces of first image data into second image data having a different image format, wherein N is a positive integer greater than or equal to 2, time-divide the second image data and output it to the data channel, output N vertical synchronization signals for the second image data to the vertical synchronization line, and output N data enable signals for the second image data to the horizontal synchronization line and the data enable line; and The separator is coupled to the channel interface and is configured to receive the second image data through the data channel, receive the N vertical synchronization signals through the vertical synchronization line, and receive the N data enable signals through the horizontal synchronization line and the data enable line.

14. The image processing apparatus according to claim 13, wherein: The separator is configured to decode the second image data to obtain the N pieces of first image data.

15. The image processing apparatus according to claim 13, wherein: The second image data has an image format having a size smaller than that of the first image data.

16. The image processing device according to any one of claims 13 to 15, wherein: The data channel includes m data lines, where m is a positive integer, and the size of a single first image data is m bits, and The separator is configured to receive the second image data from n data lines among the m data lines, wherein n is a positive integer less than m, and a size of a single piece of the second image data is n bits.

17. The image processing apparatus according to claim 16, wherein: The separator is configured to receive at least one of the N data enable signals from remaining data lines among the m data lines.

18. A method performed by an image processing apparatus, the method comprising: Converting N pieces of first image data into second image data having a different image format, wherein N is a positive integer greater than or equal to 2; Time-dividing the second image data and outputting it to the data channel; outputting N vertical synchronization signals for the second image data to the vertical synchronization lines; and N data enable signals for the second image data are output to the horizontal synchronization line and the data enable line.

19. The method of claim 18, further comprising: receiving second image data; as well as The second image data is decoded to obtain the N pieces of first image data.

20. The method of claim 18 or 19, wherein: The second image data has an image format having a size smaller than that of the first image data.

Images