Method for reducing reset noise and image sensor
By adopting the design of variable capacitance in the image sensor, controlling its capacitance value changes to reduce reset noise, the problem of limited signal-to-noise ratio and dynamic range under high exposure conditions is solved, and efficient signal quantization and noise reduction are achieved.
Patent Information
- Application Number
- CN202311869140.8
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2023-12-29
- Publication Date
- 2025-07-01
AI Technical Summary
The reset noise of existing image sensors increases under high exposure conditions, affecting the signal-to-noise ratio and dynamic range. In particular, the larger the capacitance value of the LOFIC capacitor, the greater the reset noise.
Using a variable capacitance design, the bias voltage of the second plate is controlled to maintain a low capacitance value during the reset process, and becomes a high capacitance value during sampling to reduce reset noise, and switch to a linear interval after the integration process is completed for signal quantization.
Effectively reduce reset noise, improve the signal-to-noise ratio and dynamic range of the image sensor, and the process is simple and convenient for linear signal quantization.
Smart Images
Figure CN120238762A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of semiconductor technology, and particularly to a method for reducing reset noise and an image sensor. Background Art
[0002] In traditional image sensors, the highlight range that can be output is limited by the full well electron capacity. Under high exposure conditions, the photoelectron signal higher than the full well capacity will overflow and will not be quantized into an image signal, resulting in overexposure on the output image. If the overflowing photoelectrons enter adjacent or nearby photodiodes, halos will be generated. In order to better utilize the overflowing photoelectrons and quantize them into effective image signals, an image sensor solution with a lateral overflow integration capacitor (LOFIC) architecture has emerged. Its common architecture form is as Figure 1 shown. Among them, the photodiode D n and transistor T n are repeatable units, including n photodiodes (PDs) sharing a floating diffusion region, where n≥1. The right dashed arrow indicates the electron overflow channel. LOFIC1 and LOFIC2 are lateral overflow integration capacitors, and T_LOFIC1 and T_LOFIC2 are transistors for controlling the lateral overflow integration capacitors. RST represents the reset transistor, SF represents the source follower transistor, and SEL represents the selection transistor. The purpose is achieved by designing an overflow circuit signal for photoelectrons. When excessive photoelectrons overflow, the overflowing photoelectron signal will be stored in an additional capacitor, and then this part of the photoelectric signal will be quantized and output as an image through the readout circuit, thereby realizing the high dynamic range function.
[0003] The theoretical upper limit of the high dynamic range of the image sensor with the LOFIC architecture is affected by the capacitance value of the LOFIC. The larger the capacitance value, the larger the signal it can quantize. At the current stage, the LOFIC capacitance can commonly adopt forms such as trench capacitors, MIM capacitors (metal - dielectric layer - semiconductor), and PIP capacitors (polycrystalline silicon - dielectric layer, semiconductor), etc., and ultra - high capacitance values can be obtained. However, the larger the capacitance, the greater the reset noise will be. The reset noise N ktc can be calculated by the Boltzmann constant K , the absolute temperature T and the capacitance value in the reset circuit C as shown in the following formula:
[0004] It can be seen that the currently commonly used capacitors are all capacitors with good linearity. The increase in reset noise will also affect the signal - to - noise ratio and dynamic range of the image sensor. Summary of the Invention
[0005] The object of the present invention is to provide a method for reducing reset noise, including: A variable capacitor is provided. The first electrode plate of the variable capacitor is electrically connected to an input signal through a switch. By controlling the bias voltage applied to the second electrode plate of the variable capacitor, the variable capacitor is maintained at a preset low capacitance value during the circuit reset process and changes to a required high capacitance value during sampling, so as to reduce reset noise.
[0006] Further, the variable capacitor is arranged in an uncorrelated double-sampling circuit.
[0007] Further, the uncorrelated double-sampling circuit is a high-dynamic-range image sensor using a lateral overflow integration capacitor, and the lateral overflow integration capacitor uses the variable capacitor; During the reset process of the high-dynamic-range image sensor, the bias voltage applied to the second electrode plate is controlled so that the lateral overflow integration capacitor is maintained at a preset low capacitance value to reduce reset noise; During the sampling process of the high-dynamic-range image sensor, the bias voltage applied to the second electrode plate is controlled so that the lateral overflow integration capacitor changes to a high capacitance value in the linear region to facilitate quantization and reading of the sampling signal.
[0008] Further, changing the lateral overflow integration capacitor to a high capacitance value in the linear region includes: after the integration process ends, making the bias voltage applied to the second electrode plate greater than the voltage of the first electrode plate to increase the carriers in the lateral overflow integration capacitor itself, so that the lateral overflow integration capacitor changes to the linear region, and the output signal is linearly quantized and then read out.
[0009] Further, the variable capacitor adopts a polysilicon-dielectric layer-semiconductor form, and the polysilicon electrode plate is used as the second electrode plate to apply the bias voltage. During the reset process, by changing the bias voltage, the variable capacitor is at least partially depleted and thus reduced to a preset low capacitance value.
[0010] Further, the variable capacitor adopts a metal-dielectric layer-semiconductor form, and the metal electrode plate is used as the second electrode plate to apply the bias voltage. During the reset process, by changing the bias voltage, the variable capacitor is at least partially depleted and thus reduced to a preset low capacitance value.
[0011] Further, the variable capacitor adopts a PN junction form, and the P-type doped region is used as the second electrode plate to apply the bias voltage. During the reset process, by changing the bias voltage, the variable capacitor is at least partially depleted and thus reduced to a preset low capacitance value.
[0012] Further, the variable capacitor adopts a metal-semiconductor structure. The metal plate is used as the second plate to access the bias voltage. During the reset process, by changing the bias voltage, the variable capacitor is at least partially depleted and thus reduced to a preset low capacitance value.
[0013] Further, the variable capacitor adopts a trench capacitor to reduce the capacitance area.
[0014] Further, the variable capacitor adopts a three-dimensional capacitor. The semiconductor structure in the three-dimensional capacitor is formed by an epitaxial process to reduce the capacitance area.
[0015] The present invention also provides an image sensor that uses a lateral overflow integration capacitor to obtain a high dynamic range. Among them, the lateral overflow integration capacitor is a variable capacitor, and the method for reducing reset noise as described above is used to reduce the reset noise.
[0016] Through the above solution, the present invention can minimize the reset noise in a high dynamic range image sensor using a LOFIC capacitor, improve the signal-to-noise ratio and dynamic range of the output image. Moreover, the process is simple, and the variable capacitor can be very conveniently switched to a linear capacitor by changing the bias voltage of the capacitor, so as to facilitate the linear quantization of the electronic signal by the source follower. BRIEF DESCRIPTION OF THE DRAWINGS
[0017] Other features, objects, and advantages of the present invention will become more apparent by reading the following detailed description of non-limiting embodiments with reference to the accompanying drawings.
[0018] Figure 1 Schematic diagram of the circuit structure of an image sensor with a lateral overflow integration capacitor in the prior art; Figure 2 Schematic diagram of the circuit structure of an image sensor with a variable lateral overflow integration capacitor in the present invention; Figure 3 、 Figure 5 、 Figure 6 Schematic cross-sectional view of the structure during the formation of the variable capacitor in the present invention; Figure 4 Top view structure diagram of the variable capacitor during the formation process in the present invention.
[0019] In the figures, throughout the different views, the same or similar reference numerals denote the same or similar devices (modules) or steps. EMBODIMENTS
[0020] The object of the present invention is to provide a method for reducing reset noise, including: A variable capacitor is provided. The first plate of the variable capacitor is electrically connected to an input signal through a switch. By controlling the bias voltage applied to the second plate of the variable capacitor, the variable capacitor maintains a preset low capacitance value during the circuit reset process and changes to a required high capacitance value during sampling, so as to reduce reset noise.
[0021] As Figure 2 In the specific embodiment shown, the capacitors LOFIC1 and LOFIC2 are set as variable capacitors. The first plates of the capacitors are electrically connected to control transistors, and the second plates are connected to a bias voltage. During the circuit reset process, the capacitance value of the variable capacitor is extremely small, which can minimize the recharge noise to the greatest extent. During the circuit integration process, overflow photoelectrons can be stored, thereby quantifying high-exposure electron signals and outputting high-dynamic images.
[0022] In an alternative embodiment, the variable capacitor is disposed in a correlated double sampling circuit. Preferably, the correlated double sampling circuit is a high-dynamic image sensor using a lateral overflow integration capacitor, and the lateral overflow integration capacitor employs the variable capacitor. In this embodiment, when the high-dynamic image sensor is in the reset process, by controlling the bias voltage applied to the second plate, the lateral overflow integration capacitor is maintained at a preset low capacitance value to reduce reset noise; when the reset is completed and the high-dynamic image sensor is in the sampling process, the bias voltage applied to the second plate is controlled to make the lateral overflow integration capacitor change to a high capacitance value in the linear region, so as to facilitate the quantization and readout of the sampling signal.
[0023] During the operation of the variable capacitor, in the integration state, the voltage applied to the second plate is set to 0V. After the first plate is reset, the first plate is in a high-voltage state. At this time, the variable capacitor is extremely small and the reset noise is also extremely small. After the integration state ends, the voltage applied to the first plate decreases and the capacitance value of the variable capacitor increases. During the sampling process after the reset is completed, if the variable capacitor is still in the variable region, it will be difficult for the source follower to linearly quantify the sampling signal. In this embodiment, the second plate can be biased to a high voltage to switch the capacitor from the variable region to the linear region, facilitating the linear quantization of the sampling signal by the source follower.
[0024] Preferably, in this embodiment, after the integration process ends, the bias voltage applied to the second plate can be made greater than the voltage of the first plate to increase the carriers of the lateral overflow integration capacitor itself, make the lateral overflow integration capacitor change to the linear region, and linearly quantify and read out the output signal.
[0025] On this basis, there are various structural forms of the variable capacitor in the present invention that can be realized. For example, the variable capacitor adopts a polysilicon-dielectric layer-semiconductor form, a metal-dielectric layer-semiconductor form, a PN junction form, or a metal-semiconductor structure form. The polysilicon electrode plate, the metal electrode plate, the P-type doped region, and the metal electrode plate are respectively used as the second electrode plate in the solution of the present invention to access the bias voltage. During the reset process, by changing the bias voltage, at least part of the variable capacitor is depleted to reduce it to a preset low capacitance value.
[0026] In terms of the formation process, in one embodiment, the variable capacitor in the present invention can adopt a trench capacitor to reduce the capacitance area. Further, the variable capacitor adopts a three-dimensional capacitor, and the semiconductor structure in the three-dimensional capacitor is formed by an epitaxial process to reduce the capacitance area.
[0027] For example, in an optional implementation manner, the variable capacitor in the present invention can be prepared through the following steps: Step S1: According to a preset lithography pattern, a trench 110 with a predetermined depth is etched on the semiconductor substrate 100, as Figure 3 shown. Preferably, an N-type doped semiconductor substrate 100 can be selected. In addition, the trench 110 should be able to surround a set of parallel opposite sides of the active region AA at a predetermined position, as Figure 4 shown; Step S2: A dielectric layer 111 is filled in the trench 110, as Figure 5 shown; Step S3: As Figure 6 shown, a polycrystalline semiconductor 120, such as polysilicon, is filled on the surface of the dielectric layer 111 to form the variable capacitor structure in the present invention. Preferably, a P-type doped polycrystalline semiconductor material can be selected corresponding to the N-type doped semiconductor substrate 100.
[0028] In this implementation manner, the active region AA surrounded by the trench 110 is used as the first electrode plate of the variable capacitor for storing and reading out photo-electrons. The polycrystalline semiconductor 120 part inside the trench 110 is used as the second electrode plate to access the bias voltage, so as to realize the change of the capacitance value of the variable capacitor in the present invention and help deplete the carriers in the active region AA.
[0029] In this embodiment, the doping concentration of the N-type semiconductor substrate 100 needs to be selected appropriately to ensure that a predetermined target number of photoelectrons can be stored. The size of the active region AA needs to be selected appropriately to ensure that it can be depleted. The thickness of the dielectric layer 111 also needs to be selected appropriately to have an anti-breakdown ability while ensuring the control ability of the polycrystalline semiconductor 120. Preferably, the higher the concentration of the P-type polycrystalline semiconductor 120, the stronger its ability to deplete the carriers in the active region AA. Therefore, a P-type polycrystalline semiconductor material with a high concentration can be appropriately used. In addition, the high-concentration P-type polycrystalline semiconductor 120 can also increase the bias voltage to further enhance the ability to deplete the carriers in the active region AA.
[0030] The present invention also provides an image sensor that uses a lateral overflow integration capacitor to obtain a high dynamic range. Among them, the lateral overflow integration capacitor is a variable capacitor, and the method for reducing reset noise as described above is used to reduce reset noise.
[0031] For those skilled in the art, it is obvious that the present invention is not limited to the details of the above exemplary embodiments, and the present invention can be implemented in other specific forms without departing from the spirit or basic characteristics of the present invention. Therefore, in any case, the embodiments should be regarded as exemplary and non-limiting. In addition, obviously, the word "including" does not exclude other elements and steps, and the word "a" does not exclude a plurality. A plurality of elements stated in the apparatus claims can also be implemented by one element. Words such as first and second are used to represent names and do not represent any specific order.
Claims
1. A method for reducing reset noise, characterized in that, Comprising: A variable capacitor is provided. The first plate of the variable capacitor is electrically connected to an input signal through a switch. By controlling the bias voltage applied to the second plate of the variable capacitor, the variable capacitor maintains a preset low capacitance value during the circuit reset process and changes to a required high capacitance value during sampling, so as to reduce reset noise.
2. The method for reducing reset noise according to claim 1, characterized in that, The variable capacitor is disposed in an uncorrelated double sampling circuit.
3. The method for reducing reset noise according to claim 2, wherein The uncorrelated double sampling circuit is a high-dynamic-range image sensor using a lateral overflow integration capacitor, and the lateral overflow integration capacitor uses the variable capacitor; During the reset process of the high-dynamic-range image sensor, the bias voltage applied to the second plate is controlled so that the lateral overflow integration capacitor maintains a preset low capacitance value to reduce reset noise; During the sampling process of the high-dynamic-range image sensor, the bias voltage applied to the second plate is controlled so that the lateral overflow integration capacitor changes to a high capacitance value in the linear region to facilitate quantization and reading of the sampling signal.
4. The method for reducing reset noise according to claim 3, wherein The step of changing the lateral overflow integration capacitor to a high capacitance value in the linear region includes: after the integration process ends, making the bias voltage applied to the second plate greater than the voltage of the first plate to increase the carriers in the lateral overflow integration capacitor itself, so that the lateral overflow integration capacitor changes to the linear region, and the output signal is linearly quantized and then read out.
5. The method for reducing reset noise according to claim 1, characterized in that, The variable capacitor adopts a polysilicon-dielectric layer-semiconductor form. The polysilicon plate is used as the second plate to apply the bias voltage. During the reset process, by changing the bias voltage, the variable capacitor is at least partially depleted and thus reduced to a preset low capacitance value.
6. The method for reducing reset noise according to claim 1, wherein The variable capacitor adopts a metal-dielectric layer-semiconductor form. The metal plate is used as the second plate to apply the bias voltage. During the reset process, by changing the bias voltage, the variable capacitor is at least partially depleted and thus reduced to a preset low capacitance value.
7. The method for reducing reset noise according to claim 1, wherein, The variable capacitor adopts a PN junction form. The P-type doped region is used as the second plate to apply the bias voltage. During the reset process, by changing the bias voltage, the variable capacitor is at least partially depleted and thus reduced to a preset low capacitance value.
8. The method for reducing reset noise according to claim 1, wherein The variable capacitor adopts a metal-semiconductor structure. The metal plate is used as the second plate to apply the bias voltage. During the reset process, by changing the bias voltage, the variable capacitor is at least partially depleted and thus reduced to a preset low capacitance value.
9. The method for reducing reset noise according to claim 1, wherein The variable capacitor adopts a trench capacitor to reduce the capacitance area.
10. The method for reducing reset noise according to claim 1, wherein, The variable capacitor adopts a three-dimensional capacitor, and the semiconductor structure in the three-dimensional capacitor is formed by an epitaxial process to reduce the capacitance area.
11. An image sensor, characterized in that, A lateral overflow integration capacitor is adopted to obtain a high dynamic range, wherein the lateral overflow integration capacitor is a variable capacitor, and the method for reducing reset noise as described in claims 1 to 10 is adopted to reduce reset noise.