Global exposure pixel structure and image sensor

Abstract

The invention discloses a global exposure pixel structure and an image sensor, and relates to the technical field of image sensors, and the global exposure pixel structure comprises a signal generation circuit, a first storage circuit, a second storage circuit and a signal output circuit. The signal generation circuit generates a reset voltage and a signal voltage, the first storage circuit stores the signal voltage, the second storage circuit stores the reset voltage, and the signal output circuit outputs the reset voltage and the signal voltage. Under the condition that the capacitance value of the capacitor in the first storage circuit is equal to the capacitance value of the capacitor in the second storage circuit, the effective voltage output by the global exposure pixel structure is approximate to the difference between the reset voltage and the signal voltage, compared with a traditional scheme, the global exposure pixel structure can achieve the effect that the output effective voltage is doubled without adding an MOS tube, and the overall performance of the global exposure pixel structure is improved. And the sensitivity of the global exposure pixel structure is effectively improved, so that the signal-to-noise ratio is improved.

Description

Technical Field

[0001] The present application relates to the technical field of image sensors, and in particular to a global exposure pixel structure and an image sensor. Background Art

[0002] An image sensor is a sensor that can convert light signals into electrical signals. An image sensor consists of many pixels. In order to meet the needs of photographing high-speed moving objects, the pixels adopt a global exposure pixel structure. The traditional global exposure pixel structure is as follows: Figure 1 As shown, it includes 8 transistors (Q1 to Q8), which is usually called an 8T pixel. However, Figure 1 The final effective voltage signal Veff of the global exposure pixel structure shown is Vrst = (Vrst-Vsig)*C1 / (C1+C2). Where Vrst represents the reset voltage, Vsig represents the signal voltage, C1 and C2 are Figure 1 The capacitance of the two capacitors. Usually C1 = C2, so Veff = (Vrst-Vsig) / 2, that is, the final effective voltage signal is divided by 2 compared to the output of the first-stage source follower tube in the pixel, and the voltage signal amplitude is reduced by half, which will cause the sensitivity of the entire image sensor to be reduced by half, and also reduce the signal-to-noise ratio. Although, Figure 2 The pixel shown includes 11 transistors (Q1 to Q11) which can increase the amplitude of the effective voltage signal, but it is necessary to increase the number of MOS tubes in the pixel, resulting in an increase in the pixel size, or to reduce the area of ​​the photodiode when the pixel size remains unchanged, resulting in a decrease in sensitivity.

[0003] In view of this, how to increase the amplitude of the effective voltage without increasing the number of MOS tubes in the pixel has become a technical problem that needs to be solved urgently by those skilled in the art. Summary of the invention

[0004] The purpose of the present application is to provide a global exposure pixel structure and an image sensor, which can increase the amplitude of the effective voltage without increasing the number of MOS tubes in the pixel.

[0005] In order to solve the above technical problems, the present application provides a global exposure pixel structure, including:

[0006] A signal generation circuit, a first storage circuit, a second storage circuit, and a signal output circuit; a first end of the first storage circuit is connected to an output end of the signal generation circuit, and a second end of the first storage circuit is grounded; a first end of the second storage circuit is connected to the output end of the signal generation circuit, and a second end of the second storage circuit is grounded; an input end of the signal output circuit is connected to the output end of the signal generation circuit; the signal generation circuit includes a first amplification transistor; a source electrode of the first amplification transistor serves as the output end of the signal generation circuit, a gate electrode of the first amplification transistor is connected to a floating diffusion node, and a drain electrode of the first amplification transistor is connected to a power supply end of a global exposure pixel structure;

[0007] The signal generation circuit is configured to generate a reset voltage and a signal voltage;

[0008] The first storage circuit is configured to store the signal voltage;

[0009] The second storage circuit is configured to store the reset voltage;

[0010] The signal output circuit is configured to output the reset voltage stored in the second storage circuit and the signal voltage stored in the first storage circuit.

[0011] Optionally, the signal generation circuit further includes:

[0012] A photosensitive diode, a first transistor, a second transistor, and a third transistor; an anode of the photosensitive diode is grounded, a cathode of the photosensitive diode is connected to a second end of the first transistor, a first end of the first transistor is connected to the floating diffusion node, a third end of the first transistor inputs a transfer control signal, a first end of the second transistor is connected to a voltage of a preset power supply, a second end of the second transistor is connected to the floating diffusion node, a third end of the second transistor inputs a reset control signal, a first end of the third transistor is connected to the source electrode of the first amplification transistor, a second end of the third transistor is grounded, and a third end of the third transistor inputs a precharge control signal.

[0013] Optionally, the first storage circuit includes:

[0014] A fourth transistor and a first capacitor; a first end of the fourth transistor serves as the first end of the first storage circuit, a second end of the fourth transistor is connected to one end of the first capacitor, a third end of the fourth transistor inputs a first control signal, and the other end of the first capacitor is grounded.

[0015] Optionally, the second storage circuit includes:

[0016] The fifth transistor and the second capacitor; the first end of the fifth transistor serves as the first end of the second storage circuit, the second end of the fifth transistor is connected to one end of the second capacitor, the third end of the fifth transistor inputs a second control signal, and the other end of the second capacitor is grounded.

[0017] Optionally, the signal output circuit includes:

[0018] A second amplification transistor and a sixth transistor; the gate of the second amplification transistor serves as the input end of the signal output circuit, the drain of the second amplification transistor is connected to the power supply end of the global exposure pixel structure, the source of the second amplification transistor is connected to the first end of the sixth transistor, the second end of the sixth transistor is grounded, and the third end of the sixth transistor inputs a selection signal.

[0019] Optionally, during the exposure time, the reset control signal is at a high level, the transfer control signal, the pre-charge control signal, the first control signal, the second control signal, and the selection signal are all at a low level, and the voltage of the preset power supply remains high; during the first stage of the frame header time, the reset control signal is at a high level, and during other stages of the frame header time, the reset control signal is at a low level; during the fourth stage of the frame header time, the transfer control signal is at a high level, and during other stages of the frame header time, the transfer control signal is at a low level; during all stages of the frame header time, the pre-charge control signal remains at a high level; during the sixth stage of the frame header time, the first control signal is at a low level, and during other stages of the frame header time, the first control signal is at a high level; during the first and second stages of the frame header time, the second control signal is at a high level, and during other stages of the frame header time, the second control signal is at a low level; during all stages of the frame header time, the selection signal remains at a low level; during all stages of the frame header time, the voltage of the preset power supply remains high; during the readout time, the reset control signal and the selection signal are at a high level, the transfer control signal and the pre-charge control signal are at a low level, and the voltage of the preset power supply remains low; during the fourth stage of the readout time, the first control signal is at a high level, and during other stages of the readout time, the first control signal is at a low level; during the second stage of the readout time, the second control signal is at a high level, and during other stages of the readout time, the second control signal is at a low level.

[0020] Optionally, during the exposure time, the reset control signal is at a high level, the transfer control signal, the pre-charge control signal, the first control signal, the second control signal, and the selection signal are all at a low level, and the voltage of the preset power supply remains high; during the first stage of the frame header time, the reset control signal is at a high level, and during the other stages of the frame header time, the reset control signal is at a low level; during the fourth stage of the frame header time, the transfer control signal is at a high level, and during the other stages of the frame header time, the transfer control signal is at a low level; during all stages of the frame header time, the pre-charge control signal is at a high level; during the sixth stage of the frame header time, the first control signal is at a low level, and during the other stages of the frame header time, the first control signal is at a high level; during the first and second stages of the frame header time, the second control signal is at a high level, and during the other stages of the frame header time, the second control signal is at a low level; during all stages of the frame header time, the selection signal remains at a low level; during all stages of the frame header time, the voltage of the preset power supply remains high; during the readout time, the reset control signal and the selection signal are at a high level, the transfer control signal is at a low level, and the voltage of the preset power supply remains low; during the first and fifth stages of the readout time, the pre-charge control signal is at a high level, and during the other stages of the readout time, the pre-charge control signal is at a low level; during the seventh stage of the readout time, the first control signal is at a high level, and during the other stages of the readout time, the first control signal is at a low level; during the third stage of the readout time, the second control signal is at a high level, and during the other stages of the readout time, the second control signal is at a low level.

[0021] To solve the above technical problems, the present application also provides an image sensor, including the global exposure pixel structure as described above.

[0022] The global exposure pixel structure provided by the present application includes: a signal generation circuit, a first storage circuit, a second storage circuit, and a signal output circuit; a first end of the first storage circuit is connected to an output end of the signal generation circuit, and a second end of the first storage circuit is grounded; a first end of the second storage circuit is connected to the output end of the signal generation circuit, and a second end of the second storage circuit is grounded; an input end of the signal output circuit is connected to the output end of the signal generation circuit; the signal generation circuit includes a first amplification transistor; a source electrode of the first amplification transistor serves as the output end of the signal generation circuit, a gate electrode of the first amplification transistor is connected to a floating diffusion node, and a drain electrode of the first amplification transistor is connected to a power supply end of the global exposure pixel structure; the signal generation circuit is configured to generate a reset voltage and a signal voltage; the first storage circuit is configured to store the signal voltage; the second storage circuit is configured to store the reset voltage; the signal output circuit is configured to output the reset voltage stored in the second storage circuit and the signal voltage stored in the first storage circuit.

[0023] It can be seen that in the global exposure pixel structure provided by the present application, the signal generation circuit generates a reset voltage and a signal voltage. The signal voltage is stored through the first storage circuit, a first end of the first storage circuit is connected to the output end of the signal generation circuit, and a second end of the first storage circuit is grounded. The reset voltage is stored through the second storage circuit, a first end of the second storage circuit is connected to the output end of the signal generation circuit, and a second end of the second storage circuit is grounded. The reset voltage stored in the second storage circuit and the signal voltage stored in the first storage circuit are output through the signal output circuit, and an input end of the signal output circuit is connected to the output end of the signal generation circuit. When the capacitance value of the capacitor in the first storage circuit is equal to the capacitance value of the capacitor in the second storage circuit, the effective voltage Veff output by the global exposure pixel structure is approximately Vrst - Vsig. Compared with the traditional solution, the global exposure pixel structure provided by the present application can double the output effective voltage without adding MOS transistors, effectively improving the sensitivity of the global exposure pixel structure, thereby improving the signal-to-noise ratio.

[0024] The image sensor provided by the present application also has the above technical effects. Description of the Drawings

[0025] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following will briefly introduce the drawings required for the prior art and the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0026] Figure 1Schematic diagram of an existing pixel;

[0027] Figure 2 Schematic diagram of another existing pixel;

[0028] Figure 3 Schematic diagram of a global exposure pixel structure provided by an embodiment of the present application;

[0029] Figure 4 Schematic diagram of a specific global exposure pixel structure provided by an embodiment of the present application;

[0030] Figure 5 Timing diagram provided by an embodiment of the present application;

[0031] Figure 6 Another timing diagram provided by an embodiment of the present application. Detailed implementation manners

[0032] The object of the present application is to provide a global exposure pixel structure and an image sensor, which can increase the amplitude of the effective voltage without increasing the number of devices in the pixel.

[0033] To make the objects, technical solutions, and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are some, but not all, of the embodiments of the present application. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present application without creative efforts shall fall within the protection scope of the present application.

[0034] Please refer to Figure 3 , Figure 3 Schematic diagram of a global exposure pixel structure provided by an embodiment of the present application. Referring to Figure 3 shown, the global exposure pixel structure includes:

[0035] A signal generation circuit 10, a first storage circuit 20, a second storage circuit 30, and a signal output circuit 40; a first end of the first storage circuit 20 is connected to an output end of the signal generation circuit 10, and a second end of the first storage circuit 20 is grounded; a first end of the second storage circuit 30 is connected to the output end of the signal generation circuit 10, and a second end of the second storage circuit 30 is grounded; an input end of the signal output circuit 40 is connected to the output end of the signal generation circuit 10; the signal generation circuit 10 includes a first amplification transistor M11; a source electrode of the first amplification transistor M11 serves as the output end of the signal generation circuit 10, a gate electrode of the first amplification transistor M11 is connected to a floating diffusion node, and a drain electrode of the first amplification transistor M11 is connected to a power supply end of the global exposure pixel structure;

[0036] The signal generation circuit 10 is configured to generate a reset voltage and a signal voltage;

[0037] The first storage circuit 20 is configured to store the signal voltage;

[0038] The second storage circuit 30 is configured to store the reset voltage;

[0039] The signal output circuit 40 is configured to output the reset voltage stored in the second storage circuit 30 and the signal voltage stored in the first storage circuit 20.

[0040] The signal generation circuit 10 is configured to generate a reset voltage and a signal voltage. The first storage circuit 20 and the second storage circuit 30 are respectively configured to store the signal voltage and the reset voltage. The signal output circuit 40 is configured to output the signal voltage stored in the first storage circuit 20 and the reset voltage stored in the second storage circuit 30. Among them, the signal generation circuit 10 includes a first amplification transistor M11. The first amplification transistor M11 is configured to amplify the voltage of the floating diffusion node in the signal generation circuit 10 and then output it. The gate of the first amplification transistor M11 is connected to the floating diffusion node, the source of the first amplification transistor M11 serves as the output terminal of the signal generation circuit 10, and the drain of the first amplification transistor M11 is connected to the power supply terminal of the global exposure pixel structure.

[0041] Reference Figure 4 As shown, in some embodiments, the signal generation circuit 10 further includes:

[0042] A photosensitive diode, a first transistor M1, a second transistor M2, and a third transistor M3; the anode of the photosensitive diode is grounded, the cathode of the photosensitive diode is connected to the second terminal of the first transistor M1, the first terminal of the first transistor M1 is connected to the floating diffusion node, the third terminal of the first transistor M1 inputs a transmission control signal TX, the first terminal of the second transistor M2 is connected to the voltage of a preset power supply, the second terminal of the second transistor M2 is connected to the floating diffusion node, the third terminal of the second transistor M2 inputs a reset control signal RST, the first terminal of the third transistor M3 is connected to the source of the first amplification transistor M11, the second terminal of the third transistor M3 is grounded, and the third terminal of the third transistor M3 inputs a pre-charge control signal PC.

[0043] The photosensitive diode is configured to sense light and generate charges. The first transistor M1 is configured to transfer charges to the floating diffusion node. The second transistor M2 is configured to reset the global exposure pixel structure. The third transistor M3 is configured to provide a bias current for the first amplification transistor M11.

[0044] Reference Figure 4As shown, in some embodiments, the first storage circuit 20 includes:

[0045] A fourth transistor M4 and a first capacitor C1; a first end of the fourth transistor M4 serves as a first end of the first storage circuit 20, a second end of the fourth transistor M4 is connected to one end of the first capacitor C1, a third end of the fourth transistor M4 receives a first control signal S1, and the other end of the first capacitor C1 is grounded.

[0046] Reference Figure 4 As shown, in some embodiments, the second storage circuit 30 includes:

[0047] A fifth transistor M5 and a second capacitor C2; a first end of the fifth transistor M5 serves as a first end of the second storage circuit 30, a second end of the fifth transistor M5 is connected to one end of the second capacitor C2, a third end of the fifth transistor M5 receives a second control signal S2, and the other end of the second capacitor C2 is grounded.

[0048] Reference Figure 4 As shown, in some embodiments, the signal output circuit 40 includes:

[0049] A second amplification transistor M12 and a sixth transistor M6; a gate of the second amplification transistor M12 serves as an input end of the signal output circuit 40, a drain of the second amplification transistor M12 is connected to a power supply end VDD_PIXEL of the global exposure pixel structure, a source of the second amplification transistor M12 is connected to a first end of the sixth transistor M6, a second end of the sixth transistor M6 is grounded, and a third end of the sixth transistor M6 receives a selection signal SEL.

[0050] The first transistor M1 to the sixth transistor M6 can all be NMOS transistors. The first ends of the first transistor M1 to the sixth transistor M6 are the drains of the NMOS transistors, the second ends of the first transistor M1 to the sixth transistor M6 are the sources of the NMOS transistors, and the third ends of the first transistor M1 to the sixth transistor M6 are the gates of the NMOS transistors.

[0051] Reference Figure 5As shown, in some embodiments, during the exposure time, the reset control signal RST is at a high level, and the transfer control signal TX, the precharge control signal PC, the first control signal S1, the second control signal S2, and the selection signal SEL are all at a low level, and the voltage of the preset power supply VDD_RST is continuously set high; during the first stage of the frame overhead time, the reset control signal RST is at a high level, and during other stages of the frame overhead time, the reset control signal RST is at a low level; during the fourth stage of the frame overhead time, the transfer control signal TX is at a high level, and during other stages of the frame overhead time, the transfer control signal TX is at a low level; during each stage of the frame overhead time, the precharge control signal PC is continuously at a high level; during the sixth stage of the frame overhead time, the first control signal S1 is at a low level, and during other stages of the frame overhead time, the first control signal S1 is at a high level; during the first and second stages of the frame overhead time, the second control signal S2 is at a high level, and during other stages of the frame overhead time, the second control signal S2 is at a low level; during each stage of the frame overhead time, the selection signal SEL is continuously at a low level; during each stage of the frame overhead time, the voltage of the preset power supply VDD_RST is continuously set high; during the readout time, the reset control signal RST and the selection signal SEL are at a high level, the transfer control signal TX and the precharge control signal PC are at a low level, and the voltage of the preset power supply VDD_RST is continuously set low; during the fourth stage of the readout time, the first control signal S1 is at a high level, and during other stages of the readout time, the first control signal S1 is at a low level; during the second stage of the readout time, the second control signal S2 is at a high level, and during other stages of the readout time, the second control signal S2 is at a low level.

[0052] The English for frame overhead time is Frame overhead time, abbreviated as FOT. The frame overhead time is a time state between exposure and readout. This period of time is used to store the exposed signals on the storage nodes of the pixels at the same time, and then read out the stored signals during the readout time.

[0053] The above timing provided by this embodiment is simple and more convenient to implement.

[0054] Based on Figure 5 the timing shown, Figure 4 the working principle of the global exposure pixel structure shown is as follows:

[0055] Figure 5Among them, the time from t0 to t1 is the exposure time T_exp, the time from t1 to t7 is the frame header time FOT, and the time from t7 to t12 is the readout time T_rd. The time from t1 to t2 is the first stage of the frame header time, the time from t2 to t3 is the second stage of the frame header time, the time from t3 to t4 is the third stage of the frame header time, the time from t4 to t5 is the fourth stage of the frame header time, the time from t5 to t6 is the fifth stage of the frame header time, and the time from t6 to t7 is the sixth stage of the frame header time. The time from t7 to t8 is the first stage of the readout time, the time from t8 to t9 is the second stage of the readout time, the time from t9 to t10 is the third stage of the readout time, the time from t10 to t11 is the fourth stage of the readout time, and the time from t11 to t12 is the fifth stage of the readout time. VSF1 represents the output node of the first amplifying transistor M11, and VSF2 represents the output node of the second amplifying transistor M12.

[0056] Before t0, both the transmission control signal TX and the reset control signal RST are at high level, and the global exposure pixel structure is in the reset state. At t0, the transmission control signal TX becomes low level, and the global exposure pixel structure starts to expose. At t1, the pre-charge control signal PC, the first control signal S1, and the second control signal S2 change from low level to high level, and start to enter the FOT time. At t2, the reset control signal RST changes from high level to low level. At t3, the second control signal S2 changes from high level to low level, and samples the reset voltage Vrst output from the source of the first amplifying transistor M11 onto the second capacitor C2. At t4, the transmission control signal TX changes from low level to high level, and starts to transfer the charge accumulated by the photosensitive diode PD to the floating diffusion node FD. At t5, the transmission control signal TX changes from high level to low level, and the charge transfer time ends. At t6, the first control signal S1 changes from high level to low level, and samples the signal voltage Vsig output from the first amplifying transistor M11 of the global exposure pixel structure onto the first capacitor C1. The voltage of the preset power supply VDD_RST remains high from t0 to t7.

[0057] Starting from time t7, the readout time of the global exposure pixel structure begins. At this time, the pre-charge control signal PC changes from high level to low level, the voltage of the preset power supply VDD_RST changes from high to low, the reset control signal RST and the select signal change from low level to high level, pulling the floating diffusion node FD to the low voltage of the voltage of the preset power supply VDD_RST, and the first amplifying transistor M11 is turned off. At time t8, the second control signal S2 changes from low level to high level, the fifth transistor M5 conducts, and the second capacitor C2 is connected to the VSF1 node at the source of the first amplifying transistor M11. Assuming the parasitic capacitance of the VSF1 node is Cp, the voltage of the VSF1 node becomes Vrst*C2 / (C2 + Cp) at this time. The subsequent circuit of the global exposure pixel structure samples the voltage output at the output terminal VOUT of the global exposure pixel structure from time t8 to time t9. At this time, the output voltage is VOUT1 = Vrst*C2 / (C2 + Cp) - V gs,M12 -V ds,M6 . Among them, V gs,M12 is the voltage difference between the gate and the source of the second amplifying transistor M12, and V ds,M6 is the voltage difference between the drain and the source of the sixth transistor M6. At time t9, the second control signal S2 changes from high level to low level, and the fifth transistor M5 is turned off. At time t10, the first control signal S1 changes from low level to high level, the fourth transistor M4 conducts, and the voltage of the VSF1 node becomes (Cp*Vrst*C2 / (C2 + Cp) + C1*Vsig) / (C1 + Cp). From time t10 to time t11, the subsequent circuit of the global exposure pixel structure samples the voltage output at the output terminal VOUT node for the second time. At this time, the output voltage is VOUT2 = (Cp*Vrst*C2 / (C2 + Cp) + C1*Vsig) / (C1 + Cp) - V gs,M12 -V ds,M6 . At time t11, the first control signal S1 changes from high level to low level, and the fourth transistor M4 is turned off. At time t12, the select signal changes from high level to low level, the voltage of the preset power supply VDD_RST changes from low to high, the transmission control signal TX changes from low level to high level, and the read stage ends. Finally, the effective voltage signal obtained by the subsequent circuit of the global exposure pixel structure is:

[0058] Veff = VOUT1 - VOUT2

[0059] = Vrst*C2 / (C2 + Cp) - (Cp*Vrst*C2 / (C2 + Cp) + C1*Vsig) / (C1 + Cp)

[0060] = Vrst / [(1 + Cp / C2)*(1 + Cp / C1)] - Vsig / (1 + Cp / C1).

[0061] When C1 = C2 = C, Veff = Vrst / (1 + Cp / C) 2 -Vsig / (1 + Cp / C). Since the parasitic capacitance of the VSF1 node is usually much smaller than the capacitance values C of the first capacitor C1 and the second capacitor C2, thus, Veff is approximately Vrst - Vsig. Compared with the traditional 8T structure, the global exposure pixel structure provided in this embodiment doubles the effective output voltage without adding devices, effectively improving the sensitivity of the global exposure pixel structure, thereby improving the signal-to-noise ratio.

[0062] Reference Figure 6 As shown, in some embodiments, during the exposure time, the reset control signal RST is at a high level, the transfer control signal TX, the pre-charge control signal PC, the first control signal S1, the second control signal S2, and the selection signal SEL are all at low levels, and the voltage of the preset power supply VDD_RST is continuously set high; in the first stage of the frame header time, the reset control signal RST is at a high level, and in other stages of the frame header time, the reset control signal RST is at a low level; in the fourth stage of the frame header time, the transfer control signal TX is at a high level, and in other stages of the frame header time, the transfer control signal TX is at a low level; in all stages of the frame header time, the pre-charge control signal PC is at a high level; in the sixth stage of the frame header time, the first control signal S1 is at a low level, and in other stages of the frame header time, the first control signal S1 is at a high level; in the first and second stages of the frame header time, the second control signal S2 is at a high level, and in other stages of the frame header time, the second control signal S2 is at a low level; in all stages of the frame header time, the selection signal SEL is continuously at a low level; in all stages of the frame header time, the voltage of the preset power supply VDD_RST is continuously set high; during the readout time, the reset control signal RST and the selection signal SEL are at high levels, the transfer control signal TX is at a low level, and the voltage of the preset power supply VDD_RST is continuously set low; in the first and fifth stages of the readout time, the pre-charge control signal PC is at a high level, and in other stages of the readout time, the pre-charge control signal PC is at a low level; in the seventh stage of the readout time, the first control signal S1 is at a high level, and in other stages of the readout time, the first control signal S1 is at a low level; in the third stage of the readout time, the second control signal S2 is at a high level, and in other stages of the readout time, the second control signal S2 is at a low level.

[0063] The timing provided in this embodiment can increase the amplitude of the effective voltage output and can improve the uniformity of the effective voltage output among global exposure pixel structures.

[0064] Based on Figure 6 the shown timingFigure 4 The working principle of the global exposure pixel structure shown is as follows:

[0065] Figure 5 Among them, the time from t0 to t1 is the exposure time T_exp, the time from t1 to t7 is the frame header time FOT, and the time from t7 to t15 is the readout time T_rd. The time from t1 to t2 is the first stage of the frame header time, the time from t2 to t3 is the second stage of the frame header time, the time from t3 to t4 is the third stage of the frame header time, the time from t4 to t5 is the fourth stage of the frame header time, the time from t5 to t6 is the fifth stage of the frame header time, and the time from t6 to t7 is the sixth stage of the frame header time. The time from t7 to t8 is the first stage of the readout time, the time from t8 to t9 is the second stage of the readout time, the time from t9 to t10 is the third stage of the readout time, the time from t10 to t11 is the fourth stage of the readout time, the time from t11 to t12 is the fifth stage of the readout time, the time from t12 to t13 is the sixth stage of the readout time, the time from t13 to t14 is the seventh stage of the readout time, and the time from t14 to t15 is the eighth stage of the readout time.

[0066] Before t0, both the transmission control signal TX and the reset control RST signal are at high level, and the global exposure pixel structure is in the reset state. At t0, the transmission control signal TX becomes low level, and the global exposure pixel structure starts to expose. At t1, the precharge control signal PC, the first control signal S1, and the second control signal S2 change from low level to high level, and the FOT time starts. At t2, the reset control signal RST changes from high level to low level. At t3, the second control signal S2 changes from high level to low level, and samples the reset voltage Vrst output from the source of the first amplification transistor M11 onto the second capacitor C2. At t4, the transmission control signal TX changes from low level to high level, and starts to transfer the charge accumulated by the photosensitive diode PD to the floating diffusion node FD. At t5, the transmission control signal TX changes from high level to low level, and the charge transfer time ends. At t6, the first control signal S1 changes from high level to low level, and samples the signal voltage Vsig output from the first amplification transistor M11 of the global exposure pixel structure onto the first capacitor C1. The voltage of the preset power supply VDD_RST remains high from t0 to t7.

[0067] Starting from time t7, it enters the readout time of the global exposure pixel structure. At time t8, the pre-charge control signal changes from high level to low level, and the VSF1 node is pulled to the ground voltage by the third transistor M3. From time t9 to time t10, the second control signal S2 becomes high level, and the voltage of the VSF1 node is Vrst*C2 / (C2+Cp). The voltage output by the sampling output terminal VOUT of the subsequent circuit of the global exposure pixel structure is output, and the output voltage VOUT1 = Vrst*C2 / (C2+Cp) - V gs,M12 -V ds,M6 . The pre-charge control signal PC changes from low level to high level at time t11, and the pre-charge control signal PC changes from high level to low level at time t12, pulling the voltage of the VSF1 node to the ground voltage again.

[0068] From time t13 to time t14, the first control signal S1 is high level, and the voltage of the VSF1 node is Vsig*C2 / (C2+Cp). The output terminal outputs a voltage VOUT2 = Vsig*C1 / (C1+Cp) - V gs,M12 -V ds,M6 . Thus, the effective voltage signal finally output by the global exposure pixel structure is:

[0069] Veff2 = VOUT1 - VOUT2 = Vrst*C2 / (C2+Cp) - Vsig*C1 / (C1+Cp).

[0070] When C1 = C2 = C, Veff2 = (Vrst - Vsig) / (1 + Cp / C), and Veff2 > Veff. That is Figure 6 The effective voltage finally output by the global exposure pixel structure under the shown timing control is greater than Figure 5 The effective voltage finally output by the global exposure pixel structure under the shown timing, that is Figure 6 The pixel sensitivity under the shown timing control is greater than Figure 5 The pixel sensitivity under the shown timing control, and the larger Cp / C is, the more obvious the improvement of the pixel sensitivity is. In addition, from the formula Veff2 = (Vrst - Vsig) / (1 + Cp / C), it can be seen that Veff2 is only related to the difference between Vrst and Vsig, and has nothing to do with the absolute voltage values of Vrst and Vsig. Therefore, the situation of inconsistent response between pixels can be avoided, and the uniformity of the image is improved.

[0071] In summary, for the global exposure pixel structure provided by the present application, the signal generation circuit generates a reset voltage and a signal voltage. The first storage circuit stores the signal voltage, with the first end of the first storage circuit connected to the output end of the signal generation circuit and the second end of the first storage circuit grounded. The second storage circuit stores the reset voltage, with the first end of the second storage circuit connected to the output end of the signal generation circuit and the second end of the second storage circuit grounded. The signal output circuit outputs the reset voltage stored in the second storage circuit and the signal voltage stored in the first storage circuit, with the input end of the signal output circuit connected to the output end of the signal generation circuit. When the capacitance value of the capacitor in the first storage circuit is equal to the capacitance value of the capacitor in the second storage circuit, the effective voltage Veff output by the global exposure pixel structure is approximately Vrst - Vsig. Compared with the traditional solution, the global exposure pixel structure provided by the present application can double the output effective voltage without adding MOS transistors, effectively improving the sensitivity of the global exposure pixel structure and thus increasing the signal-to-noise ratio.

[0072] The present application also provides an image sensor, which includes the global exposure pixel structure described in the above embodiments. For the image sensor provided by the present application, reference can be made to the introduction of the global exposure pixel structure in the above embodiments, which will not be elaborated herein.

[0073] Due to the complex situation and inability to list and elaborate one by one, those skilled in the art should be able to realize that there can be multiple examples under the basic principle of the embodiments provided by the present application in combination with the actual situation. Without sufficient creative labor, they should all fall within the scope of the present application.

[0074] The various embodiments in the specification are described in a progressive manner. Each embodiment focuses on the differences from other embodiments, and the same or similar parts among the embodiments can be referred to each other.

[0075] The above provides a detailed introduction to the global exposure pixel structure and the image sensor provided by the present application. Specific examples are used herein to elaborate on the principle and implementation manner of the present application. The description of the above embodiments is only used to help understand the method and its core idea of the present application. It should be noted that for those of ordinary skill in the art in this technical field, without departing from the principle of the present application, several improvements and modifications can be made to the present application, and these improvements and modifications also fall within the protection scope of the claims of the present application.

[0076] It should also be noted that in this specification, relational terms such as first and second are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the term "comprising", "including" or any other variant thereof is intended to cover non-exclusive inclusion, such that a process, method, article or device comprising a series of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such process, method, article or device. Without further limitation, an element defined by the statement "comprising an..." does not exclude the presence of additional identical elements in the process, method, article or device comprising the element.

Claims

1. A global exposure pixel structure, characterized in that, Including: A signal generation circuit, a first storage circuit, a second storage circuit, and a signal output circuit; A first end of the first storage circuit is connected to an output end of the signal generation circuit, and a second end of the first storage circuit is grounded; a first end of the second storage circuit is connected to the output end of the signal generation circuit, and a second end of the second storage circuit is grounded; an input end of the signal output circuit is connected to the output end of the signal generation circuit; the signal generation circuit includes a first amplification transistor; a source electrode of the first amplification transistor serves as the output end of the signal generation circuit, a gate electrode of the first amplification transistor is connected to a floating diffusion node, and a drain electrode of the first amplification transistor is connected to a power supply end of a global exposure pixel structure; The signal generation circuit is configured to generate a reset voltage and a signal voltage; The first storage circuit is configured to store the signal voltage; The second storage circuit is configured to store the reset voltage; The signal output circuit is configured to output the reset voltage stored in the second storage circuit and the signal voltage stored in the first storage circuit.

2. The global exposure pixel structure according to claim 1, wherein The signal generation circuit further includes: A photosensitive diode, a first transistor, a second transistor, and a third transistor; an anode of the photosensitive diode is grounded, a cathode of the photosensitive diode is connected to a second end of the first transistor, a first end of the first transistor is connected to the floating diffusion node, a third end of the first transistor inputs a transmission control signal, a first end of the second transistor is connected to a voltage of a preset power supply, a second end of the second transistor is connected to the floating diffusion node, a third end of the second transistor inputs a reset control signal, a first end of the third transistor is connected to the source electrode of the first amplification transistor, a second end of the third transistor is grounded, and a third end of the third transistor inputs a pre-charge control signal.

3. The global exposure pixel structure according to claim 2, wherein, The first storage circuit includes: A fourth transistor and a first capacitor; a first end of the fourth transistor serves as the first end of the first storage circuit, a second end of the fourth transistor is connected to one end of the first capacitor, a third end of the fourth transistor inputs a first control signal, and the other end of the first capacitor is grounded.

4. The global exposure pixel structure according to claim 3, characterized in that The second storage circuit includes: A fifth transistor and a second capacitor; a first end of the fifth transistor serves as the first end of the second storage circuit, a second end of the fifth transistor is connected to one end of the second capacitor, a third end of the fifth transistor inputs a second control signal, and the other end of the second capacitor is grounded.

5. The global exposure pixel structure according to claim 4, wherein The signal output circuit includes: A second amplification transistor and a sixth transistor; a gate electrode of the second amplification transistor serves as the input end of the signal output circuit, a drain electrode of the second amplification transistor is connected to the power supply end of the global exposure pixel structure, a source electrode of the second amplification transistor is connected to a first end of the sixth transistor, a second end of the sixth transistor is grounded, and a third end of the sixth transistor inputs a selection signal.

6. The global exposure pixel structure according to any one of claims 1 to 5, characterized in that, During the exposure time, the reset control signal is at a high level, the transfer control signal, the precharge control signal, the first control signal, the second control signal, and the selection signal are all at a low level, and the voltage of the preset power supply remains high; during the first stage of the frame header time, the reset control signal is at a high level, and during other stages of the frame header time, the reset control signal is at a low level; during the fourth stage of the frame header time, the transfer control signal is at a high level, and during other stages of the frame header time, the transfer control signal is at a low level; during all stages of the frame header time, the precharge control signal remains at a high level; during the sixth stage of the frame header time, the first control signal is at a low level, and during other stages of the frame header time, the first control signal is at a high level; during the first and second stages of the frame header time, the second control signal is at a high level, and during other stages of the frame header time, the second control signal is at a low level; during all stages of the frame header time, the selection signal remains at a low level; during all stages of the frame header time, the voltage of the preset power supply remains high; during the readout time, the reset control signal and the selection signal are at a high level, the transfer control signal and the precharge control signal are at a low level, and the voltage of the preset power supply remains low; during the fourth stage of the readout time, the first control signal is at a high level, and during other stages of the readout time, the first control signal is at a low level; during the second stage of the readout time, the second control signal is at a high level, and during other stages of the readout time, the second control signal is at a low level.

7. The global exposure pixel structure according to any one of claims 1 to 5, characterized in that, During the exposure time, the reset control signal is at a high level, the transfer control signal, the pre-charge control signal, the first control signal, the second control signal, and the selection signal are all at low levels, and the voltage of the preset power supply is continuously set high; during the first stage of the frame header time, the reset control signal is at a high level, and during other stages of the frame header time, the reset control signal is at a low level; during the fourth stage of the frame header time, the transfer control signal is at a high level, and during other stages of the frame header time, the transfer control signal is at a low level; during each stage of the frame header time, the pre-charge control signal is at a high level; during the sixth stage of the frame header time, the first control signal is at a low level, and during other stages of the frame header time, the first control signal is at a high level; during the first and second stages of the frame header time, the second control signal is at a high level, and during other stages of the frame header time, the second control signal is at a low level; during each stage of the frame header time, the selection signal is continuously at a low level; during each stage of the frame header time, the voltage of the preset power supply is continuously set high; during the readout time, the reset control signal and the selection signal are at high levels, the transfer control signal is at a low level, and the voltage of the preset power supply is continuously set low; during the first and fifth stages of the readout time, the pre-charge control signal is at a high level, and during other stages of the readout time, the pre-charge control signal is at a low level; during the seventh stage of the readout time, the first control signal is at a high level, and during other stages of the readout time, the first control signal is at a low level; during the third stage of the readout time, the second control signal is at a high level, and during other stages of the readout time, the second control signal is at a low level.

8. An image sensor, characterized in that, Comprising the global exposure pixel structure according to any one of claims 1 to 7.

Images