Pixel unit and image sensor
By designing signal generation, sampling and storage circuits and output circuits in the CMOS image sensor and controlling the signal path, the problem of signal attenuation in the global exposure mode is solved and the signal amplitude is improved.
Patent Information
- Application Number
- CN202311845476.0
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2023-12-28
- Publication Date
- 2025-07-01
AI Technical Summary
In the global exposure mode, the final output signal of the pixel unit is attenuated due to capacitance scaling.
By using a signal generation circuit, a signal sampling and storage circuit and a signal output circuit, the first switching circuit, the second switching circuit and the third switching circuit are controlled to turn on and off, and the exposure signal and the reset signal are output through different paths respectively to avoid the signal being scaled by capacitance.
Ensure that the final output signal is not attenuated, the signal amplitude is larger and the effect is better.
Smart Images
Figure CN120238769A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the technical field of image sensors, and particularly to a pixel unit and an image sensor. Background Art
[0002] CMOS image sensors are divided into a rolling shutter exposure mode and a global exposure mode. For the global exposure mode, existing pixel units store the exposure signal and the reset signal through two capacitors. However, the final output signal of the existing pixel unit will be scaled by the ratio of the two capacitors, and the amplification factor is C1 / (C1 + C2). C1 is the capacitance value of one capacitor, and C2 is the capacitance value of the other capacitor. As a result, the final output signal has a certain degree of attenuation. Therefore, how to prevent the final output signal from being attenuated has become a technical problem that needs to be solved urgently by those skilled in the art. Summary of the Invention
[0003] The purpose of this application is to provide a pixel unit and an image sensor, which do not have a coefficient with an amplification factor less than 1, and the final output signal will not be attenuated.
[0004] To solve the above technical problems, this application provides a pixel unit, including:
[0005] A signal generation circuit for generating a reset signal and an exposure signal;
[0006] A signal sampling and storage circuit for sampling and storing the reset signal and the exposure signal; wherein, the signal sampling and storage circuit includes: a first switch circuit, a second switch circuit, a third switch circuit, a first capacitor, and a second capacitor; a first end of the first switch circuit is connected to the signal generation circuit, a second end of the first switch circuit is connected to a first end of the first capacitor, and a second end of the first capacitor is grounded; a first end of the second switch circuit is connected to a first end of the second capacitor, a second end of the second switch circuit is connected to the signal output circuit, and the other end of the second capacitor is grounded; a first end of the third switch circuit is connected to the second end of the first switch circuit, and a second end of the third switch circuit is connected to the second end of the second switch circuit;
[0007] The signal output circuit for outputting the reset signal and the exposure signal stored by the signal sampling and storage circuit.
[0008] Optionally, the first switch circuit includes:
[0009] A first transistor; a first end of the first transistor serves as the first end of the first switch circuit, a second end of the first transistor serves as the second end of the first switch circuit, and a third end of the first transistor inputs a first control signal.
[0010] Optionally, the second switching circuit includes:
[0011] A second transistor; a first end of the second transistor serves as a first end of the first switching circuit, a second end of the first transistor serves as a second end of the second switching circuit, and a third end of the second transistor receives a second control signal.
[0012] Optionally, the third switching circuit includes:
[0013] A third transistor; a first end of the third transistor serves as a first end of the third switching circuit, a second end of the third transistor serves as a second end of the third switching circuit, and a third end of the third transistor receives a third control signal.
[0014] Optionally, the third switching circuit is a wire.
[0015] Optionally, the signal generation circuit includes:
[0016] A photodiode, a fourth transistor, a fifth transistor, and a sixth transistor; an anode of the photodiode is grounded, a cathode of the photodiode is connected to a first end of the fourth transistor, a second end of the fourth transistor is connected to a floating diffusion node, a third end of the fourth transistor receives a transfer control signal, a first end of the fifth transistor is connected to the floating diffusion node, a second end of the fifth transistor is connected to a first potential, a third end of the fifth transistor receives a reset control signal, a first end of the sixth transistor is connected to the signal sampling and storage circuit, a second end of the sixth transistor is connected to a second potential, and a third end of the sixth transistor is connected to the floating diffusion node.
[0017] Optionally, the signal generation circuit further includes:
[0018] A seventh transistor; a first end of the seventh transistor is grounded, a second end of the seventh transistor is connected to a first end of the sixth transistor, and a third end of the seventh transistor receives a bias signal.
[0019] Optionally, the signal output circuit includes:
[0020] An eighth transistor and a ninth transistor; a first end of the eighth transistor is connected to a second end of the ninth transistor, a second end of the eighth transistor is connected to a second potential, a third end of the eighth transistor is connected to the signal sampling and storage circuit, a first end of the ninth transistor is grounded and serves as an output end of the pixel unit, and a third end of the ninth transistor receives a selection control signal.
[0021] Optionally, the first capacitor and the second capacitor are MIM capacitors or MOS capacitors.
[0022] To solve the above technical problems, the present application also provides an image sensor, including the pixel unit as described above.
[0023] The pixel unit provided by the present application includes: a signal generation circuit for generating a reset signal and an exposure signal; a signal sampling and storage circuit for sampling and storing the reset signal and the exposure signal; wherein, the signal sampling and storage circuit includes: a first switch circuit, a second switch circuit, a third switch circuit, a first capacitor and a second capacitor; a first end of the first switch circuit is connected to the signal generation circuit, a second end of the first switch circuit is connected to a first end of the first capacitor, and a second end of the first capacitor is grounded; a first end of the second switch circuit is connected to a first end of the second capacitor, a second end of the second switch circuit is connected to the signal output circuit, and the other end of the second capacitor is grounded; a first end of the third switch circuit is connected to the second end of the first switch circuit, and a second end of the third switch circuit is connected to the second end of the second switch circuit; the signal output circuit is configured to output the reset signal and the exposure signal stored by the signal sampling and storage circuit.
[0024] It can be seen that for the pixel unit provided by the present application, by controlling the conduction and cutoff of the first switch circuit, the second switch circuit, and the third switch circuit, it is possible to store the exposure signal by the first capacitor, store the reset signal by the second capacitor, and realize that the exposure signal stored by the first capacitor and the reset signal stored by the second capacitor are output to the signal output circuit through different paths. When the exposure signal is output to the signal output circuit, it will not pass through the second capacitor, and when the reset signal is output to the signal output circuit, it will not pass through the first capacitor. As a result, the finally output signal will not be attenuated. Compared with the existing solution, the signal output by the pixel unit provided by the present application is larger and the effect is better.
[0025] The image sensor provided by the present application also has the above technical effects. BRIEF DESCRIPTION OF THE DRAWINGS
[0026] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following will briefly introduce the drawings required in the prior art and the embodiments. Obviously, the drawings in the following description are only some embodiments of the present application. For those of ordinary skill in the art, without creative efforts, other drawings can be obtained based on these drawings.
[0027] Figure 1 Schematic diagram of the first pixel unit provided by the embodiment of the present application;
[0028] Figure 2 Schematic diagram of the second pixel unit provided by the embodiment of the present application;
[0029] Figure 3 Schematic diagram of the third pixel unit provided by the embodiment of the present application;
[0030] Figure 4 Schematic diagram of the first pixel timing provided by the embodiment of the present application;
[0031] Figure 5 Schematic diagram of the second pixel timing provided by the embodiment of the present application; Detailed implementation manners
[0032] The core of the present application is to provide a pixel unit and an image sensor, where there is no coefficient with a magnification factor less than 1, and the finally output signal will not be attenuated.
[0033] To make the objectives, technical solutions, and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are some, but not all, of the embodiments of the present application. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present application without creative efforts shall fall within the protection scope of the present application.
[0034] Please refer to Figure 1 , Figure 1 Schematic diagram of a pixel unit provided by the embodiment of the present application. Refer to Figure 1 As shown in
[0035] A signal generation circuit 10, configured to generate a reset signal and an exposure signal;
[0036] A signal sampling and storage circuit 20, configured to sample and store the reset signal and the exposure signal; wherein, the signal sampling and storage circuit 20 includes: a first switch circuit 201, a second switch circuit 202, a third switch circuit 203, a first capacitor C1, and a second capacitor C2; a first end of the first switch circuit 201 is connected to the signal generation circuit 10, a second end of the first switch circuit 201 is connected to a first end of the first capacitor C1, and a second end of the first capacitor C1 is grounded; a first end of the second switch circuit 202 is connected to a first end of the second capacitor C2, a second end of the second switch circuit 202 is connected to the signal output circuit 30, and the other end of the second capacitor C2 is grounded; a first end of the third switch circuit 203 is connected to the second end of the first switch circuit 201, and a second end of the third switch circuit 203 is connected to the second end of the second switch circuit 202;
[0037] The signal output circuit 30 is configured to output the reset signal and the exposure signal stored by the signal sampling and storage circuit 20.
[0038] Through the first switch circuit 201, the exposure signal generated by the signal generation circuit 10 can be transmitted and stored in the first capacitor C1. Through the first switch circuit 201, the second switch circuit 202, and the third switch circuit 203, the reset signal generated by the signal generation circuit 10 can be transmitted and stored in the second capacitor C2. Through the third switch circuit 203, the exposure signal stored in the first capacitor C1 can be output to the signal output circuit 30. Through the second switch circuit 202, the reset signal stored in the second capacitor C2 can be output to the signal output circuit 30. Among them, the first capacitor C1 and the second capacitor C2 are high-density capacitors. In some embodiments, the first capacitor C1 and the second capacitor C2 are MIM capacitors or MOS capacitors.
[0039] Reference Figure 2 As shown, in some embodiments, the first switch circuit 201 includes:
[0040] A first transistor M1; the first end of the first transistor M1 serves as the first end of the first switch circuit 201, the second end of the first transistor M1 serves as the second end of the first switch circuit 201, and the third end of the first transistor M1 inputs a first control signal S1.
[0041] The second switch circuit 202 includes:
[0042] A second transistor M2; the first end of the second transistor M2 serves as the first end of the first switch circuit 201, the second end of the first transistor M1 serves as the second end of the second switch circuit 202, and the third end of the second transistor M2 inputs a second control signal S2.
[0043] The third switch circuit 203 includes:
[0044] A third transistor M3; the first end of the third transistor M3 serves as the first end of the third switch circuit 203, the second end of the third transistor M3 serves as the second end of the third switch circuit 203, and the third end of the third transistor M3 inputs a third control signal S3.
[0045] In this embodiment, the third switch circuit 203 is provided with the third transistor M3 to isolate the interference between two nodes.
[0046] Reference Figure 3 As shown, in some other embodiments, the first switch circuit 201 includes:
[0047] The first transistor M1; the first end of the first transistor M1 serves as the first end of the first switch circuit 201, the second end of the first transistor M1 serves as the second end of the first switch circuit 201, and the third end of the first transistor M1 inputs a first control signal S1.
[0048] The second switch circuit 202 includes:
[0049] A second transistor M2; the first end of the second transistor M2 serves as the first end of the first switch circuit 201, the second end of the first transistor M1 serves as the second end of the second switch circuit 202, and the third end of the second transistor M2 inputs a second control signal S2.
[0050] The third switch circuit 203 is a wire.
[0051] In this embodiment, the third switch circuit 203 being a wire can simplify the circuit structure and reduce timing control.
[0052] Reference Figure 2 Or Figure 3 As shown, the signal generation circuit 10 may include:
[0053] A photodiode PD, a fourth transistor M4, a fifth transistor M5, a sixth transistor M6; the anode of the photodiode PD is grounded, the cathode of the photodiode PD is connected to the first end of the fourth transistor M4, the second end of the fourth transistor M4 is connected to a floating diffusion node, the third end of the fourth transistor M4 inputs a transmission control signal TX, the first end of the fifth transistor M5 is connected to the floating diffusion node, the second end of the fifth transistor M5 is connected to a first potential VDD_RST, the third end of the fifth transistor M5 inputs a reset control signal RST, the first end of the sixth transistor M6 is connected to the signal sampling and storage circuit 20, the second end of the sixth transistor M6 is connected to a second potential VDD_PIXEL, and the third end of the sixth transistor M6 is connected to the floating diffusion node.
[0054] In some embodiments, the signal generation circuit 10 further includes:
[0055] A seventh transistor M7; the first end of the seventh transistor M7 is grounded, the second end of the seventh transistor is connected to the first end of the sixth transistor M6, and the third end of the seventh transistor M7 inputs a bias signal VB.
[0056] The signal output circuit 30 may include:
[0057] The eighth transistor M8 and the ninth transistor M9; a first end of the eighth transistor M8 is connected to a second end of the ninth transistor M9, a second end of the eighth transistor M8 is connected to a second potential VDD_PIXEL, a third end of the eighth transistor M8 is connected to the signal sampling and storage circuit 20, a first end of the ninth transistor M9 is grounded and serves as an output end of the pixel unit, and a third end of the ninth transistor M9 inputs a selection control signal SEL.
[0058] The first transistor M1 to the ninth transistor M9 can all be NMOS transistors. The first end of each transistor is the source of the NMOS transistor, the second end of each transistor is the drain of the NMOS transistor, and the third end of each transistor is the gate of the NMOS transistor.
[0059] Figure 4 It is a pixel timing diagram. Among them, at time T1, the pixel unit is in a pixel reset state; at time T2, the pixel unit is in an exposure state; at time T3, the pixel unit samples the reset signal during the transfer time; at time T4, the pixel unit samples the photosensitive signal during the transfer time; at time T5, the pixel unit reads the reset signal during the readout stage; at time T6, the pixel unit reads the photosensitive signal during the readout stage; at time T7, the pixel unit is in a pixel reset state.
[0060] Combined Figure 4 as shown Figure 2 The operating principle of the pixel unit shown is as follows:
[0061] In the pixel reset state, the first potential VDD_RST is at a high value, the reset control signal RST and the transmission control signal TX are at a high level, the photodiode PD is in a reset state, the first control signal S1, the second control signal S2, and the third control signal S3 are at a high level, and the selection control signal SEL is at a low level.
[0062] Entering the exposure state, the reset control signal RST remains at a high level, the transmission control signal TX becomes a low level, so that the fourth transistor M4 is turned off, and the photodiode PD is in an exposure state. After the exposure ends, the bias signal VB rises, and the first control signal S1, the second control signal S2, and the third control signal S3 are at a high level. After the reset control signal RST becomes a low level, the second control signal S2 and the third control signal S3 become low levels, sample the reset state of the pixel unit, and the sampled voltage value is stored on the second capacitor C2. This voltage value is the reset signal called V1. Then the transmission control signal TX becomes a high level, so that the fourth transistor M4 is turned on, and the corresponding charge on the photodiode PD is transferred to the floating diffusion node FD, and the voltage on the first capacitor C1 changes with the floating diffusion node FD. Then the first transistor M1 is turned off, and the corresponding exposure signal is stored on the first capacitor C1. The stored exposure signal is called V2.
[0063] After the exposure ends, the reading stage begins, and the signal reading starts. The second transistor M2 is turned on, and V1 is read through the eighth transistor M8 and the ninth transistor M9. Then the second transistor M2 is turned off, the third transistor M3 is turned on, and V2 is read through the eighth transistor M8 and the ninth transistor M9. Finally, Vo = V1 - V2 is obtained. Vo is the final output signal.
[0064] Figure 5 It is another pixel timing diagram. Similarly, at time T1, the pixel unit is in the pixel reset state; at time T2, the pixel unit is in the exposure state; at time T3, the pixel unit samples the reset signal during the transfer time; at time T4, the pixel unit samples the photosensitive signal during the transfer time; at time T5, the pixel unit reads the reset signal during the readout stage; at time T6, the pixel unit reads the photosensitive signal during the readout stage; at time T7, the pixel unit is in the pixel reset state.
[0065] Combined Figure 5 as shown Figure 3 The operating principle of the pixel unit shown is as follows:
[0066] In the pixel reset state, the first potential VDD_RST is at a high value, the reset control signal RST and the transmission control signal TX are at high levels, the photodiode PD is in the reset state, the first control signal S1 and the second control signal S2 are at high levels, and the selection control signal SEL is at a low level.
[0067] Entering the exposure state, the reset control signal RST remains at a high level, the transmission control signal TX becomes low, turning off the fourth transistor M4, and the photodiode PD is in the exposure state. After the exposure ends, the bias signal VB rises, and the first control signal S1 and the second control signal S2 are at high levels. After the reset control signal RST becomes low, the second control signal S2 becomes low, sampling the reset state of the pixel unit, and the sampled voltage value is stored on the second capacitor C2. This voltage value, which is the reset signal, is called V1. Then the transmission control signal TX becomes high, turning on the fourth transistor M4, and the corresponding charge on the photodiode PD is transferred to the floating diffusion node FD, and the voltage on the first capacitor C1 changes with the floating diffusion node FD. Then the first transistor M1 is turned off, and the corresponding exposure signal is stored on the first capacitor C1. This stored exposure signal is called V2.
[0068] After the exposure ends, the reading stage is entered, and the reading of the signal starts. The second transistor M2 is turned on, and V1 is read through the eighth transistor M8 and the ninth transistor M9. The second transistor M2 is turned off, and V2 is read through the eighth transistor M8 and the ninth transistor M9. Finally, Vo = V1 - V2 is obtained. Vo is the final output signal.
[0069] In summary, for the pixel unit provided in this application, by controlling the conduction and turn-off of the first switch circuit, the second switch circuit, and the third switch circuit, it is possible to store the exposure signal in the first capacitor, store the reset signal in the second capacitor, and output the exposure signal stored in the first capacitor and the reset signal stored in the second capacitor to the signal output circuit through different paths. When the exposure signal is output to the signal output circuit, it will not pass through the second capacitor, and when the reset signal is output to the signal output circuit, it will not pass through the first capacitor. As a result, the final output signal will not be attenuated. Compared with the existing solutions, the signal output by the pixel unit provided in this application is larger and has a better effect.
[0070] This application also provides an image sensor, which includes the pixel unit described in the above embodiments. For the image sensor provided in this application, reference can be made to the introduction of the pixel unit, which will not be elaborated here.
[0071] Because the situation is complex and cannot be listed one by one for elaboration, those skilled in the art should be able to realize that under the basic principle of the embodiments provided in this application, multiple examples can exist in combination with the actual situation. Without sufficient creative labor, they should all fall within the scope of this application.
[0072] The various embodiments in the specification are described in a progressive manner. Each embodiment focuses on the differences from other embodiments. The same or similar parts between the various embodiments can be referred to each other.
[0073] The pixel unit and the image sensor provided in this application have been introduced in detail above. Specific examples are used in this article to elaborate on the principle and implementation manner of this application. The description of the above embodiments is only used to help understand the method and its core idea of this application. It should be noted that for those of ordinary skill in the art in this technical field, without departing from the principle of this application, several improvements and modifications can still be made to this application, and these improvements and modifications also fall within the protection scope of the claims of this application.
[0074] It should also be noted that in this specification, relational terms such as first and second are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the term "comprising", "including" or any other variant thereof is intended to cover non-exclusive inclusion, such that a process, method, article or device comprising a series of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such process, method, article or device. Without further limitation, an element defined by the statement "comprising an..." does not exclude the presence of additional identical elements in the process, method, article or device comprising the element.
Claims
1. A pixel unit, characterized in that, Comprising: A signal generation circuit for generating a reset signal and an exposure signal; A signal sampling and storage circuit for sampling and storing the reset signal and the exposure signal; wherein, the signal sampling and storage circuit includes: a first switch circuit, a second switch circuit, a third switch circuit, a first capacitor and a second capacitor; a first end of the first switch circuit is connected to the signal generation circuit, a second end of the first switch circuit is connected to a first end of the first capacitor, and a second end of the first capacitor is grounded; a first end of the second switch circuit is connected to a first end of the second capacitor, a second end of the second switch circuit is connected to the signal output circuit, and the other end of the second capacitor is grounded; a first end of the third switch circuit is connected to the second end of the first switch circuit, and a second end of the third switch circuit is connected to the second end of the second switch circuit; The signal output circuit for outputting the reset signal and the exposure signal stored by the signal sampling and storage circuit.
2. The pixel unit according to claim 1, characterized in that, The first switch circuit includes: A first transistor; a first end of the first transistor serves as the first end of the first switch circuit, a second end of the first transistor serves as the second end of the first switch circuit, and a third end of the first transistor inputs a first control signal.
3. The pixel unit according to claim 1, wherein The second switch circuit includes: A second transistor; a first end of the second transistor serves as the first end of the first switch circuit, a second end of the first transistor serves as the second end of the second switch circuit, and a third end of the second transistor inputs a second control signal.
4. The pixel unit according to any one of claims 1 to 3, characterized in that The third switch circuit includes: A third transistor; a first end of the third transistor serves as the first end of the third switch circuit, a second end of the third transistor serves as the second end of the third switch circuit, and a third end of the third transistor inputs a third control signal.
5. The pixel unit according to any one of claims 1 to 3, characterized in that, The third switch circuit is a wire.
6. The pixel unit according to claim 1, wherein The signal generation circuit includes: A photodiode, a fourth transistor, a fifth transistor, a sixth transistor; an anode of the photodiode is grounded, a cathode of the photodiode is connected to a first end of the fourth transistor, a second end of the fourth transistor is connected to a floating diffusion node, a third end of the fourth transistor inputs a transfer control signal, a first end of the fifth transistor is connected to the floating diffusion node, a second end of the fifth transistor is connected to a first potential, a third end of the fifth transistor inputs a reset control signal, a first end of the sixth transistor is connected to the signal sampling and storage circuit, a second end of the sixth transistor is connected to a second potential, and a third end of the sixth transistor is connected to the floating diffusion node.
7. The pixel unit according to claim 6, wherein The signal generation circuit further includes: A seventh transistor; a first end of the seventh transistor is grounded, a second end of the seventh transistor is connected to the first end of the sixth transistor, and a third end of the seventh transistor inputs a bias signal.
8. The pixel unit according to claim 1, characterized in that The signal output circuit includes: The eighth transistor and the ninth transistor; a first end of the eighth transistor is connected to a second end of the ninth transistor, a second end of the eighth transistor is connected to a second potential, a third end of the eighth transistor is connected to the signal sampling and storage circuit, a first end of the ninth transistor is grounded and serves as an output end of the pixel unit, and a third end of the ninth transistor inputs a selection control signal.
9. The pixel unit according to claim 1, wherein The first capacitor and the second capacitor are MIM capacitors or MOS capacitors.
10. An image sensor, characterized in that, Comprising the pixel unit according to any one of claims 1 to 9.