Semiconductor structure and manufacturing method thereof

Abstract

The invention provides a semiconductor structure and a manufacturing method thereof, and relates to the field of semiconductors, the semiconductor structure comprises a substrate, a bit line and an isolation layer, the isolation layer comprises a first isolation part and a second isolation part which are parallel to the substrate, and the second isolation part is located below the first isolation part; the projection of the first isolation part on the substrate encloses a plurality of first preset patterns arranged according to a second array, the bottom of the bit line is provided with a bit line contact structure penetrating through the isolation layer, the projection of the bit line contact structure on the substrate is located in the first preset patterns, and the first isolation part at least covers part of the second isolation part to form an overlapping area. The first isolation part and the second isolation part of the semiconductor structure are formed in the manufacturing process of the semiconductor structure, and a step structure can be formed around the bit line contact hole, so that the bit line contact hole is prevented from being shielded, the filling effect of the insulation structure is ensured, the coupling effect and the electric leakage problem are reduced, and the yield and the performance of products are improved.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor technology, and in particular, to a semiconductor structure and a manufacturing method thereof. Background Art

[0002] As the size of semiconductor devices gradually decreases, the interference generated between adjacent metal conductors becomes more and more obvious, seriously affecting the circuit turn-on speed and circuit reliability of the devices. In order to reduce the interference between metal conductors, an insulating structure is filled in the bit line contact hole to reduce the influence caused by the coupling effect.

[0003] Due to the different etching selectivity ratios of the substrate material and the isolation layer material on the substrate, the isolation layer will block the bit line contact holes formed in the substrate, resulting in poor filling effect of the insulating structure formed by the bit line structure holes, which is likely to cause problems such as leakage, and further affect the yield and performance of semiconductor products. Summary of the Invention

[0004] The following is an overview of the subject matter described in detail in the present disclosure. This overview is not intended to limit the scope of protection of the claims.

[0005] In a first aspect of the present disclosure, a semiconductor structure is provided, including:

[0006] A substrate including a plurality of active regions arranged in a first array;

[0007] A bit line located on the substrate;

[0008] An isolation layer, the isolation layer includes a first isolation portion and a second isolation portion parallel to the substrate, the second isolation portion is disposed below the first isolation portion, the projection of the first isolation portion on the substrate encloses a plurality of first preset patterns arranged in a second array, and the bottom of the bit line has a bit line contact structure penetrating the isolation layer, and the projection of the bit line contact structure on the substrate is located within the first preset pattern;

[0009] Wherein, the first isolation portion at least covers a part of the second isolation portion, the first isolation portion includes a coincidence region, the coincidence region is set as the region where the first isolation portion covers the second isolation portion, and the coincidence region is located outside the bit line contact structure.

[0010] In some embodiments, the semiconductor structure further includes an insulating structure located within the first preset pattern, and the insulating structure covers the outer wall surface of the bit line contact structure.

[0011] In some embodiments, along the extending direction of the active region, storage node contact structures are respectively disposed at two end portions of the active region. The storage node contact structures cover a part of the top surface of the active region, and the overlapping region is at least located between the storage node contact structures and the bit line contact structures.

[0012] In some embodiments, the second isolation portion is arranged according to the first array and disposed on the top surface of the active region. The second isolation portion covers the top surface of the active region that is not covered by the bit line contact structures, the insulating structures, and the storage node contact structures.

[0013] In some embodiments, the second isolation portion includes a first part and a second part. The first part is covered by the first isolation portion, and the second part is not covered by the first isolation portion. The projection of the second part on the substrate is located outside the first preset pattern.

[0014] In some embodiments, the second isolation portion is arranged according to the second array and is annular. The inner sidewall of the second isolation portion is connected to the outer sidewall of the insulating structure.

[0015] According to a second aspect of the present disclosure, there is provided a method for manufacturing a semiconductor structure, including:

[0016] Providing a substrate, the substrate including a plurality of active regions arranged according to a first array;

[0017] Forming a plurality of bit line contact holes arranged according to a second array in the substrate;

[0018] Forming a bit line contact structure and an insulating structure in the bit line contact holes. The insulating structure coats the bit line contact structure, and the bit line contact structure is in direct contact with the active region;

[0019] Wherein, before forming the insulating structure, a step structure is formed in at least a part of the region outside the bit line contact holes. The step structure is used to form an isolation layer. The step structure includes a first surface and a second surface that are parallel to each other. The first surface is higher than the second surface. A second isolation portion of the isolation layer is formed on the second surface, and a first isolation portion is formed on the first surface. The first isolation portion covers at least a part of the second isolation portion.

[0020] In some embodiments, before forming the insulating structure, forming a step structure in at least a part of the region outside the bit line contact holes includes:

[0021] Form a second initial isolation portion and a first initial isolation portion in sequence. The projection of the second initial isolation portion on the substrate coincides with the projection of the active region on the substrate, and the top surface of the first initial isolation portion completely covers the top surface of the second initial isolation portion;

[0022] Remove a part of the first initial isolation portion, form a first preset hole in the first initial isolation portion and expose a part of the top surface of the second initial isolation portion. The top surface of the remaining first initial isolation portion and the exposed top surface of the second initial isolation portion constitute the step structure.

[0023] In some embodiments, forming a plurality of bit line contact holes arranged in a second array on the substrate includes:

[0024] Form a supplementary isolation structure, the supplementary isolation structure fills the first preset hole, and the top surface of the supplementary isolation structure is flush with the top surface of the first initial isolation portion;

[0025] Remove a part of the supplementary isolation structure, the second initial isolation portion and a part of the active region to form the bit line contact holes. The projection of the bit line contact holes is located in the central region of the projection of the first preset hole.

[0026] In some embodiments, forming a bit line contact structure in the bit line contact holes includes:

[0027] Form a first conductive material layer, the first conductive material layer fills the bit line contact holes and covers the top surface of the remaining first initial isolation portion and the top surface of the remaining supplementary isolation structure;

[0028] Form a second conductive material layer, the second conductive material layer covers the top surface of the first conductive material layer;

[0029] Form an insulating cover material layer, the insulating cover material layer covers the top surface of the second conductive material layer;

[0030] Remove a part of the insulating cover material layer, the second conductive material layer and the first conductive material layer to form a bit line. Among them, the structure of the bit line located in the bit line contact holes constitutes the bit line contact structure.

[0031] In some embodiments, before forming the insulating structure, form a step structure in at least a part of the region outside the bit line contact holes, including:

[0032] Form a first initial isolation layer, the first initial isolation layer covers the top isolation layer of the substrate;

[0033] Remove a portion of the first initial isolation layer, a portion of the top isolation layer, and a portion of the active region to form the bit line contact hole;

[0034] Form a first conductive material layer, a second conductive material layer, and an insulating capping material layer;

[0035] Remove a portion of the first conductive material layer, the second conductive material layer, and the insulating capping material layer to form a bit line, and the structure of the bit line located within the bit line contact hole constitutes the bit line contact structure;

[0036] Etch the remaining first initial isolation layer and the remaining top isolation layer such that the top surface of the top isolation structure between two adjacent bit lines is lower than the bottom surface of the first initial isolation layer to form the step structure.

[0037] In some embodiments, the manufacturing method further includes:

[0038] Form an insulating structure within the bit line contact hole, the insulating structure covering the sidewalls of the bit line contact structure, a portion of the insulating structure covering the second surface of the step structure forms a second isolation layer, and a portion of the insulating structure located on the top surface of the second isolation layer forms a first additional isolation layer, wherein the first additional isolation layer and the remaining first initial isolation layer together serve as the first isolation layer.

[0039] The first isolation portion and the second isolation portion of the semiconductor structure provided by the present disclosure are formed during the manufacturing process of the semiconductor structure, and can form a step structure around the bit line contact hole to avoid blocking the bit line contact hole, ensure the filling effect of the insulating structure, reduce the coupling effect and leakage problems, and improve the yield and performance of the product.

[0040] Other aspects can be understood after reading and understanding the drawings and the detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0041] The drawings incorporated into the specification and constituting a part of the specification illustrate embodiments of the present disclosure and, together with the description, are used to explain the principles of the embodiments of the present disclosure. In these drawings, like reference numerals are used to represent like elements. The following drawings are some embodiments of the present disclosure, not all embodiments. Those skilled in the art can obtain other drawings based on these drawings without creative efforts.

[0042] Figure 1 is a schematic cross-sectional view of a semiconductor structure in the related art.

[0043] Figure 2 is a schematic diagram of a semiconductor structure shown according to an exemplary embodiment.

[0044] Figure 3 is Figure 2 a cross-sectional view taken along the A-A direction in

[0045] Figure 4 a cross-sectional view of a semiconductor structure shown according to an exemplary embodiment.

[0046] Figure 5 a top view of a semiconductor structure shown according to an exemplary embodiment.

[0047] Figure 6 a schematic diagram of a semiconductor structure shown according to another exemplary embodiment.

[0048] Figure 7 is Figure 6 a cross-sectional view taken along the B-B direction in

[0049] Figure 8 a cross-sectional view of a semiconductor structure shown according to another exemplary embodiment.

[0050] Figure 9 a flowchart of a method for fabricating a semiconductor structure shown according to an exemplary embodiment.

[0051] Figure 10 a flowchart of a method for fabricating a semiconductor structure shown according to an exemplary embodiment.

[0052] Figure 11 a flowchart of a method for fabricating a semiconductor structure shown according to another exemplary embodiment.

[0053] Figure 12 a schematic diagram of a substrate shown according to an exemplary embodiment.

[0054] Figure 13 a schematic diagram of a substrate shown according to an exemplary embodiment.

[0055] Figure 14 a schematic diagram of forming a photoresist layer on a substrate shown according to an exemplary embodiment.

[0056] Figure 15 a schematic diagram of removing a partial structure of the substrate shown according to an exemplary embodiment.

[0057] Figure 16 a schematic diagram of forming an initial isolation layer shown according to an exemplary embodiment.

[0058] Figure 17 a schematic diagram of forming a photoresist layer on the initial isolation layer shown according to an exemplary embodiment.

[0059] Figure 18 Schematic diagram after removing a part of the structure of the initial isolation layer shown according to an exemplary embodiment.

[0060] Figure 19 Schematic diagram after forming a supplementary isolation layer shown according to an exemplary embodiment.

[0061] Figure 20 Schematic diagram after forming a supplementary isolation structure shown according to an exemplary embodiment.

[0062] Figure 21 Schematic diagram of a semiconductor structure shown according to an exemplary embodiment.

[0063] Figure 22 Schematic diagram of a semiconductor structure shown according to an exemplary embodiment.

[0064] Figure 23 Schematic diagram of a semiconductor structure shown according to an exemplary embodiment.

[0065] Figure 24 Schematic diagram of a semiconductor structure shown according to an exemplary embodiment.

[0066] Figure 25 Schematic diagram of a semiconductor structure shown according to an exemplary embodiment.

[0067] Figure 26 Schematic diagram of a semiconductor structure shown according to another exemplary embodiment.

[0068] Figure 27 Schematic diagram of a semiconductor structure shown according to another exemplary embodiment.

[0069] Figure 28 Schematic diagram of a semiconductor structure shown according to another exemplary embodiment.

[0070] Figure 29 Schematic diagram of a semiconductor structure shown according to another exemplary embodiment.

[0071] Figure 30 Schematic diagram of a semiconductor structure shown according to another exemplary embodiment.

[0072] Figure 31 is Figure 30 Cross-sectional view in the C-C direction in

[0073] Reference numerals:

[0074] 10’, Substrate; 11’, Active region; 12’, Shallow trench isolation structure; 13’, Top isolation structure; 20’, Bit line; 30’, Bit line contact structure; 40’, Isolation layer; 50’, Bit line contact hole;

[0075] 10, Substrate; 11, Active region; 12, Shallow trench isolation structure; 13, Top isolation structure; 13a, Top isolation layer;

[0076] 20, Bit line; 21, First conductive structure; 21a, First conductive material layer; 211a, Initial conductive material layer; 212a, Supplementary conductive material layer; 22, Second conductive structure; 22a, Second conductive material layer; 23, Insulating cover; 23a, Insulating cover material layer;

[0077] 30, Bit line contact structure;

[0078] 40, Isolation layer; 40a, Initial isolation layer;

[0079] 41, First isolation part; 41a, First initial isolation part; 410, First preset pattern; 411, First preset hole; 412, Supplementary isolation structure; 412a, Supplementary isolation layer; 42, Second isolation part; 42a, Second initial isolation part;

[0080] 43, First isolation layer; 431, First initial isolation layer; 432, First additional isolation layer; 44, Second isolation layer;

[0081] 50, Bit line contact hole; 60, Insulating structure; 70, Photoresist layer; 80, First mask layer; 90, Second mask layer; 100, Storage node contact structure. Detailed implementation manners

[0082] To make the objectives, technical solutions and advantages of the embodiments of the present disclosure clearer, the technical solutions in the embodiments of the present disclosure will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present disclosure. Apparently, the described embodiments are some, but not all, of the embodiments of the present disclosure. All other embodiments obtained by those of ordinary skill in the art based on the embodiments in the present disclosure without creative efforts shall fall within the protection scope of the present disclosure. It should be noted that, without conflict, the embodiments in the present disclosure and the features in the embodiments may be combined with each other arbitrarily.

[0083] There will be a coupling effect between conductive structures that are close to each other (such as adjacent bit lines and adjacent bit line contact structures). With the continuous advancement of process technology, the size of semiconductor devices is gradually decreasing, and the integration is becoming higher and higher. The higher integration makes the distance between adjacent conductive structures smaller, so the coupling effect becomes more and more obvious. The coupling effect will affect the read and write and reliability of the memory. Therefore, it is necessary to form an insulating structure at the conductive structure to reduce the impact of the coupling effect. If the insulating structure is not filled well, the shielding effect will be poor, which may cause leakage in the conductive structure, affecting the yield and performance of the memory.

[0084] refer to Figure 1 , shows a semiconductor structure after a bit line 20' is formed and before an insulating structure is filled in a related art. The conductor structure includes a substrate 10' and a bit line 20' formed on the substrate 10', and the bottom of the bit line 20' is in contact with the active area 11'. After the bit line 20' is formed by etching, a reactant with a certain corrosiveness (such as hydrogen fluoride) is used to clean the bit line 20' and the area around the bottom bit line contact structure 30' of the bit line 20' to remove etching residues and contaminants.

[0085] Continue to refer Figure 1 Since the reactant (such as HF) used in the cleaning process will corrode the oxide on the side wall of the bit line contact hole 50' (including the shallow trench isolation structure 12' and the top isolation structure 13'), and the HF etching rate of the nitride layer (such as the isolation layer 40') above the oxide is lower than the etching rate of the oxide, the size of the isolation layer 40' will not change substantially, while the etching effect of the oxide below the isolation layer 40' is more obvious. That is, after the bit line contact hole 50' is cleaned, the size of the opening formed at the isolation layer 40' is smaller than the size of the top opening of the bit line contact hole 50', and the isolation layer 40' will block part of the bit line contact hole 50'.

[0086] by Figure 1 Based on the structure shown in the figure, in the process of filling the insulating structure (not shown in the figure) into the bit line contact hole 50' by a deposition process, the portion of the isolation layer 40' protruding from the inner wall of the bit line contact hole 50' will block the material entering the bit line contact hole 50', and the material forming the insulating structure is partially blocked by the isolation layer 40', and cannot enter the area of ​​the bit line contact hole 50' blocked by the protruding isolation layer 40', thereby causing part of the area in the bit line contact hole 50' to be unable to be filled, resulting in holes and air gaps in the insulating structure, which in turn causes the insulating structure to be poorly filled in the bit line contact hole 50', resulting in poor shielding and insulation effects, and a high risk of leakage, resulting in low performance and yield of the semiconductor structure.

[0087] To solve the problems existing in the related art, the present application provides a semiconductor structure and a manufacturing method thereof. The semiconductor structure includes a substrate, a bit line, and an isolation layer. The isolation layer includes a first isolation portion and a second isolation portion parallel to the substrate. The second isolation portion is located below the first isolation portion. The projection of the first isolation portion on the substrate encloses a plurality of first preset patterns arranged in a second array. The bottom of the bit line has a bit line contact structure penetrating the isolation layer, and the projection of the bit line contact structure on the substrate is located within the first preset pattern. Wherein, the first isolation portion at least covers a part of the second isolation portion, and the first isolation portion has an overlapping region, that is, the region where the first isolation portion covers the second isolation portion. The first isolation portion and the second isolation portion of the semiconductor structure are formed during the manufacturing process of the semiconductor structure, and can form a stepped structure around the bit line contact hole to avoid blocking the bit line contact hole, completely expose the area inside the bit line contact hole before forming the insulating structure, ensure the filling effect of the insulating structure, reduce the coupling effect and leakage problems, and improve the yield and performance of the product.

[0088] According to an exemplary embodiment of the present disclosure, as Figure 2 and Figure 6 shown, the embodiments of the present disclosure provide a semiconductor structure, which can be used to fabricate and form a memory, such as a Dynamic Random Access Memory (DRAM), a Static Random-Access Memory (SRAM), etc.

[0089] Referring to Figures 2 to 8 , the semiconductor structure includes a substrate 10, and the substrate 10 is used to support various structures formed thereon during the manufacturing process. The substrate 10 is formed based on a substrate, and the material of the substrate can be silicon (Si), germanium (Ge), or silicon germanium (GeSi), silicon carbide (SiC), silicon on insulator (SOI), germanium on insulator (GOI), gallium arsenide and other group III-V materials. Referring to Figure 12 , the substrate 10 includes a plurality of active regions 11 arranged in a first array. The active regions 11 include a channel region and source and drain regions located on both sides of the channel region. Some impurity ions can be doped in a specified region in the substrate to form the active regions 11. Here, it should be noted that by adopting the first array arrangement mode of the active regions 11 shown in the present disclosure, a structure in which two adjacent memory cells share a drain region can be formed, that is, two memory structures can be controlled by two word lines and one bit line. This pattern of the active regions 11 is conducive to achieving a higher storage density.

[0090] Referring to Figures 2 to 8, The semiconductor structure includes bit lines 20. The bit lines 20 are disposed on the substrate 10 and can be connected to the drain regions of the active regions 11 in the substrate 10. In the extending direction of the bit lines 20, one bit line 20 can be connected to the drain regions of multiple active regions 11 simultaneously. Generally, multiple bit lines 20 are provided, and the arrangement direction of the multiple bit lines 20 is perpendicular to the extending direction of each bit line 20, so that any active region 11 in the substrate 10 can be connected through the multiple bit lines 20. The bit lines 20 generally include a multi-layer conductive structure (the first conductive structure 21 and the second conductive structure 22) and an insulating cover 23. The material of the first conductive structure 21 can be doped polysilicon, and the material of the second conductive structure 22 can include conductive metals, such as tungsten (W), titanium (Ti), titanium nitride (TiN), etc. The insulating cover 23 is used to protect the conductive structure, and the material of the insulating cover 23 can be a nitride, such as silicon nitride (SiN).

[0091] Reference Figure 2 , The semiconductor structure provided by the embodiment of the present disclosure further includes an isolation layer 40. The isolation layer 40 includes a first isolation portion 41 and a second isolation portion 42 parallel to the substrate 10. The second isolation portion 42 is disposed below the first isolation portion 41, and the first isolation portion 41 at least covers a part of the second isolation portion 42. The region where the first isolation portion 41 covers the second isolation portion 42 is the overlapping region. The overlapping region of the isolation layer 40 has a larger thickness (the sum of the thicknesses of the first isolation portion 41 and the second isolation portion 42).

[0092] Continue to refer to Figure 2 and Figure 5 , The first isolation portion 41 encloses multiple first preset patterns 410 arranged in a second array in the projection on the substrate 10. The bottom of the bit line 20 has a bit line contact structure 30. The projection of the bit line contact structure 30 on the substrate 10 is located within the first preset pattern 410. During the process of manufacturing the semiconductor structure, the first preset pattern 410 is used to define the shape, position, size, etc. of the bit line contact hole 50. The first preset pattern 410 can be, for example, a circle (refer to Figure 2 ), a square, an irregular shape, etc.

[0093] Reference Figure 2The bit line contact structure 30 is located at the bottom of the bit line 20, and sequentially penetrates the first isolation portion 41 and the second isolation portion 42 from top to bottom until it directly contacts the drain region of the active region 11. The bit line contact structure 30 is used to connect the bit line 20 and the active region 11. Since the bit line contact structure 30 is conductive, the bit line 20 and the active region 11 are electrically connected. The material of the bit line contact structure 30 is, for example, doped polysilicon. It should be noted that the bit line contact structure 30 and the first conductive structure 21 of the bit line 20 can be an integral structure, and the materials of both can be doped polysilicon. The bit line contact structure 30 and the first conductive structure 21 are divided based on the top surface of the isolation layer 40. The first conductive structure 21 is located above the top surface of the isolation layer 40, and the bit line contact structure 30 is located below the top surface of the isolation layer 40, that is, the bit line contact structure 30 penetrates the isolation layer 40.

[0094] In one example, reference Figures 2 to 5 ,exist Figure 2 In the semiconductor structure shown, the first isolation portion 41 covers part of the top surface of the second isolation portion 42, that is, a part of the structure (the first part) of the second isolation portion 42 is located directly below the first isolation portion 41, and the other part of the structure (the second part) is staggered with the first isolation portion 41, and the projection of the second part of the second isolation portion 42 on the substrate 10 is located outside the first preset pattern 410. Since the second part of the second isolation portion 42 is not covered by the first isolation portion 41, and the second part of the second isolation portion 42 is closer to the first preset pattern 410 than the first part, a gap (the gap is a part of the step structure described later) is formed outside the first preset pattern 410 in a stage of the manufacturing process of the semiconductor structure. By setting the gap, the isolation layer 40 is prevented from blocking the bit line contact hole 50 (described later), which is beneficial to the filling process of the insulation structure, and the insulation structure filling effect is better, avoiding leakage problems.

[0095] In another example, refer to Figures 6 to 8 ,exist Figure 6 In the semiconductor structure shown, during the formation of the isolation layer 40, an initial isolation layer may be formed first, the initial isolation layer surrounds the bit line contact hole 50, and then a portion of the initial isolation layer is removed, and a plane lower than the initial isolation layer is formed in a portion of the area around the bit line contact hole 50, so as to avoid the initial isolation layer from affecting the filling process of the insulating structure. The structural form in this example is used to assist the filling process of the insulating structure, and in the semiconductor structure finally formed, the first isolation layer 43 covers the entire top surface of the second isolation layer 44, that is, the entire structure of the second isolation layer 44 is located below the first isolation layer 43 (described in detail later).

[0096] In the embodiments of the present disclosure, the structure of the isolation layer is beneficial to the filling process of the insulating structure during the semiconductor manufacturing process, can avoid the shielding of the isolation layer from the deposition process of the material for forming the insulating structure, and air gaps are not likely to be generated in the insulating structure, thereby improving the reliability of the insulating structure.

[0097] In one exemplary embodiment, as Figures 2 to 8 shown, the embodiments of the present disclosure provide a semiconductor structure, which includes a substrate 10, a bit line 20, and an isolation layer 40. The isolation layer 40 includes a first isolation portion 41 parallel to the substrate 10 and a second isolation portion 42. The second isolation portion 42 is located below the first isolation portion 41. The projection of the first isolation portion 41 on the substrate 10 encloses a plurality of first preset patterns 410 arranged in a second array. The bottom of the bit line 20 has a bit line contact structure 30 that penetrates the isolation layer 40. The projection of the bit line contact structure 30 on the substrate 10 is located within the first preset pattern 410. Among them, the first isolation portion 41 at least covers a part of the second isolation portion 42, and the first isolation portion 41 has an overlapping region, which is the region where the first isolation portion 41 covers the second isolation portion 42.

[0098] In this embodiment, as Figure 4 and Figure 8 shown, the semiconductor structure further includes an insulating structure 60 located within the first preset pattern 410. The insulating structure 60 covers the outer wall surface of the bit line contact structure 30. The insulating structure 60 can form an insulating and shielding effect between two adjacent bit line contact structures 30 to reduce the parasitic coupling between adjacent bit line contact structures 30, or between the bit line contact structure 30 and the storage node contact structure 100 adjacent thereto (refer to Figure 5 ). Among them, parasitic coupling refers to an undesired coupling phenomenon that occurs additionally due to wiring and device characteristics in addition to the pre-designed coupling. For example, parasitic coupling will occur when the wire distances are too close. Parasitic coupling affects the transmission of electrical signals, and reducing parasitic coupling can improve the signal quality. Moreover, the insulating structure 60 coats the outer wall surface of the bit line contact structure 30, so that the insulating structure 60 can also avoid the leakage problem of the bit line contact structure 30, and avoid short circuits between adjacent bit line contact structures 30, or between the bit line contact structure 30 and the storage node contact structure 100 adjacent thereto (refer to Figure 5 ).

[0099] In one example, refer to Figure 4 and Figure 8, the insulating structure 60 can be an N-O-N (SiN-SiO-SiN) structure, that is, a silicon nitride - silicon oxide - silicon nitride structure. The insulating structure 60 can be formed by technologies such as Chemical Vapor Evaporation (abbreviated as CVD) and Physical Vapor Deposition (abbreviated as PVD).

[0100] In this embodiment, by arranging an insulating structure within the first preset pattern, the insulating structure covers the outer wall surface of the bit line contact structure, effectively reducing the influence of parasitic coupling between adjacent bit line contact structures or between the bit line contact structure and the adjacent storage node contact structure, and can also avoid the occurrence of leakage in the bit line contact structure.

[0101] Among them, as Figure 5 shown, and in combination with Figure 18 , along the extension direction of the active region 11 ( Figure 5 the a direction shown in Figure 2 ), storage node contact structures 100 are respectively arranged at both end portions of the active region 11. The storage node contact structure 100 covers a part of the top surface of the end portion of the active region 11 to be in direct contact with the top surface of the active region 11. The other end of the storage node contact structure 100 is in direct contact with a storage structure (not shown in the drawings) so that the storage structure is electrically connected to the active region 11. The storage structure is, for example, a capacitor. The capacitor can store charges representing data information, and the charge can be controlled to flow into or out of the capacitor through the word line, thereby realizing writing or reading data. Refer to Figure 5 and Figure 18 , the overlapping region of the first isolation portion 41 is at least located between the storage node contact structure 100 and the bit line contact structure 30.

[0102] In one example, referring to Figure 2 and Figure 5 and Figure 18 , the projection of the first isolation portion 41 on the substrate 10 encloses a second preset pattern (corresponding to the first preset hole 411). The area of the second preset pattern is larger than that of the first preset pattern 410. A bit line contact structure A31 is provided within the second preset pattern. The bit line contact structure A31 has an adjacent bit line contact structure B32. The second preset pattern exposes a part of the surface of the end portion of the second isolation portion 42 penetrated by the bit line contact structure B32. Since the storage node contact structure 100 covers a part of the top surface of the end portion of the active region 11, and the second isolation portion 42 and the overlapping region are located above the end portion of the active region 11, the storage node contact structure 100 needs to penetrate the second isolation portion 42 and the overlapping region. By Figure 5It can be determined that, for the first isolation portion 41 and the second isolation portion 42 on a single active region 11 , a portion of the structure in the overlapped region is located between the storage node contact structure 100 and the bit line contact structure 30 .

[0103] In another example, the overlapping area of ​​the isolation layer is staggered with the storage node contact structure, so that the storage node contact structure only needs to pass through the first isolation portion to connect to the end of the active area, that is, the entire structure of the overlapping area is located between the storage node contact structure and the bit line contact structure.

[0104] Among them, Figure 5 As shown, the second isolation portion 42 is arranged in a first array and is disposed on the top surface of the active area 11. Since the bit line contact structure 30 and the storage node contact structure 100 are both used to connect the active area 11 with external structures (such as the bit line 20 and the storage structure), the second isolation portion 42 disposed on the top surface of the active area 11 will be penetrated by the bit line contact structure 30 and the storage node contact structure 100. The insulating structure 60 fills the area in the bit line contact hole 50 that is not filled by the bit line contact structure 30 to cover the side wall of the bit line contact structure 30. The bottom surface of the insulating structure 60 is flush with the bottom surface of the bit line contact structure 30 (that is, the bottom surface of the structure is in direct contact with the active area). As can be seen from the above, the second isolation portion 42 covers the top surface of the active area 11 that is not covered by the bit line contact structure 30, the insulating structure 60 and the storage node contact structure 100.

[0105] Among them, reference Figure 3 , the second isolation portion 42 includes a first portion and a second portion, the first portion of the second isolation portion 42 is covered by the first isolation portion 41, and the second portion of the second isolation portion 42 is not covered by the first isolation portion 41, that is, the first portion of the second isolation portion 42 overlaps with the first isolation portion 41. As can be seen from the aforementioned embodiment, the first preset pattern 410 is used to define the bit line contact structure 30, and the second portion of the second isolation portion 42 is located outside the first preset pattern 410, that is, the second portion of the second isolation portion 42 is located outside the bit line contact structure 30, thereby forming a gap in the isolation layer in the peripheral area of ​​the bit line contact hole 50, thereby avoiding the isolation layer 40 from affecting the filling process of the insulation structure and ensuring the filling effect of the insulation structure.

[0106] Among them, reference Figure 3 The semiconductor structure further includes a supplementary isolation structure 412, which is located between adjacent active regions 11 and has a through hole therein, which is used to avoid the bit line contact structure 30. The supplementary isolation structure 412 has a shielding portion, which can cover the top surface of the second portion of the second isolation portion 42.

[0107] In an exemplary embodiment, Figures 6 to 8As shown, an embodiment of the present disclosure provides a semiconductor structure. The semiconductor structure includes a substrate 10, a bit line 20, and an isolation layer 40. The isolation layer 40 includes a first isolation portion 41 and a second isolation portion 42 parallel to the substrate 10. The second isolation portion 42 is located below the first isolation portion 41. The projection of the first isolation portion 41 on the substrate encloses a plurality of first preset patterns 410 arranged in a second array (refer to Figure 5 ), the bottom of the bit line 20 has a bit line contact structure 30 penetrating through the isolation layer 40, and the projection of the bit line contact structure 30 on the substrate 10 is located within the first preset pattern 410. Among them, the first isolation portion 41 at least covers a part of the second isolation portion 42, and the first isolation portion 41 has a coincidence region, that is, the region where the first isolation portion 41 covers the second isolation portion 42. The semiconductor structure further includes an insulating structure 60 located within the first preset pattern 410, and the insulating structure 60 covers the sidewall of the bit line contact structure 30.

[0108] In this embodiment, as Figures 6 to 8 shown, a second isolation layer 44 (corresponding to the second isolation portion in the previous embodiment) is arranged in a second array, and the pattern surrounded by the second isolation layer 44 is two semi - rings with opposite openings. The inner sidewall of the second isolation layer 44 is connected to the outer sidewall of the insulating structure 60, and the inner ring of the first isolation layer 43 (the top surface of the first isolation layer 43 is formed during the formation of the insulating structure 60, which will be introduced in detail later) coincides with the projection of the inner edge of the second isolation layer 44 on the substrate 10. Refer to Figure 8 , and the inner sidewall of the coincidence region of the first isolation layer 43 is also connected to the outer sidewall of the insulating structure 60.

[0109] From Figure 8It can be known that if a part of the top surface of the first isolation layer 43 is removed during the formation of the insulating structure 60, the remaining part of the first isolation layer 43 and the second isolation layer 44 can form a stepped structure. The stepped structure includes a first surface and a second surface that are parallel to each other, and the first surface is higher than the second surface. The removed top surface part of the first isolation layer 43 during the formation of the insulating structure 60 constitutes the first surface, and the second surface is constituted by the top isolation structure 13. The subsequently formed second isolation layer 44 covers the second surface. It should be noted that when the bit line contact hole, the stepped structure, and the insulating structure are sequentially formed in the semiconductor structure, that is, when the stepped structure is formed in the semiconductor structure, the insulating structure 60 has not been filled in the bit line contact hole 50 yet. Since the second surface of the stepped structure is lower than the first surface and the second surface is relatively closer to the bit line contact hole 50 than the first surface, when the insulating structure 60 is filled in the bit line contact hole 50, the isolation layer 40 will not have the problem of blocking the bit line contact hole 50 existing in the related art, which can ensure that the insulating structure 60 fully fills the bit line contact hole 50, improve the shielding performance of the insulating structure 60, avoid the leakage problem caused by the poor filling effect of the insulating structure 60, and thus improve the yield and performance of the semiconductor structure.

[0110] Among them, referring to Figure 8 , a top isolation structure 13 is further included on the substrate 10 of the semiconductor structure. The top isolation structure 13 is located between adjacent bit line contact structures 30. The outer sidewall and the bottom wall of the second isolation layer 44 are both connected to the top isolation structure 13, and the top isolation structure 13 covers the surface of the active region 11 that is not covered by the bit line contact structure 30 and the insulating structure 60.

[0111] According to an exemplary embodiment of the present disclosure, as Figure 9 shown, the present disclosure provides a method for manufacturing a semiconductor structure. This manufacturing method is used to manufacture the semiconductor structure provided in the foregoing embodiments of the present disclosure. The method for manufacturing the semiconductor structure includes:

[0112] Step S110: Provide a substrate, and the substrate includes a plurality of active regions arranged in a first array.

[0113] In this step, as Figure 2 shown, the substrate 10 is used to support various structures formed subsequently above it. The substrate 10 is formed by a substrate, and the material of the substrate can be silicon (Si), germanium (Ge), or silicon germanium (GeSi), silicon carbide (SiC); the material of the substrate can also be silicon on insulator (SOI), germanium on insulator (GOI); or it can also be other materials, such as gallium arsenide and other group III-V compounds.

[0114] Referring to Figure 12, the substrate 10 includes a plurality of active regions 11 arranged in a first array. The active regions 11 include a channel region and source and drain regions located on both sides of the channel region. Some impurity ions can be doped in a specified region in the substrate to form the active regions 11. Here, it should be noted that by adopting the first array arrangement mode of the active regions 11 shown in the present disclosure, a structure in which two adjacent memory cells share a drain region can be formed. That is, two memory structures can be controlled by two word lines and one bit line. This pattern of the active regions 11 is conducive to achieving a higher storage density.

[0115] Step S120: Form a plurality of bit line contact holes arranged in a second array on the substrate.

[0116] In this step, as Figure 2 and Figure 6 shown, an etching process can be used to remove part of the structure of the substrate 10 from the top surface of the substrate 10 downward to form a plurality of bit line contact holes 50 arranged in a second array in the substrate. The number of the bit line contact holes 50 is the same as the number of the active regions 11, and the bit line contact holes 50 correspond to the active regions 11 one by one. It should be noted that in order to ensure a reliable electrical connection between the bit line contact structure 30 formed in the bit line contact holes 50 and the active regions 11 in the subsequent process, part of the structure of the active regions 11 needs to be etched away to form a groove in the active regions 11 so that the bit line contact structure 30 extends into the interior of the substrate 10, and the bottom surface and part of the side wall surface of the bit line contact structure 30 can form an electrical connection with the active regions 11.

[0117] Wherein, before forming the bit line contact holes 50 on the substrate 10, some dielectric layers can also be formed on the top surface of the substrate 10 (part of the structure in this part of the dielectric layers will constitute the isolation layer 40 formed subsequently). The dielectric layers are located between adjacent bit line contact holes 50, can provide support and protection for the bit line contact structure 50, and moreover, the isolation layer 40 formed based on the dielectric layers can also shield the coupling generated by the bit line contact structures 30 in adjacent bit line contact holes 50 to reduce the parasitic coupling effect between adjacent bit line contact structures 30 or between the bit line contact structures 30 and adjacent memory node contact structures (formed subsequently).

[0118] Step S130: Form a bit line contact structure and an insulating structure in the bit line contact holes. The insulating structure coats the bit line contact structure, and the bit line contact structure is in direct contact with the active region; wherein, before forming the insulating structure, a step structure is formed in at least part of the region outside the bit line contact holes, and the step structure is used to form an isolation layer.

[0119] In this step, referring to Figure 2, a bit line contact structure 30 can be formed in the bit line contact hole 50 by deposition and etching processes. The bottom of the bit line contact structure 30 is in direct contact with the active region 11 and forms an electrical connection. The material of the bit line contact structure 30 includes doped polysilicon (doped poly). Ion doping of polysilicon can make the doped polysilicon conductive, and the doped ions are, for example, phosphorus (P) ions, boron (B) ions, and arsenic (As) ions. In some embodiments, after etching to form the bit line contact structure 30, the semiconductor structure can be cleaned. By cleaning, etching residues and contaminants can be removed, and the cleaning solution is, for example, hydrofluoric acid (HF).

[0120] The insulating structure 60 is formed after the bit line contact structure 30 is fabricated. The insulating structure 60 is used to coat the sidewalls of the bit line contact structure 30. The insulating structure 60 serves as a shield between adjacent bit line contact structures 30, or between the bit line contact structure 30 and the storage node contact structure (formed later, refer to Figure 5 ) adjacent thereto, to reduce parasitic coupling.

[0121] Among them, before forming the insulating structure, a step structure is formed in at least a part of the region outside the bit line contact hole. The step structure is used to form an isolation layer. For the method of forming the step structure, any one of the following two embodiments can be adopted.

[0122] In one example, refer to Figures 2 to 5 , before filling the insulating structure 60 into the bit line contact hole 50, a step structure is formed outside the bit line contact hole 50. The isolation layer 40 formed in the subsequent process is formed based on the step structure. The second isolation part 42 of the isolation layer 40 is correspondingly arranged with the active region 11 in the substrate 10. The top surface of the second isolation part 42 is substantially flush with the top surface of the oxide layer on the top of the substrate 10. The step structure includes a first surface and a second surface. The first surface is higher than the second surface, and the first surface and the second surface are connected by a step surface. The second surface is the top surface of the second isolation part 42. Before filling the insulating structure 60 into the bit line contact hole 50, an oxide material layer is supplemented on the second surface and the step surface, so as to ensure that the materials on the second surface and the step surface are the same as the materials on the sidewalls of the bit line contact hole 50, thereby avoiding the nitride material in the step structure from affecting the filling process of the insulating material, and further affecting the filling effect of the insulating structure 60.

[0123] In addition, refer to Figures 2 to 5 , in this example, during the filling process of the insulating structure, the nitride material of the insulating structure covers the first surface of the step structure and the oxide material formed on the second surface, and together with the nitride material constituting the step structure, forms the isolation layer 40 of the semiconductor structure.

[0124] In another example, refer toFigures 6 to 8 Before forming the bit line contact structure 30, a stepped structure can be formed in at least a partial region outside the bit line contact hole 50. The stepped structure includes a first surface and a second surface that are parallel to each other, and the first surface is higher than the second surface. A partial dielectric layer and oxide layer around the bit line contact hole 50 can be removed to form the stepped structure. The second surface of the stepped structure is closer to the bit line contact hole 50. The first surface can be formed by etching to remove a partial nitride dielectric layer formed on the top surface of the substrate 10, and the second surface can be formed by removing a partial oxide layer on the top surface of the substrate 10, so as to avoid the nitride dielectric layer from blocking the insulating material when filling the insulating structure into the bit line contact hole 50 subsequently.

[0125] In this example, referring to Figure 8 , Figure 8 FIG. [FIG. number not provided in the original] is a schematic diagram of the semiconductor structure after forming the bit line contact structure 30. The finally formed isolation layer 40 is formed during the process of filling the insulating structure 60 into the bit line contact hole 50. The filled insulating structure is an N - O - N structure. The nitride material will cover the first surface and the second surface of the stepped structure and finally form the isolation layer 40. The isolation layer 40 refers to the oxide layer on the top of the substrate 10. A partial structure of the isolation layer higher than the oxide layer constitutes the first isolation layer 43, and a partial structure of the isolation layer lower than the oxide layer constitutes the second isolation layer 44.

[0126] In the manufacturing method of the semiconductor structure in the embodiments of the present disclosure, before filling the insulating structure into the bit line contact hole, a stepped structure is formed outside the bit line contact hole. The lower second surface of the stepped structure is closer to the bit line contact hole, and most of the region of the second surface in contact with the side wall of the bit line contact hole is made of oxide material, which is the same as the material of the side wall of the bit line contact hole, so as to ensure that when filling the insulating structure into the bit line contact hole after cleaning, there is no nitride material around the bit line contact hole to block the insulating material, and the filling effect of the insulating structure is ensured.

[0127] In an exemplary embodiment, as Figure 10 shown, before forming the insulating structure, a stepped structure is formed in at least a partial region outside the bit line contact hole. The manufacturing method of the semiconductor structure provided by the embodiments of the present disclosure may include the following steps:

[0128] Step S210: Provide a substrate, where the substrate includes a plurality of active regions arranged in a first array.

[0129] In this step, referring to Figure 13, the top of the substrate 10 has a top isolation layer 13a, and the top isolation layer 13a covers the top surfaces of the active region 11 and the shallow trench isolation structure 12. In an exemplary embodiment, the top isolation layer 13a and the shallow trench isolation structure 12 comprise the same insulating material. Further, the top isolation layer 13a and the shallow trench isolation structure 12 are integrally formed. A partial structure of the top isolation layer 13a can be removed by an etching process to expose the top surface of the active region 11 in the substrate 10.

[0130] In one example, referring to Figures 12 to 15 , a photoresist layer 70 (taking a positive photoresist as an example, and all the photoresists described hereinafter are also positive photoresists) can be formed on the substrate 10. After the photoresist layer 70 is exposed and developed, a part of it is removed. Combining Figure 12 and Figure 14 , it can be known that the removed photoresist is located directly above the active region 11, and the remaining photoresist is located directly above the shallow trench isolation structure 12. Using the remaining photoresist layer 70 as a mask, the top surface of the substrate 10 is etched to remove a partial structure of the top isolation layer 13a above the active region 11, so that the top surface of the active region 11 is exposed. Referring to Figure 15 , it can be determined that the remaining top isolation layer 13a forms a top isolation structure 13, and a height difference is formed between the top isolation structure 13 and the top surface of the active region 11. Subsequently, a step structure will be formed based on this height difference by depositing a nitride material and etching the nitride material.

[0131] Step S220: Sequentially form a second initial isolation portion and a first initial isolation portion. The projection of the second initial isolation portion on the substrate coincides with the projection of the active region on the substrate, and the first initial isolation portion completely covers the top surface of the second initial isolation portion.

[0132] In this step, referring to Figure 16 , an isolation material (such as a nitride material) can be deposited on the top surface of the substrate 10 by a deposition process. The isolation material formed above the active region 11 and with a height not exceeding the top surface of the top isolation structure 13 forms a second initial isolation portion 42a, and the projection of the second initial isolation portion 42a on the substrate 10 coincides with the projection of the active region 11 on the substrate 10. Continuing to refer to Figure 16 , the isolation material is continuously deposited, and the isolation material higher than the top surface of the top isolation structure 13 forms a first initial isolation portion 41a. The first initial isolation portion 41a completely covers the top surface of the second initial isolation portion 42a and the top surface of the top isolation structure 13. In some alternative embodiments, after the first initial isolation portion 41a is formed, chemical mechanical polishing (CMP for short) can be performed on the top of the first initial isolation portion 41a to make the top of the first initial isolation portion 41a flat.

[0133] Step S230: Remove part of the first initial isolation portion, form a first preset hole in the first initial isolation portion, and expose the top surface of part of the second initial isolation portion. The top surface of the remaining first initial isolation portion and the exposed top surface of the second initial isolation portion form a stepped structure.

[0134] In this step, referring to Figure 17 and Figure 18 , an etching process can be used to remove part of the first initial isolation portion 41a to form a first preset hole 411 in the first initial isolation portion 41a. The first preset hole 411 exposes part of the top surface of the second initial isolation portion 42a, and the remaining first initial isolation portion 41a forms the first isolation portion 41. In one example, referring to Figure 17 , a photoresist layer 70 can be formed on the top surface of the first initial isolation portion 41a. After the photoresist layer 70 is exposed and developed, part of it is removed. The projection of the removed photoresist on the substrate 10 encloses a second preset pattern, and the multiple second preset patterns correspond to the multiple active regions 11 one by one. Using the remaining photoresist as a mask, the first initial isolation portion 41a is etched to form a first preset hole 411 in the first initial isolation portion 41a. Among them, the first preset hole 411 has a larger size than the bit line contact hole 50 formed subsequently, so as to reserve sufficient space for depositing oxide materials on the second surface and the stepped surface of the stepped structure, so as to ensure that the area not blocked by the bit line 20 around the bit line contact hole 50 is covered with the same oxide material as the side wall of the bit line contact hole 50, so as to avoid the presence of nitride materials in the edge region of the bit line contact hole 50 and prevent the insulating material from being blocked by the first isolation portion 41 when filling the insulating structure 60.

[0135] Referring to Figure 18 , it can be determined that the first preset hole 411 exposes part of the top surface of the second initial isolation portion 42a. Since the height of the first initial isolation portion 41a is higher than that of the second initial isolation portion 42a, the exposed top surface of the second initial isolation portion 42a forms the lower plane (i.e., the second plane) of the stepped structure, and the top surface of the first initial isolation portion 41a forms the higher plane (i.e., the first plane) of the stepped structure. The side wall of the first preset hole 411 forms the side surface of the stepped structure (i.e., the stepped surface in the previous text), and this side surface is used to connect the first plane and the second plane.

[0136] The first initial isolation portion 41a and the second initial isolation portion 42a formed with the first preset hole 411 form an initial isolation layer 40a. Based on the initial isolation layer, an isolation layer can be formed. The manufacturing method of the semiconductor structure may further include the following steps:

[0137] Step S240: Form a supplementary isolation structure which fills the first preset hole, and the top surface of the supplementary isolation structure is flush with the top surface of the first initial isolation portion.

[0138] In this step, referring to Figure 19 , a supplementary isolation layer 412a can be formed by a deposition process. The supplementary isolation layer 412a fills the first preset hole 411 (refer to Figure 18 ), and a part of the structure of the supplementary isolation layer 412a is higher than the top surface of the first preset hole 411.

[0139] Referring to Figure 20 , the part of the supplementary isolation layer 412a that is higher than the first preset hole 411 can be removed by chemical mechanical polishing (CMP), and the structure of the remaining supplementary isolation layer 412a that fills the first preset hole 411 forms a supplementary isolation structure 412. The material of the supplementary isolation structure 412 includes an oxide, such as silicon dioxide.

[0140] Step S250: Remove part of the supplementary isolation structure, the second initial isolation portion, and part of the active region to form a bit line contact hole, and the projection of the bit line contact hole is located in the central region of the projection of the first preset hole.

[0141] In this step, referring to Figure 21 , a first mask layer 80 and a second mask layer 90 can be formed on the top surfaces of the supplementary isolation structure 412 and the first initial isolation portion 41a. In an exemplary embodiment, the first mask layer 80 is an oxide layer, and the second mask layer 90 is a spin on hard-mask (SOH for short). A first preset pattern 410 is formed in the second mask layer 90 and the first mask layer 80 (refer to Figure 5 ). The projection of the first preset pattern 410 on the substrate 10 is located in the central region of the first preset hole 411 (refer to Figure 18 ). Using the second mask layer 90 as a mask, etch to remove the supplementary isolation structure 412, the second initial isolation portion 42a, and part of the active region 11. The removed region forms a bit line contact hole 50. The size of the bit line contact hole 50 is smaller than that of the first preset hole 411 and is located in the central region of the first preset hole 411. In another exemplary embodiment, the first mask layer 80 and the second mask layer 90 can be other material layers suitable as masks.

[0142] Among them, after removing part of the second initial isolation portion 42a to form the bit line contact hole 50, the remaining second initial isolation portion 42a forms a second isolation portion 42, and the second isolation portion 42 and the first isolation portion 41 formed in step S220 in the foregoing embodiment constitute an isolation layer 40.

[0143] Referring to Figure 21, before forming the first mask layer 80 on the top surface of the first initial isolation portion 41a, an initial conductive material layer 211a may also be formed. The material of the initial conductive material layer 211a is, for example, doped polysilicon. Refer to Figure 21 and Figure 22 , after forming the bit line contact hole 50, the second mask layer 90 above the first mask layer 80 is cleaned and removed, and the first mask layer 80 and the initial conductive material layer 211a are retained.

[0144] Step S260: Form a bit line contact structure and an insulating structure. The insulating structure covers the bit line contact structure, and the bit line contact structure is in direct contact with the active region.

[0145] In this step, the steps of forming the bit line contact structure may include:

[0146] Step S261: Sequentially form a first conductive material layer, a second conductive material layer, and an insulating cover material layer. Among them, the first conductive material layer fills the bit line contact hole and covers the top surface of the retained first initial isolation portion, the second conductive material layer covers the top surface of the first conductive material layer, and the insulating cover material layer covers the top surface of the second conductive layer.

[0147] In this step, refer to Figure 23 , a supplementary conductive material layer 212a may be formed. The supplementary conductive material layer 212a is located above the first mask layer 80 and fills the bit line contact hole 50. Refer to Figure 24 , the first mask layer 80 and the supplementary conductive material layer 212a above the initial conductive material layer 211a are removed. The initial conductive material layer 211a and the retained supplementary conductive material layer 212 within the bit line contact hole 50 constitute the first conductive material layer 21a. The material of the first conductive material layer 21a includes ion-doped polysilicon.

[0148] Refer to Figure 25 , after forming the first conductive material layer 21a, the second conductive material layer 22a and the insulating cover material layer 23a may be sequentially formed by a deposition process. The material of the second conductive material layer 22a includes conductive metals, such as tungsten (W), titanium (Ti), titanium nitride (TiN), etc. The material of the insulating cover material layer 23a includes nitrides, such as silicon nitride (SiN). In some alternative embodiments, after forming the first conductive material layer 21a, a barrier layer (not shown in the drawings) may also be formed. The barrier layer covers the top surface of the first conductive material layer. The barrier layer is located between the first conductive material layer and the second conductive material layer. The barrier layer is used to prevent material diffusion between the second conductive material layer and the first conductive material layer. The material of the barrier layer includes titanium nitride (TiN).

[0149] Step S262: Remove partial structures of the insulating capping material layer, the second conductive material layer, and the first conductive material layer, and the remaining material layers form bit lines.

[0150] In this step, referring to Figure 25 , two photomasks can be formed on the top surface of the insulating capping material layer 23a, and the shape, size, position, etc. of the bit lines are defined through the two photomasks. It should be noted that the technique of forming two photomasks is also called Double Pattern, which splits the original single photomask into two layers, capable of improving the clarity. Among them, the structure at the bottom of the bit line 20 located within the bit line contact hole 50 constitutes the bit line contact structure 30. It should be noted that when forming the bit line contact structure 30, the first conductive material layer 21a filled in the bit line contact hole 50 and located between adjacent bit lines 20 is also removed to reserve a space for forming the insulating structure 60 within the bit line contact hole 50.

[0151] After forming the bit line contact structure, referring to Figure 4 , processes such as deposition can be used to form an N - O - N stacked insulating structure in the space reserved within the bit line contact hole 50. In one example, referring to Figure 4 , the initially formed nitride layer can also cover the top wall and side walls of the bit line 20, as well as cover a part of the top surface of the isolation layer 40.

[0152] In an exemplary embodiment, as Figure 11 shown, the manufacturing method provided by the embodiments of the present disclosure may include the following steps:

[0153] Step S310: Provide a substrate, the substrate including a plurality of active regions arranged in a first array.

[0154] The implementation manner and principle of Step S310 are the same as those of Step S110 in the foregoing embodiments, and will not be elaborated here.

[0155] Step S320: Form a first initial isolation layer, the first initial isolation layer covering the top isolation layer of the substrate.

[0156] In this step, as Figure 26 shown, the first initial isolation layer 431 can be formed by a deposition process. The first initial isolation layer 431 covers the top surface of the top isolation layer 13a, and the first initial isolation layer 431 is used to form the first isolation layer 43 in subsequent steps (refer to Figure 8 ). The material of the first initial isolation layer 431 includes nitrides, such as silicon nitride (SiN).

[0157] It should be noted that the top isolation layer 13a is a structure located on the top of the substrate 10, and the top isolation layer 13a covers the active region 11 of the substrate 10 and the top surface of the shallow trench isolation structure 12. In an exemplary embodiment, the top isolation layer 13a and the shallow trench isolation structure 12 include the same insulating material. Further, the top isolation layer 13a and the shallow trench isolation structure 12 are integrally formed.

[0158] Step S330: Remove a part of the first initial isolation layer, a part of the top isolation layer, and a part of the active region to form a bit line contact hole.

[0159] In this step, as Figure 26 shown, an etching process can be used to remove the first initial isolation layer, a part of the top isolation layer, and a part of the active region to form a bit line contact hole. In subsequent steps, a bit line contact structure and an insulating structure are formed in the bit line contact hole. In one example, referring to Figure 26 , an initial conductive material layer 211a, a first mask layer 80, and a second mask layer 90 can be formed on the top of the first initial isolation layer 431. Preset patterns are formed in the second mask layer 90 and the first mask layer 80. The preset patterns are used to define the shape, position, size, etc. of the bit line contact hole 50. Using the second mask layer 90 as a mask for etching to remove a part of the initial conductive material layer 211a, the first initial isolation layer 431, the top isolation layer 13a, and a part of the active region 11, thereby forming the bit line contact hole 50.

[0160] As Figure 27 shown, after the bit line contact hole 50 is formed, the first mask layer 80 above the initial conductive material layer 211a can be removed.

[0161] Step S340: Form a first conductive material layer, a second conductive material layer, and an insulating capping material layer.

[0162] In this step, as Figure 28 shown, after the first mask layer 80 is removed, a supplementary conductive material layer 212a can be formed by a deposition process. The supplementary conductive material layer 212a fills the bit line contact hole 50. After the supplementary conductive material layer 212a is formed, its top surface can be polished by chemical mechanical polishing to make its surface flat. The initial conductive material layer 211a and the remaining supplementary conductive material layer 212a form the first conductive material layer 21a. The material of the supplementary conductive material layer 212a is, for example, doped polysilicon. The material of the supplementary conductive material layer 212a is the same as that of the initial conductive material layer 211a to better combine.

[0163] As Figure 29As shown, after forming the first conductive material layer 21a, a deposition process can be used to sequentially form a second conductive material layer 22a and an insulating cover material layer 23a on the top surface of the first conductive material layer 21a. The material of the second conductive material layer 22a includes conductive metals such as tungsten (W), titanium (Ti), titanium nitride (TiN), etc., and the material of the insulating cover material layer 23a includes nitrides such as silicon nitride (SiN). In some alternative embodiments, after forming the first conductive material layer 21a, a barrier layer (not shown in the drawings) can also be formed. The barrier layer covers the top surface of the first conductive layer, is located between the first conductive material layer and the second conductive material layer, and is used to prevent material diffusion between the second conductive material layer and the first conductive material layer. The material of the barrier layer includes titanium nitride (TiN).

[0164] Among them, referring to Figure 27 , when forming the first conductive material layer 21a, a part of the structure of the first conductive material layer 21a will fill the bit line contact hole 50. In subsequent process steps, the part of the first conductive material layer 21a filled in the bit line contact hole 50 is used to form the bit line contact structure 30.

[0165] Step S350: Remove part of the first conductive material layer, the second conductive material layer, and the insulating cover material layer to form bit lines. The structure of the bit lines located in the bit line contact holes constitutes the bit line contact structure.

[0166] In this step, referring to Figures 29 to 31 , a mask can be formed on the top surface of the insulating cover material layer 23a, and a double patterning etching process is used to remove part of the first conductive material layer 21a, the second conductive material layer 22a, and the insulating cover material layer 23a to form multiple bit lines 20. The first conductive material layer 21a located at the bottom of the bit lines 20 and within the line contact hole 50 constitutes the bit line contact structure 30.

[0167] In some embodiments, referring to Figure 31 , after etching to form the bit lines 20 and the bit line contact structure 30, the semiconductor structure can be cleaned to remove residues and contaminants after etching. The cleaning solution is, for example, hydrofluoric acid (HF).

[0168] Step S360: Etch the remaining first initial isolation layer and the remaining top isolation layer so that the top surface of the top isolation structure between adjacent two bit lines is lower than the bottom surface of the first initial isolation layer to form a step structure.

[0169] In this step, referring to Figure 7, an etching process can be used to remove a part of the first initial isolation layer 431 and the remaining top isolation layer (i.e., the top isolation structure 13), so that the top surface of the top isolation structure 13 between two adjacent bit lines 20 is lower than the bottom surface of the first initial isolation layer 431, to form a stepped structure. The stepped structure includes a first surface and a second surface. The surface of the top isolation structure 13 lower than the first initial isolation layer 431 is the second surface of the stepped structure. In an exemplary embodiment, the remaining first initial isolation layer 431 may only be the part covered by the bit line 20.

[0170] Step S370: Form an insulating structure in the bit line contact hole, and the insulating structure coats the bit line contact structure.

[0171] In this step, when forming the bit line, the first conductive material layer filled in the bit line contact hole and located between adjacent bit lines is also etched away. The remaining first conductive material layer located in the bit line contact hole is directly below the bit line, and this part of the first conductive material layer forms the bit line contact structure.

[0172] It can be understood that after the first conductive material layer located between adjacent bit lines is etched away, a vacant area will be formed in the bit line contact hole. The vacant area exposes part of the side wall of the bit line contact structure. An insulating structure 60 can be filled in the vacant area by a deposition process, and the insulating structure 60 coats the side wall of the bit line contact structure 30. The structure and material of the insulating structure 60 are the same as those of the insulating structure described in the foregoing embodiments, and will not be elaborated here.

[0173] In some embodiments, this embodiment is a further description of step S370 in the above embodiments. The manufacturing method of the semiconductor structure may include the following steps:

[0174] Form an insulating structure in the bit line contact hole. The insulating structure coats the side wall of the bit line contact structure. The part of the insulating structure covering the second surface of the stepped structure forms a second isolation layer, and the part of the insulating structure located on the top surface of the second isolation layer forms a first additional isolation layer, where the first additional isolation layer and the remaining first initial isolation layer together serve as the first isolation layer.

[0175] In this step, referring to Figure 7 and Figure 8 , an insulating material can be deposited in the bit line contact hole 50 to form the bottom film layer (nitride, such as SiN) of the insulating structure 60. Since the second surface of the stepped structure surrounds and is close to the bit line contact hole 50, the insulating material will also be deposited on the second surface of the stepped structure, so that part of the structure of the insulating structure 60 covers the second surface of the stepped structure, to form a second isolation layer 44 on the second surface of the stepped structure. The top surface of the second isolation layer 44 is flush with the bottom surface of the first initial isolation layer 431.

[0176] In one example, referring to Figure 8 , a portion of the insulating structure 60 located on the top surface of the second isolation layer 44 forms a first additional isolation layer 432. The first additional isolation layer 432 and the retained first initial isolation layer 431 together serve as the first isolation layer 43.

[0177] In some embodiments, the bottom film layer of the insulating structure 60, the second isolation layer 44, and the first additional isolation layer 432 comprise the same material, that is, the second isolation layer 44 and the first additional isolation layer 432 are formed synchronously during the formation of the insulating structure 60.

[0178] In some embodiments, after forming the insulating structure in the bit line contact hole, the method for fabricating a semiconductor structure further includes:

[0179] Forming a storage node contact hole between adjacent bit lines, the storage node contact hole exposing a partial top surface of the end of the active region. In one example, referring to Figure 5 , a mask layer can be formed on the top surface of the isolation layer 40. The mask layer has a hollow pattern, and the projection of the hollow pattern on the substrate falls on the end of the active region 11. Then, an etching process can be used to remove the isolation layer 40 above the active region 11 and a partial structure of the insulating structure 60 to expose a partial top surface of the end of the active region 11.

[0180] Forming a storage node contact structure, the storage node contact structure filling the storage node contact hole and connecting to the top surface of the active region.

[0181] Forming a storage node, the storage node connecting to the top of the storage node contact structure. During subsequent use, the storage node (not shown in the drawings) forms an electrical connection with the storage node contact structure 100 to store data in the storage node. Depending on the formed storage node contact structure 100, different memories can be formed in the semiconductor structure, and the memories include Dynamic Random Access Memory (abbreviated as DRAM), Magnetoresistive Random Access Memory (abbreviated as MRAM), Ferroelectric Random Access Memory (abbreviated as FeRAM), and Phase-Change Random Access Memory (abbreviated as PCRAM).

[0182] The embodiments or implementations in this specification are described in a progressive manner. Each embodiment focuses on the differences from other embodiments. The same or similar parts among the embodiments can be referred to each other.

[0183] In the description of this specification, the descriptions referring to terms such as "embodiment", "exemplary embodiment", "some embodiments", "schematic embodiments", "example", etc. mean that the specific features, structures, materials or characteristics described in connection with the embodiments or examples are included in at least one embodiment or example of the present disclosure.

[0184] In this specification, the schematic expressions of the above terms do not necessarily refer to the same embodiments or examples. Moreover, the specific features, structures, materials or characteristics described can be combined in a suitable manner in any one or more embodiments or examples.

[0185] In the description of the present disclosure, it should be noted that the orientation or positional relationship indicated by terms such as "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc. is based on the orientation or positional relationship shown in the drawings. It is only for the convenience of describing the present disclosure and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and thus should not be construed as a limitation to the present disclosure.

[0186] It can be understood that the terms "first", "second", etc. used in the present disclosure can be used in the present disclosure to describe various structures, but these structures are not limited by these terms. These terms are only used to distinguish one structure from another.

[0187] In one or more of the drawings, the same elements are denoted by like reference numerals. For clarity, the various parts in the drawings are not drawn to scale. In addition, some well-known parts may not be shown. For the sake of brevity, the structure obtained after several steps can be described in one figure. Many specific details of the present disclosure are described hereinafter, such as the structure, materials, dimensions, processing techniques and technologies of the device, so as to understand the present disclosure more clearly. However, as those skilled in the art can understand, the present disclosure can be implemented without these specific details.

[0188] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present disclosure, rather than to limit them; although the present disclosure has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that they can still modify the technical solutions recorded in the foregoing embodiments, or perform equivalent replacements on some or all of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the present disclosure.

Claims

1. A semiconductor structure, characterized in that, Comprising: A substrate including a plurality of active regions arranged in a first array; Bit lines located on the substrate; An isolation layer, the isolation layer including a first isolation portion and a second isolation portion parallel to the substrate, the second isolation portion being disposed below the first isolation portion, the first isolation portion enclosing a plurality of first preset patterns arranged in a second array in the projection of the substrate on the substrate, the bottom of the bit line having a bit line contact structure penetrating the isolation layer, and the projection of the bit line contact structure on the substrate being located within the first preset pattern; Wherein, the first isolation portion at least covers a part of the second isolation portion, the first isolation portion includes a coincidence region, the coincidence region is set as the region where the first isolation portion covers the second isolation portion, and the coincidence region is located outside the bit line contact structure.

2. The semiconductor structure according to claim 1, wherein The semiconductor structure further includes an insulating structure located within the first preset pattern, and the insulating structure covers the outer wall surface of the bit line contact structure.

3. The semiconductor structure according to claim 2, wherein Along the extending direction of the active region, storage node contact structures are respectively disposed at two end portions of the active region, the storage node contact structures cover a part of the top surface of the active region, and the coincidence region is at least located between the storage node contact structure and the bit line contact structure.

4. The semiconductor structure according to claim 3, wherein, The second isolation portion is arranged in the first array and disposed on the top surface of the active region, and the second isolation portion covers the top surface of the active region that is not covered by the bit line contact structure, the insulating structure, and the storage node contact structure.

5. The semiconductor structure according to claim 4, wherein, The second isolation portion includes a first part and a second part, the first part is covered by the first isolation portion, the second part is not covered by the first isolation portion, and the projection of the second part on the substrate is located outside the first preset pattern.

6. The semiconductor structure according to claim 2, wherein The second isolation portion is arranged in the second array and is annular, and the inner side wall of the second isolation portion is connected to the outer side wall of the insulating structure.

7. A method for fabricating a semiconductor structure, characterized in that, Comprising: Providing a substrate, the substrate including a plurality of active regions arranged in a first array; Forming a plurality of bit line contact holes arranged in a second array in the substrate; Forming a bit line contact structure and an insulating structure in the bit line contact holes, the insulating structure covering the bit line contact structure, and the bit line contact structure being in direct contact with the active region; Wherein, before forming the insulating structure, a step structure is formed in at least a part of the region outside the bit line contact hole, the step structure is used to form an isolation layer, the step structure includes a first surface and a second surface parallel to each other, the first surface is higher than the second surface, the second isolation portion of the isolation layer is formed on the second surface, and the first isolation portion is formed on the first surface, and the first isolation portion at least covers a part of the second isolation portion.

8. The method for fabricating a semiconductor structure according to claim 7, wherein Before forming the insulating structure, forming a step structure in at least a part of the region outside the bit line contact hole includes: Sequentially forming a second initial isolation portion and a first initial isolation portion, the projection of the second initial isolation portion on the substrate coincides with the projection of the active region on the substrate, and the first initial isolation portion completely covers the top surface of the second initial isolation portion; Remove a part of the first initial isolation portion, form a first preset hole in the first initial isolation portion and expose the top surface of a part of the second initial isolation portion, and the top surface of the remaining first initial isolation portion and the exposed top surface of the second initial isolation portion constitute the step structure.

9. The method for fabricating a semiconductor structure according to claim 8, wherein, Forming a plurality of bit line contact holes arranged in a second array on the substrate, including: Form a supplementary isolation structure, the supplementary isolation structure fills the first preset hole, and the top surface of the supplementary isolation structure is flush with the top surface of the first initial isolation portion; Remove a part of the supplementary isolation structure, the second initial isolation portion and a part of the active region to form the bit line contact hole, and the projection of the bit line contact hole is located in the central region of the projection of the first preset hole.

10. The manufacturing method of the semiconductor structure according to claim 9, wherein, Forming a bit line contact structure in the bit line contact hole, including: Form a first conductive material layer, the first conductive material layer fills the bit line contact hole and covers the top surface of the remaining first initial isolation portion and the top surface of the remaining supplementary isolation structure; Form a second conductive material layer, the second conductive material layer covers the top surface of the first conductive material layer; Form an insulating cover material layer, the insulating cover material layer covers the top surface of the second conductive material layer; Remove a part of the insulating cover material layer, the second conductive material layer and the first conductive material layer to form a bit line, wherein the structure of the bit line located in the bit line contact hole constitutes the bit line contact structure.

11. The manufacturing method of the semiconductor structure according to claim 7, wherein, Before forming the insulating structure, form a step structure in at least a part of the region outside the bit line contact hole, including: Form a first initial isolation layer, the first initial isolation layer covers the top isolation layer of the substrate; Remove a part of the first initial isolation layer, a part of the top isolation layer and a part of the active region to form the bit line contact hole; Form a first conductive material layer, a second conductive material layer and an insulating cover material layer; Remove a part of the first conductive material layer, the second conductive material layer and the insulating cover material layer to form a bit line, and the structure of the bit line located in the bit line contact hole constitutes the bit line contact structure; Etch the remaining first initial isolation layer and the remaining top isolation layer so that the top surface of the top isolation structure between two adjacent bit lines is lower than the bottom surface of the first initial isolation layer to form the step structure.

12. The method for fabricating a semiconductor structure according to claim 11, wherein, The manufacturing method further includes: Form an insulating structure in the bit line contact hole, the insulating structure coats the side wall of the bit line contact structure, the part of the insulating structure covering the second surface of the step structure forms a second isolation layer, and the part of the insulating structure located on the top surface of the second isolation layer forms a first additional isolation layer, wherein the first additional isolation layer and the remaining first initial isolation layer together serve as the first isolation layer.

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