Semiconductor structure, preparation method thereof and storage system

Abstract

The embodiment of the invention provides a semiconductor structure, a preparation method and a memory system. The semiconductor structure comprises a semiconductor column, a bit line and a bit line isolation structure. The semiconductor column extends along a first direction and comprises a top part and a bottom part which are opposite in the first direction; a bit line extending in a second direction intersecting the first direction and connecting the bottoms of the plurality of semiconductor columns; and in a third direction intersecting with the first direction and the second direction, the plurality of bit line isolation structures and the plurality of bit lines are alternately arranged. Wherein at least one of the plurality of bit line isolation structures includes an air gap, a size of a first end of the air gap is larger than a size of a second end of the air gap in a direction intersecting with the first direction, and the first end is closer to the top relative to the second end.

Description

Technical Field

[0001] This application relates to the field of semiconductor design and fabrication, and more particularly, to semiconductor structures, methods for fabricating semiconductor structures, and memory systems. Background Art

[0002] Memory is one of the important components in an electronic system. Taking the dynamic random access memory (DRAM) in the memory as an example, a semiconductor device may include memory cells composed of capacitors and transistors, and multiple memory cells may be arranged in the form of a two-dimensional array.

[0003] To further reduce the size of the two-dimensional array, the transistor may include a vertical gate transistor (VGT). In this structure, a source electrode and a drain electrode of the transistor may be formed at both ends of the channel of the transistor in the extending direction, and a gate electrode of the transistor may be formed on at least one side of the channel.

[0004] However, with the continuous reduction of the feature size of semiconductor devices and the continuous decrease of the power consumption of semiconductor devices, the influence of the coupling interference between bit lines in semiconductor devices becomes increasingly prominent. Summary of the Invention

[0005] This application provides a method for fabricating a semiconductor structure, a semiconductor structure, and a memory system that can at least partially solve the above problems or other problems in the art.

[0006] On the one hand, this application provides a semiconductor structure, which includes: a semiconductor pillar extending along a first direction and including a top and a bottom opposite to each other in the first direction; a bit line extending in a second direction intersecting the first direction and connecting the bottoms of multiple semiconductor pillars; and a bit line isolation structure, in a third direction intersecting the first direction and the second direction, multiple bit line isolation structures and multiple bit lines are alternately arranged, wherein at least one of the multiple bit line isolation structures includes an air gap, and in a direction intersecting the first direction, a first end size of the air gap is larger than a second end size thereof, and the first end is closer to the top than the second end.

[0007] In an embodiment of this application, the first ends of the multiple air gaps have the same height in the first direction; and / or the second ends of the multiple air gaps have the same height in the first direction.

[0008] In an embodiment of this application, the sizes of the multiple air gaps in the first direction are the same.

[0009] In one embodiment of the present application, the surface of the bit line away from the top has the same height as the second end in the first direction.

[0010] In one embodiment of the present application, the first ends of the plurality of air gaps have the same height in the first direction; and / or the second ends of the plurality of air gaps have the same height in the first direction.

[0011] In one embodiment of the present application, at least one of the plurality of bit line isolation structures further includes an isolation dielectric layer, the air gap is surrounded by the isolation dielectric layer, wherein the isolation dielectric layer includes a first dielectric layer near the first end, a second dielectric layer near the second end, and a third dielectric layer located between the first dielectric layer and the second dielectric layer, wherein the material of the second dielectric layer is different from the material of the first dielectric layer; and / or the material of the second dielectric layer is different from the material of the third dielectric layer.

[0012] In one embodiment of the present application, at least one of the plurality of bit line isolation structures further includes an isolation dielectric layer, the air gap is surrounded by the isolation dielectric layer, and the plurality of bit line isolation structures include a first bit line isolation structure and a second bit line isolation structure, wherein the first bit line isolation structure includes the air gap; and the second bit line isolation structure includes the isolation dielectric layer and a filling dielectric layer surrounded by the isolation dielectric layer, and the material of the filling dielectric layer is different from the material of the isolation dielectric layer.

[0013] In one embodiment of the present application, the semiconductor structure includes at least one storage region formed with the semiconductor pillar, the storage region includes a first region located at the edge of the storage region and a second region different from the first region, wherein the second bit line isolation structure is located in the first region.

[0014] In one embodiment of the present application, the size of the air gap in the first direction is adjusted based on the size of the filling dielectric layer in the first direction.

[0015] In one embodiment of the present application, the size of the air gap in the direction intersecting the first direction gradually decreases from the first end to the second end.

[0016] In one embodiment of the present application, the semiconductor structure further includes a gate, wherein the semiconductor pillar further includes sidewalls located between the top and the bottom, and the gate is located on at least one of the plurality of sidewalls.

[0017] In one embodiment of the present application, the bit line includes a first bit line layer and a second bit line layer stacked in the first direction, wherein the first bit line layer is closer to the bottom than the second bit line layer, and the first bit line layer includes a semiconductor material layer.

[0018] On the other hand, the present application provides a method for manufacturing a semiconductor structure, the method including: forming a semiconductor pillar extending in a first direction, wherein the semiconductor pillar includes a top and a bottom opposite to each other in the first direction; and forming a bit line and a bit line isolation structure on the back side close to the bottom, wherein the bit line extends in a second direction intersecting the first direction and connects the bottoms of a plurality of the semiconductor pillars; a plurality of the bit line isolation structures and a plurality of the bit lines are alternately arranged in a third direction, the third direction intersecting the first direction and the second direction; and at least one of the plurality of the bit line isolation structures includes an air gap, and in a direction intersecting the first direction, a size of a first end of the air gap is larger than a size of a second end thereof, wherein the first end is closer to the top than the second end.

[0019] In one embodiment of the present application, forming the air gap includes: forming a filling dielectric layer between adjacent semiconductor pillars from the front side close to the top; and after completing the front side process, removing a part of the filling dielectric layer from the back side to form the air gap.

[0020] In one embodiment of the present application, forming the bit line and the bit line isolation structure on the back side close to the bottom includes: after removing a part of the filling dielectric layer to form an opening, forming the bit line at the bottoms of a plurality of semiconductor pillars arranged along the second direction; and closing the opening with a second dielectric layer to form the bit line isolation structure including the void gap.

[0021] In one embodiment of the present application, closing the opening with the second dielectric layer includes: forming the second dielectric layer covering a surface of the bit line away from the top and the opening, wherein the surface of the bit line away from the top and the second end of the air gap have the same height in the first direction.

[0022] In one embodiment of the present application, forming the semiconductor pillar extending in the first direction includes forming an initial semiconductor pillar extending in the lower direction, and forming the filling dielectric layer between adjacent semiconductor pillars includes: filling an initial filling dielectric layer between adjacent initial semiconductor pillars; removing a part of the initial filling dielectric layer to form the filling dielectric layer; and removing a part of the initial semiconductor pillar to form the semiconductor pillar, wherein the filling dielectric layer has a predetermined thickness in the first direction, and adjusts a size of the air gap in the first direction based on the predetermined thickness.

[0023] In one embodiment of the present application, the method further includes: before forming the initial filling dielectric layer, forming a third dielectric layer between adjacent initial semiconductor pillars, where the third dielectric layer is at least located on the sidewalls of the semiconductor pillars; and after forming the filling dielectric layer, forming a first dielectric layer on the filling dielectric layer, where the formation rate of the second dielectric layer is greater than that of at least one of the first dielectric layer and the third dielectric layer.

[0024] In one embodiment of the present application, the material of the second dielectric layer is different from that of the first dielectric layer; and / or the material of the second dielectric layer is different from that of the third dielectric layer.

[0025] In one embodiment of the present application, the material of the second dielectric layer contains at least one of silicon element, carbon element, oxygen element and hydrogen element.

[0026] On the other hand, the present application provides a storage system, which includes the semiconductor structure provided by one aspect of the present application and a controller coupled to the semiconductor structure, and the controller is used to store data in the semiconductor structure.

[0027] According to the semiconductor structure, preparation method and memory system provided by at least one embodiment of the present application, the semiconductor structure includes semiconductor pillars, bit lines and bit line isolation structures. The bit lines are located on the back side of the semiconductor structure and are connected to multiple semiconductor pillars. The bit line isolation structures are located between adjacent bit lines and can reduce the interference between adjacent bit lines. In addition, in order to enhance the above anti-interference effect, the bit line isolation structure includes air gaps. According to at least one embodiment of the present application, the air gaps can be formed by pre-burying a sacrificial layer from the front side of the intermediate during the preparation of the semiconductor structure. Thus, the air gaps can have a structure feature of being larger at the top and smaller at the bottom, and the structural consistency of multiple air gaps is improved, thereby effectively improving the adverse impact on the above anti-interference performance due to the difference in the air gap structure. Description of the Drawings

[0028] Other features, purposes and advantages of the present application will become more obvious by reading the detailed description of the non-limiting embodiments with reference to the following drawings. Among them:

[0029] Figure 1 is a cross-sectional view of a semiconductor structure according to an exemplary embodiment of the present application;

[0030] Figure 2 is Figure 1 a schematic diagram of the semiconductor structure shown taken along line A-A';

[0031] Figure 3 is Figure 1 a schematic enlarged cross-sectional view of the semiconductor structure shown at B;

[0032] Figure 4 is Figure 1 a schematic enlarged cross-sectional view of the semiconductor structure shown at C;

[0033] Figure 5A is a perspective view of a semiconductor structure according to an exemplary embodiment of the present application;

[0034] Figure 5B is a perspective view of a semiconductor structure of an embodiment;

[0035] Figure 6 is a flowchart of a method for fabricating a semiconductor structure according to an exemplary embodiment of the present application;

[0036] Figures 7 - 18 are process schematic diagrams of a method for fabricating a semiconductor structure according to an embodiment of the present application respectively; and

[0037] Figure 19 is a schematic diagram of a storage system structure according to an embodiment of the present application. Detailed Embodiments

[0038] To better understand the present application, various aspects of the present application will be described in more detail with reference to the accompanying drawings. It should be understood that these detailed descriptions are only descriptions of exemplary embodiments of the present application and do not limit the scope of the present application in any way. Throughout the specification, the same reference numerals refer to the same elements. The expression "and / or" includes any and all combinations of one or more of the associated listed items.

[0039] It should be noted that in this specification, the expressions such as first, second, third, etc. are only used to separate one feature from another feature region and do not represent any limitation on the features, especially not any order. Therefore, without departing from the teachings of the present application, the first end discussed in the present application may also be referred to as the second end, and vice versa.

[0040] In the drawings, for ease of illustration, the thickness, dimensions, and shapes of the components have been slightly adjusted. The drawings are only examples and are not drawn to an exact scale. As used herein, the terms "substantially", "about", and similar terms are used as terms indicating approximation and not as terms indicating degree, and are intended to account for the inherent deviations in measured or calculated values that would be recognized by a person of ordinary skill in the art.

[0041] It should also be understood that expressions such as "including", "comprising", "having", "containing" and / or "comprising of" in this specification are open-ended rather than closed-ended expressions, which mean the presence of the stated features, elements and / or components, but do not exclude the presence of one or more other features, elements, components and / or their combinations. In addition, when an expression such as "at least one of..." appears after a list of listed features, it modifies the entire list of features rather than just individual elements in the list. In addition, when describing embodiments of the present application, the use of "may" means "one or more embodiments of the present application". And the term "exemplary" is intended to refer to an example or illustration.

[0042] Unless otherwise defined, all terms used herein (including engineering terms and scientific and technical terms) have the same meaning as commonly understood by those of ordinary skill in the art to which this application belongs. It should also be understood that, unless clearly stated in this application, words defined in common dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant art, and should not be interpreted in an idealized or overly formal sense.

[0043] It should be noted that, without conflict, the embodiments in this application and the features in the embodiments can be combined with each other. In addition, unless clearly defined or in contradiction with the context, the specific steps included in the methods described in this application do not have to be limited to the recorded order, but can be executed in any order or executed in parallel.

[0044] In addition, in this application, when using "connected" or "coupled", it may mean direct contact or indirect contact between the corresponding components, unless there are clear other limitations or can be deduced from the context.

[0045] The present application will be described in detail below with reference to the drawings and in combination with embodiments.

[0046] Some embodiments of the present application provide a semiconductor structure. Figure 1 is a cross-sectional view of a semiconductor structure 1000 according to an exemplary embodiment of the present application. Figure 2 is Figure 1 a schematic diagram of the semiconductor structure 1000 shown taken along line A-A'. Figure 3 is Figure 1 a schematic enlarged cross-sectional view of the semiconductor structure 1000 at B. Figure 4 is Figure 1 a schematic enlarged cross-sectional view of the semiconductor structure 1000 at C.

[0047] As Figures 1 - 4As shown, the semiconductor structure 1000 includes a semiconductor pillar 100, a bit line 200, and a bit line isolation structure 300. The semiconductor pillar 100 extends along a first direction (z direction) and includes a top 101 and a bottom 102 that are opposite to each other in the z direction. The bit line 200 extends in a second direction (x direction) that intersects the z direction and is connected to the bottoms 102 of a plurality of semiconductor pillars 100. The bit line isolation structure 300 is located between adjacent bit lines 200, and in a third direction (y direction) that intersects the z direction and the x direction, a plurality of bit line isolation structures 300 and a plurality of bit lines 200 are alternately arranged. At least one of the plurality of bit line isolation structures 300 (for example, the first bit line isolation structure 301) includes an air gap 321. In a direction that intersects the z direction (for example, the x direction or the y direction), a first end 321-1 of the air gap 321 is closer to the top 101 of the semiconductor pillar 100 than its second end 321-2. In addition, a size d1 of the first end 321-1 is greater than a size d2 of the second end 321-2.

[0048] Memory is one of the important components in an electronic system. Taking memory as an example, a semiconductor structure may include memory cells composed of storage units and transistors, and a plurality of memory cells may be arranged in the form of a two-dimensional array. In addition, in order to further reduce the size of the two-dimensional array, the transistors may include vertical gate transistors.

[0049] Figure 5A is a perspective view of the semiconductor structure 1000 according to an exemplary embodiment of the present application. Figure 5B is a perspective view of a semiconductor structure of an embodiment.

[0050] Reference Figure 1 、 Figure 2 、 Figure 3 and Figure 5A and

[0051] In addition, the semiconductor structure 1000 may further include a source and a drain formed at two end portions of the semiconductor pillar 100 in the z direction, respectively, which can be understood as doped regions of the semiconductor pillar 100 and can also be referred to as a source electrode and a drain electrode. As an option, the source and the drain may be doped with any suitable p-type dopant, and the p-type dopant may include any one or combination of boron (B) or gallium (Ga). As another option, the source and the drain may be doped with any suitable n-type dopant, and the n-type dopant may include any one or combination of phosphorus (P), arsenic (As), and antimony (Sb).

[0052] In addition, the semiconductor structure 1000 may further include a gate 400 in contact with one or more sidewalls of the semiconductor pillar 100. For example, the gate 400 may be located on one of two opposite sidewalls of the semiconductor pillar 100 in the x direction. In other words, the gate 400 is formed between the source and the drain of the semiconductor structure 1000 in the z direction, and the source and the drain may be separated by the gate 400 in the z direction.

[0053] In addition, on this basis, the gate 400 may also be located on multiple sidewalls of the semiconductor pillar 100 to form a multi-gate vertical transistor, which is not limited in this application.

[0054] The bit line 200 of the semiconductor structure 1000 extends in the x direction and is connected to the bottoms 102 of multiple semiconductor pillars 100. The bit line 200 and the bit line isolation structure 300 are alternately arranged in the y direction. The air gap layer 321 included in the bit line isolation structure 300 can enhance the anti-interference effect of the bit line.

[0055] The bit line 200 and the gate 400 of the vertical transistor may extend in two mutually intersecting transverse directions, and the semiconductor pillar 100 also extends in a direction intersecting the two transverse directions along which the bit line 200 and the gate 400 extend. Therefore, with this arrangement of the vertical transistor, the bit line and the gate are arranged in different planes along the extension direction of the semiconductor pillar, simplifying the wiring of the bit line and the gate.

[0056] Optionally, the bit line 200 may be a composite structure, for example, including a first bit line layer 210 and a second bit line layer 220 stacked in the z direction. Optionally, the first bit line layer 210 is closer to the bottom 102 of the semiconductor pillar 100 than the second bit line layer 220, and the first bit line layer 210 may include but is not limited to silicon (e.g., single-crystalline silicon c-Si), silicon germanium (SiGe), gallium arsenide (GaAs), germanium (Ge), silicon on insulator (SOI), or any other suitable semiconductor material. The second bit line layer 220 may include but is not limited to tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), crystalline silicon, silicide, etc.

[0057] As Figure 5BAs shown, in one embodiment, taking a planar transistor as an example, it may include a substrate 100-1, where the substrate 100-1 may include a source electrode 100-2 and a drain electrode 100-3 of the planar transistor. In addition, the planar transistor further includes a gate 400' located between the source electrode 100-2 and the drain electrode 100-3, and a bit line 200' connected to the source electrode 100-2 or the drain electrode 100-3.

[0058] In at least one embodiment of the present application, a vertical transistor is used instead of a planar transistor as the transfer transistor of the memory cell, which can reduce the occupied area, coupling capacitance, and interconnect wiring complexity of the transfer transistor. In addition, different from the planar transistor that only includes a single planar gate, due to the three-dimensional structure of the semiconductor pillar 100 and the gates around the multiple sidewalls of the semiconductor pillar 100, more than one channel can be formed between the source and the drain during operation. Therefore, compared with the planar transistor, the multi-gate vertical transistor can have a larger gate control area to achieve better channel control with a smaller subthreshold swing.

[0059] In addition, in some embodiments, the semiconductor structure 1000 may further include a back gate (not shown), the back gate is located on at least one sidewall of the semiconductor pillar 100, and the sidewall of the semiconductor pillar 100 forming the back gate does not coincide with the sidewall of the semiconductor pillar 100 forming the gate 400. By applying a reference voltage (for example, a ground voltage) to the back gate of the semiconductor structure 1000, the interference between adjacent gates 400 in the semiconductor structure 1000 can be reduced.

[0060] However, as the feature size of semiconductor devices continues to shrink and the power consumption of semiconductor devices continues to decline, in semiconductor devices such as vertical transistors, the influence of coupling interference between bit lines becomes increasingly prominent.

[0061] To enhance the anti-interference ability of the bit line, a bit line isolation structure may be provided between adjacent bit lines, and an air gap may be provided in the bit line isolation structure. In addition, according to at least one embodiment of the present application, the air gap can be formed by the method of pre-burying a sacrificial layer from the front side of the intermediate during the preparation of the semiconductor structure, whereby the air gap can have a structure feature of being larger at the top and smaller at the bottom, and the structural consistency of multiple air gaps is improved, thus effectively improving the adverse effect of the difference in the air gap structure on the anti-interference performance.

[0062] Specifically, in combination with Figure 1 and Figure 3, in one embodiment of the present application, the dimensions h1 of the plurality of air gaps 321 in the z-direction are the same. In addition, as an option, the first ends 321-1 of the plurality of air gaps 321 may have the same height in the z-direction; as another option, the second ends 321-2 of the plurality of air gaps 321 may have the same height in the z-direction; as yet another option, the first ends 321-1 of the plurality of air gaps 321 may have the same height in the z-direction, and the second ends 321-2 of the plurality of air gaps 321 may have the same height in the z-direction. By improving the structural consistency of the plurality of air gaps, the adverse effects on the above anti-interference performance due to the differences in the air gap structures can be improved. It should be noted that limited by the process, the error range of the same dimensions of the plurality of air gaps in the z-direction can be between -10% and 10%. Similarly, the error range of the first ends of the plurality of air gaps having the same height in the z-direction, or the second ends of the plurality of air gaps having the same height in the z-direction can be between -10% and 10%.

[0063] Combined with Figure 1 and Figure 3 , in one embodiment of the present application, at least one of the plurality of bit line isolation structures 300 further includes an isolation dielectric layer 310, and the air gap 321 is surrounded by the isolation dielectric layer 310, where the isolation dielectric layer 310 may include a first dielectric layer 311 near the first end 321-1 of the air gap 321, a second dielectric layer 312 near the second end 321-2 of the air gap 321, and a third dielectric layer 313 located between the first dielectric layer 311 and the second dielectric layer 312.

[0064] In other words, the second dielectric layer 312 extends in a direction intersecting the z-direction (for example, the x-direction or the y-direction), and the air gap 321 may extend along the z-direction and towards the bottom 102 of the semiconductor column 100 to the second dielectric layer 312. The first dielectric layer 311 is located between adjacent semiconductor columns 100 and extends in the z-direction, and the air gap 321 may extend along the z-direction and towards the top 101 of the semiconductor column 100 to the first dielectric layer 311.

[0065] As an option, multiple air gaps 321 can all extend along the z direction and towards the bottom 102 of the semiconductor pillar 100 to the second dielectric layer 312; as another option, multiple air gaps 321 can all extend along the z direction and towards the top 101 of the semiconductor pillar 100 to the first dielectric layer 311; as yet another option, multiple air gaps 321 can all extend along the z direction and towards the bottom 102 of the semiconductor pillar 100 to the second dielectric layer 312, and multiple air gaps 321 can all extend along the z direction and towards the top 101 of the semiconductor pillar 100 to the first dielectric layer 311. Therefore, the first ends of the multiple air gaps being flush in the z direction or the second ends of the multiple air gaps being flush in the z direction can improve the structural consistency of the multiple air gaps and mitigate the adverse impact on the anti-interference performance due to the differences in the air gap structures.

[0066] In addition, the bit line 200 is located on the surface of the second dielectric layer 312 and extends along the x direction. In other words, the surface of the bit line 200 away from the top 101 of the semiconductor pillar 100 is in contact with the surface of the second dielectric layer. The surface of the bit line 200 away from the top 101 of the semiconductor pillar 100 is also flush with the second ends 321-2 of the multiple air gaps 321.

[0067] In addition, in an embodiment of the present application, the cross-section of the air gap 321 in a plane parallel to the z direction is trapezoidal in shape. As an option, the dimension of the air gap 321 in a direction intersecting the z direction (e.g., the x direction or the y direction) can gradually decrease from its first end 321-1 to its second end 321-2. The cross-sections of the multiple air gaps 321 in a plane parallel to the z direction can all be trapezoidal in shape with the same size. It should be noted that limited by the process, the error range of the cross-sections of the multiple air gaps being trapezoidal in shape with the same size in a plane parallel to the z direction can be between -10% and 10%.

[0068] As an option, the material of the second dielectric layer 312 can be different from the material of the first dielectric layer 311; as another option, the material of the second dielectric layer 312 can be different from the material of the third dielectric layer 313; as yet another option, the material of the second dielectric layer 312 can be different from the material of the first dielectric layer 311, and the material of the second dielectric layer 312 can be different from the material of the third dielectric layer 313.

[0069] In at least one embodiment of the present application, the air gap can be formed by pre-burying a sacrificial layer from the front side of the intermediate during the process of fabricating the semiconductor structure. After the front-side process is completed, the pre-buried sacrificial layer is removed from the back side of the intermediate to form an opening, and the second dielectric layer is used to quickly cover the opening and the surface of the bit line exposed on the back side. Therefore, the first dielectric layer 311, the second dielectric layer 312, and the third dielectric layer 313 included in the isolation dielectric layer 310 are formed in the above different manufacturing processes, and different manufacturing processes or materials can be adopted for formation.

[0070] In addition, since the air gap is formed by using the second dielectric layer to quickly cover the opening and the surface of the bit line exposed on the back side during the process of forming the air gap described above, in at least one embodiment of the present application, the surface of the bit line 200 away from the top 101 of the semiconductor pillar 100 and the second end 321-2 of the air gap 321 can have the same height in the z direction. It should be noted that limited by the process, the error range of the surface of the bit line away from the top of the semiconductor pillar and the second end of the air gap having the same height in the z direction can be between -10% and 10%.

[0071] In addition, in combination with Figures 1 - 4 , the bit line isolation structure 300 can include a first bit line isolation structure 301 and a second bit line isolation structure 302. The first bit line isolation structure 301 can include an isolation dielectric layer 310 and an air gap 321. The second bit line isolation structure 302 can include an isolation dielectric layer 310 and a filling dielectric layer 322 surrounded by the isolation dielectric layer 310, and the material of the filling dielectric layer 322 is different from the material of the isolation dielectric layer 310.

[0072] Optionally, the isolation dielectric layer surrounding the filling dielectric layer and the isolation dielectric layer including the air gap can have different layer structures, and the present application does not limit this.

[0073] As an option, the semiconductor structure 100 can include at least one storage area 12 formed with semiconductor pillars 100. The storage area 12 includes a first area 01 located at the edge of the storage area and a second area 02 different from the first area 01. Optionally, the second bit line isolation structure 302 can be located in the first area 01. In addition, as an option, the memory cells located in the first area 01 can be used for process and electrical buffering, and thus can also be referred to as pseudo memory cells.

[0074] Optionally, as described above, the air gap can be formed by pre-embedding a sacrificial layer from the front side of the intermediate during the preparation of the semiconductor structure, and after completing the front-side process, removing the pre-embedded sacrificial layer from the back side of the intermediate to form an opening, and quickly covering the opening and the surface of the bit line exposed on the back side with the second dielectric layer. During the process of removing the pre-embedded sacrificial layer, only a part of the pre-embedded sacrificial layer can be removed to form the air gap; and a part of the pre-embedded sacrificial layer that is retained is formed into a filling dielectric layer.

[0075] In addition, in combination with Figure 1 and Figure 3 , in at least one embodiment of the present application, the size h1 of the air gap 321 in the z direction can be designed according to the actual needs of the semiconductor structure 1000, and by controlling the size of the pre-embedded sacrificial layer in the z direction, the size h1 of the air gap 321 in the z direction can be adjusted. In other words, the size h1 of the air gap 321 in the z direction can be adjusted based on the size of the filling dielectric layer 322 in the z direction.

[0076] According to the semiconductor structure provided by at least one embodiment of the present application, the semiconductor structure includes semiconductor pillars, bit lines, and bit line isolation structures, wherein the bit lines are located on the back side of the semiconductor structure and are connected to a plurality of semiconductor pillars, and the bit line isolation structures are located between adjacent bit lines and can reduce interference between adjacent bit lines. In addition, in order to enhance the above anti-interference effect, the bit line isolation structure includes an air gap, wherein according to at least one embodiment of the present application, the air gap can be formed by the method of pre-embedding a sacrificial layer from the front side of the intermediate during the preparation of the semiconductor structure, whereby the air gap can have a structure feature of being larger at the top and smaller at the bottom, and the structural consistency of a plurality of air gaps is improved, thereby effectively improving the adverse effect of the difference in the air gap structure on the above anti-interference performance.

[0077] Some embodiments of the present application provide a method for preparing a semiconductor structure. Figure 6 is a flowchart of a method 2000 for preparing a semiconductor structure according to an exemplary embodiment of the present application. Figures 7 - 18 are respectively process schematic diagrams of a method 2000 for preparing a semiconductor structure according to an embodiment of the present application.

[0078] As Figure 6 shown, the method 2000 for preparing a semiconductor structure provided by the present application includes:

[0079] S1, forming semiconductor pillars extending along a first direction, wherein the semiconductor pillars include a top and a bottom opposite to each other in the first direction.

[0080] S2. Form bit lines and bit line isolation structures on the dorsal side near the bottom, where the bit lines extend along a second direction intersecting the first direction and connect the bottoms of multiple semiconductor pillars; multiple bit line isolation structures and multiple bit lines are alternately arranged in a third direction, and the third direction intersects the first direction and the second direction; and at least one of the multiple bit line isolation structures includes an air gap, and in a direction intersecting the first direction, the size of the first end of the air gap is larger than the size of its second end, where the first end is closer to the top relative to the second end.

[0081] The following will be combined with Figures 6 - 18 to detail the specific processes of each step of the above preparation method 2000 in Example 1.

[0082] Step S1

[0083] Figure 7 It is a cross-sectional schematic diagram of the structure formed after forming the initial semiconductor pillar 100' according to a preparation method of an embodiment of the present application. Figure 8 It is a cross-sectional schematic diagram of the structure formed after forming the initial third dielectric layer 313' according to a preparation method of an embodiment of the present application. Figure 9 It is a cross-sectional schematic diagram of the structure formed after forming the initial filling dielectric layer 322' according to a preparation method of an embodiment of the present application. Figure 10 It is a cross-sectional schematic diagram of the structure formed after forming the filling dielectric layer 322 according to a preparation method of an embodiment of the present application. Figure 11 It is a cross-sectional schematic diagram of the structure formed after forming the initial first dielectric layer 311' according to a preparation method of an embodiment of the present application. Figure 12 It is a cross-sectional schematic diagram of the structure formed after forming the first dielectric layer 311 according to a preparation method of an embodiment of the present application. Figure 13 It is a cross-sectional schematic diagram of the structure formed after flipping the intermediate 180° after the front-side process according to a preparation method of an embodiment of the present application. Figure 14 It is a cross-sectional schematic diagram of the structure formed after forming the semiconductor pillar 100 according to a preparation method of an embodiment of the present application.

[0084] As Figures 6 - 14 shown, step S1 forms semiconductor pillars extending along the first direction, where the semiconductor pillars include a top and a bottom opposite to each other in the first direction and may, for example, include: providing a substrate (not shown); and forming semiconductor pillars 100 extending along the first direction (z direction) on or in the substrate.

[0085] Specifically, forming the semiconductor pillar 100 may include: removing a portion of the substrate through, for example, an etching process, or selectively epitaxially growing on the substrate through, for example, an epitaxial process to form an initial semiconductor pillar 100'; and removing a portion of the initial semiconductor pillar 100' through, for example, an etching process to form the semiconductor pillar 100.

[0086] As an option, in an embodiment of the present application, the material for preparing the substrate may be selected from any suitable semiconductor material, for example, it may be single-crystalline silicon (Si), single-crystalline germanium (Ge), silicon germanium (GeSi), silicon carbide (SiC), silicon-on-insulator (SOI), germanium-on-insulator (GOI), or group III-V compounds such as gallium arsenide. As an option, the substrate may be selected as single-crystalline silicon.

[0087] In an embodiment of the present application, the substrate may be, for example, a composite substrate for supporting the device structure thereon. Multiple layers made of different materials may be sequentially provided through a thin-film deposition process such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof to form the substrate.

[0088] In an embodiment of the present application, the substrate may include a substrate sacrificial layer. Optionally, the substrate sacrificial layer may include a single layer, multiple layers, or a suitable composite layer. For example, the substrate sacrificial layer may include any one or more of a silicon oxide layer, a silicon nitride layer, and a silicon oxynitride layer. As an option, the substrate sacrificial layer may be a high-k dielectric layer. As another option, the substrate sacrificial layer may include a dielectric layer, a sacrificial layer, and a dielectric layer provided in sequence, where the dielectric layer may be a silicon nitride layer and the sacrificial layer may be a silicon oxide layer. As yet another option, the substrate sacrificial layer may include any one or more of a dielectric material, a semiconductor material, and a conductive material. For example, the sacrificial layer may be single-crystalline silicon or polycrystalline silicon. Specifically, in an embodiment of the present application, an exemplary material for forming the sacrificial layer may be polycrystalline silicon.

[0089] In addition, well regions formed by doping with an N-type or P-type dopant through an ion implantation or diffusion process may also be formed in some regions of the substrate. The dopant may include any one or combination of phosphorus (P), arsenic (As), and antimony (Sb); or any one or combination of boron (B), gallium (Ga), or indium (In). In some embodiments of the present application, the well regions may be prepared with the same dopant or different dopants. Further, the doping concentrations of the well regions may be the same or different, and the present application does not limit this.

[0090] As Figure 7As shown, after the substrate is formed, it can be formed by, for example, a dry etching process or a combination of dry and wet etching processes; in addition, other manufacturing processes can also be performed, such as patterning processes including lithography, cleaning, and chemical mechanical polishing, etc., to remove part of the substrate to form a plurality of initial semiconductor pillars 100' extending in the z direction. The initial semiconductor pillars 100' are located on the remaining substrate 100'-1 after the above treatment and extend in the z direction. The initial semiconductor pillars 100' include an initial top 101' and an initial bottom 102' that are opposite in the z direction.

[0091] For example, a patterned hard mask layer 123 can be covered on the substrate, and the substrate can be etched using the patterned hard mask layer 123 as a mask to remove the part of the substrate corresponding to the pattern of the patterned hard mask layer 123 and form the initial semiconductor pillars 100'. Optionally, the hard mask layer 123 can be a composite structure and include multiple layers stacked in the z direction, such as a silicon nitride layer, a silicon oxide layer, etc.

[0092] As another option, after the substrate is formed, the initial semiconductor pillars 100' can be formed by the SEG (Selective Epitaxial Growth) process. The process for epitaxially growing to form the initial semiconductor pillars 100' can include, but is not limited to: Vapor Phase Epitaxy (VPE), Liquid Phase Epitaxy (LPE), Molecular Beam Epitaxy (MPE), or any combination thereof. The material of the semiconductor pillars 100 can be at least one of silicon, silicon germanium, germanium, III-V compound materials, II-VI compound materials, organic semiconductor materials, and other suitable semiconductor materials. Among them, the initial semiconductor pillars 100' are located on the substrate and extend in the z direction. The initial semiconductor pillars 100' include an initial top 101' and an initial bottom 102' that are opposite in the z direction.

[0093] The initial semiconductor pillar 100' may extend above the top surface of the substrate or the remaining substrate 100'-1, exposing not only the top surface of the semiconductor pillar 100 but also one or more sidewalls of the initial semiconductor pillar 100'. In other words, the initial semiconductor pillar 100' further includes at least one sidewall located between the initial top 101' and the initial bottom 102'. For example, the initial semiconductor pillar 100' may have a cubic shape to expose its four sidewalls. However, those skilled in the art should understand that the initial semiconductor pillar 100' may have any suitable three-dimensional shape, such as a polyhedral shape or a cylindrical shape. In other words, the initial semiconductor pillar 100' may have a square shape, a rectangular shape, a trapezoidal shape, a circular shape, an oval shape, or any other suitable shape in a cross-section perpendicular to the z-direction. It should be understood that, consistent with the scope of the present application, for the initial semiconductor pillar 100' having a circular or oval-shaped cross-section in the above plane, the initial semiconductor pillar 100' can still be considered to have multiple sidewalls.

[0094] As Figures 7 - 14 shown, in some embodiments of the present application, the method 2000 for fabricating a semiconductor structure may further include forming a pre-buried sacrificial layer to facilitate the formation of an air gap in a subsequent in-situ line isolation structure, where the pre-buried sacrificial layer is hereinafter referred to as the filling dielectric layer 322.

[0095] Specifically, forming the filling dielectric layer 322 may include, for example: filling an initial filling dielectric layer 322' between adjacent initial semiconductor pillars 100'; removing a portion of the initial filling dielectric layer 322' to form the filling dielectric layer 322'; and removing a portion of the initial semiconductor pillar 100' to form the semiconductor pillar 100, where the filling dielectric layer 322 has a predetermined thickness h2 in the z-direction and adjusts the size of the subsequently formed air gap in the z-direction based on the predetermined thickness h2.

[0096] As an alternative, as Figure 7 and Figure 8 shown, an initial third dielectric layer 313' may be formed on the sidewalls of the initial semiconductor pillar 100' and on the portions of the substrate or the remaining substrate 100'-1 located between adjacent initial semiconductor pillars 100' through one or more thin film deposition processes, and the thin film deposition processes may include but are not limited to chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof.

[0097] Optionally, the initial third dielectric layer 313' may include any suitable dielectric material, for example, silicon oxide, silicon nitride, silicon oxynitride, or a high-k dielectric. For example, the initial third dielectric layer 313' may include silicon oxide.

[0098] As Figure 8 andFigure 9 As shown, after forming the initial third dielectric layer 313', an initial filling dielectric layer 322' can be formed on the surface of the initial third dielectric layer 313' through one or more thin film deposition processes. The thin film deposition processes can include, but are not limited to, chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof.

[0099] As an option, the initial filling dielectric layer 322' can be formed of a material with a high deposition rate to facilitate rapid filling, and the initial filling dielectric layer 322' can be any material that has a high dry etching selectivity relative to the initial third dielectric layer 313' to facilitate removal in subsequent steps. For example, the initial filling dielectric layer 322' can include a carbon-containing material layer.

[0100] As Figure 9 and Figure 10 shown, after forming the initial filling dielectric layer 322', it can be formed through, for example, a dry etching process or a combination of dry and wet etching processes; in addition, other manufacturing processes can also be performed, such as patterning processes including lithography, cleaning, and chemical mechanical polishing, etc., to remove a part of the initial filling dielectric layer 322' from the front side 1001 of the intermediate body to form the filling dielectric layer 322. The filling dielectric layer 322 has a predetermined thickness h2 in the z direction, and the size of the subsequently formed air gap in the z direction can be adjusted based on the predetermined thickness h2.

[0101] As Figures 10 - 12 shown, after forming the filling dielectric layer 322, a first dielectric layer 311 can be formed on the filling dielectric layer 322, and the remaining space located between adjacent initial semiconductor pillars 100' can be filled with the first dielectric layer 311. Specifically, as Figures 10 - 11 shown, an initial first dielectric layer 311' can be formed on the surface of the filling dielectric layer 322 and the exposed surface of the initial third dielectric layer 313' through one or more thin film deposition processes. The thin film deposition processes can include, but are not limited to, chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof.

[0102] The initial first dielectric layer 311' can include any suitable dielectric material, for example, silicon oxide, silicon nitride, silicon oxynitride, or a high-k dielectric. For example, the initial third dielectric layer 313' can include silicon oxide.

[0103] As Figures 11 - 12As shown, after forming the initial first dielectric layer 311', it can be formed by, for example, a dry etching process or a combination of dry and wet etching processes; in addition, other manufacturing processes can also be performed, such as patterning processes including lithography, cleaning, and chemical mechanical polishing, etc., to remove a part of the initial first dielectric layer 311' to form the first dielectric layer 311.

[0104] In addition, the first dielectric layer 311 and the part of the initial third dielectric layer 313' located at the initial top 101' of the initial semiconductor pillar 100' (hereinafter referred to as the top part of the initial third dielectric layer 313') can be processed by any suitable technique for planarization, such as front grinding and / or chemical mechanical polishing, etc., so that the processed first dielectric layer 311 and the top part of the initial third dielectric layer 313' have a flat coplanar surface.

[0105] In addition, during the formation of the first dielectric layer 311, it can also be formed by, for example, a dry etching process or a combination of dry and wet etching processes; in addition, other manufacturing processes can also be performed, such as patterning processes including lithography, cleaning, and chemical mechanical polishing, etc., to remove the remaining hard mask layer 123 after being used in the process of forming the initial semiconductor pillar 100'.

[0106] In some embodiments of the present application, after forming the first dielectric layer 311, the method 2000 for preparing a semiconductor structure may further include: forming source and drain electrodes at the initial top 101' and the initial bottom 102' of the initial semiconductor pillar 100'; and forming a gate (not shown) on at least one sidewall of the initial semiconductor pillar 100'. It should be noted that the formation of the above structures can all be completed on the front side 1001 of the intermediate shown, and thus can also be called the front side process in the method 2000 for preparing a semiconductor structure. Figure 12 As shown, it can be completed on the front side 1001 of the intermediate shown, and thus can also be called the front side process in the method 2000 for preparing a semiconductor structure.

[0107] Specifically, as an option, the source and drain electrodes can be doped with any suitable P-type dopant, and the P-type dopant can include any one or a combination of boron (B) or gallium (Ga). As another option, the source and drain electrodes can be doped with any suitable N-type dopant, and the N-type dopant can include any one or a combination of phosphorus (P), arsenic (As), and antimony (Sb).

[0108] Optionally, the method of doping to form the source and drain electrodes in the form of ions of conductive impurities can be, for example, ion implantation or ion diffusion, and the present application does not limit this.

[0109] In addition, a source electrode can be formed on the initial top 101' of the initial semiconductor column 100', and a drain electrode can be formed on the initial bottom 102' of the initial semiconductor column 100'; alternatively, a drain electrode can be formed on the initial top 101' of the initial semiconductor column 100', and a source electrode can be formed on the initial bottom 102' of the initial semiconductor column 100'. This application does not make any limitations in this regard. In subsequent steps, the bottom of the semiconductor column formed from the initial semiconductor column 100' can be connected to the bit line, and the top of the semiconductor column can be connected to the storage cell.

[0110] In addition, a gate electrode can be formed on at least one sidewall of the initial semiconductor column 100'. For example, a gate electrode is formed on one of the two opposite sidewalls of the initial semiconductor column 100' in the x direction. The gate electrode can be a composite structure. For example, the gate electrode can include a gate dielectric layer (not shown), a gate adhesion layer (not shown), and a gate conductive layer (not shown).

[0111] As an option, the gate electrode can be formed by one or more thin film deposition processes, and the thin film deposition processes can include but are not limited to chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination of thin film deposition processes or any combination thereof.

[0112] Optionally, the gate dielectric layer can include any suitable dielectric material. For example, silicon oxide, silicon nitride, silicon oxynitride, or high-k dielectrics. For example, the gate dielectric layer can include silicon oxide. In addition, the gate adhesion layer can include but is not limited to titanium, titanium nitride, tantalum, tantalum nitride, etc. Additionally, the gate conductive layer can include any suitable conductive material. For example, the gate conductive layer can include but is not limited to tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), crystalline silicon, silicide, etc. The gate adhesion layer is used to block the diffusion of metal materials in the gate conductive layer and also to improve the adhesion between the gate conductive layer and the gate dielectric layer.

[0113] In addition, in one embodiment of this application, a back gate (not shown) can also be formed on at least one sidewall of the initial semiconductor column 100' by one or more thin film deposition processes. The sidewall of the initial semiconductor column 100' where the back gate is formed does not coincide with the sidewall of the initial semiconductor column 100' where the gate electrode is formed. By applying a reference voltage (e.g., ground voltage) to the back gate, the interference between adjacent gate electrodes in the subsequently formed semiconductor structure can be reduced.

[0114] As an option, the back gate can be formed by one or more thin film deposition processes, and the thin film deposition processes can include but are not limited to chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination of thin film deposition processes or any combination thereof.

[0115] Optionally, the back gate may be a composite structure. For example, the back gate may include a back gate dielectric layer (not shown) and a back gate conductive layer (not shown). The back gate dielectric layer may include any suitable dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride, or a high-k dielectric. For example, the back gate dielectric layer may include silicon oxide. In addition, the back gate conductive layer may include, but is not limited to, titanium, titanium nitride, tantalum, tantalum nitride, etc.

[0116] Combined with Figure 12 and Figure 13 , as described above, the air gap of the bit line isolation structure can be formed by pre-burying a filling dielectric layer 322 from the front side 1001 of the intermediate body during the preparation of the semiconductor structure, and after completing the front side process, removing the pre-buried filling dielectric layer 322 from the back side 1002 of the intermediate body to form an opening, and then quickly covering the opening and the surface of the bit line exposed on the back side with a second dielectric layer. Among them, the front side process may include the process steps of forming the source electrode, drain electrode, forming the gate, and forming the back gate described above.

[0117] In some embodiments, the air gap may also be directly formed on the back side 1002 of the intermediate body after completing the above front side process. For example, an initial bit line covering the back side 1002 may be formed on the back side 1002 of the intermediate body through one or more thin film deposition processes. The thin film deposition processes may include, but are not limited to, chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination of thin film deposition processes. After forming the initial bit line, other manufacturing processes may be performed, such as patterning processes including lithography, cleaning, and chemical mechanical polishing, etc., to remove part of the initial bit line to form a bit line and an opening alternately arranged with the bit line. Then, a bit line isolation structure may be formed in the opening through one or more thin film deposition processes. The thin film deposition processes may include, but are not limited to, chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination of thin film deposition processes. The bit line isolation structure may include an isolation dielectric layer and an air gap surrounded by the isolation dielectric layer.

[0118] However, the process of directly forming an air gap on the back side of the intermediate body is likely to cause damage to the already formed gate or back gate structures, etc., thereby affecting the functions of the gate or back gate structures, etc. In addition, affected by the already formed gate or back gate structures, etc., the consistency of the air gap directly formed on the back side of the intermediate body is not high, and the structural differences of the air gap are relatively large. The relatively large structural differences will reduce the anti-interference performance of the air gap.

[0119] For example, multiple formed gates or multiple back gates can all extend from the front side to the back side of the intermediate body along the z direction, and the multiple gates or multiple back gates can have different heights in the z direction. In addition, the multiple formed gates or multiple back gates can also have different extension dimensions in a plane perpendicular to the z direction. Therefore, in the process of forming bit lines and openings alternately arranged with the bit lines on the back side of the above intermediate body, the multiple openings may have multiple different extension dimensions in the z direction, which may cause the ends of the multiple subsequently formed air gaps to have different heights in the z direction; in addition, the multiple openings may also have multiple different extension dimensions in a plane perpendicular to the z direction, which may cause the sizes of the subsequently formed air gaps to be inconsistent. These structural differences in the air gaps will all reduce the anti-interference performance of the air gaps.

[0120] Therefore, by forming air gaps in the way of pre-embedding a filling dielectric layer from the front side of the intermediate body during the preparation of the semiconductor structure, the air gaps can have the structural feature of being larger at the top and smaller at the bottom, and the structural consistency of the multiple air gaps is improved, thereby effectively improving the adverse effects on the anti-interference performance due to the structural differences of the air gaps.

[0121] Specifically, as Figure 13 and Figure 14 shown, it can be formed by, for example, a dry etching process or a combination of dry and wet etching processes; in addition, other manufacturing processes can also be performed, such as a patterning process including photolithography, cleaning, and chemical mechanical polishing, etc., to remove a part of the initial semiconductor column 100' from Figure 13 the back side 1002 of the intermediate body shown, to form the semiconductor column 100. Optionally, the initial third dielectric layer 313' can be used as the stop layer for this removal process.

[0122] Step S2

[0123] Figure 15 FIG. is a cross-sectional schematic view of the structure formed after forming the hard mask layer 124 according to a preparation method of an embodiment of the present application. Figure 16 FIG. is a cross-sectional schematic view of the structure formed after forming the opening 125 according to a preparation method of an embodiment of the present application. Figure 17 FIG. is a cross-sectional schematic view of the structure formed after forming the bit line 200 according to a preparation method of an embodiment of the present application. Figure 18 FIG. is a cross-sectional schematic view of the structure formed after forming the air gap 321 according to a preparation method of an embodiment of the present application.

[0124] As Figures 14 - 18As shown, step S2 forms bit lines 200 on the back side 1002 near the bottom 102. The bit line isolation structure 300 may include, for example: after removing a part of the filling dielectric layer 322 to form an opening 125, forming bit lines 200 at the bottom 102 of a plurality of semiconductor pillars 100 arranged in the x direction; and using a second dielectric layer 312 to seal the opening 125 to form a bit line isolation structure 300 including a void gap 321.

[0125] Specifically, as Figures 14 - 18 shown, in some embodiments of the present application, after the front side process is completed, a part of the filling dielectric layer 322 may be removed from the back side 1002 to form an air gap 321.

[0126] Figure 15 The intermediate shown may include a storage area 12. The storage area 12 includes a first area 01 located at the edge of the storage area and a second area 02 different from the first area 01. Optionally, a patterned hard mask layer 124 may be provided on the back side 1002 of the intermediate. The patterned hard mask layer 124 may cover a part of the intermediate located in the first area 01, so that the filling dielectric layer 322 located in the first area 01 is not removed. Optionally, in the finally formed semiconductor structure, the memory cells in the first area 01 can be used for process and electrical buffering, and thus can also be called pseudo memory cells.

[0127] As an option, as Figure 15 and Figure 16 shown, it is formed by, for example, a dry etching process or a combination of dry and wet etching processes; in addition, other manufacturing processes may also be performed, such as patterning processes including lithography, cleaning, and chemical mechanical polishing, etc., to remove from Figure 15 the back side 1002 of the intermediate shown the part of the filling dielectric layer 322 not covered by the hard mask layer 124 and the corresponding part of the initial third dielectric layer 313', forming an opening 125. Wherein, after a part of the initial third dielectric layer 313' is removed, the remaining part of the initial third dielectric layer 313' is formed into a third dielectric layer 313.

[0128] As Figure 16 and Figure 17 shown, after the opening 125 is formed, it can be at Figure 16The back side 1002 of the shown intermediate forms bit lines 200 connected to a plurality of semiconductor pillars 100 arranged in the x direction. As an option, the bit lines 200 can be formed at the bottom 102 of the semiconductor pillars 100 through one or more thin film deposition processes. The bit lines 200 can be a composite structure. For example, the bit lines 200 can include a first bit line layer (not shown) and a second bit line layer (not shown) stacked in the z direction. Optionally, the first bit line layer is closer to the bottom 102 of the semiconductor pillars 100 than the second bit line layer. The first bit line layer can include, but is not limited to, silicon (e.g., single crystal silicon c-Si), silicon germanium (SiGe), gallium arsenide (GaAs), germanium (Ge), silicon on insulator (SOI), or any other suitable semiconductor material. The second bit line layer can include, but is not limited to, tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), crystalline silicon, silicide, etc.

[0129] Optionally, as Figure 17 and Figure 18 shown, after forming the bit lines 200, a second dielectric layer 312 can be used to cover the surface of the bit lines 200 and seal the opening 125 through a rapid deposition process with a relatively fast deposition rate to form a bit line isolation structure 300 including a void gap 312. Optionally, the deposition rate of forming the second dielectric layer 312 is greater than the deposition rate of forming at least one of the first dielectric layer 311 and the third dielectric layer 313.

[0130] In addition, as an option, the material of the second dielectric layer 312 is different from the material of the first dielectric layer 311; as another option, the material of the second dielectric layer 312 is different from the material of the third dielectric layer 313; as yet another option, the material of the second dielectric layer 312 is different from the material of the first dielectric layer 311, and the material of the second dielectric layer 312 is different from the material of the third dielectric layer 313.

[0131] Optionally, the material of the second dielectric layer 312 can include at least one of silicon element, carbon element, oxygen element, and hydrogen element.

[0132] The bit line isolation structure 300 can include a first bit line isolation structure 301 and a second bit line isolation structure 302. The first bit line isolation structure 301 can include an isolation dielectric layer 310 and an air gap 321. The second bit line isolation structure 302 can include an isolation dielectric layer 310 and a filling dielectric layer 322 surrounded by the isolation dielectric layer 310, and the material of the filling dielectric layer 322 is different from the material of the isolation dielectric layer 310.

[0133] Optionally, the isolation dielectric layer 310 of the first bit line isolation structure 301 may include a first dielectric layer 311 near the first end 321-1 of the air gap 321, a second dielectric layer 312 near the second end 321-2 of the air gap 321, and a third dielectric layer 313 located between the first dielectric layer 311 and the second dielectric layer 312.

[0134] Optionally, the isolation dielectric layer 310 of the first bit line isolation structure 301 may include a first dielectric layer 311 near the first end 321-1 of the air gap 321, a third dielectric layer 313 surrounding the remaining part of the air gap 321 except the first end 321-1, and a second dielectric layer 312 covering the third dielectric layer 313.

[0135] A method for manufacturing a semiconductor structure according to at least one embodiment of the present application, the semiconductor structure includes semiconductor pillars, bit lines, and bit line isolation structures, wherein the bit lines are located on the back side of the semiconductor structure and are connected to a plurality of semiconductor pillars, and the bit line isolation structures are located between adjacent bit lines and can reduce interference between adjacent bit lines. To enhance the above anti-interference effect, the bit line isolation structure includes an air gap, wherein according to at least one embodiment of the present application, the air gap can be formed by pre-burying a sacrificial layer from the front side of the intermediate during the process of manufacturing the semiconductor structure, whereby the air gap can have a structure feature of being larger at the top and smaller at the bottom, and the structural consistency of a plurality of air gaps is improved, thereby effectively improving the adverse effect on the above anti-interference performance due to the difference in the air gap structure.

[0136] In addition, Figure 19 is a schematic structural diagram of a storage system 30000 according to an embodiment of the present application.

[0137] As Figure 19 shown, at least one embodiment of another aspect of the present application further provides a storage system 30000. The storage system 30000 may include a semiconductor structure 20000 and a controller 32000. The semiconductor structure 20000 may be the same as the semiconductor structure described in any of the above embodiments, and the present application will not elaborate on this. The semiconductor structure 20000 may be a two-dimensional semiconductor structure or a three-dimensional semiconductor structure, or even a part of a two-dimensional semiconductor structure or a part of a three-dimensional semiconductor structure. Hereinafter, a three-dimensional semiconductor structure will be taken as an example for illustration.

[0138] As an option, the three-dimensional semiconductor structure may include at least one of a three-dimensional NAND memory and a three-dimensional NOR memory.

[0139] The storage system 30000 may include a semiconductor structure 20000 and a controller 32000. The semiconductor structure 20000 may be the same as the semiconductor structures described in any of the above embodiments, and details thereof will not be described herein again. The controller 32000 may control the semiconductor structure 20000 through a channel CH, and the semiconductor structure 20000 may perform operations in response to requests from a host 31000 based on the control of the controller 32000. The semiconductor structure 20000 may receive a command CMD and an address ADDR from the controller 32000 through the channel CH and access a region selected from a memory cell array in response to the address. In other words, the semiconductor structure 20000 may perform internal operations corresponding to the command on the region selected by the address.

[0140] In some embodiments, a three-dimensional storage system may be implemented as a storage device in the form of, for example, a Universal Flash Storage (UFS) device, a Solid State Drive (SSD), a multimedia card in the form of an MMC, eMMC, RS-MMC, and micro MMC, a Secure Digital card in the form of an SD, mini SD, and micro SD, a storage device of a Personal Computer Memory Card International Association (PCMCIA) card type, a storage device of a Peripheral Component Interconnect (PCI) type, a storage device of a High-Speed PCI (PCI-E) type, a Compact Flash (CF) card, a Smart Media card, or a Memory Stick. Since the semiconductor structure provided in the present application is provided, the storage system provided in the present application has the same beneficial effects as the semiconductor structure, and details thereof will not be described herein.

[0141] Although exemplary methods of manufacturing and structures of the semiconductor structure are described herein, it is understood that one or more features may be omitted, substituted, or added from the structure of the semiconductor structure. In addition, the materials of the exemplified layers are merely exemplary.

[0142] The above description is only a preferred embodiment of the present application and an explanation of the applied technical principles. Those skilled in the art should understand that the scope of protection involved in the present application is not limited to the technical solutions formed by the selected combination of the above technical features, and should also cover other technical solutions formed by any combination of the above technical features or their equivalent features without departing from the technical concept. For example, technical solutions formed by mutually replacing the above features with (but not limited to) technical features having similar functions disclosed in the present application.

Claims

1. A semiconductor structure, characterized in that, Comprising: A semiconductor pillar extending along a first direction and including a top and a bottom opposite to each other in the first direction; A bit line extending in a second direction intersecting the first direction and connecting the bottoms of a plurality of the semiconductor pillars; And A bit line isolation structure, in a third direction intersecting the first direction and the second direction, a plurality of the bit line isolation structures and a plurality of the bit lines are alternately arranged, Wherein, at least one of the plurality of bit line isolation structures includes an air gap, in a direction intersecting the first direction, a first end size of the air gap is larger than a second end size thereof, and the first end is closer to the top than the second end.

2. The semiconductor structure according to claim 1, wherein, The plurality of air gaps have the same size in the first direction.

3. The semiconductor structure according to claim 1, wherein, A surface of the bit line away from the top and the second end have the same height in the first direction.

4. The semiconductor structure according to claim 1, wherein, The first ends of the plurality of air gaps have the same height in the first direction; And / or The second ends of the plurality of air gaps have the same height in the first direction.

5. The semiconductor structure according to claim 1, wherein, At least one of the plurality of bit line isolation structures further includes an isolation dielectric layer, the air gap is surrounded by the isolation dielectric layer, wherein the isolation dielectric layer includes a first dielectric layer close to the first end, a second dielectric layer close to the second end, and a third dielectric layer located between the first dielectric layer and the second dielectric layer, Wherein, a material of the second dielectric layer is different from a material of the first dielectric layer; and / or The material of the second dielectric layer is different from the material of the third dielectric layer.

6. The semiconductor structure according to claim 1, wherein, At least one of the plurality of bit line isolation structures further includes an isolation dielectric layer, the air gap is surrounded by the isolation dielectric layer, and a plurality of the bit line isolation structures include a first bit line isolation structure and a second bit line isolation structure, Wherein, the first bit line isolation structure includes the air gap; and The second bit line isolation structure includes the isolation dielectric layer and a filling dielectric layer surrounded by the isolation dielectric layer, and a material of the filling dielectric layer is different from a material of the isolation dielectric layer.

7. The semiconductor structure according to claim 6, wherein, The semiconductor structure includes at least one storage region formed with the semiconductor pillar, the storage region includes a first region located at an edge of the storage region and a second region different from the first region, Wherein, the second bit line isolation structure is located in the first region.

8. The semiconductor structure according to claim 6, wherein, The size of the air gap in the first direction is adjusted based on the size of the filling dielectric layer in the first direction.

9. The semiconductor structure according to claim 1, wherein, The size of the air gap in a direction intersecting the first direction gradually decreases from the first end to the second end.

10. The semiconductor structure according to any one of claims 1-9, wherein, The semiconductor structure further includes a gate, Wherein, the semiconductor pillar further includes sidewalls located between the top and the bottom, and the gate is located on at least one of the plurality of sidewalls.

11. The semiconductor structure according to any one of claims 1-9, wherein, The bit line includes a first bit line layer and a second bit line layer stacked in the first direction, Wherein, the first bit line layer is closer to the bottom relative to the second bit line layer, and the first bit line layer includes a semiconductor material layer.

12. A method for preparing a semiconductor structure, characterized in that, The method includes: Forming a semiconductor pillar extending in a first direction, wherein the semiconductor pillar includes a top and a bottom opposite to each other in the first direction; and Forming a bit line and a bit line isolation structure on the back side near the bottom, Wherein, the bit line extends in a second direction intersecting the first direction and connects the bottoms of a plurality of the semiconductor pillars; A plurality of the bit line isolation structures are alternately arranged with a plurality of the bit lines in a third direction, and the third direction intersects the first direction and the second direction; and At least one of the plurality of bit line isolation structures includes an air gap, and in a direction intersecting the first direction, a size of a first end of the air gap is larger than a size of a second end thereof, wherein the first end is closer to the top relative to the second end.

13. The method according to claim 12, wherein, Forming the air gap includes: Forming a filling dielectric layer between adjacent semiconductor pillars from the front side near the top; and After completing the front side process, removing a part of the filling dielectric layer from the back side to form the air gap.

14. The method according to claim 13, wherein, Forming a bit line and a bit line isolation structure on the back side near the bottom includes: After removing a part of the filling dielectric layer to form an opening, forming the bit line at the bottoms of a plurality of semiconductor pillars arranged in the second direction; and Closing the opening with a second dielectric layer to form the bit line isolation structure including the void gap.

15. The method according to claim 14, wherein, Closing the opening with a second dielectric layer includes: Forming the second dielectric layer covering a surface of the bit line away from the top and the opening, Wherein, the surface of the bit line away from the top and the second end of the air gap have the same height in the first direction.

16. The method according to claim 14, wherein, Forming a semiconductor pillar extending in a first direction includes forming an initial semiconductor pillar extending in the lower direction, and forming a filling dielectric layer between adjacent semiconductor pillars includes: Filling an initial filling dielectric layer between adjacent initial semiconductor pillars; Removing a part of the initial filling dielectric layer to form the filling dielectric layer; and Removing a part of the initial semiconductor pillar to form the semiconductor pillar, Wherein, the filling dielectric layer has a predetermined thickness in the first direction, and adjusts a size of the air gap in the first direction based on the predetermined thickness.

17. The method according to claim 16, wherein, The method further includes: Before forming the initial filling dielectric layer, forming a third dielectric layer between adjacent initial semiconductor pillars, wherein the third dielectric layer is at least located on sidewalls of the initial semiconductor pillars; and After forming the filling dielectric layer, forming a first dielectric layer on the filling dielectric layer, Wherein, the formation rate of the second dielectric layer is greater than the formation rate of at least one of the first dielectric layer and the third dielectric layer.

18. The method according to claim 17, wherein the material of the second dielectric layer is different from the material of the first dielectric layer; and / or the material of the second dielectric layer is different from the material of the third dielectric layer.

19. The method according to claim 14, wherein the material of the second dielectric layer contains at least one of silicon element, carbon element, oxygen element and hydrogen element.

20. A memory system, characterized in that, Comprising: at least one semiconductor structure according to any one of claims 1-11; and a controller, coupled to the semiconductor structure and configured to control the semiconductor structure to store data.

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