Semiconductor device

Abstract

A semiconductor device includes: a first chip structure; and a second chip structure on the first chip structure. The first chip structure includes: a base substrate; a memory structure on the base substrate; a first substrate on the memory structure; a first through via penetrating the first substrate; a first wiring structure disposed on the first substrate; a first bonding pad on an upper surface of the first wiring structure; and a hydrogen-containing insulating layer disposed in a region adjacent to the memory structure in the first chip structure. The second chip structure comprises a second substrate; a peripheral circuit transistor and a lower wiring structure disposed on a lower surface of the second substrate; second bonding pads electrically connected to the lower wiring structure and bonded to the first bonding pads, respectively; and an upper wiring structure.

Description

Technical Field

[0001] Some implementations of the present disclosure provide a semiconductor device having improved reliability and a method of manufacturing the same. Background Art

[0002] With the development of the electronics industry, the demand for high reliability, high speed, and / or multi-functionality of semiconductor devices has increased. To meet such characteristics, the structures in semiconductor devices have become complex, and semiconductor devices have become highly integrated. Summary of the Invention

[0003] According to some implementations, a semiconductor device includes: a first chip structure; and a second chip structure on the first chip structure, wherein the first chip structure includes: a base substrate; a memory structure disposed on the base substrate; a first substrate disposed on the memory structure; a first through via penetrating the first substrate and electrically connected to the memory structure; a first wiring structure disposed on the first substrate and including a first wiring layer electrically connected to the memory structure through the first through via; a first bonding pad disposed on an upper surface of the first wiring structure and electrically connected to the first wiring layer; and a hydrogen-containing insulating layer disposed in a region adjacent to the memory structure in the first chip structure, wherein the second chip structure includes: a second substrate; peripheral circuit transistors disposed on a lower surface of the second substrate; a lower wiring structure disposed on the lower surface of the second substrate and including a lower wiring layer electrically connected to the peripheral circuit transistors; a second bonding pad disposed on a lower surface of the lower wiring structure, electrically connected to the lower wiring layer, and respectively bonded to the first bonding pad; a second through via penetrating the second substrate and electrically connected to the lower wiring layer; and an upper wiring structure disposed on an upper surface of the second substrate and having an upper wiring layer electrically connected to the lower wiring layer through the second through via.

[0004] According to some implementations, a semiconductor device includes: a first chip structure; and a second chip structure on the first chip structure, wherein the first chip structure includes: a base substrate having an upper surface on which a hydrogen-containing insulating layer is provided; a memory structure disposed on the base substrate and adjacent to the hydrogen-containing insulating layer; a first wiring structure disposed on the memory structure and including a first wiring layer electrically connected to the memory structure; and a first bonding pad disposed on an upper surface of the first wiring structure and electrically connected to the first wiring layer, wherein the second chip structure includes: a second substrate; peripheral circuit transistors disposed on a lower surface of the second substrate; a lower wiring structure disposed on the lower surface of the second substrate, including a lower wiring layer electrically connected to the peripheral circuit transistors, and bonded to the first wiring structure; a second bonding pad disposed on a lower surface of the lower wiring structure, electrically connected to the lower wiring layer, and respectively bonded to the first bonding pad; a second via penetrating the second substrate and electrically connected to the lower wiring layer; and an upper wiring structure disposed on an upper surface of the second substrate and including an upper wiring layer electrically connected to the lower wiring layer through the second via.

[0005] According to some implementations, a semiconductor device includes: a second chip structure; and a first chip structure on the second chip structure, wherein the second chip structure includes: a base substrate; a second substrate having a lower surface opposite to an upper surface of the base substrate; peripheral circuit transistors disposed on the lower surface of the second substrate; a second lower wiring structure disposed between an upper surface of the base substrate and the lower surface of the second substrate and including a second lower wiring layer electrically connected to the peripheral circuit transistors; a second via penetrating the second substrate and electrically connected to the second lower wiring layer; a second upper wiring structure disposed on the upper surface of the second substrate and having a second upper wiring layer electrically connected to the second lower wiring layer through the second via; a second bonding pad disposed on an upper surface of the second upper wiring structure and electrically connected to the second upper wiring layer, wherein the first chip structure includes: a first substrate having an upper surface on which a hydrogen-containing insulating layer is provided; a memory structure disposed on a lower surface of the first substrate; a first lower wiring structure disposed on a lower surface of the memory structure, including a first lower wiring layer electrically connected to the memory structure, and bonded to the second upper wiring structure; a first bonding pad disposed on a lower surface of the first lower wiring structure, electrically connected to the first lower wiring layer and respectively bonded to the second bonding pad; a first via penetrating the first substrate and electrically connected to the memory structure; and a first upper wiring structure disposed on the first substrate and having a first upper wiring layer electrically connected to the memory structure through the first via.

[0006] According to some implementations, a method of manufacturing a semiconductor device includes: forming a memory structure on a first substrate; preparing a base substrate having an upper surface on which a hydrogen-containing insulating layer is provided; initially bonding the memory structure together with the first substrate to the upper surface of the base substrate; grinding the first substrate after the initial bonding; forming a first through-via that penetrates the first substrate and is electrically connected to the memory structure; forming a first wiring structure on the first substrate, the first wiring structure including a first wiring layer electrically connected to the first through-via; forming a first bonding pad on the upper surface of the first wiring structure, the first bonding pad being electrically connected to the first wiring layer; forming peripheral circuit transistors and a lower wiring structure on a second substrate, where the lower wiring structure includes a lower wiring layer electrically connected to the peripheral circuit transistors; forming a second bonding pad on the lower surface of the lower wiring structure, the second bonding pad being electrically connected to the lower wiring layer; secondarily bonding the upper surface of the lower wiring structure to the upper surface of the first wiring structure by bonding the first bonding pad to the second bonding pad; forming a second through-via that penetrates the second substrate and is electrically connected to the lower wiring layer; and forming an upper wiring structure on the second substrate, the upper wiring structure including an upper wiring layer electrically connected to the second through-via.

[0007] According to some implementations, a method of manufacturing a semiconductor device includes: forming a memory structure on a first substrate; forming a first lower wiring structure on the memory structure, the first lower wiring structure including a first lower wiring layer electrically connected to the memory structure; forming a first bonding pad on the lower surface of the first lower wiring structure, the first bonding pad being electrically connected to the first lower wiring layer; forming peripheral circuit transistors and a second lower wiring structure on a second substrate, where the second lower wiring structure includes a second lower wiring layer electrically connected to the peripheral circuit transistors; initially bonding the second lower wiring structure together with the second substrate on which the peripheral circuit transistors are formed to the upper surface of a base substrate; grinding the second substrate after the initial bonding; forming a second through-via that penetrates the second substrate and is electrically connected to the second lower wiring layer; forming a second upper wiring structure on the second substrate, the second upper wiring structure including a second upper wiring layer electrically connected to the second through-via; forming a second bonding pad on the upper surface of the second upper wiring structure, the second bonding pad being electrically connected to the second upper wiring layer; secondarily bonding the lower surface of the first lower wiring structure to the upper surface of the second upper wiring structure by bonding the first bonding pad to the second bonding pad; grinding the first substrate after the secondary bonding; forming a hydrogen-containing insulating layer on the ground surface of the first substrate; forming a first through-via that penetrates the first substrate and is electrically connected to the first lower wiring layer; and forming a first upper wiring structure on the first substrate, the first upper wiring structure including a first upper wiring layer electrically connected to the first through-via. Description of the Drawings

[0008] The above and other aspects, features, and advantages of the present disclosure will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0009] Figure 1Ais a perspective view showing a semiconductor device according to some implementations of the present disclosure;

[0010] Figure 1B is showing Figure 1A a plan view of a part of a bank in;

[0011] Figure 2A is a cross-sectional view showing a semiconductor device according to some implementations of the present disclosure;

[0012] Figure 2B is Figure 2A a graph of the hydrogen content distribution of the semiconductor device in according to the stacking direction;

[0013] Figure 3 is showing Figure 2A a magnified view of part "A1" of the semiconductor device in;

[0014] Figure 4A and Figure 4B is showing Figure 2A a magnified view of an example of part "A2" of the semiconductor device in;

[0015] Figure 5A and Figure 5B is a plan view showing a base substrate;

[0016] Figure 6A is a cross-sectional view showing a semiconductor device according to some implementations of the present disclosure;

[0017] Figure 6B is Figure 6A a graph of the hydrogen content distribution of the semiconductor device in according to the stacking direction;

[0018] Figure 7 is showing Figure 6A a magnified view of part "B" of the semiconductor device in;

[0019] Figure 8 is a cross-sectional view showing a semiconductor device according to some implementations of the present disclosure;

[0020] Figure 9 is a flowchart showing a method of manufacturing a semiconductor device according to some implementations of the present disclosure;

[0021] Figures 10A to 10D is a cross-sectional view showing a process of manufacturing a lower chip structure according to some implementations of the present disclosure;

[0022] Figure 11A and Figure 11B is a cross-sectional view showing a process of manufacturing an upper chip structure according to some implementations of the present disclosure;

[0023] Figures 12A to 12C is a cross-sectional view showing a bonding process and a wiring structure according to some implementations of the present disclosure;

[0024] Figures 13A to 13D is a cross-sectional view showing a process of a method for manufacturing a semiconductor device according to some implementations of the present disclosure;

[0025] Figure 14 is a flowchart showing a method for manufacturing a semiconductor device according to some implementations of the present disclosure;

[0026] Figures 15A to 15E is a cross-sectional view showing a process of manufacturing a semiconductor device according to some implementations of the present disclosure;

[0027] Figure 16 is a cross-sectional view showing a semiconductor device according to some implementations of the present disclosure;

[0028] Figures 17A to 17C is a cross-sectional view showing a semiconductor device according to some implementations of the present disclosure; and

[0029] Figure 18A and Figure 18B is a view showing a semiconductor device according to some implementations of the present disclosure. DETAILED DESCRIPTION

[0030] Hereinafter, examples according to the present disclosure will be described with reference to the drawings.

[0031] Figure 1A is a perspective view showing a semiconductor device according to some implementations. Figure 1B is showing Figure 1A a plan view of a part of the blocks in.

[0032] Referring to Figure 1A and Figure 1B , the semiconductor device 300 includes a first chip structure CS1 (sometimes referred to as a "lower chip structure") and a second chip structure CS2 (sometimes referred to as an "upper chip structure") stacked on the first chip structure CS1 in a vertical direction (Z direction). The labels "first" and "second" and "CS1" and "CS2" are not intended to limit the relative arrangement of the chip structures; in some implementations, the first chip structure CS1 may be the upper chip structure and the second chip structure CS2 may be the lower chip structure.

[0033] The semiconductor device 300 includes a plurality of blocks BA and a first peripheral region PER1. Each of the plurality of blocks BA includes a lower region BAa in the first chip structure CS1 and an upper region BAb in the second chip structure CS2. Similarly, the first peripheral region PER1 includes a first lower region PER1a in the first chip structure CS1 and a first upper region PER1b in the second chip structure CS2. The first peripheral region PER1 may be configured as a peripheral circuit region where peripheral circuits for input / output of data or commands and / or power / ground input are provided.

[0034] Referring to Figure 1B , part “I” of the block BA is shown in an enlarged manner. Each block BA may include a storage region CR, extension regions EXTb and EXTw adjacent to the storage region CR, and a peripheral circuit region PC vertically overlapping the storage region CR. The storage region CR and the extension regions EXTb and EXTw may be provided in the lower region BAa of the block BA in the first chip structure CS1, and the peripheral circuit region PC may be provided in the upper region BAb of the block BA in the second chip structure CS2. Figure 1A

[0035] Each storage region CR may include a cell switching device including a gate electrode, a bit line electrically connected to the cell switching device, and a data storage structure electrically connected to the cell switching device. The gate electrode of the cell switching device may be configured as a word line.

[0036] The extension regions EXTb and EXTw may include a first extension region EXTb adjacent to the storage region CR in a first direction (X direction) and a second extension region EXTw adjacent to the storage region CR in a second direction (Y direction). The first extension region EXTb adjacent to the storage region CR in the first direction (X direction) may be a bit line extension region where the bit lines in the storage region CR extend, and the second extension region EXTw adjacent to the storage region CR in the second direction (Y direction) may be configured as a word line extension region where the word lines in the storage region CR extend.

[0037] The storage region CR may include a first storage region CR1 and a second storage region CR2, and the second storage region CR2 is adjacent to the first storage region CR1 and is spaced apart from the first storage region CR1 by the first extension region EXTb. Each peripheral circuit region PC may include a sense amplifier array region SAR, a sub-word line driver region SWDR, and a second peripheral region PER2 between the sense amplifier array region SAR and the sub-word line driver region SWDR. The peripheral circuit region PC may overlap the first storage region CR1 and the second storage region CR2 respectively.

[0038] ​Therefore, the first chip structure CS1 may include a storage structure including a first storage region CR1 and a second storage region CR2, and the second chip structure CS2 may include a peripheral circuit region PC having a sense amplifier array region SAR. The first chip structure CS1 and the second chip structure CS2 may be electrically connected to each other through a first bonding pad and a second bonding pad ( Figure 2A 195 and 295 in

[0039] Figure 2A shown Figure 1B a cross-section of a part of the block BA of the semiconductor device 300 shown in

[0040] Referring to Figure 2A , the semiconductor device 300 may include a first chip structure CS1 and a second chip structure CS2 stacked in sequence. Here, as described above, the first chip structure CS1 may include a first peripheral region PER1, a first storage region CR1, a second storage region CR2, and a first extension region EXTb between the first storage region CR1 and the second storage region CR2. However, in Figure 2A , for ease of description, only the first storage region CR1 and the first extension region EXTb are shown.

[0041] The first chip structure CS1 may include a base substrate 130, a storage structure MS on the base substrate 130, a first substrate 110 on the storage structure MS, and a first wiring structure 160 (sometimes referred to as a first lower wiring structure) on the first substrate 110.

[0042] In some implementations, the first chip structure CS1 further includes a first through-via 170 that penetrates the first substrate 110 and is electrically connected to the storage structure MS. The first wiring structure 160 may include a first insulating layer 161 (sometimes referred to as a first lower insulating layer) and a first wiring layer 165 (sometimes referred to as a first lower wiring layer) disposed in the first insulating layer 161. The first wiring layer 165 may be electrically connected to the storage structure MS through the first through-via 170. Each first through-via 170 may include a first conductive plug 175 and a first insulating pad 172 surrounding the first conductive plug 175 to electrically insulate it from the first substrate 110. The first wiring layer 165 may include a plurality of first wiring patterns 162 disposed at different levels in the first insulating layer 161 and a first wiring via 163 connected to the plurality of first wiring patterns 162.

[0043] Figure 3 is an enlarged view of a part “A1” of the semiconductor device in Figure 2A shown in

[0044] Referring to Figure 3 together with Figure 2A, the memory structure MS may include a memory cell structure MC, a data storage structure DS, a word line ML, and a bit line BL. In some implementations, the memory cell structure MC and the data storage structure DS may be sequentially disposed from the upper surface of the base substrate 130.

[0045] The data storage structure DS may include a first electrode E1, a second electrode E2 covering the first electrode E1, and a dielectric layer DL between the first electrode E1 and the second electrode E2. The data storage structure DS may be configured as a memory cell capacitor for storing data. The memory structure MS may be disposed in the first storage region CR1 or may be disposed in the second storage region CR2. The bit line BL may include a first bit line BLa in the first storage region CR1 and a second bit line BLb in the second storage region CR2.

[0046] The memory cell structure MC may include a cell active region 113 defined by a cell device isolation region 111 and a cell transistor on the cell active region 113. Each cell transistor may be configured as a cell switching device and may include a first source / drain region 112a and a second source / drain region 112b disposed in the cell active region 113 and a cell gate structure on the cell active region 113. The gate electrode of the cell gate structure may be provided as the word line WL.

[0047] In some implementations, the first substrate 110 may include a first device isolation region ST1, and the word line WL may be buried in the first substrate 110. The cell device isolation region 111 may be formed as a shallow trench isolation. The cell device isolation region 111 may be formed simultaneously with the first device isolation region ST1. For example, the cell device isolation region 111 may include an insulating material such as silicon oxide and / or silicon nitride.

[0048] Referring to Figure 3 , the first chip structure CS1 may include a buffer insulating layer 118 on the cell active region 113 and the cell device isolation region 111, a bit line BL on the buffer insulating layer 118, a bit line capping layer 115 on the bit line BL, a cell contact structure 125 having pad portions extending to the bit line capping layer 115 on both sides of the bit line BL, an insulating isolation structure 126 disposed between the pad portions of the cell contact structure 125 and extending downward, and insulating spacers 116 on the side surfaces of the bit line BL and the side surfaces of the bit line capping layer 115. The bit line BL may be electrically connected to the first source / drain region 112a, and the cell contact structure 125 may be electrically connected to the second source / drain region 112b.

[0049] As described above, a portion of the first lower wiring layer 165 can be electrically connected to the bit line BL of the memory structure MS through the first via 170. In the first memory region CR1, a portion of the first wiring layer 165 can be disposed on the data storage structure DS of the memory structure MS.

[0050] The first chip structure CS1 in some implementations can include a first bonding structure for connection to a second chip structure CS2. The first bonding structure can include a first bonding insulating layer 192 disposed on the first wiring structure 160 and a first bonding pad 195 that is open to (i.e., disposed in) the first bonding insulating layer 192 and electrically connected to the first wiring layer 165. The first bonding pad 195 can be substantially coplanar with the surface of the first bonding insulating layer 192.

[0051] The second chip structure CS2 can include a second substrate 210, peripheral circuit transistors 250 disposed on the lower surface of the second substrate 210, a lower wiring structure (sometimes referred to as a second wiring structure or a second upper wiring structure) 260 disposed on the lower surface of the second substrate 210, and an upper wiring structure 280 disposed on the upper surface of the second substrate 210.

[0052] The second substrate 210 can include a second device isolation region ST2 that defines an active region in which the peripheral circuit transistors 250 are formed. The peripheral circuit transistors 250 can include gate electrodes 255 on the active region, gate dielectric layers 256 between the gate electrodes 255 and the active region, and source / drains 252 and 253 in the active region on both sides of the gate electrodes 255. For example, the peripheral circuit transistors 250 can include transistors that vertically overlap the memory structures MS of the first memory region CR1 and the second memory region CR2 and transistors that vertically overlap the first peripheral region PER1.

[0053] An intermediate wiring structure (sometimes referred to as a second lower wiring structure) 220 can be disposed between the second substrate 210 and the lower wiring structure 260. The intermediate wiring structure 220 can include an intermediate insulating layer 221 and an intermediate wiring layer (sometimes referred to as a second lower wiring layer) 225 disposed in the intermediate insulating layer 221 and connected to the peripheral circuit transistors 250. The intermediate wiring layer 225 can electrically connect the peripheral circuit transistors 250 on the second substrate 210 and can form a peripheral circuit. The intermediate wiring layer 225 can include conductive lines 222 and contact vias 223 connected to the conductive lines 222.

[0054] The lower wiring structure 260 may include a lower insulating layer (sometimes referred to as the second insulating layer) 261 on the intermediate wiring structure 220 and a lower wiring layer (sometimes referred to as the second wiring layer or the second upper wiring layer) 265 disposed in the lower insulating layer 261 and connected to the intermediate wiring layer 225. The lower wiring layer 265 may include a plurality of lower wiring patterns 262 disposed at different levels in the lower insulating layer 261 and lower wiring vias 263 connecting to the plurality of lower wiring patterns 262.

[0055] In some implementations, the second chip structure CS2 may further include second through vias 270 that penetrate the second substrate 210 and are electrically connected to the lower wiring layer 265. Each second through via 270 may include a second conductive plug 275 and a second insulating liner 272 surrounding the second conductive plug 275 to electrically insulate it from the second substrate 210. The upper wiring structure 280 may include an upper insulating layer 281 and an upper wiring layer 285 disposed in the upper insulating layer 281. The upper wiring layer 285 may be electrically connected to the lower wiring layer 265 through the second through vias 270. The upper wiring layer 285 may include a plurality of upper wiring patterns 282 disposed at different levels in the upper insulating layer 281 and upper wiring vias 283 connecting to the plurality of upper wiring patterns 282. In some implementations, input / output pads may be electrically connected to the upper wiring layer 285 and may be arranged to be exposed on the upper surface of the upper wiring structure 280.

[0056] Similar to the first chip structure CS1, the second chip structure CS2 may include a second bonding structure for connecting to the first chip structure CS1. The second bonding structure may include a second bonding insulating layer 292 disposed on the lower wiring structure 260 and second bonding pads 295 that are open to the second bonding insulating layer 292 and electrically connected to the lower wiring layer 265.

[0057] The first bonding pad 195 of the first chip structure CS1 and the second bonding pad 295 of the second chip structure CS2 may be bonded to each other. The directly bonded first bonding pad 195 and second bonding pad 295 may be joined to each other through the mutual diffusion of metals (such as copper) via a high-temperature annealing process. The metals included in the first bonding pad 195 and the second bonding pad 295 are not limited to copper and may include other suitable metal materials (such as Au) that can be bonded to each other under similar conditions. Through the bonding between the first bonding pad 195 and the second bonding pad 295, the first chip structure CS1 and the second chip structure CS2 may be firmly mechanically coupled and electrically connected to each other.

[0058] In addition, in some implementations, the first bonding insulating layer 192 of the first chip structure CS1 and the second bonding insulating layer 292 of the second chip structure CS2 may be bonded to each other.

[0059] The first bonding insulating layer 192 and the second bonding insulating layer 292 may include the same dielectric material, such as silicon oxide. In some implementations, the first bonding insulating layer 192 and the second bonding insulating layer 292 may include an insulating film formed of an insulating material different from the insulating materials of the first insulating layer 161 and the lower insulating layer 261. For example, other materials may include another insulating film such as SiCN, SiON, or SiCO.

[0060] In some cases, during the process of manufacturing a semiconductor device (such as an oxidation process, a plasma etching process, etc.), defects (such as dangling bonds) may occur in the memory cell. To reduce or prevent leakage current caused by defects, a process of supplying hydrogen to the memory structure MS (especially the memory cell structure MC) may be necessary. By including a hydrogen-containing insulating layer 155 (which may be a hydrogen source) in the semiconductor device 300 and diffusing hydrogen through an annealing process, hydrogen can be supplied to the memory cell structure MC.

[0061] However, hydrogen may have an adverse effect on the peripheral circuit transistors 250 and various wiring layers (especially the upper wiring layer 285). For example, when a large amount of hydrogen is supplied around the peripheral circuit transistors 250, hydrogen may react with halogen elements (such as chlorine) and may produce an acid, which may cause reliability problems in the peripheral circuit transistors 250, such as the negative bias temperature instability (NBTI) phenomenon.

[0062] In some implementations, to increase the positive effect while reducing or preventing the adverse effect of hydrogen supply, the time point at which the hydrogen-containing insulating layer 155 is included and / or the position of the hydrogen-containing insulating layer 155 may be changed. The semiconductor device 300 may include a hydrogen-containing insulating layer 155 disposed in a region close to the memory structure MS. The hydrogen-containing insulating layer 155 may be included in the process of manufacturing the lower chip structure CS1 (see Figures 10A to 10D ). Adjusting the position of the hydrogen-containing insulating layer 155 to meet its purpose can ensure sufficient hydrogen supply to the memory structure MS (the ultimate target of hydrogen), while reducing the adverse effect on other components. The adjustment of the position of the hydrogen-containing insulating layer 155 can be achieved in various ways.

[0063] For example, referring to Figure 2A, the semiconductor device 300 further includes a hydrogen-containing insulating layer 155 that is adjacent to the memory structure MS on the upper surface of the substrate 130. The hydrogen-containing insulating layer 155 can be configured as an insulating material containing a relatively high concentration of hydrogen and / or deuterium to supply hydrogen to surrounding components. For example, the hydrogen-containing insulating layer 155 can be a silicon oxide containing hydrogen and / or deuterium. In some implementations, the hydrogen-containing insulating layer 155 can be a silicon oxide deposited using oxygen (O2) and silane (SiH4) gases. For example, the hydrogen-containing insulating layer 155 can be an oxide formed by plasma-enhanced chemical vapor deposition (PECVD) or high-density plasma chemical vapor deposition (HDP-CVD).

[0064] In some implementations, the hydrogen-containing insulating layer 155 can be in direct contact with the interlayer insulating layer 121 disposed on the first substrate 110 and covering the memory structure MS. Since the hydrogen diffusing from the hydrogen-containing insulating layer 155 is disposed near the memory structure MS without passing through other wiring structures 160, 260, 280 or the peripheral circuit transistors 250, the hydrogen can be effectively supplied to the memory cell structure MC.

[0065] Figure 2B is Figure 2A a graph of the hydrogen content (or concentration) distribution of the semiconductor device according to the stacking direction.

[0066] Referring to Figure 2B , “C0” can represent an ideal hydrogen content distribution suitable for repairing defects in the memory structure MS. The hydrogen content can be the highest at the level of the memory cell structure MC.

[0067] “C1” can represent the hydrogen content distribution diffused from the hydrogen-containing insulating layer 155 in the actually implemented semiconductor device 300. For example, the hydrogen content in the semiconductor device 300 can be the highest at the level of the upper surface of the substrate 130 (e.g., the hydrogen-containing insulating layer 155), and due to hydrogen diffusion, it can gradually decrease toward the second chip structure CS2.

[0068] “C2” can be a comparative example and can represent the hydrogen content distribution diffused under the same diffusion conditions (hydrogen concentration of the hydrogen supply layer and annealing conditions) as C1 when the passivation layer PL is used as the hydrogen supply layer. The content of hydrogen can be the highest at the uppermost end of the semiconductor device 300, and due to hydrogen diffusion, it can gradually decrease toward the substrate 130.

[0069] Regarding the hydrogen content distribution of C1, in some implementations, the hydrogen-containing insulating layer can be disposed closer to the memory cell structure MC than in the example of C2. Therefore, the hydrogen content of C1 can be closer to the hydrogen content of C0 at the level of the memory cell structure MC than the hydrogen content of C2.

[0070] In addition, referring to C2, a relatively high hydrogen content distribution may be present in several wiring layers (especially the upper wiring layer 285) and the peripheral circuit transistors 250, while referring to C1, a relatively low hydrogen content distribution may be present in the upper wiring layer 285 and the peripheral circuit transistors 250. In some implementations, before the process of bonding with the second chip structure CS2 (e.g., after the process of bonding the memory structure MS to the substrate 130 (see Figure 10B ))), by performing an annealing process for hydrogen diffusion, hydrogen diffusion into the second chip structure CS2 can be prevented.

[0071] As described above, by maintaining a relatively low hydrogen content in components that may be adversely affected by diffusion, or by fundamentally preventing diffusion, the reliability of the semiconductor device 300 can be improved.

[0072] The hydrogen-containing insulating layer 155 may include insulating patterns buried in a plurality of trenches formed on the upper surface of the substrate 130. The insulating patterns can be implemented in various structures and arrangements.

[0073] Figure 4A and Figure 4B are enlarged views showing various examples of part "A2" of the semiconductor device in Figure 2A .

[0074] Referring to Figure 4A , the insulating patterns of the hydrogen-containing insulating layer 155 can be buried in the substrate 130. A dielectric layer 132 having an upper surface substantially coplanar with the upper surface of the insulating pattern can be provided on the upper surface of the substrate 130. The dielectric layer 132 on the substrate 130 can be bonded to the interlayer insulating layer 121. Similar to the bonding between the first bonding insulating layer 192 and the second bonding insulating layer 292 described above, the bonding can be achieved by bonding between dielectrics. The dielectric layer 132 and the interlayer insulating layer 121 can include the same dielectric material, such as silicon oxide. For example, the dielectric layer 132 can be configured as a film in which the surface of the substrate 130 is naturally oxidized. In some implementations, the dielectric layer 132 and the interlayer insulating layer 121 can alternatively or optionally include other insulating films, such as SiCN, SiON, or SiCO.

[0075] Referring to Figure 4B , a first barrier insulating film 151 can be further provided between the hydrogen-containing insulating layer 155 and the substrate 130. The first barrier insulating film 151 can reduce or prevent hydrogen in the hydrogen-containing insulating layer 155 from diffusing into the substrate 130. The first barrier insulating film 151 can guide more hydrogen to diffuse in a desired direction (e.g., toward the memory structure MS). For example, the first barrier insulating film 151 can include silicon nitride, aluminum oxide, or aluminum nitride.

[0076] Figure 5A and Figure 5B is a plan view showing a base substrate, showing Figure 2A various examples of the hydrogen-containing insulating layer 155 employed in the semiconductor device 300 in

[0077] Referring to Figure 5A , each insulating pattern of the hydrogen-containing insulating layer 155 may have a linear shape. Different from the above examples, referring to Figure 5B , each insulating pattern 155P of the hydrogen-containing insulating layer 155 may have a quadrilateral island structure. As described above, the insulating patterns may be formed in various shapes and arrangements and are not limited to Figures 5A to 5B those of

[0078] In some implementations, for example, as shown in Figure 8 , the hydrogen-containing insulating layer 155 may be provided as a single-layer structure rather than a pattern (see Figure 8 ). In some implementations, the single-layer structure of the hydrogen-containing insulating layer 155 may also be used as a bonding insulating layer for bonding to the interlayer insulating layer 121.

[0079] In some implementations, the employed hydrogen-containing insulating layer 155 may be included in the process of manufacturing the first chip structure CS1 (for example, see Figure 9 and Figures 10A to 10D ). Since the memory structure MS is formed on the first substrate 110 and bonded to the base substrate 130 (as shown in Figure 2A ), the memory structure MS may be provided in the order of the data storage structure DS and the memory cell structure MC from the upper surface of the base substrate 130.

[0080] According to some implementations, by disposing the hydrogen-containing insulating layer 155 on the upper surface of the base substrate 130 adjacent to the memory structure MS, hydrogen can be stably supplied to the memory cell structure MC, thereby repairing silicon defects (such as dangling bonds) and improving the electrical characteristics of the semiconductor device 300 (such as reduced leakage current). For example, when the semiconductor device 300 is configured as a DRAM device, a reduction in data retention time can be prevented or reduced. In addition, by reducing the hydrogen supplied to the upper wiring layer 285 and the peripheral circuit transistors 250 (which may be adversely affected by hydrogen), the reliability of the semiconductor device 300 can be improved.

[0081] In the above example, the hydrogen-containing insulating layer 155 is disposed on the upper surface of the base substrate 130 adjacent to the memory structure MS. However, other arrangements for disposing the hydrogen-containing insulating layer to reduce adverse effects while improving hydrogen supply efficiency are also within the scope of the present disclosure.

[0082] Figure 6A is a cross-sectional view showing a semiconductor device according to some implementations.

[0083] Referring to Figure 6A , except for the configuration providing the hydrogen-containing insulating layer 155A therein, the semiconductor device 300A may be similar to the example shown in Figures 1A to 5B . Thus, unless otherwise indicated, the description of the example shown in Figures 1A to 5B may be applied to the example of Figure 6A .

[0084] The first chip structure CS1 adopted in some implementations may include a base substrate 130, a memory structure MS on the base substrate 130, a first substrate 110A on the memory structure MS, and a hydrogen-containing insulating layer 155A and a first wiring structure 160 provided on the first substrate 110A. The hydrogen-containing insulating layer 155A may include insulating patterns buried in a plurality of trenches formed on the upper surface of the first substrate 110A.

[0085] Figure 7 is an enlarged view showing part "B" of the semiconductor device in Figure 6A .

[0086] Referring to Figure 7 , the insulating pattern of the hydrogen-containing insulating layer 155A may have an upper surface substantially coplanar with the upper surface of the first substrate 110A. After bonding the memory structure MS to the base substrate 130, by applying a grinding process to the first substrate 110A, the thickness of the first substrate 110A may be reduced, and after the grinding process, a hydrogen-containing insulating layer 155A may be formed on the upper surface of the first substrate (see Figure 13B ). The first wiring structure 160 may be formed on the upper surface of the first substrate 110A on which the hydrogen-containing insulating layer 155A is formed (see Figure 13C ).

[0087] Figure 6B is Figure 6A a graph of the hydrogen content distribution of the semiconductor device in accordance with the stacking direction.

[0088] Referring to Figure 6B , the hydrogen content distribution generated due to diffusion from the hydrogen-containing insulating layer 155A in the semiconductor device 300A is represented by "C1′", and "C2" is the above comparative example (which represents the hydrogen content distribution of the example where the passivation layer PL serves as the hydrogen supply layer).

[0089] Specifically, the hydrogen content in the semiconductor device 300A can be the highest at the level of the upper surface of the first substrate 110A, and a large amount of hydrogen can also diffuse into the storage structure MS disposed on the lower surface (which can be the active surface of the first substrate 110A). Therefore, at the level of the memory cell structure MC, the hydrogen content of C1' can be similar to the hydrogen content of C0', for example, more similar compared to the hydrogen content of C2.

[0090] In addition, in the wiring layers (especially the upper wiring layer 285) and the peripheral circuit transistors 250 (where adverse effects of hydrogen may occur), C1' can have a relatively lower hydrogen content distribution compared to C2. In some implementations, before the process of bonding to the second chip structure CS2 (e.g., before the process of forming the first wiring structure 160 (see Figure 13C ), an annealing process for hydrogen diffusion can be performed so that hydrogen does not diffuse into the second chip structure CS2.

[0091] Therefore, the reliability of the semiconductor device 300A can be improved by maintaining a low hydrogen content or preventing diffusion in the wiring layers (such as the upper wiring layer 285) and the peripheral circuit transistors 250.

[0092] Figure 8 is a cross-sectional view showing a semiconductor device according to some implementations.

[0093] Referring to Figure 8 , except for the configurations of the first chip structure CS1 (such as the peripheral circuit transistors 250) and the second chip structure CS2 (such as the storage structure MS), the semiconductor device 300B can be configured similarly to the semiconductor device shown in Figures 1A to 5B . In the semiconductor device 300B, a hydrogen-containing insulating layer 155B is disposed on the first substrate 110 in the second chip structure CS2, and the hydrogen-containing insulating layer 155B is provided as a single layer. Therefore, Figures 1A to 5B 's description can be applied to the example of Figure 8 , unless otherwise indicated.

[0094] In the semiconductor device 300B, the first chip structure CS1 and the second chip structure CS2 can be configured differently from the semiconductor device 300. The first chip structure CS1 bonded to the base substrate 130 can include a second substrate 210 having peripheral circuit transistors 250, and the second chip structure CS2 on the first chip structure CS1 can include a first substrate 110 having a storage structure MS.

[0095] For example, the first chip structure CS1 may include a base substrate 130, a second substrate 210 having a lower surface opposite to the upper surface of the base substrate 130, peripheral circuit transistors 250 disposed on the lower surface of the second substrate 210, a second lower wiring structure 220 disposed between the upper surface of the base substrate 130 and the lower surface of the second substrate 210, a second through-via 270 penetrating the second substrate 210, and a second upper wiring structure 260 disposed on the upper surface of the second substrate 210.

[0096] The second lower wiring structure 220 may include a second lower wiring layer 225 electrically connected to the peripheral circuit transistors 250, and the second upper wiring structure 260 may include a second upper wiring structure 260 disposed on the upper surface of the second substrate 210.

[0097] The second chip structure CS2 may include: a first substrate 110 having an upper surface that includes a hydrogen-containing insulating layer 155B disposed thereon; a memory structure MS disposed on the lower surface of the first substrate 110; a first lower wiring structure 160 disposed on the lower surface of the memory structure MS; a first through-via 170 penetrating the first substrate 110; and a first upper wiring structure 180 disposed on the first substrate 110.

[0098] The first lower wiring structure 160 may have a first lower wiring layer 165 electrically connected to the memory structure MS, and the first upper wiring structure 180 may have a first upper wiring layer 185 electrically connected to the first lower wiring layer 165 through the first through-via.

[0099] In some implementations, the first chip structure CS1 may include a second bonding insulating layer 292 disposed on the second upper wiring structure 260 and a second bonding pad 295 disposed on the upper surface of the second upper wiring structure 260 and electrically connected to the second upper wiring layer 265. Similarly, the second chip structure CS2 may include a first bonding insulating layer 192 disposed on the lower surface of the first lower wiring structure 160 and a first bonding pad 195 disposed on the lower surface of the first lower wiring structure 160 and electrically connected to the first lower wiring layer 165.

[0100] The second bonding pad 295 of the first chip structure CS1 and the first bonding pad 195 of the second chip structure CS2 can be bonded to each other. The second bonding pad 295 and the first bonding pad 195 that are directly bonded to each other can be coupled to each other through interdiffusion between metals (such as copper) via a high-temperature annealing process. Through the bonding between the second bonding pad 295 and the first bonding pad 195, a firm mechanical connection between the second chip structure CS2 and the first chip structure CS1 and an electrical connection between the second chip structure CS2 and the first chip structure CS1 can be achieved. In addition, the second bonding insulating layer 292 of the first chip structure CS1 and the first bonding insulating layer 192 of the second chip structure CS2 can be bonded to each other.

[0101] Figure 8 The hydrogen-containing insulating layer 155B in the example of can be formed, for example, as a complete layer instead of the pattern described for the devices 300, 300A. The second barrier insulating film 152 can be disposed between the hydrogen-containing insulating layer 155B and the first upper wiring structure 180. The second barrier insulating film 152 can prevent hydrogen from diffusing toward the first upper wiring structure 180. The first via 170 can penetrate the hydrogen-containing insulating layer 155B, the second barrier insulating film 152, and the first substrate 110.

[0102] In some implementations, after the process of forming the first upper wiring structure 180 on the first substrate 110 (see Figure 15E ), an annealing process for hydrogen diffusion can be performed to reduce or prevent hydrogen from diffusing into the first upper wiring layer 185.

[0103] Therefore, by maintaining a low hydrogen content in components that may be adversely affected by diffusion or by preventing diffusion, the reliability of the semiconductor device 300B can be improved.

[0104] Figure 9 is a flowchart showing a method of manufacturing a semiconductor device according to some implementations.

[0105] Referring to Figure 9 , in the process (S510), a lower chip structure (also referred to as the first chip structure) including a lower bonding pad can be formed, and in the process of forming the lower chip structure, a hydrogen-containing insulating layer can be formed. The hydrogen-containing insulating layer can be formed on a base substrate bonded to a memory structure (see Figures 10A to 10D ), or can be formed on a first substrate bonded to the base substrate (see Figures 13A to 13D ).

[0106] By forming an upper chip structure (also referred to as the second chip structure) including an upper bonding pad (S520) and bonding the upper bonding pad and the lower bonding pad, the upper chip structure can be disposed on the lower chip structure (S540).

[0107] Thereafter, a wiring structure (e.g., Figure 2A and Figure 6A the upper wiring structure 280 in

[0108] can be formed (S560), and external connection pads can be further formed on the wiring structure.

[0109] As Figure 2A shown, the hydrogen-containing insulating layer 155 can be disposed on the upper surface of the base substrate 130 in the first chip structure CS1 adjacent to the memory structure MS. Refer to Figures 10A to 10D , Figure 11A and Figure 11B and Figures 12A to 12C for a method of manufacturing the semiconductor device 300.

[0110] Figures 10A to 10D is a cross-sectional view showing a process of manufacturing the lower chip structure (e.g., corresponding to process S510).

[0111] Refer to Figure 10A , a memory structure MS can be formed on the first substrate 110'.

[0112] The memory structure MS can be configured as a DRAM memory. The memory structure MS can include a memory cell structure ( Figure 3 "MC" in

[0113] ), a data storage structure DS, a word line WL, and a bit line BL. The memory cell structure can be formed in an active region defined by a first device isolation region ST1 on the first substrate 110', and the data storage structure DS can be formed on the memory cell structure. Figure 3 )).

[0114] Thereafter, refer to Figure 10B , a base substrate 130 having an upper surface on which the hydrogen-containing insulating layer 155 is disposed can be prepared, and the memory structure MS together with the first substrate 110' can be bonded to the upper surface of the base substrate 130.

[0115] In some implementations, trenches can be formed on the upper surface of the base substrate 130, a hydrogen-containing insulating material can be deposited, and a planarization process such as CMP can be performed to form a hydrogen-containing insulating layer 155 including an insulating pattern. Before forming the hydrogen-containing insulating layer 155, a dielectric layer 132 for bonding to the memory structure MS can be formed on the base substrate 130. In some implementations, the dielectric layer 132 (e.g., silicon oxide) can be formed by natural oxidation without an additional deposition process. Additionally, the initial bonding can be achieved by bonding between dielectrics. For example, the memory structure MS formed on the first substrate 110' can be disposed on the base substrate 130 through the bonding between the interlayer insulating layer 121 and the dielectric layer 132.

[0116] After the bonding process, an annealing process for diffusing hydrogen from the hydrogen-containing insulating layer 155 can be performed. Hydrogen can diffuse into the memory structure MS, especially into the memory cell structure MC, and can repair defects (e.g., dangling bonds) in the memory cells, thereby reducing the leakage current. In this process, by performing the annealing process for hydrogen diffusion (e.g., before the second chip structure CS2 is attached to the first chip structure CS1), hydrogen diffusion into the second chip structure CS2 can be prevented. The annealing process can be performed in another process before the process of bonding to the second chip structure CS2 (see Figure 12A ). For example, the annealing process can be performed after a grinding process (see Figure 10C ).

[0117] Referring to Figure 10C , the first substrate 110' (represented by the dashed line) can be ground, and a first via 170 penetrating the first substrate 110 and electrically connected to the memory structure MS can be formed.

[0118] After the initial bonding, a thinning process of grinding the first substrate 110' on which the memory structure MS is formed can be performed. A first via 170 connected to the memory structure MS (e.g., bit line BL) can be formed on the thin first substrate 110. The first via 170 can be used as a path for connecting the memory structure MS to the first wiring structure 160 to be formed in subsequent processes.

[0119] Thereafter, referring to Figure 10D , a first wiring structure 160 can be formed on the first substrate 110, and a first bonding structure can be formed on the first wiring structure 160.

[0120] The first wiring structure 160 may include a first insulating layer 161 and a first wiring layer 165 in the first insulating layer 161. The first wiring layer 165 may be electrically connected to the first through-via 170. The first bonding structure may include a first bonding insulating layer 192 disposed on the first wiring structure 160 and a first bonding pad 195 buried in the first bonding insulating layer 192 and electrically connected to the first wiring layer 165. A surface 195T of the first bonding pad 195 may be substantially coplanar with a surface 192T of the first bonding insulating layer 192. For example, the metal included in the first bonding pad 195 is not limited to copper and may include additional metal materials (e.g., Au) that can be bonded under similar conditions.

[0121] Thus, in the process of forming the first chip structure CS1, the hydrogen-containing insulating layer 155 may be formed adjacent to the memory structure MS, and before bonding to the second chip structure CS2, by diffusing the hydrogen of the hydrogen-containing insulating layer 155, the hydrogen is supplied to the memory cells through an annealing process, and an effective repair process may be performed.

[0122] Figure 11A and Figure 11B is a cross-sectional view showing a process of manufacturing an upper chip structure (e.g., corresponding to process S520) according to some implementations.

[0123] Referring to Figure 11A , the peripheral circuit transistors 250 and the intermediate wiring structure 220 may be formed on the second substrate 210'. The intermediate wiring structure 220 may have an intermediate wiring layer 225 electrically connected to the peripheral circuit transistors 250. The intermediate wiring layer 225 may include contact vias 223 connected to the gate electrode 255 and the source / drain 252 and 253 and conductive lines 222 connecting components.

[0124] Thereafter, referring to Figure 11B , the lower wiring structure 260 may be formed on the intermediate wiring structure 220, and a second bonding structure may be formed on an upper surface of the lower wiring structure 260.

[0125] The lower wiring structure 260 may include a lower insulating layer 261 on the intermediate wiring structure 220 and a lower wiring layer 265 disposed in the lower insulating layer 261 and connected to the intermediate wiring layer 225. The lower wiring layer 265 may include a plurality of lower wiring patterns 262 disposed at different levels in the lower insulating layer 261 and lower wiring vias 263 connected to the plurality of lower wiring patterns 262. The second bonding structure may include a second bonding insulating layer 292 disposed on the lower wiring structure 260 and second bonding pads 295 buried in the second bonding insulating layer 292 and electrically connected to the lower wiring layer 265. The second bonding pads 295 may be substantially coplanar with the surface of the second bonding insulating layer 292. Similar to the first bonding pads 195, the metal included in the second bonding pads 295 is not limited to copper and may include other metal materials (e.g., Au) that can be bonded under similar conditions.

[0126] Thereafter, a process of bonding the first chip structure CS1 to the second chip structure CS2 may be performed. Figures 12A to 12C is a cross-sectional view showing a bonding process (e.g., corresponding to process S540) according to some implementations.

[0127] Referring to Figure 12A , by bonding the second bonding pads 295 to the first bonding pads 195, the upper surface of the lower wiring structure 260 may be bonded (in a secondary bonding process) to the upper surface of the first wiring structure 160. Thus, the first chip structure CS1 and the second chip structure CS2 may be bonded to each other.

[0128] In this process, the first bonding pads 195 of the first chip structure CS1 and the second bonding pads 295 of the second chip structure CS2 may be bonded to each other. The first bonding pads 195 and the second bonding pads 295 that are directly bonded to each other may be joined to each other via an interdiffusion between metals (e.g., copper) through a high-temperature annealing process. Through the bonding between the first bonding pads 195 and the second bonding pads 295, a strong mechanical connection between the first chip structure CS1 and the second chip structure CS2 and an electrical connection between the first chip structure CS1 and the second chip structure CS2 may be achieved. In addition, the first bonding insulating layer 192 of the first chip structure CS1 and the second bonding insulating layer 292 of the second chip structure CS2 may be bonded to each other.

[0129] Thereafter, referring to Figure 12B , the second substrate 210' may be polished, and second vias 270 may be formed on the polished second substrate 210.

[0130] After the secondary bonding, a thinning process can be performed by grinding the second substrate 210' on which the peripheral circuit transistors 250 are formed. The second vias 270 connected to the intermediate wiring layer 225 or the lower wiring layer 265 can be formed on the ground second substrate 210. The second vias 270 can be used as a path for connecting the lower wiring layer 265 to the upper wiring layer 285 to be formed in subsequent processes.

[0131] Thereafter, referring to Figure 12C , an upper wiring structure 280 can be formed on the second substrate 210.

[0132] The upper wiring structure 280 can include an upper insulating layer 281 and an upper wiring layer 285 in the upper insulating layer 281. The upper wiring layer 285 can be electrically connected to the second vias 270. Therefore, the upper wiring layer 285 can be electrically connected to the lower wiring layer 265 disposed below the second substrate 210.

[0133] As discussed above with reference to Figure 6A , in some implementations, a hydrogen-containing insulating layer 155A can be provided to the first substrate 110 in the first chip structure CS1 on which the memory structure MS is formed. Referring to Figures 13A to 13D describes an example of a method for manufacturing Figure 6A the semiconductor device 300A.

[0134] Referring to Figure 13A , a memory structure MS can be formed on the first substrate 110', and the memory structure MS can be bonded to the upper surface of the base substrate 130 together with the first substrate 110'. This process can be performed similarly to the processes described in Figure 10A and Figure 10B . However, in this case, a hydrogen-containing insulating layer may not be provided on the upper surface of the base substrate 130.

[0135] Thereafter, referring to Figure 13B , the first substrate 110' can be ground, and a hydrogen-containing insulating layer 155A can be formed on the upper surface of the ground first substrate 110A.

[0136] After performing the grinding process, trenches 155T can be formed on the upper surface 110T of the first substrate 110A, and a hydrogen-containing insulating material can be deposited. Thereafter, a planarization process such as CMP can be performed to expose the upper surface of the first substrate 110A again, thereby forming a hydrogen-containing insulating layer 155A including an insulating pattern.

[0137] Thereafter, an annealing process for diffusing hydrogen from the hydrogen-containing insulating layer 155A can be performed. Hydrogen can diffuse into the memory structure MS, particularly the memory cell structure MC, and can repair defects in the memory cells, thereby reducing the leakage current. By performing the annealing process for hydrogen diffusion in this process (e.g., before attaching to the second chip structure CS2), hydrogen diffusion into the second chip structure CS2 can be prevented. The annealing process can be performed in another process before the process of bonding to the second chip structure CS2 (see Figure 13D )).

[0138] Thereafter, referring to Figure 13C , similar to the description provided for Figure 10D , a first through-via 170 electrically connected to the memory structure MS can be formed on the first substrate 110A (see Figure 10C as part of the process). Thereafter, a first wiring structure 160 having a first wiring layer 165 electrically connected to the first through-via 170 can be formed on the first substrate 110A, and a first bonding insulating layer 192 and a first bonding pad 195 can be formed on the upper surface of the first wiring structure 160. The first bonding pad 195 can be electrically connected to the first wiring layer 165 (see Figure 10D in the process).

[0139] Thereafter, referring to Figure 13D , a process of bonding the second chip structure CS2 manufactured through the processes in Figure 11A and Figure 11B to the first chip structure CS1 can be performed.

[0140] By bonding the second bonding pad 295 of the second chip structure CS2 to the first bonding pad 195 of the first chip structure CS1, the first wiring structure 160 and the lower wiring structure 260 can be bonded to each other.

[0141] In this process, the first bonding pad 195 of the first chip structure CS1 and the second bonding pad 295 of the second chip structure CS2 can be bonded to each other. The directly bonded first bonding pad 195 and second bonding pad 295 can be joined to each other through interdiffusion of metals (such as copper) via a high-temperature annealing process. In addition, the first bonding insulating layer 192 of the first chip structure CS1 and the second bonding insulating layer 292 of the second chip structure CS2 can be bonded to each other.

[0142] Figure 14 is a flowchart showing a method of manufacturing a semiconductor device according to some implementations.

[0143] Referring to Figure 14 , similar to Figure 9The process can form a lower chip structure (also referred to as the "first chip structure") including a lower bonding pad (S610), and can form an upper chip structure (also referred to as the "second chip structure") including an upper bonding pad (S620). Here, the lower chip structure can include peripheral circuit transistors, and the upper chip structure can include a memory structure containing memory cells.

[0144] Thereafter, by bonding the upper bonding pad to the lower bonding pad, the upper chip structure can be disposed on the lower chip structure (S640).

[0145] In this example, before forming a wiring structure on the substrate of the upper chip structure, a hydrogen-containing insulating layer can be included (S650). Thereafter, a wiring structure (e.g., Figure 8 the first upper wiring structure 180 in

[0146] can be formed (S660), and external connection pads can be further formed on the wiring structure.

[0147] Thus, by forming a hydrogen-containing insulating layer in a region adjacent to the memory structure in the upper chip structure, hydrogen can be supplied to effectively repair defects in the memory cells. In addition, before forming the wiring structure, by performing an annealing process for hydrogen diffusion, hydrogen diffusion into the wiring layer can be prevented. Figure 8 As shown in Figures 15A to 15E , in some implementations, a hydrogen-containing insulating layer 155B can be provided on a first substrate 110 of a second chip structure CS2 including a memory structure MS. The method of manufacturing a semiconductor device 300B will be described with reference to Figure 14 and is an example of the process of

[0148] Referring to Figure 15A , a second substrate 210' on which peripheral circuit transistors 250 and an intermediate wiring structure 220 are formed can be bonded to the upper surface of a base substrate 130. In this process, the second substrate 210' on which peripheral circuit transistors 250 are formed can be formed by a process similar to the process in Figure 11A .

[0149] The connection between the second substrate 210' and the base substrate 130 can be achieved by bonding between a dielectric layer 132 on the base substrate 130 and a dielectric of an intermediate insulating layer 221. In some implementations, the dielectric layer 132 can be formed by natural oxidation without an additional deposition process.

[0150] Thereafter, referring to Figure 15B, the second substrate 210' can be polished, and a second via 270 that penetrates the polished second substrate 210 and is electrically connected to the intermediate wiring structure 220 can be formed. Thereafter, a second upper wiring structure 260 having a second upper wiring layer 265 electrically connected to the second via 270 can be formed on the second substrate 210. In addition, a second bonding structure can be formed on the upper surface of the second upper wiring structure 260. The second bonding structure can include a second bonding insulating layer 292 provided on the second upper wiring structure 260 and second bonding pads 295 buried in the second bonding insulating layer 292.

[0151] The second bonding pads 295 can be electrically connected to the second upper wiring layer 265.

[0152] Thereafter, referring to Figure 15C , a memory structure MS (e.g., similar to the process in Figure 10A ) can be formed on the first substrate 110'. Thereafter, a first lower wiring structure 160 having a first lower wiring layer 165 electrically connected to the memory structure MS can be formed on the first substrate 110', and similar to the process in Figure 10D , a first bonding structure can be formed on the upper surface of the first lower wiring structure 160. The first bonding structure can include a first bonding insulating layer 192 provided on the first lower wiring structure 160 and first bonding pads 195 buried in the first bonding insulating layer 192. The first bonding pads 195 can be electrically connected to the first lower wiring layer 165.

[0153] Thereafter, referring to Figure 15D , by bonding the first bonding pads 195 to the second bonding pads 295, the first lower wiring structure 160 can be bonded (in a secondary bonding process) to the upper surface of the second upper wiring structure 260. After the secondary bonding process, the first substrate 110' can be polished, and a hydrogen-containing insulating layer 155B (as shown in Figure 8 ) can be formed on the polished first substrate 110.

[0154] The hydrogen-containing insulating layer 155B can be provided on the upper surface of the first substrate 110 such that the hydrogen-containing insulating layer 155B can be disposed adjacent to the memory structure MS provided on the lower surface of the first substrate 110. In some implementations, the hydrogen-containing insulating layer 155B is formed as a complete layer, e.g., rather than multiple insulating patterns, or in addition to multiple insulating patterns. In some implementations, a second barrier insulating film 152 can be disposed between the hydrogen-containing insulating layer 155B and the first upper wiring structure 180 ( Figure 15EAs shown in []. The second barrier insulating film 152 can prevent hydrogen from diffusing toward the first upper wiring structure 180. By performing an annealing process for hydrogen diffusion, hydrogen diffusion into the first upper wiring layer 185 can be reduced or prevented. Therefore, in components that may be adversely affected by diffusion, a low hydrogen content can be maintained or diffusion can be prevented.

[0155] Thereafter, referring to Figure 15E , a first through-via 170 that penetrates the first substrate 110 and is electrically connected to the first lower wiring layer 165 can be formed, and a first upper wiring structure 180 having a first upper wiring layer 185 electrically connected to the first through-via 170 can be formed on the first substrate 110. The first through-via 170 can be formed to penetrate the hydrogen-containing insulating layer 155B, the second barrier insulating film 152, and the first substrate 110. In addition, input / output pads connected to the first upper wiring layer 185 can be formed on the first upper wiring structure 180.

[0156] Figure 16 is a cross-sectional view showing a semiconductor device according to some implementations.

[0157] Referring to Figure 16 , the semiconductor device 300D includes a second chip structure CS2 (or “lower chip structure”) and a first chip structure CS1 (also referred to as “upper chip structure”), and the first chip structure CS1 is stacked on the second chip structure CS2 in the vertical direction (Z direction).

[0158] The first chip structure CS1 can include a memory structure MS, a cell routing wiring structure 140 electrically connected to the memory structure MS, and an interlayer insulating layer 121 covering the memory structure MS.

[0159] The memory structure MS may include a bit line BL, a cell transistor CTR, and a data storage structure DS. As described with respect to semiconductor device 300D, the bit line BL may be electrically connected to a sense amplifier. In some implementations, the data storage structure DS and the cell transistor CTR are disposed on the bit line BL. The cell transistor CTR may be disposed between the bit line BL and the data storage structure DS. As described with respect to semiconductor device 300D, the cell transistor CTR may be included in a memory cell region. The cell transistor CTR may be configured as a vertical channel transistor and may include first and second source / drain regions 112a and 112b, a cell active region (in this example, a cell vertical channel region) 113, and a word line WL (or gate electrode). The first and second source / drain regions 112a and 112b may be disposed in an upper region of the cell transistor CTR. The first source / drain region 112a may be spaced apart from the second source / drain region 112b in a vertical direction (e.g., the Z direction). The first source / drain region 112a may be connected to a cell contact structure 125 disposed thereon, and the second source / drain region 112b may be connected to the bit line BL disposed thereunder.

[0160] In some implementations, the word line WL (or gate electrode) is disposed to face one side surface of the cell vertical channel region 113. For example, the word line WL may include doped polysilicon, metal, conductive nitride, metal semiconductor compound, conductive oxide, conductive graphene, carbon nanotube, or a combination thereof. In some implementations, the word line WL includes a single layer or multiple layers formed of the above materials.

[0161] The cell transistor CTR may include a gate dielectric layer 114 between the cell vertical channel region 113 and the word line WL. The gate dielectric layer 114 may include at least one of silicon oxide and a high-k dielectric. The high-k dielectric may have a dielectric constant higher than that of silicon oxide. The high-k dielectric may include a metal oxide or a metal nitride oxide. For example, the high-k dielectric may include HfO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, ZrO2, Al2O3, or a combination thereof. In some implementations, the gate dielectric layer 114 is formed as a single layer or multiple layers formed of the above materials.

[0162] The data storage structure DS may include a first electrode E1, a second electrode E2 on the first electrode E1, and a dielectric layer DL between the first electrode E1 and the second electrode E2. The data storage structure DS may be a storage cell capacitor capable of storing data in a memory such as DRAM.

[0163] In some implementations, the memory structure MS includes a cell contact structure 125 disposed between the cell transistor CTR and the data storage structure DS. In some implementations, the cell contact structure 125 penetrates the cell insulation layer 124 and may include a first cell contact layer 125a and a second cell contact layer 125b. The first cell contact layer 125a may contact the cell transistor CTR and may be electrically connected to the second source / drain region 112b. For example, the first cell contact layer 125a may be formed as a silicon layer.

[0164] The first chip structure CS1 may further include an etch stop layer 123 covering the cell insulation layer 124 and the cell contact structure 125. The data storage structure DS may penetrate the etch stop layer 123 and may be electrically connected to the cell contact structure 125. The second cell contact layer 125b may be disposed on the first cell contact layer 125a and may contact the data storage structure DS. As described above, the second cell contact layer 125b may serve as a landing pad for the data storage structure DS.

[0165] In some implementations, the cell routing wiring structure 140 includes a routing wiring layer 145 electrically connected to the bit line BL and an insulation layer 141 covering the routing wiring layer 145. The routing wiring layer 145 may include routing wiring vias 143 and routing wiring patterns 142 connected to the routing wiring vias 143. In some implementations, the cell routing wiring structure 140 includes a wiring layer that includes a third through via 170a disposed in the interlayer insulation layer 121.

[0166] In some implementations, the first chip structure CS1 may include a first upper wiring structure 180 disposed on the interlayer insulation layer 121 including the memory structure MS. The first upper wiring structure 180 may have a first upper insulation layer 181 and a first upper wiring layer 185 disposed in the first upper insulation layer 181. The first upper wiring layer 185 may be electrically connected to the bit line and / or the routing wiring layer 145 through the third through via 170a and the fourth through via 170b. The first upper wiring layer 185 may include a plurality of first upper wiring patterns 182 disposed at different levels in the first upper insulation layer 181 and first upper wiring vias 183 connected to the plurality of first upper wiring patterns 182. In some implementations, the input / output pad 310 is electrically connected to the first upper wiring layer 185 and may be formed on the upper surface of the first upper wiring structure 180.

[0167] In some implementations, the first chip structure CS1 may further include a first lower wiring structure 160 disposed on the lower surface of the cell routing and wiring structure 140. The first wiring structure 160 may include a first wiring layer 165 connected to the routing and wiring layer 145 and a first insulating layer 161 covering the first wiring layer 165. The first wiring layer 165 may include a plurality of first wiring patterns 162 disposed at different levels in the first insulating layer 161 and first wiring vias 163 connected to the plurality of first wiring patterns 162. In some implementations, the first wiring layer 165 is electrically connected to the bit line BL of the storage structure MS through a portion of the routing and wiring layer 145. In addition, the first wiring layer 165 may be connected to the data storage structure DS through a fourth through-via 170b connected to the first upper wiring layer 185 and another portion of the routing and wiring layer 145.

[0168] The first chip structure CS1 may include a bonding structure for connecting to the second chip structure CS2, and may include a first bonding insulating layer 192 disposed on the lower surface of the first lower wiring structure 160 and a first bonding pad 195 that is open to the first bonding insulating layer 192 and electrically connected to the first lower wiring layer 165. The first bonding pad 195 may be substantially coplanar with the surface of the first bonding insulating layer 192.

[0169] Figure 16 The second chip structure CS2 may include a second substrate 210, peripheral circuit transistors 250 disposed on the upper surface of the second substrate 210, and a second wiring structure 260 disposed on the upper surface of the second substrate 210.

[0170] The second substrate 210 may include an active region in which peripheral circuit transistors 250 similar to those described with reference to the semiconductor device 300 are formed. The peripheral circuit transistors 250 may include gate electrodes 255 on the active region, gate dielectric layers 256 between the gate electrodes 255 and the active region, and source / drains 252 and 253 in the active region on both sides of the gate electrodes 255. For example, the peripheral circuit transistors 250 may include transistors that vertically overlap the storage structure MS and transistors that vertically overlap the peripheral circuit region.

[0171] An intermediate wiring structure 220 may be disposed between the second substrate 210 and the second wiring structure 260. The intermediate wiring structure 220 may include an intermediate insulating layer 221 and an intermediate wiring layer 225 disposed in the intermediate insulating layer 221 and connected to the peripheral circuit transistors 250. The intermediate wiring layer 225 may electrically connect the peripheral circuit transistors 250 on the second substrate 210 and may form a peripheral circuit. The intermediate wiring layer 225 may include conductive lines 222 and contact vias 223 connected to the conductive lines 222.

[0172] The second wiring structure 260 may include a second insulating layer 261 disposed on the intermediate wiring structure 220, and may include a second wiring layer 265 connected to the intermediate wiring layer 225. The second wiring layer 265 may include a plurality of lower wiring patterns 262 disposed at different levels in the second insulating layer 261 and lower wiring vias 263 connected to the plurality of lower wiring patterns 262.

[0173] The second chip structure CS2 may include a second bonding structure 290, similar to the first bonding structure of the first chip structure CS1. The second bonding structure may include a second bonding insulating layer 292 disposed on the second wiring structure 260 and second bonding pads 295 that are open to the second bonding insulating layer 292 and electrically connected to the second wiring layer 265.

[0174] The first bonding pad 195 of the first chip structure CS1 and the second bonding pad 295 of the second chip structure CS2 may be bonded to each other. The directly bonded first bonding pad 195 and second bonding pad 295 may be joined to each other via a high-temperature annealing process by interdiffusion between metals (such as copper). The metals included in the first bonding pad 195 and the second bonding pad 295 are not limited to copper and may include other metal materials (such as Au) that can be bonded under similar conditions. Through the bonding between the first bonding pad 195 and the second bonding pad 295, the first chip structure CS1 and the second chip structure CS2 may be firmly mechanically joined and electrically connected to each other.

[0175] In addition, the first bonding insulating layer 192 of the first chip structure CS1 and the second bonding insulating layer 292 of the second chip structure CS2 may be bonded to each other. The first bonding insulating layer 192 and the second bonding insulating layer 292 may include the same dielectric material, such as silicon oxide. In some implementations, the first bonding insulating layer 192 and the second bonding insulating layer 292 respectively include insulating materials different from the insulating materials of the first lower insulating layer 161 and the second insulating layer 261, or may also include insulating films of different materials. For example, other materials may include other insulating films, such as SiCN, SiON, or SiCO.

[0176] In some implementations, a portion of the insulating structure of semiconductor device 300D can be provided as a hydrogen supply layer formed of a hydrogen-containing insulating material. The insulating structure serving as hydrogen supply layer HP can be included in the process of manufacturing first chip structure CS1 and second chip structure CS2. Similar to the hydrogen-containing insulating layer described above, by diffusing hydrogen via an annealing process before or after bonding first chip structure CS1 and second chip structure CS2, defects (such as dangling bonds) of the memory cells generated during the process of manufacturing semiconductor device 300D (such as oxidation process, plasma etching process, etc.) can be resolved. By including the hydrogen-containing insulating layer 155 (hydrogen source) in semiconductor device 300D and diffusing hydrogen via an annealing process, hydrogen can be supplied to memory cell structure MC.

[0177] In some implementations, at least one of first bonding insulating layer 192 and second bonding insulating layer 292 is provided as hydrogen supply layer HP. As Figure 16 shown, second bonding insulating layer 292 (HP1) can be formed of an insulating material containing a high enough concentration of hydrogen and / or deuterium to supply hydrogen to surrounding components. For example, second bonding insulating layer 292 serving as hydrogen supply layer HP1 can be a silicon oxide containing hydrogen and / or deuterium. In some implementations, second bonding insulating layer 292 can be a silicon oxide deposited using oxygen (O2) and silane (SiH4) gases. For example, second bonding insulating layer 292 can be deposited using plasma enhanced chemical vapor deposition (PECVD), or can be an oxide formed by high density plasma chemical vapor deposition (HDP-CVD). Instead of, or in addition to, second bonding insulating layer 292, these descriptions can equally apply to first bonding insulating layer 192.

[0178] As described above, in the process of manufacturing each of first chip structure CS1 and second chip structure CS2, various different insulating structures can be selectively provided as hydrogen-containing insulating layers.

[0179] Figures 17A to 17C is a cross-sectional view of a semiconductor device according to some implementations. Referring to Figure 17A , semiconductor device 300E can be similar to the structure described with reference to Figure 16 (e.g., can have the same characteristics except as otherwise noted), and can have a configuration in which multiple insulating layers 161 and 192 of first chip structure CS1 are provided as hydrogen supply layer HP.

[0180] In Figure 17AIn the example, each of the first lower insulating layer 161 and the first bonding insulating layer 192 of the first chip structure CS1 can be provided as a hydrogen supply layer HP. The first lower insulating layer 161 and the first bonding insulating layer 192 can be formed of an insulating material containing hydrogen and / or deuterium. For example, the first lower insulating layer 161 and the first bonding insulating layer 192 as the hydrogen supply layer HP can be silicon oxides containing hydrogen and / or deuterium. In an annealing process for treating defects in adjacent memory structures MS, hydrogen can diffuse from the first lower insulating layer 161 and the first bonding insulating layer 192 into the memory structures MS. In some implementations, the annealing process can be performed in the process of manufacturing the first chip structure before bonding to the second chip structure.

[0181] Referring to Figure 17B , semiconductor device 300F can be similar to Figure 16 the example shown in (e.g., can have the same characteristics except as otherwise described). Semiconductor device 300F has a configuration in which the first lower insulating layer 161 of the first chip structure CS1 is provided as the hydrogen supply layer HP.

[0182] For example, only the first lower insulating layer 161 of the first chip structure CS1 can be provided as the hydrogen supply layer HP. The first lower insulating layer 161 can include a plurality of insulating layers, and each insulating layer can be formed of an insulating material containing hydrogen and / or deuterium. For example, the first lower insulating layer 161 as the hydrogen supply layer HP can be silicon oxide containing hydrogen and / or deuterium. In an annealing process for treating defects in adjacent memory structures MS, hydrogen can diffuse from the first lower insulating layer 161 into the memory structures MS.

[0183] Referring to Figure 17C , semiconductor device 300G can be similar to Figure 16 the example shown in (e.g., can have the features described with respect to Figure 16 except as otherwise described), and can have a configuration in which the insulating layers 161 and 192 of the first chip structure CS1 and the insulating layers 261 and 292 of the second chip structure CS2 are respectively provided as the hydrogen supply layer HP.

[0184] Each of the first lower insulating layer 161 and the first bonding insulating layer 192 of the first chip structure CS1 and the second insulating layer 261 and the second bonding insulating layer 292 of the second chip structure CS2 can be provided as the hydrogen supply layer HP. The first insulating layer 161 and the second insulating layer 261 and the first bonding insulating layer 192 and the second bonding insulating layer 292 can be formed of an insulating material containing hydrogen and / or deuterium. For example, the hydrogen supply layer HP can be silicon oxide containing hydrogen and / or deuterium.

[0185] Various configurations and arrangements of the hydrogen supply layer can be applied to various semiconductor device structures.Figure 18A and Figure 18B is a view showing a semiconductor device according to some implementations.

[0186] Referring to Figure 18A , the semiconductor device 300H includes a second chip structure CS2 and two first chip structures CS1a and CS1b stacked in sequence on the second chip structure CS2.

[0187] The two first chip structures can be configured such that each has a first lower chip structure CS1a and a first upper chip structure CS1b having a storage structure ( Figure 16 "MS" in Figure 16 ), similar to the first chip structure CS1 in

[0188] Similar to Figure 16 the second chip structure CS2 in

[0189] The second chip structure CS2 may include a peripheral circuit. Bonding structures 190B and 190C may be formed on the first upper wiring structure 180 of the first lower chip structure CS1a and on the lower wiring structure 160B of the first upper chip structure CS1b, respectively. The first lower chip structure CS1a and the first upper chip structure CS1b may be electrically and mechanically connected to each other through the bonding structures 190B and 190C.

[0190] Referring to Figure 18B , a semiconductor device 300I according to some implementations may be similar to Figure 18Aconfigured with the examples of (e.g., they may have the same characteristics, except where otherwise noted), and may have a configuration in which the second chip structure includes a second lower chip structure CS2a and a second upper chip structure CS2b, and the first hydrogen supply layer HP_A′ may be implemented differently.

[0191] Similar to Figure 16 the second chip structure CS2 in , the two second chip structures may be configured as a second lower chip structure CS2a and a second upper chip structure CS2b, where the peripheral circuit transistors are separately provided. Bonding structures 290B and 290A may be formed on the lower wiring structure 260B of the second upper chip structure CS2b and on the upper wiring structure 260A of the second lower chip structure CS2a, respectively. In addition, the second lower chip structure CS2a and the second upper chip structure CS2b may be electrically and mechanically connected to each other through the bonding structures 290B and 290A.

[0192] The insulating structure of the semiconductor device 300I may be provided as a hydrogen supply layer. For example, similar to Figure 18A the configuration of , the insulating structure between the first lower chip structure CS1a and the first upper chip structure CS1b may be provided as a second hydrogen supply layer HP_B. The second hydrogen supply layer HP_B may include the insulating layers of each of the first upper wiring structure 180 of the first lower chip structure CS1a and the bonding structure 190B, and the insulating layers of each of the lower wiring structure 160B of the first upper chip structure CS1b and the bonding structure 190C.

[0193] The insulating structure between the second upper chip structure CS2b and the first lower chip structure CS1a may be provided as a first hydrogen supply layer HP_A'. The first hydrogen supply layer HP_A′ may include the insulating layers of each of the lower wiring structure 160A of the first lower chip structure CS1a and the bonding structure 190A, and the insulating layers of each of the upper wiring structure 260C of the second upper chip structure CS2b and the bonding structure 290C.

[0194] The insulating structure between the second upper chip structure CS2b and the second lower chip structure CS2a may not include any hydrogen supply layer. In some implementations, the insulating layers of each of the lower wiring structure 260B of the second upper chip structure CS2b and the bonding structure 290B, and the insulating layers of each of the upper wiring structure 260A of the second lower chip structure CS2a and the bonding structure 290A may be provided as insulating layers that do not intentionally contain hydrogen.

[0195] The configuration including the hydrogen supply layer may be selectively applied to the desired insulating structure in semiconductor devices having various structures.

[0196] Therefore, by stably supplying hydrogen through providing a hydrogen-containing insulating layer for hydrogen supply near a defect generation region (e.g., a memory cell structure), the electrical performance of a semiconductor device can be improved.

[0197] Although the present disclosure contains many specific implementation details, these should not be construed as limitations on the scope of the claimed subject matter. Certain features described in the context of separate implementations in the present disclosure can also be implemented in combination in a single implementation. Conversely, the various features described in the context of a single implementation can also be implemented separately in multiple implementations or in any suitable sub-combination. In addition, although the features may be described above as acting in certain combinations, one or more features from a combination can in some cases be deleted from the combination, and the combination can be directed to a sub-combination or a variation of the sub-combination.

[0198] Furthermore, although the various examples have been shown and described above, it will be apparent to those skilled in the art that modifications and variations can be made without departing from the scope of the present disclosure.

[0199] This application claims the benefit of the priority of Korean Patent Application No. 10-2023-0196196, filed on December 29, 2023, with the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety.

Claims

1. A semiconductor device, comprising: A first chip structure; as well as A second chip structure, based on the first chip structure, The first chip structure includes: Base substrate, A storage structure is disposed on the base substrate, A first substrate is disposed on the storage structure. a first through-via extending through the first substrate and electrically connected to the storage structure, a first wiring structure disposed on the first substrate and including a first wiring layer electrically connected to the storage structure through the first through-via, a first bonding pad disposed on an upper surface of the first wiring structure and electrically connected to the first wiring layer, and a hydrogen-containing insulating layer, arranged in a region adjacent to the storage structure in the first chip structure, and The second chip structure comprises: the second substrate, A peripheral circuit transistor is disposed on the lower surface of the second substrate, a lower wiring structure disposed on the lower surface of the second substrate and comprising a lower wiring layer electrically connected to the peripheral circuit transistor; a second bonding pad disposed on a lower surface of the lower wiring structure and electrically connected to the lower wiring layer, the second bonding pad being bonded to the first bonding pad, a second through via extending through the second substrate and electrically connected to the lower wiring layer, and An upper wiring structure is disposed on an upper surface of the second substrate and includes an upper wiring layer electrically connected to the lower wiring layer through the second through via. 2 . The semiconductor device according to claim 1 , wherein the hydrogen-containing insulating layer is disposed on an upper surface of the base substrate and adjacent to the memory structure. 3 . The semiconductor device according to claim 2 , wherein the hydrogen-containing insulating layer comprises insulating patterns provided at a plurality of trenches formed in the upper surface of the base substrate, and wherein the insulating patterns have an upper surface coplanar with the upper surface of the base substrate. 4 . The semiconductor device according to claim 2 , wherein the hydrogen-containing insulating layer is provided on the upper surface of the base substrate and has a flat upper surface.

5. The semiconductor device according to claim 2, further comprising: A barrier insulating film is provided between the hydrogen-containing insulating layer and the base substrate. 6 . The semiconductor device according to claim 1 , wherein the hydrogen-containing insulating layer is provided on an upper surface of the first substrate. 7 . The semiconductor device according to claim 6 , wherein the hydrogen-containing insulating layer comprises insulating patterns buried in a plurality of trenches formed in the upper surface of the first substrate, and wherein the insulating patterns have an upper surface coplanar with the upper surface of the first substrate. 8 . The semiconductor device according to claim 6 , wherein the hydrogen-containing insulating layer is provided on the entire area of ​​the upper surface of the first substrate and has a flat surface. 9 . The semiconductor device according to claim 1 , wherein the memory structure comprises a data storage structure on an upper surface of the base substrate and a memory cell structure stacked on the data storage structure.

10. The semiconductor device according to claim 1, wherein the upper surface of the first wiring structure is coplanar with the upper surface of the first bonding pad, and wherein the lower surface of the lower wiring structure is coplanar with the lower surface of the second bonding pad, and The upper surface of the first wiring structure is bonded to the lower surface of the lower wiring structure.

11. A semiconductor device comprising: A first chip structure; as well as A second chip structure, based on the first chip structure, The first chip structure includes: a base substrate having an upper surface on which a hydrogen-containing insulating layer is disposed, a storage structure disposed on the base substrate and adjacent to the hydrogen-containing insulating layer, a first wiring structure disposed on the storage structure and comprising a first wiring layer electrically connected to the storage structure, and a first bonding pad disposed on an upper surface of the first wiring structure and electrically connected to the first wiring layer, and The second chip structure comprises: the second substrate, A peripheral circuit transistor is disposed on the lower surface of the second substrate, a lower wiring structure disposed on the lower surface of the second substrate, the lower wiring structure comprising a lower wiring layer electrically connected to the peripheral circuit transistor, wherein the lower wiring structure is bonded to the first wiring structure, a second bonding pad disposed on a lower surface of the lower wiring structure and electrically connected to the lower wiring layer, wherein the second bonding pad is bonded to the first bonding pad, a second through via extending through the second substrate and electrically connected to the lower wiring layer, and An upper wiring structure is disposed on an upper surface of the second substrate and includes an upper wiring layer electrically connected to the lower wiring layer through the second through via.

12. The semiconductor device according to claim 11, wherein the first chip structure comprises: A first substrate, disposed between the storage structure and the first wiring structure; as well as A first through via extends through the first substrate and electrically connects the memory structure to the first wiring layer. 13 . The semiconductor device according to claim 11 , wherein the hydrogen-containing insulating layer comprises insulating patterns provided at a plurality of trenches formed in the upper surface of the base substrate, and wherein the insulating patterns have an upper surface coplanar with the upper surface of the base substrate.

14. The semiconductor device according to claim 13, further comprising: A barrier insulating film is provided between the hydrogen-containing insulating layer and the base substrate.

15. A semiconductor device comprising: A second chip structure; as well as a first chip structure, on the second chip structure, The second chip structure comprises: Base substrate, a second substrate having a lower surface opposite to the upper surface of the base substrate, a peripheral circuit transistor, disposed on the lower surface of the second substrate, a second lower wiring structure disposed between the upper surface of the base substrate and the lower surface of the second substrate and including a second lower wiring layer electrically connected to the peripheral circuit transistor, a second through via extending through the second substrate and electrically connected to the second lower wiring layer, a second upper wiring structure disposed on the upper surface of the second substrate and having a second upper wiring layer electrically connected to the second lower wiring layer through the second through via, and a second bonding pad disposed on an upper surface of the second upper wiring structure and electrically connected to the second upper wiring layer, and The first chip structure includes: a first substrate having an upper surface on which a hydrogen-containing insulating layer is disposed, A storage structure is disposed on the lower surface of the first substrate, a first lower wiring structure disposed on a lower surface of the storage structure, the first lower wiring structure comprising a first lower wiring layer electrically connected to the storage structure, wherein the first lower wiring structure is bonded to the second upper wiring structure, a first bonding pad disposed on a lower surface of the first lower wiring structure and electrically connected to the first lower wiring layer, wherein the first bonding pad is bonded to the second bonding pad, a first through via extending through the first substrate and electrically connected to the storage structure, and A first upper wiring structure is disposed on the first substrate and has a first upper wiring layer electrically connected to the memory structure through the first through via. 16 . The semiconductor device according to claim 15 , wherein the hydrogen-containing insulating layer is provided on the upper surface of the first substrate. 17 . The semiconductor device according to claim 16 , wherein the hydrogen-containing insulating layer is provided on the upper surface of the first substrate and has a flat upper surface.

18. The semiconductor device according to claim 15, further comprising: A barrier insulating film is provided between the hydrogen-containing insulating layer and the first upper wiring structure. 19 . The semiconductor device according to claim 15 , wherein the memory structure comprises a memory cell structure disposed below the lower surface of the first substrate and a data storage structure disposed below the memory cell structure.

20. A semiconductor device comprising: A second chip structure; as well as a first chip structure, on the second chip structure, The first chip structure includes: A layer structure comprising a storage structure and an interlayer insulating layer covering the storage structure, a first lower wiring structure disposed on a lower surface of the layer structure, wherein the first lower wiring structure comprises a first lower wiring layer electrically connected to the storage structure and a first lower insulating layer covering the first lower wiring layer, a first upper wiring structure disposed on an upper surface of the layer structure and comprising a first upper wiring layer, wherein the first upper wiring layer is electrically connected to the storage structure and the first lower wiring layer, a first bonding structure disposed on a lower surface of the first lower wiring structure, wherein the first bonding structure includes a first bonding pad electrically connected to the first lower wiring layer and a first bonding insulating layer surrounding the first bonding pad, and The second chip structure comprises: substrate, A peripheral circuit transistor is disposed on the upper surface of the substrate, a second wiring structure disposed on the upper surface of the substrate, wherein the second wiring structure includes a second wiring layer electrically connected to the peripheral circuit transistor and a second insulating layer covering the second wiring layer, and a second bonding structure disposed on an upper surface of the second wiring structure and electrically connected to the second wiring layer, wherein the second bonding structure includes a second bonding pad bonded to the first bonding pad and a second bonding insulating layer surrounding the second bonding pad, At least one of the first lower insulating layer, the first bonding insulating layer, the second insulating layer and the second bonding insulating layer includes a hydrogen-containing insulating material.

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