Semiconductor memory device

Abstract

A semiconductor memory device is provided. The semiconductor memory device includes: a semiconductor pattern extending in a first direction; a bit line extending in a second direction perpendicular to the first direction and connected to a first end of the semiconductor pattern in the first direction; a unit capacitor extending in the first direction and connected to a second end of the semiconductor pattern in the first direction; a gate structure extending in a third direction perpendicular to both the first direction and the second direction; and back gate structures each extending in a direction perpendicular to the third direction. The semiconductor pattern is between the gate structure and the back gate structure. The back gate structure covers one surface of the semiconductor pattern, and the gate structure covers other surfaces of the semiconductor pattern.

Description

[0001] This application claims the priority of Korean Patent Application No. 10-2023-0197698, filed with the Korean Intellectual Property Office on December 29, 2023, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0002] The present disclosure relates to a semiconductor memory device, and more particularly, to a three-dimensional semiconductor memory device. Background Art

[0003] To meet the demands for miniaturization, multi-functionality, and high performance of electronic products, high-capacity semiconductor memory devices are required. To this end, increased integration is needed to provide high-capacity semiconductor memory devices. The integration of two-dimensional semiconductor memory devices is mainly determined by the area occupied by a unit memory cell. Therefore, although the integration of two-dimensional semiconductor memory devices has been increased, the increase is still limited. Thus, three-dimensional semiconductor memory devices have been proposed to increase the memory capacity by stacking multiple memory cells vertically on a substrate. Summary of the Invention

[0004] One or more example embodiments provide a three-dimensional semiconductor memory device having improved operational reliability.

[0005] According to an aspect of an example embodiment, a semiconductor memory device includes: a semiconductor pattern extending in a first direction; a bit line extending in a second direction perpendicular to the first direction and connected to a first end of the semiconductor pattern in the first direction; a cell capacitor extending in the first direction and connected to a second end of the semiconductor pattern in the first direction; a gate structure extending in a third direction perpendicular to both the first direction and the second direction; and a back gate structure each extending perpendicular to the third direction. The semiconductor pattern is between the gate structure and the back gate structure, the back gate structure covers one surface of the semiconductor pattern, and the gate structure covers the other surface of the semiconductor pattern.

[0006] According to another aspect of the exemplary embodiment, a semiconductor memory device includes: a plurality of semiconductor patterns, each of the plurality of semiconductor patterns extending in a first horizontal direction on a substrate, wherein the plurality of semiconductor patterns are spaced apart from each other in a second horizontal direction perpendicular to the first horizontal direction and in a vertical direction; a plurality of bit lines extending in a vertical direction on the substrate, wherein the plurality of bit lines are spaced apart from each other in the second horizontal direction and are connected to a first end of the plurality of semiconductor patterns in the first horizontal direction; a plurality of unit capacitors extending in the first horizontal direction on the substrate and connected to a second end of the plurality of semiconductor patterns in the first horizontal direction; a plurality of back gate structures extending in the second horizontal direction and covering a first one of an upper surface and a lower surface of the plurality of semiconductor patterns, wherein the plurality of back gate structures are spaced apart from each other in the vertical direction; and a plurality of gate structures extending in the second horizontal direction and covering a second one of the upper surface and the lower surface of the plurality of semiconductor patterns and each of two side surfaces of the plurality of semiconductor patterns in the second horizontal direction. An upper surface and a lower surface of one of the plurality of back gate structures cover a lower surface of a first semiconductor pattern and an upper surface of a second semiconductor pattern, respectively, the first semiconductor pattern being one of the plurality of semiconductor patterns disposed above the one back gate structure, and the second semiconductor pattern being another one of the plurality of semiconductor patterns disposed below the one back gate structure.

[0007] According to another aspect of the exemplary embodiment, a semiconductor memory device includes: a plurality of semiconductor patterns, each of the plurality of semiconductor patterns extending in a first horizontal direction on a substrate, wherein the plurality of semiconductor patterns are spaced apart from each other in a second horizontal direction perpendicular to the first horizontal direction and in a vertical direction; a plurality of bit lines extending in a vertical direction on the substrate, wherein the plurality of bit lines are spaced apart from each other in the second horizontal direction and are connected to a first end of the plurality of semiconductor patterns in the first horizontal direction; a plurality of unit capacitors extending in the first horizontal direction on the substrate and connected to a second end of the plurality of semiconductor patterns in the first horizontal direction; a plurality of back gate structures, each of the plurality of back gate structures extending in the second horizontal direction, wherein the plurality of back gate structures are spaced apart from each other in the vertical direction, and each of the plurality of back gate structures includes a back gate dielectric film covering a first one of an upper surface and a lower surface of a corresponding one of the plurality of semiconductor patterns and a back gate electrode film covering the back gate dielectric film; and a plurality of gate structures, each of the plurality of gate structures extending in the second horizontal direction, wherein the plurality of gate structures are spaced apart from each other in the vertical direction, and each of the plurality of gate structures includes a gate dielectric film and a gate electrode film covering the gate dielectric film, the gate dielectric film covering a second one of an upper surface and a lower surface of a corresponding one of the plurality of semiconductor patterns and two side surfaces of the corresponding semiconductor pattern in the second horizontal direction. Two of the plurality of gate structures are between one of the plurality of semiconductor patterns and another semiconductor pattern above the one semiconductor pattern, and one of the plurality of back gate structures is between one of the plurality of semiconductor patterns and another semiconductor pattern below the one semiconductor pattern. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] The above and other aspects will become more apparent from the following description of exemplary embodiments with reference to the accompanying drawings, in which:

[0009] Figure 1 is an equivalent circuit diagram showing a cell array of a semiconductor memory device according to an exemplary embodiment;

[0010] Figure 2A 、 Figure 2B 、 Figure 2C 、 Figure 2D 、 Figure 2E 、 Figure 2F 、 Figure 2G 、 Figure 3A 、 Figure 3B 、 Figure 3C 、 Figure 3D 、 Figure 3E 、 Figure 3F 、 Figure 3G 、Figure 4A 、 Figure 4B 、 Figure 4C 、 Figure 4D 、 Figure 4E 、 Figure 4F 、 Figure 4G 、 Figure 5A 、 Figure 5B 、 Figure 5C 、 Figure 5D 、 Figure 5E 、 Figure 5F 、 Figure 5G 、 Figure 6A 、 Figure 6B 、 Figure 6C 、 Figure 6D 、 Figure 6E 、 Figure 6F 、 Figure 6G 、 Figure 7A 、 Figure 7B 、 Figure 7C 、 Figure 7D 、 Figure 7E 、 Figure 7F 、 Figure 7G 、 Figure 8A 、 Figure 8B 、 Figure 8C 、 Figure 8D 、 Figure 8E 、 Figure 8F 、 Figure 8G 、 Figure 9A 、 Figure 9B 、 Figure 9C 、 Figure 9D 、 Figure 9E 、 Figure 9F 、 Figure 9G 、 Figure 10A 、 Figure 10B 、 Figure 10C 、 Figure 10D 、 Figure 10E 、 Figure 10F 、 Figure 10G 、 Figure 11A 、 Figure 11B 、 Figure 11C 、 Figure 11D 、 Figure 11E 、 Figure 11F 、 Figure 11G 、 Figure 12A 、 Figure 12B 、 Figure 12C 、 Figure 12D 、 Figure 12E 、 Figure 12F 、 Figure 12G 、 Figure 13A 、 Figure 13B 、 Figure 13C 、 Figure 13D 、 Figure 13E 、 Figure 13F 、 Figure 13G 、 Figure 14A 、Figure 14B , Figure 14C , Figure 14D , Figure 14E , Figure 14F , Figure 14G , Figure 15A , Figure 15B , Figure 15C , Figure 15D , Figure 15E , Figure 15F , Figure 15G , Figure 16A , Figure 16B , Figure 16C , Figure 16D , Figure 16E , Figure 16F , Figure 16G , Figure 17A , Figure 17B , Figure 17C , Figure 17D , Figure 17E , Figure 17F and Figure 17G are diagrams showing a method of manufacturing a semiconductor memory device in a process sequence according to an exemplary embodiment;

[0011] Figure 18A , Figure 18B , Figure 18C , Figure 18D , Figure 18E , Figure 18F and Figure 18G are diagrams showing a semiconductor memory device according to an exemplary embodiment;

[0012] Figure 19 , Figure 20A , Figure 20B , Figure 20C and Figure 20D is a partial enlarged view of a semiconductor memory device according to an exemplary embodiment;

[0013] Figure 21 is an equivalent circuit diagram showing a cell array of a semiconductor memory device according to an exemplary embodiment;

[0014] Figure 22A , Figure 22B , Figure 22C , Figure 22D , Figure 22E , Figure 22F , Figure 22G , Figure 23A , Figure 23B , Figure 23C , Figure 23D , Figure 23E , Figure 23F , Figure 23G , Figure 24A , Figure 24B ,Figure 24C , Figure 24D , Figure 24E , Figure 24F , Figure 24G , Figure 25A , Figure 25B , Figure 25C , Figure 25D , Figure 25E , Figure 25F , Figure 25G , Figure 26A , Figure 26B , Figure 26C , Figure 26D , Figure 26E , Figure 26F , Figure 26G , Figure 27A , Figure 27B , Figure 27C , Figure 27D , Figure 27E , Figure 27F , Figure 27G , Figure 28A , Figure 28B , Figure 28C , Figure 28D , Figure 28E , Figure 28F , Figure 28G , Figure 29A , Figure 29B , Figure 29C , Figure 29D , Figure 29E , Figure 29F , Figure 29G , Figure 30A , Figure 30B , Figure 30C , Figure 30D , Figure 30E , Figure 30F , Figure 30G , Figure 31A , Figure 31B , Figure 31C , Figure 31D , Figure 31E , Figure 31F , Figure 31G , Figure 32A , Figure 32B , Figure 32C , Figure 32D , Figure 32E , Figure 32F and Figure 32G are diagrams showing a method of manufacturing a semiconductor memory device in a process sequence according to an exemplary embodiment;

[0015] Figure 33A , Figure 33B , Figure 33C , Figure 33D , Figure 33E , Figure 33F andFigure 33G is a view showing a semiconductor memory device according to an exemplary embodiment;

[0016] Figure 34 , Figure 35A , Figure 35B , Figure 35C and Figure 35D are partial enlarged views of a semiconductor memory device according to an exemplary embodiment;

[0017] Figure 36 is an equivalent circuit diagram showing a cell array of a semiconductor memory device 3 according to an exemplary embodiment;

[0018] Figure 37 is a partial enlarged view of a semiconductor memory device 3 according to an exemplary embodiment;

[0019] Figure 38 is an equivalent circuit diagram showing a cell array of a semiconductor memory device 4 according to an exemplary embodiment; and

[0020] Figure 39 is a partial enlarged view of a semiconductor memory device 4 according to an exemplary embodiment. DETAILED DESCRIPTION

[0021] Hereinafter, exemplary embodiments will be described in detail with reference to the accompanying drawings. Throughout the specification, the same components are denoted by the same reference numerals, and the repeated description thereof is omitted. It will be understood that when an element or layer is referred to as being "on," "connected to," or "coupled to" another element or layer, it can be directly on, directly connected to, or directly coupled to the other element or layer, or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on," "directly connected to," or "directly coupled to" another element or layer, there are no intervening elements or layers. The embodiments described herein are exemplary embodiments, and thus, the present disclosure is not limited thereto and can be implemented in various other forms. Each exemplary embodiment provided in the following description does not exclude being associated with one or more features of another exemplary or another exemplary embodiment provided herein or not provided herein but consistent with the present disclosure.

[0022] Figure 1 is an equivalent circuit diagram showing a cell array of a semiconductor memory device 1 according to an exemplary embodiment.

[0023] Referring to Figure 1 , the cell array of the semiconductor memory device 1 according to an exemplary embodiment may include a plurality of sub-cell arrays SCA. The plurality of sub-cell arrays SCA may be arranged in a first horizontal direction (X direction).

[0024] Each in the sub - unit array SCA may include multiple bit lines BL, multiple word lines WL, multiple back - gate lines BG, and multiple cell transistors CTR. One cell transistor CTR may be located between one word line WL and one bit line BL.

[0025] The word line WL may be spaced apart from the substrate and include a conductive pattern (e.g., a metal line) disposed above the substrate. Multiple word lines WL may extend in a second horizontal direction (Y - direction). The second horizontal direction (Y - direction) may be perpendicular to the first horizontal direction (X - direction). The word lines WL in one sub - unit array SCA may be spaced apart from each other in a vertical direction (Z - direction). Each of the back - gate lines BG may be spaced apart from the substrate and include a conductive pattern (e.g., a metal line) disposed above the substrate. Multiple back - gate lines BG may extend in the second horizontal direction (Y - direction). The back - gate lines BG in one sub - unit array SCA may be spaced apart from each other in the vertical direction (Z - direction).

[0026] The word lines WL and the back - gate lines BG in one sub - unit array SCA may be spaced apart from each other in the vertical direction (Z - direction) and extend parallel to each other in the second horizontal direction (Y - direction). Each of the multiple back - gate lines BG may be located between a pair of adjacent word lines WL among the word lines WL. In one sub - unit array SCA, the number of word lines WL may be approximately twice the number of back - gate lines BG. For example, the word lines WL and the back - gate lines BG in one sub - unit array SCA may be configured such that two word lines WL among the word lines WL and one back - gate line BG among the back - gate lines BG are alternately arranged in the vertical direction (Z - direction). In this regard, one back - gate line BG among the back - gate lines BG may be located between two word lines WL that are adjacent to each other in the vertical direction (Z - direction) in one sub - unit array SCA. In addition, two word lines WL among the word lines WL may be arranged between two back - gate lines BG that are adjacent to each other in the vertical direction (Z - direction) in one sub - unit array SCA.

[0027] The bit line BL may include a conductive pattern (e.g., a metal line) extending from the substrate in the vertical direction (Z - direction). The bit lines BL in one sub - unit array SCA may be spaced apart from each other in the second horizontal direction (Y - direction).

[0028] The gate of the cell transistor CTR may be connected to the word line WL, and the source of the cell transistor CTR may be connected to the bit line BL. The cell transistor CTR may be connected to the cell capacitor CAP. The drain of the cell transistor CTR may be connected to the first electrode of the cell capacitor CAP, and the second electrode of the cell capacitor CAP may be connected to the ground line PP.

[0029] The semiconductor memory device 1 may include a plurality of sub - cell arrays SCA. Each of the plurality of sub - cell arrays SCA includes a plurality of memory cells MC, a plurality of bit lines BL, and a plurality of word lines WL. The plurality of memory cells MC are spaced apart from each other in the second horizontal direction (Y - direction) and the vertical direction (Z - direction) and are arranged in rows and columns. The plurality of bit lines BL are connected to the cell transistors CTR of the memory cells MC arranged in the vertical direction (Z - direction), extend in the vertical direction (Z - direction), and are spaced apart from each other in the second horizontal direction (Y - direction). The plurality of word lines WL extend in the second horizontal direction (Y - direction) and are spaced apart from each other in the vertical direction (Z - direction). The plurality of sub - cell arrays SCA may be arranged in the first horizontal direction (X - direction).

[0030] The first horizontal direction (X - direction), the vertical direction (Z - direction), and the second horizontal direction (Y - direction) may be referred to as the first direction, the second direction, and the third direction, respectively. The first direction, the second direction, and the third direction may be perpendicular to each other.

[0031] Figures 2A to 17G is a diagram showing a method of manufacturing a semiconductor memory device in a process sequence according to an exemplary embodiment. Specifically, Figure 2A 、 Figure 3A 、 Figure 4A 、 Figure 5A 、 Figure 6A 、 Figure 7A 、 Figure 8A 、 Figure 9A 、 Figure 10A 、 Figure 11A 、 Figure 12A 、 Figure 13A 、 Figure 14A 、 Figure 15A 、 Figure 16A and Figure 17A are horizontal cross - sectional views of the semiconductor memory device taken along the vertical height A of Figure 2D 、 Figure 3D 、 Figure 4D 、 Figure 5D 、 Figure 6D 、 Figure 7D 、 Figure 8D 、 Figure 9D 、 Figure 10D 、 Figure 11D 、 Figure 12D 、 Figure 13D 、 Figure 14D 、 Figure 15D 、 Figure 16D and Figure 17D In addition, Figure 2B 、 Figure 3B 、 Figure 4B 、 Figure 5B 、 Figure 6B 、 Figure 7B 、 Figure 8B 、Figure 9B , Figure 10B , Figure 11B , Figure 12B , Figure 13B , Figure 14B , Figure 15B , [[ID=26 and ​ are the horizontal cross-sectional views of the semiconductor memory device taken along the vertical height B of ​ , ​ , ​ , Figure 5D , Figure 6D , Figure 7D , Figure 8D , Figure 9D , Figure 10D , Figure 11D , Figure 12D , Figure 13D , Figure 14D , Figure 15D , Figure 16D and Figure 17D In addition, Figure 2C , Figure 3C , Figure 4C , Figure 5C , Figure 6C , Figure 7C , Figure 8C , Figure 9C , Figure 10C , Figure 11C , Figure 12C , Figure 13C , Figure 14C , Figure 15C , Figure 16C and Figure 17C are the horizontal cross-sectional views of the semiconductor memory device taken along the vertical height C of Figure 2D , Figure 3D , Figure 4D , Figure 5D , Figure 6D , Figure 7D , Figure 8D , Figure 9D , Figure 10D , Figure 11D , Figure 12D , Figure 13D , Figure 14D , Figure 15D , Figure 16D and Figure 17D In addition, Figure 2D , Figure 3D , Figure 4D , Figure 5D , Figure 6D , Figure 7D , Figure 8D , Figure 9D , Figure 10D , Figure 11D , Figure 12D, Figure 13D , Figure 14D , Figure 15D , Figure 16D and Figure 17D are vertical cross-sectional views of a semiconductor memory device taken along line D-D' of Figure 2A , Figure 3A , Figure 4A , Figure 5A , Figure 6A , Figure 7A , Figure 8A , Figure 9A , Figure 10A , Figure 11A , Figure 12A , Figure 13A , Figure 14A , Figure 15A , Figure 16A and Figure 17A . In addition, Figure 2E , Figure 3E , Figure 4E , Figure 5E , Figure 6E , Figure 7E , Figure 8E , Figure 9E , Figure 10E , Figure 11E , Figure 12E , Figure 13E , Figure 14E , Figure 15E , Figure 16E and Figure 17E are vertical cross-sectional views of a semiconductor memory device taken along line E-E' of Figure 2A , Figure 3A , Figure 4A , Figure 5A , Figure 6A , Figure 7A , Figure 8A , Figure 9A , Figure 10A , Figure 11A , Figure 12A , Figure 13A , Figure 14A , Figure 15A , Figure 16A and Figure 17A . In addition, Figure 2F , Figure 3F , Figure 4F , Figure 5F , Figure 6F , Figure 7F , Figure 8F , Figure 9F , Figure 10F , Figure 11F , Figure 12F , Figure 13F , Figure 14F , Figure 15F ,Figure 16F and Figure 17F is a vertical cross-sectional view of a semiconductor memory device taken along line F-F' of Figure 2A , Figure 3A , Figure 4A , Figure 5A , Figure 6A , Figure 7A , Figure 8A , Figure 9A , Figure 10A , Figure 11A , Figure 12A , Figure 13A , Figure 14A , Figure 15A , Figure 16A and Figure 17A . In addition, Figure 2G , Figure 3G , Figure 4G , Figure 5G , Figure 6G , Figure 7G , Figure 8G , Figure 9G , Figure 10G , Figure 11G , Figure 12G , Figure 13G , Figure 14G , Figure 15G , Figure 16G and Figure 17G is a vertical cross-sectional view of a semiconductor memory device taken along line G-G' of Figure 2A , Figure 3A , Figure 4A , Figure 5A , Figure 6A , Figure 7A , Figure 8A , Figure 9A , Figure 10A , Figure 11A , Figure 12A , Figure 13A , Figure 14A , Figure 15A , Figure 16A and Figure 17A .

[0032] Refer to together Figures 2A to 2G, a plurality of first insulating layers 210, a plurality of semiconductor layers 220, and a plurality of second insulating layers 230 are formed on a substrate 110. The plurality of first insulating layers 210, the plurality of semiconductor layers 220, and the plurality of second insulating layers 230 can be formed by a chemical vapor deposition (CVD) process, a plasma enhanced CVD (PECVD) process, or an atomic layer deposition (ALD) process. The semiconductor layers 220 can be disposed above and below the second insulating layers 230, and the first insulating layers 210 or the second insulating layers 230 can be disposed above and below the semiconductor layers 220. A sub-stack structure including the first insulating layer 210, the semiconductor layer 220, the second insulating layer 230, and the semiconductor layer 220 can be repeatedly stacked on the substrate 110. In some example embodiments, each of the first insulating layer 210, the semiconductor layer 220, and the second insulating layer 230 can have a thickness of about 10 nm to about 40 nm.

[0033] In some example embodiments, a first insulating layer 210M among the plurality of first insulating layers 210 that is located between two semiconductor layers 220 adjacent to each other in a vertical direction (Z direction) can be thicker than other first insulating layers 210. For ease of description, the first insulating layer 210M among the plurality of first insulating layers 210 that is located between two semiconductor layers 220 adjacent to each other in the vertical direction (Z direction) can be referred to as an intermediate insulating layer 210M. For example, the intermediate insulating layer 210M can have a thickness that is about twice the thickness of other first insulating layers 210. In some example embodiments, the intermediate insulating layer 210M can have a thickness of about 20 nm to about 40 nm, and other first insulating layers 210 can have a thickness of about 10 nm to about 40 nm.

[0034] In some example embodiments, the intermediate insulating layer 210M can include a stack of two first insulating layers 210 obtained by forming the first insulating layer 210 twice continuously. For example, a sub-stack structure including the first insulating layer 210, the semiconductor layer 220, the second insulating layer 230, the semiconductor layer 220, and the first insulating layer 210 can be repeatedly stacked on the substrate 110. In some example embodiments, the intermediate insulating layer 210M can include a stack of two first insulating layers 210 obtained by forming the first insulating layer 210 twice continuously, and an interface between the two stacked first insulating layers 210 may not be observable. In some example embodiments, an interface between the two stacked first insulating layers 210 can be observable.

[0035] The substrate 110 may include, for example, silicon (Si) (such as crystalline Si, polycrystalline Si, and amorphous Si). In addition, the substrate 110 may include a semiconductor element (such as germanium (Ge)), or may include at least one compound semiconductor selected from the group consisting of silicon germanium (SiGe), silicon carbide (SiC), gallium arsenide (GaAs), indium arsenide (InAs), and indium phosphide (InP). In addition, the substrate 110 may include a silicon-on-insulator (SOI) substrate or a germanium-on-insulator (GeOI) substrate. For example, the substrate 110 may have a buried oxide (BOX) layer. The substrate 110 may include a conductive region (e.g., a well doped with impurities or a structure doped with impurities).

[0036] The first insulating layer 210, the semiconductor layer 220, and the second insulating layer 230 may include materials having an etching selectivity with respect to each other. For example, different etching recipes may be used to etch each of the first insulating layer 210, the semiconductor layer 220, and the second insulating layer 230. In some example embodiments, the first insulating layer 210 may include a nitride, and the second insulating layer 230 may include an oxide. For example, the first insulating layer 210 may include silicon nitride, and the second insulating layer 230 may include silicon oxide. In some example embodiments, the semiconductor layer 220 may include a material having the same or similar etching characteristics as the substrate 110, or include the same material as the substrate 110. In some example embodiments, the semiconductor layer 220 may include Si. In some example embodiments, the semiconductor layer 220 may include a single-crystal semiconductor material. For example, the semiconductor layer 220 may include single-crystal Si. In some example embodiments, the semiconductor layer 220 may include a 2D semiconductor material or an oxide semiconductor material. For example, the 2D semiconductor material may include MoS2, WSe2, graphene, carbon nanotubes, or a combination thereof. For example, the oxide semiconductor material may include InxGayZnzO, In x Ga y Si z O, In x Sn y Zn z O, In x Zn y O, Zn x O, Zn x Sn y O, Zn x O y N, Zr x Zn y Sn z O, Sn x O, Hf x In y Zn z O, Ga x Zn y Snz O, Al x Zn y Sn z O, Yb x Ga y Zn z O, In x Ga y O or a combination thereof, where each of x, y, and z represents a value greater than or equal to 1. For example, the semiconductor layer 220 may include a single layer or multiple layers of an oxide semiconductor material. In some example embodiments, the semiconductor layer 220 may include a material having a bandgap energy greater than that of silicon. For example, the semiconductor layer 220 may include a material having a bandgap energy of about 1.5 eV to 5.6 eV. For example, each of the semiconductor layers 220 may include a material that exhibits optimal channel performance when having a bandgap energy of about 2.0 eV to 4.0 eV.

[0037] Refer to together Figures 3A to 3G , a plurality of first trim spaces TS1 are formed, and the plurality of first trim spaces TS1 pass through the plurality of first insulating layers 210, the plurality of semiconductor layers 220, and the plurality of second insulating layers 230, but are spaced apart from each other in a plan view. Two of the plurality of first trim spaces TS1 may be arranged in a first horizontal direction (X direction), and the first trim spaces TS1 may be arranged in rows in a second horizontal direction (Y direction). The substrate 110 may be exposed from the bottom surface of each of the plurality of first trim spaces TS1.

[0038] The plurality of first trim spaces TS1 may have substantially the same horizontal width and horizontal area in a vertical direction (Z direction), but the example embodiments are not limited thereto. For example, each of the plurality of first trim spaces TS1 may have a tapered shape in which its horizontal width and horizontal area increase away from the substrate 110 in the vertical direction (Z direction).

[0039] Refer to together Figures 4A to 4G , a portion of the plurality of semiconductor layers 220 is removed through the plurality of first trim spaces TS1 to form a plurality of first expansion spaces ES1 in each of the plurality of semiconductor layers 220. For example, a portion of the semiconductor layer may be removed through an etching operation. Each of the plurality of first expansion spaces ES1 may be formed such that two first trim spaces TS1 adjacent to each other in a first horizontal direction (X direction) in each of the plurality of semiconductor layers 220 are connected.

[0040] The horizontal width of the first expansion space ES1 of the semiconductor layer 220 in each of the first horizontal direction (X direction) and the second horizontal direction (Y direction) may be greater than the horizontal width of the coverage area occupied by two first trimming spaces TS1 disposed in each of the first insulating layer 210 and the second insulating layer 230 and adjacent to each other in the first horizontal direction (X direction).

[0041] Refer to together Figures 4A to 4G and Figures 5A to 5G , portions of each of the plurality of first insulating layers 210 and the plurality of second insulating layers 230 are removed to form a plurality of second trimming spaces TS2, in which the plurality of first trimming spaces TS1 disposed in each of the plurality of first insulating layers 210 and the plurality of second insulating layers 230 are expanded.

[0042] In some example embodiments, a mask layer is formed on the stacked structure of the plurality of first insulating layers 210, the plurality of semiconductor layers 220, and the plurality of second insulating layers 230. The mask layer corresponds to the semiconductor layer 220 and portions of the first insulating layer 210 and the second insulating layer 230 located between two first trimming spaces TS1 adjacent to each other in the first horizontal direction (X direction) in a plan view. Subsequently, portions of each of the plurality of first insulating layers 210 and the plurality of second insulating layers 230 may be removed using the mask layer as an etching mask to form a plurality of second trimming spaces TS2.

[0043] In some example embodiments, portions of each of the plurality of first insulating layers 210 and the plurality of second insulating layers 230 are removed using an etching solution or an etching gas having an etching selectivity with respect to the semiconductor layer 220 such that two second trimming spaces TS2 adjacent to each other in the first horizontal direction (X direction) among the plurality of second trimming spaces TS2 in which the plurality of first trimming spaces TS1 are expanded are not connected to each other. As a result, a plurality of second trimming spaces TS2 may be formed.

[0044] In some example embodiments, the horizontal width of the coverage area occupied by two second trimming spaces TS2 may have a horizontal width substantially the same as the horizontal width of the first expansion space ES1 of the semiconductor layer 220. The two second trimming spaces TS2 are disposed in each of the first insulating layer 210 and the second insulating layer 230 in the first horizontal direction (X direction) and the second horizontal direction (Y direction) and are adjacent to each other in the first horizontal direction (X direction).

[0045] Refer to together Figures 6A to 6G , a sacrificial layer 240 is provided to fill the plurality of second trimming spaces TS2 and the plurality of first expansion spaces ES1. The sacrificial layer 240 may fill all of the plurality of second trimming spaces TS2 and the plurality of first expansion spaces ES1.

[0046] The sacrificial layer 240 may include a semiconductor material. The sacrificial layer 240 may include a semiconductor material that has an etching selectivity relative to the semiconductor layer 220. For example, different etching recipes may be used to etch the sacrificial layer 240 and the semiconductor layer 220. In some example embodiments, the sacrificial layer 240 may have an etching selectivity relative to the substrate 110. For example, different etching recipes may be used to etch the sacrificial layer 240 and the substrate 110. In some example embodiments, for example, when each of the plurality of semiconductor layers 220 includes Si, the sacrificial layer 240 may include SiGe.

[0047] Referring Figures 7A to 7G , portions of the sacrificial layer 240 are removed to form a plurality of third trimming spaces TS3. Portions of the sacrificial layer 240 that are located in regions adjacent to each of two second trimming spaces TS2 adjacent to each other in the first horizontal direction (X direction) in a plan view may be removed to form a plurality of third trimming spaces TS3.

[0048] In each of the first horizontal direction (X direction) and the second horizontal direction (Y direction), the horizontal width of each of the plurality of third trimming spaces TS3 may be less than the horizontal width of each of the plurality of second trimming spaces TS2. For example, in a plan view, the sacrificial layer 240 may be exposed from three of the four sides of each of two third trimming spaces TS3 adjacent to each other in the first horizontal direction (X direction), except for the sides facing each other.

[0049] Referring together Figures 8A to 8G , a portion of each of the plurality of second insulating layers 230 is removed through the plurality of third trimming spaces TS3 to form a plurality of second expansion spaces ES2. For example, a portion of each of the plurality of second insulating layers 230 may be removed by an etching operation. In a plan view, each of the plurality of second expansion spaces ES2 may extend in the second horizontal direction (Y direction). For example, the second expansion space ES2 may extend in the second horizontal direction (Y direction) between two second trimming spaces TS2 adjacent to each other in the first horizontal direction (X direction) or between two third trimming spaces TS3 adjacent to each other in a plan view.

[0050] Referring together Figures 9A to 9G , a back gate dielectric film 252 is formed to cover each surface of the first insulating layer 210, the semiconductor layer 220, the second insulating layer 230, and the sacrificial layer 240, and the first insulating layer 210, the semiconductor layer 220, the second insulating layer 230, and the sacrificial layer 240 are exposed in the plurality of second expansion spaces ES2 and the plurality of third trimming spaces TS3.

[0051] The back gate dielectric film 252 may include at least one selected from the group consisting of silicon oxide, a high-k dielectric material having a dielectric constant higher than that of silicon oxide, and a ferroelectric material. In some example embodiments, the back gate dielectric film 252 may have a stacked structure including a first dielectric film including silicon oxide and a second dielectric film including at least one selected from the group consisting of a high dielectric material and a ferroelectric material. For example, the high-k dielectric material and the ferroelectric material may include at least one selected from the group consisting of: hafnium oxide (HfO), hafnium silicate (HfSiO), hafnium oxynitride (HfON), hafnium silicon oxynitride (HfSiON), lanthanum oxide (LaO), lanthanum aluminum oxide (LaAlO), zirconium oxide (ZrO), zirconium silicate (ZrSiO), zirconium oxynitride (ZrON), zirconium silicon oxynitride (ZrSiON), tantalum oxide (TaO), titanium oxide (TiO), barium strontium titanate (BaSrTiO), barium titanate (BaTiO), lead zirconate titanate (PZT), strontium bismuth tantalate (STB), bismuth ferrite oxide (BFO), strontium titanate (SrTiO), yttrium oxide (YO), aluminum oxide (AlO), and lead scandium tantalum oxide (PbScTaO).

[0052] Referring together Figures 10A to 10G , a back gate material layer 254P is provided to cover the back gate dielectric film 252 and fill the plurality of second extension spaces ES2 and the plurality of third trimming spaces TS3.

[0053] In some example embodiments, the back gate material layer 254P may include a conduction blocking film covering the back gate dielectric film 252 and a conductive filling layer covering the conduction blocking film. The conduction blocking film may include, for example, a metal, a conductive metal nitride, a conductive metal silicide, or a combination thereof. For example, the conduction blocking film may include TiN. The conductive filling layer may include, for example, doped silicon, Ru, RuO, Pt, PtO, Ir, IrO, SRO (SrRuO), BSRO ((Ba,Sr)RuO), CRO (CaRuO), BaRuO, La(Sr,Co)O, Ti, TiN, W, WN, Ta, TaN, TiAlN, TiSiN, TaAlN, TaSiN, or a combination thereof. In some example embodiments, the conductive filling layer may include W.

[0054] Referring together Figures 10A to 10G and Figures 11A to 11G, a portion of the back gate dielectric film 252 and a portion of the back gate material layer 254P filling the plurality of third trimming spaces TS3 are removed, and a portion of the first insulating layer 210 overlapping with the plurality of second extension spaces ES2 in the vertical direction (Z direction) is removed, thereby forming a fourth trimming space TS4. For example, the portion of the back gate dielectric film 252 and the portion of the back gate material layer 254P may be removed by an etching operation. The fourth trimming space TS4 may correspond to a space in which a portion of the first insulating layer 210 overlapping with the plurality of second extension spaces ES2 in the vertical direction (Z direction) is removed and the plurality of third trimming spaces TS3.

[0055] The remaining portions of the back gate dielectric film 252 and the back gate material layer 254P may respectively form the back gate dielectric film 252 and the back gate electrode film 254 filling the plurality of second extended spaces ES2. That is, Figures 10A to 10G The back gate dielectric film 252 and the back gate material layer 254P shown in FIG. 1 are removed from the portions filling the plurality of third trimming spaces TS3, and thus, the back gate dielectric film 252 and the back gate electrode film 254 filling each of the plurality of second extended spaces ES2 may remain. The back gate dielectric film 252 and the back gate electrode film 254 may constitute a back gate structure 250. The plurality of back gate structures 250 may extend in the second horizontal direction (Y direction) and be spaced apart from each other in the vertical direction (Z direction). The back gate electrode film 254 may correspond to Figure 1 The back gate line BG is shown in FIG.

[0056] Refer to Figures 12A to 12G , a first filling insulating layer 260 is provided to fill the fourth trimming space TS4. The first filling insulating layer 260 may include oxide. For example, the first filling insulating layer 260 may include silicon oxide.

[0057] Refer to Figures 13A to 13G , a portion of the sacrificial layer 240 and a portion of the first filling insulating layer 260 are removed to form a plurality of fifth trimming spaces TS5. For example, the portion of the sacrificial layer 240 and the portion of the first filling insulating layer 260 may be removed by an etching operation. The plurality of fifth trimming spaces TS5 may be arranged in a plan view with Figures 5A to 5G For example, a plurality of fifth trimming spaces TS5 may be formed by removing a portion of the sacrificial layer 240 and a portion of the first filling insulating layer 260 that are not overlapped with the second extended space ES2 in the vertical direction (Z direction). That is, a plurality of fifth trimming spaces TS5 may be formed by removing a portion of the sacrificial layer 240 and a portion of the first filling insulating layer 260 that are not overlapped with the plurality of back gate structures 250 in the vertical direction (Z direction).

[0058] Refer to Figures 14A to 14G, a plurality of second fill insulating layers 265 are provided to fill the plurality of fifth trim spaces TS5. Each of the second fill insulating layers 265 may include a nitride. For example, the second fill insulating layer 265 may include silicon nitride.

[0059] Referring to Figures 15A to 15G , the sacrificial layer 240 and the first fill insulating layer 260 are removed to form a plurality of sixth trim spaces TS6. For example, the sacrificial layer 240 and the first fill insulating layer 260 may be removed by an etching operation. The plurality of sixth trim spaces TS6 may be stacked with the plurality of second extension spaces ES2 in the vertical direction (Z direction). The plurality of sixth trim spaces TS6 may be stacked with the plurality of back gate structures 250 in the vertical direction (Z direction).

[0060] Between two sixth trim spaces TS6 adjacent to each other in the vertical direction (Z direction), a back gate structure 250 may be disposed, or a back gate structure 250 and two semiconductor layers 220 covering the top and bottom of the back gate structure 250 may be arranged.

[0061] Referring together to Figures 16A to 16G , a gate dielectric film 272 is provided to cover the surfaces exposed in each of the plurality of fourth trim spaces TS4 and the plurality of sixth trim spaces TS6, and a gate material layer 274P is provided to cover the gate dielectric film 272. The gate dielectric film 272 may conformally cover the surfaces of the first insulating layer 210, the semiconductor layer 220, the back gate dielectric film 252, and the second fill insulating layer 265 exposed in the plurality of fourth trim spaces TS4 and the sixth trim spaces TS6. In some example embodiments, the gate material layer 274P may fill a portion of the plurality of fourth trim spaces TS4 and the sixth trim spaces TS6, but may not completely fill the sixth trim spaces TS6.

[0062] The gate dielectric film 272 may include at least one selected from the group consisting of silicon oxide, a high-k dielectric material having a dielectric constant higher than that of silicon oxide, and a ferroelectric material. In some example embodiments, the gate dielectric film 272 may have a stacked structure including a first dielectric film including silicon oxide and a second dielectric film including at least one selected from the group consisting of a high dielectric material and a ferroelectric material. For example, the high-k dielectric material and the ferroelectric material may include at least one selected from the group consisting of: hafnium oxide (HfO), hafnium silicate (HfSiO), hafnium oxynitride (HfON), hafnium silicon oxynitride (HfSiON), lanthanum oxide (LaO), lanthanum aluminum oxide (LaAlO), zirconium oxide (ZrO), zirconium silicate (ZrSiO), zirconium oxynitride (ZrON), zirconium silicon oxynitride (ZrSiON), tantalum oxide (TaO), titanium oxide (TiO), barium strontium titanate (BaSrTiO), barium titanate (BaTiO), lead zirconate titanate (PZT), strontium bismuth tantalate (STB), bismuth ferrite oxide (BFO), strontium titanate (SrTiO), yttrium oxide (YO), aluminum oxide (AlO), and lead scandium tantalum oxide (PbScTaO).

[0063] In some example embodiments, the gate material layer 274P may include a conduction barrier film covering the gate dielectric film 272 and a conductive filling layer covering the conduction barrier film. The conduction barrier film may include, for example, a metal, a conductive metal nitride, a conductive metal silicide, or a combination thereof. For example, the conduction barrier film may include TiN. The conductive filling layer may include, for example, doped silicon, Ru, RuO, Pt, PtO, Ir, IrO, SRO (SrRuO), BSRO ((Ba,Sr)RuO), CRO (CaRuO), BaRuO, La(Sr,Co)O, Ti, TiN, W, WN, Ta, TaN, TiAlN, TiSiN, TaAlN, TaSiN, or a combination thereof. In some example embodiments, the conductive filling layer may include W.

[0064] Referring together Figures 16A to 16G and Figures 17A to 17G , a portion of the gate material layer 274P is removed to form a plurality of gate structures 270, each of the plurality of gate structures 270 including a gate dielectric film 272 and a gate electrode film 274 that is the remaining portion of the gate material layer 274P. For example, when a portion of the gate material layer 274P is removed, the gate dielectric film 272 and the gate material layer 274P disposed between two back gate structures 250 spaced apart from each other in the vertical direction (Z direction) respectively form the gate dielectric film 272 and the gate electrode film 274. Accordingly, two gate structures 270 spaced apart from each other in the vertical direction (Z direction) may be formed. The gate electrode film 274 may correspond to Figure 1The word line WL shown in [the figure]. In some example embodiments, during the process of removing a portion of the gate material layer 274P, a portion of the gate dielectric film 272 may also be removed together.

[0065] Figures 18A to 18G is a view showing a semiconductor memory device 1 according to an example embodiment. Specifically, Figure 18A is a view showing Figure 18D a horizontal cross-sectional view of a portion of the semiconductor memory device 1 taken along the vertical height A of [the figure], Figure 18B is a view showing Figure 18D a horizontal cross-sectional view of a portion of the semiconductor memory device 1 taken along the vertical height B of [the figure], Figure 18C is a view showing Figure 18D a horizontal cross-sectional view of a portion of the semiconductor memory device 1 taken along the vertical height C of [the figure], Figure 18D is a view showing Figure 18A a vertical cross-sectional view of a portion of the semiconductor memory device 1 taken along the line D-D' of [the figure], Figure 18E is a view showing Figure 18A a vertical cross-sectional view of a portion of the semiconductor memory device 1 taken along the line E-E' of [the figure], Figure 18F is a view showing Figure 18A a vertical cross-sectional view of a portion of the semiconductor memory device 1 taken along the line F-F' of [the figure], and Figure 18G is a view showing Figure 18A a vertical cross-sectional view of a portion of the semiconductor memory device 1 taken along the line G-G' in [the figure].

[0066] Referring together to Figures 17A to 17G and Figures 18A to 18G , a portion of each of the first insulating layer 210, the semiconductor layer 220, and the second insulating layer 230 that are "arranged on the opposite sides of the gate structure 270 and the back gate structure 250 in the first horizontal direction (X direction) starting from the second filling insulating layer 265" is removed. For example, this portion of each of the first insulating layer 210, the semiconductor layer 220, and the second insulating layer 230 may be removed by an etching operation. The remaining portion of the semiconductor layer 220 may form a plurality of semiconductor patterns 220P. The plurality of semiconductor patterns 220P may extend in the first horizontal direction (X direction) and be spaced apart from each other in each of the vertical direction (Z direction) and the second horizontal direction (Y direction).

[0067] In the first horizontal direction (X direction), a plurality of bit lines 280 are formed on one side of the plurality of semiconductor patterns 220P, a plurality of unit capacitors 300 are formed on the other side of the plurality of semiconductor patterns 220P, and the third filling insulating layer 290 surrounds the plurality of bit lines 280 and the plurality of unit capacitors 300. Thus, the semiconductor memory device 1 can be formed. In some example embodiments, the third filling insulating layer 290 may fill "referring toFigures 16A to 16G and Figures 17A to 17G a region where a portion of the gate material layer 274P described in Figures 17A to 17G has been removed. For example, a portion of the third fill insulating layer 290 may be located between two gate structures 270, and the two gate structures 270 are between two back gate structures 250 spaced apart from each other in the vertical direction (Z direction).

[0068] In some example embodiments, a plurality of unit capacitors 300 may be formed before forming the third fill insulating layer 290, and thus, the third fill insulating layer 290 may surround the plurality of unit capacitors 300. A plurality of bit lines 280 are formed after forming the third fill insulating layer 290, and thus, the plurality of bit lines 280 may pass through the third fill insulating layer 290.

[0069] The plurality of bit lines 280 may extend in the vertical direction (Z direction) and be spaced apart from each other in the second horizontal direction (Y direction). Each of the plurality of bit lines 280 may be connected to one side of each of the semiconductor patterns 220P spaced apart from each other in the vertical direction (Z direction). The bit line 280 may correspond to Figure 1 the bit line BL shown in Figure 1 . The plurality of unit capacitors 300 may extend in the first horizontal direction (X direction) and be spaced apart from each other in each of the vertical direction (Z direction) and the second horizontal direction (Y direction). The plurality of unit capacitors 300 may be connected to the other side of the plurality of semiconductor patterns 220P. The bit lines 280, the semiconductor patterns 220P, and the unit capacitors 300 connected to each other in a plan view may be sequentially arranged in the first horizontal direction (X direction). The unit capacitor 300 may correspond to Figure 1 the unit capacitor CAP shown in Figure 1 .

[0070] The bit line 280 may include a conduction blocking film in contact with one side of the semiconductor pattern 220P and a conductive fill layer covering the conduction blocking film. The conduction blocking film may include, for example, a metal, a conductive metal nitride, a conductive metal silicide, or a combination thereof. For example, the conduction blocking film may include TiN. The conductive fill layer may include, for example, doped silicon, Ru, RuO, Pt, PtO, Ir, IrO, SRO (SrRuO), BSRO ((Ba,Sr)RuO), CRO (CaRuO), BaRuO, La(Sr,Co)O, Ti, TiN, W, WN, Ta, TaN, TiAlN, TiSiN, TaAlN, TaSiN, or a combination thereof. In some example embodiments, the conductive fill layer may include W.

[0071] The unit capacitor 300 may include a lower electrode layer, a capacitor dielectric film covering the lower electrode layer, and an upper electrode layer covering the capacitor dielectric film. The lower electrode layer is connected to the other side of the semiconductor pattern 220P and extends in a first horizontal direction (X direction). The lower electrode layer and the upper electrode layer of the unit capacitor 300 may correspond to the first electrode and the second electrode of the unit capacitor CAP shown in Figure 1 respectively. The capacitor dielectric film may be located between the lower electrode layer and the upper electrode layer. The lower electrode layer may include, for example, a metal, a conductive metal nitride, a conductive metal silicide, or a combination thereof. In some example embodiments, the lower electrode layer may include a metal film having a high melting point (such as cobalt, titanium, nickel, tungsten, and molybdenum). For example, the lower electrode layer may include a metal nitride film (such as a titanium nitride film, a titanium nitride silicon film, a titanium nitride aluminum film, a tantalum nitride film, a tantalum nitride silicon film, a tantalum nitride aluminum film, and a tungsten nitride film). The capacitor dielectric film may include at least one selected from the group consisting of silicon oxide, a high-k dielectric material having a dielectric constant higher than that of silicon oxide, and a ferroelectric material. For example, the capacitor dielectric film may include at least one of a metal oxide and a dielectric material having a perovskite structure. In some example embodiments, the capacitor dielectric film includes at least one selected from the group consisting of hafnium oxide (HfO), hafnium silicate (HfSiO), hafnium oxynitride (HfON), hafnium silicon oxynitride (HfSiON), lanthanum oxide (LaO), lanthanum aluminum oxide (LaAlO), zirconium oxide (ZrO), zirconium silicate (ZrSiO), zirconium oxynitride (ZrON), zirconium silicon oxynitride (ZrSiON), tantalum oxide (TaO), titanium oxide (TiO), barium strontium titanate (BaSrTiO), barium titanate (BaTiO), lead zirconate titanate (PZT), strontium bismuth tantalate (STB), bismuth ferrite oxide (BFO), strontium titanate (SrTiO), yttrium oxide (YO), aluminum oxide (AlO), and lead scandium tantalum oxide (PbScTaO). The upper electrode layer may include, for example, doped silicon, Ru, RuO, Pt, PtO, Ir, IrO, SRO (SrRuO), BSRO ((Ba,Sr)RuO), CRO (CaRuO), BaRuO, La(Sr,Co)O, Ti, TiN, W, WN, Ta, TaN, TiAlN, TiSiN, TaAlN, TaSiN, or a combination thereof. In some example embodiments, the upper electrode layer may include W.

[0072] In some example embodiments, a first impurity of a first conductivity type may be implanted into a plurality of semiconductor patterns 220P. Further, before forming a plurality of bit lines 280 and a plurality of cell capacitors 300, a second impurity of a second conductivity type different from the first conductivity type may be implanted into each of one end and the other end of the plurality of semiconductor patterns 220P. One end and the other end of the plurality of semiconductor patterns 220P into which the second impurity is implanted may be referred to as a source region and a drain region, respectively. Further, a portion of the plurality of semiconductor patterns 220P into which the first impurity is implanted between the source region and the drain region may be referred to as a channel region. In some example embodiments, the first conductivity type may be a p-type, and the second conductivity type may be an n-type. The bit line 280 may be connected to the source region, and a lower electrode of the cell capacitor 300 may be connected to the drain region. The source region, the channel region, and the drain region may be sequentially arranged in a first horizontal direction (X direction). The semiconductor pattern 220P, the gate dielectric film 272, and the gate electrode film 274 may constitute Figure 1 the cell transistor CTR shown in

[0073] The plurality of semiconductor patterns 220P may be spaced apart from each other in a vertical direction (Z direction). In some example embodiments, two gate structures 270 may be disposed between two semiconductor patterns adjacent to each other in the vertical direction (Z direction) among the plurality of semiconductor patterns 220P, and one back gate structure 250 may be disposed between two semiconductor patterns adjacent to each other in the vertical direction (Z direction) among the plurality of semiconductor patterns 220P. The two gate structures 270 may be disposed between “one semiconductor pattern 220P among the plurality of semiconductor patterns 220P” and “another semiconductor pattern 220P above one semiconductor pattern 220P”. Further, one back gate structure 250 may be located between one semiconductor pattern 220P and another semiconductor pattern 220P below one semiconductor pattern 220P.

[0074] In some example embodiments, a portion of the back gate dielectric film 252 and a portion of the gate dielectric film 272 may be in contact with each other. For example, the back gate dielectric film 252 and the gate dielectric film 272 covering two semiconductor patterns 220P adjacent to each other in a second horizontal direction (Y direction) may be in contact with each other between the two semiconductor patterns 220P adjacent to each other in the second horizontal direction (Y direction).

[0075] Figure 19 and Figures 20A to 20D are partial enlarged views of a semiconductor memory device according to an example embodiment.

[0076] Refer together to Figures 18A to 18G and Figure 19, the semiconductor memory device 1 may include a plurality of gate structures 270 extending in a second horizontal direction (Y direction), a plurality of bit lines 280 extending in a vertical direction (Z direction), and a plurality of semiconductor patterns 220P connected to the plurality of bit lines 280 and extending in a first horizontal direction (X direction). The semiconductor memory device 1 may include a plurality of cell capacitors 300. One end of the plurality of semiconductor patterns 220P is connected to the plurality of bit lines 280, and the other end of the plurality of semiconductor patterns 220P opposite to one end of the plurality of semiconductor patterns 220P is connected to the plurality of cell capacitors 300. The semiconductor memory device 1 may further include a plurality of back gate structures 250, and each of the plurality of back gate structures 250 is located between two gate structures 270 adjacent to each other in the vertical direction (Z direction) and extending in the second horizontal direction (Y direction).

[0077] The back gate structure 250 may cover one side surface of the semiconductor pattern 220P and the gate structure 270 may cover the remaining side surface of the semiconductor pattern 220P. For example, the back gate dielectric film 252 may be in contact with one side surface of the semiconductor pattern 220P, and the gate dielectric film 272 may be in contact with the remaining side surface of the semiconductor pattern 220P. For example, the back gate electrode film 254 may cover one side surface of the semiconductor pattern 220P, where the back gate dielectric film 252 is between the back gate electrode film 254 and one side surface of the semiconductor pattern 220P, and the gate electrode film 274 may cover the other side surface of the semiconductor pattern 220P, where the gate dielectric film 272 is between the gate electrode film 274 and the other side surface of the semiconductor pattern 220P.

[0078] For example, in a cross-section perpendicular to the direction in which the semiconductor pattern 220P extends (i.e., in a Y-Z cross-section perpendicular to the first horizontal direction (X direction)), the back gate structure 250 may cover one of the edges of the semiconductor pattern 220P, and the gate structure 270 may cover the remaining edges of the semiconductor pattern 220P except for one edge of the semiconductor pattern 220P. The back gate structure 250 may be in contact with each of the two semiconductor patterns 220P adjacent to each other in the vertical direction (Z direction).

[0079] For example, the lower surface of a semiconductor pattern 220P located above the back gate structure 250 may be in contact with the upper surface of the back gate structure 250. In addition, the remaining surfaces of a semiconductor pattern 220P (i.e., the upper surface of a semiconductor pattern 220P and the two side surfaces of a semiconductor pattern 220P in the second horizontal direction (Y direction)) may be in contact with a gate structure 270 located above the back gate structure 250. For example, the upper surface of another semiconductor pattern 220P located below the back gate structure 250 may be in contact with the lower surface of the back gate structure 250. In addition, the remaining surfaces of another semiconductor pattern 220P (i.e., the lower surface of another semiconductor pattern 220P and the two side surfaces of another semiconductor pattern 220P in the second horizontal direction (Y direction)) may be in contact with another gate structure 270 located below the back gate structure 250. Accordingly, the back gate structure 250 may be shared by a semiconductor pattern 220P and a gate structure 270 disposed above the back gate structure 250 and another semiconductor pattern 220P and another gate structure 270 disposed below the back gate structure 250.

[0080] Referring to Figure 20A , compared with the semiconductor memory device 1 shown in Figure 19 , the semiconductor memory device 1a may further include a sub-insulating layer 222. The sub-insulating layer 222 may be located between the back gate structure 250 and the semiconductor pattern 220P. For example, the back gate structure 250 and the semiconductor pattern 220P may be spaced apart from each other, and the sub-insulating layer 222 is therebetween. The sub-insulating layer 222 may be formed by depositing an insulating material layer corresponding to the sub-insulating layer 222 on the lower or upper part of the semiconductor layer 220 during the process of forming Figures 2A to 2G the semiconductor layer 220 shown in

[0081] The semiconductor memory device 1a may include a semiconductor pattern 220P having a relatively small thickness due to the sub-insulating layer 222. In some exemplary embodiments, the semiconductor pattern 220P may have a thickness of about 5 nm or less. The semiconductor memory device 1a includes a semiconductor pattern 220P having a relatively small thickness, and thus, the occurrence of the floating body effect may be prevented to improve the operation reliability.

[0082] Referring to Figure 20B , compared with Figure 19Compared with the semiconductor memory device 1 shown in [reference], the semiconductor memory device 1b may further include a sub-insulating layer 222a. The sub-insulating layer 222a may be located between the back gate structure 250 and the semiconductor pattern 220P. The sub-insulating layer 222a extends from the back gate structure 250 into the semiconductor pattern 220P, but may not extend to the gate structure 270. For example, the semiconductor pattern 220P may cover one of the upper and lower surfaces of the sub-insulating layer 222a and two side surfaces of the sub-insulating layer 222a in the second horizontal direction (Y direction). The sub-insulating layer 222a may be formed by depositing an insulating material layer corresponding to the sub-insulating layer 222a on the lower or upper part of the semiconductor layer 220 during the process of forming the semiconductor layer 220 shown in [reference]. Figures 2A to 2G During the process of forming the semiconductor layer 220 shown in [reference], the sub-insulating layer 222a may be formed by depositing an insulating material layer corresponding to the sub-insulating layer 222a on the lower or upper part of the semiconductor layer 220.

[0083] The semiconductor memory device 1b may include a semiconductor pattern 220P having a relatively small thickness due to the sub-insulating layer 222a. In some exemplary embodiments, the semiconductor pattern 220P may have a thickness of about 5 nm or less between the sub-insulating layer 222a and the gate structure 270. The semiconductor memory device 1b includes a semiconductor pattern 220P having a relatively small thickness, and thus, the occurrence of the floating body effect can be prevented to improve the operation reliability.

[0084] Referring to Figure 20C , compared with the semiconductor memory device 1 shown in [reference], the semiconductor memory device 1c may further include a sub-semiconductor layer 224. The sub-semiconductor layer 224 may be located between the back gate structure 250 and the semiconductor pattern 220P. For example, the back gate structure 250 and the semiconductor pattern 220P may be spaced apart from each other, and the sub-semiconductor layer 224 is between the back gate structure 250 and the semiconductor pattern 220P. The sub-semiconductor layer 224 may be formed by depositing a semiconductor material layer corresponding to the sub-semiconductor layer 224 on the lower or upper part of the semiconductor layer 220 during the process of forming the semiconductor layer 220 shown in [reference]. The sub-semiconductor layer 224 may include a semiconductor material different from that of the semiconductor pattern 220P. Figure 19 During the process of forming the semiconductor layer 220 shown in [reference], the sub-semiconductor layer 224 may be formed by depositing a semiconductor material layer corresponding to the sub-semiconductor layer 224 on the lower or upper part of the semiconductor layer 220. Figures 2A to 2G In some exemplary embodiments, the sub-semiconductor layer 224 may include a semiconductor material having a bandgap smaller than that of the semiconductor material of the semiconductor pattern 220P. For example, the sub-semiconductor layer 224 may include SiGe, AlGaAs, GaAs, InGaP, or ZnSe. When the semiconductor pattern 220P and the sub-semiconductor layer 224 are in contact with each other, the bandgap of the balance band becomes smaller than the bandgap of the conduction band. Therefore, the movement of holes from the semiconductor pattern 220P to the sub-semiconductor layer 224 can be promoted, and the operation reliability of the semiconductor memory device 1c can be improved.

[0085] In some exemplary embodiments, the sub-semiconductor layer 224 may include a semiconductor material having a bandgap smaller than that of the semiconductor material of the semiconductor pattern 220P. For example, the sub-semiconductor layer 224 may include SiGe, AlGaAs, GaAs, InGaP, or ZnSe. When the semiconductor pattern 220P and the sub-semiconductor layer 224 are in contact with each other, the bandgap of the balance band becomes smaller than the bandgap of the conduction band. Therefore, the movement of holes from the semiconductor pattern 220P to the sub-semiconductor layer 224 can be promoted, and the operation reliability of the semiconductor memory device 1c can be improved.

[0086] Referring toFigure 20D , compared with the semiconductor memory device 1 shown in Figure 19 , the semiconductor memory device 1d may further include a sub-semiconductor layer 224a. The sub-semiconductor layer 224a may be located between the back gate structure 250 and the semiconductor pattern 220P. The sub-semiconductor layer 224a extends from the back gate structure 250 into the semiconductor pattern 220P, but may not extend to the gate structure 270. For example, the semiconductor pattern 220P may cover one of the upper and lower surfaces of the sub-semiconductor layer 224a and the two side surfaces of the sub-semiconductor layer 224a in the second horizontal direction (Y direction). The sub-semiconductor layer 224a may be formed by depositing a semiconductor material layer corresponding to the sub-semiconductor layer 224a on the lower or upper part of the semiconductor layer 220 during the process of forming the Figures 2A to 2G semiconductor layer 220 shown in. The sub-semiconductor layer 224a may include a semiconductor material different from that of the semiconductor pattern 220P.

[0087] In some example embodiments, the sub-semiconductor layer 224a may include a semiconductor material having a smaller bandgap than the bandgap of the semiconductor material of the semiconductor pattern 220P. For example, the sub-semiconductor layer 224a may include SiGe. When the semiconductor pattern 220P and the sub-semiconductor layer 224a are in contact with each other, the bandgap of the equilibrium band becomes smaller than the bandgap of the conduction band. Therefore, the movement of holes from the semiconductor pattern 220P to the sub-semiconductor layer 224a can be promoted, and the operation reliability of the semiconductor memory device 1d can be improved.

[0088] Figure 21 is an equivalent circuit diagram showing a cell array of a semiconductor memory device 2 according to an example embodiment.

[0089] Referring to Figure 21 , the cell array of the semiconductor memory device 2 according to an example embodiment may include a plurality of sub-cell arrays SCA. The plurality of sub-cell arrays SCA may be arranged in the first horizontal direction (X direction). Each of the sub-cell arrays SCA may include a plurality of bit lines BL, a plurality of word lines WL, a plurality of back gate lines BG, and a plurality of cell transistors CTR. One cell transistor CTR may be located between one word line WL and one bit line BL.

[0090] Multiple word lines WL may extend in a second horizontal direction (Y direction). The word lines WL in a sub - cell array SCA may be spaced apart from each other in a vertical direction (Z direction). Multiple back - gate lines BG may extend in the second horizontal direction (Y direction). The back - gate lines BG in a sub - cell array SCA may be spaced apart from each other in the vertical direction (Z direction). The word lines WL and the back - gate lines BG in a sub - cell array SCA may be spaced apart from each other in the vertical direction (Z direction) and extend parallel to each other in the second horizontal direction (Y direction). In a sub - cell array SCA, the number of word lines WL may be equal to or substantially similar to the number of back - gate lines BG. For example, the word lines WL and the back - gate lines BG in a sub - cell array SCA may be alternately arranged in the vertical direction (Z direction). The bit lines BL in a sub - cell array SCA may be spaced apart from each other in the second horizontal direction (Y direction).

[0091] Multiple bit lines BL may extend in the vertical direction (Z direction). The bit lines BL in a sub - cell array SCA may be spaced apart from each other in the second horizontal direction (Y direction).

[0092] The gate of the cell transistor CTR may be connected to the word line WL, and the source of the cell transistor CTR may be connected to the bit line BL. The cell transistor CTR may be connected to the cell capacitor CAP. The drain of the cell transistor CTR may be connected to the first electrode of the cell capacitor CAP, and the second electrode of the cell capacitor CAP may be connected to the ground line PP.

[0093] The semiconductor memory device 2 may include a plurality of sub - cell arrays SCA, each of the plurality of sub - cell arrays SCA including a plurality of memory cells MC, a plurality of bit lines BL, and a plurality of word lines WL. The plurality of memory cells MC are spaced apart from each other in the second horizontal direction (Y direction) and the vertical direction (Z direction) and are arranged in rows and columns. The plurality of bit lines BL are connected to the cell transistors CTR of the memory cells MC arranged in the vertical direction (Z direction), extend in the vertical direction (Z direction), and are spaced apart from each other in the second horizontal direction (Y direction). The plurality of word lines WL extend in the second horizontal direction (Y direction) and are spaced apart from each other in the vertical direction (Z direction). The plurality of sub - cell arrays SCA may be arranged in a first horizontal direction (X direction).

[0094] Figures 22A to 32G is a diagram showing a method of manufacturing a semiconductor memory device according to an exemplary embodiment. Specifically, Figure 22A 、 Figure 23A 、 Figure 24A 、 Figure 25A 、 Figure 26A 、 Figure 27A 、 Figure 28A 、 Figure 29A 、Figure 30A , 31A and Figure 32A are horizontal cross-sectional views of a semiconductor memory device taken along the vertical height A of Figure 22D , Figure 23D , Figure 24D , Figure 25D , Figure 26D , Figure 27D , Figure 28D , Figure 29D , Figure 30D , Figure 31D and Figure 32D . In addition, Figure 22B , Figure 23B , Figure 24B , Figure 25B , Figure 26B , Figure 27B , Figure 28B , Figure 29B , Figure 30B , Figure 31B and Figure 32B are horizontal cross-sectional views of a semiconductor memory device taken along the vertical height B of Figure 22D , Figure 23D , Figure 24D , Figure 25D , Figure 26D , Figure 27D , Figure 28D , Figure 29D , Figure 30D , Figure 31D and Figure 32D . In addition, Figure 22C , Figure 23C , Figure 24C , Figure 25C , Figure 26C , Figure 27C , Figure 28C , Figure 29C , Figure 30C , Figure 31C and Figure 32C are horizontal cross-sectional views of a semiconductor memory device taken along the vertical height C of Figure 22D , Figure 23D , Figure 24D , Figure 25D , Figure 26D , Figure 27D , Figure 28D , Figure 29D , Figure 30D , Figure 31D and Figure 32D . In addition, Figure 22D , Figure 23D , Figure 24D , Figure 25D , Figure 26D , Figure 27D , Figure 28D , Figure 29D, Figure 30D , Figure 31D and Figure 32D are vertical cross-sectional views of the semiconductor memory device taken along line D-D' of Figure 22A , Figure 23A , Figure 24A , Figure 25A , Figure 26A , Figure 27A , Figure 28A , Figure 29A , Figure 30A , Figure 31A and Figure 32A . In addition, Figure 22E , Figure 23E , Figure 24E , Figure 25E , Figure 26E , Figure 27E , Figure 28E , Figure 29E , Figure 30E , Figure 31E and Figure 32E are vertical cross-sectional views of the semiconductor memory device taken along line E-E' of Figure 22A , Figure 23A , Figure 24A , Figure 25A , Figure 26A , Figure 27A , Figure 28A , Figure 29A , Figure 30A , Figure 31A and Figure 32A . In addition, Figure 22F , Figure 23F , Figure 24F , Figure 25F , Figure 26F , Figure 27F , Figure 28F , Figure 29F , Figure 30F , Figure 31F and Figure 32F are vertical cross-sectional views of the semiconductor memory device taken along line F-F' of Figure 22A , Figure 23A , Figure 24A , Figure 25A , Figure 26A , Figure 27A , Figure 28A , Figure 29A , Figure 30A , Figure 31A and Figure 32A . In addition, Figure 22G , Figure 23G , Figure 24G , Figure 25G , Figure 26G , Figure 27G , Figure 28G ,Figure 29G , Figure 30G , Figure 31G and Figure 32G are the vertical cross-sectional views of the semiconductor memory device taken along the line G-G' of Figure 22A , Figure 23A , Figure 24A , Figure 25A , Figure 26A , Figure 27A , Figure 28A , Figure 29A , Figure 30A , Figure 31A and Figure 32A .

[0095] Referring together to Figures 22A to 22G , a plurality of first insulating layers 210, a plurality of semiconductor layers 220, and a plurality of sacrificial layers 242 are formed on a substrate 110. A sub-stack structure including the first insulating layer 210, the semiconductor layer 220, and the sacrificial layer 242 may be repeatedly stacked on the substrate 110.

[0096] The first insulating layer 210, the semiconductor layer 220, and the sacrificial layer 242 may include materials having etch selectivity with respect to each other. For example, different etch recipes may be used to etch each of the first insulating layer 210, the semiconductor layer 220, and the second insulating layer 230. In some example embodiments, the first insulating layer 210 may include a nitride. For example, the first insulating layer 210 may include silicon nitride. In some example embodiments, the semiconductor layer 220 may include a material having the same or similar etch characteristics as the substrate 110, or include the same material as the substrate 110. In some example embodiments, the semiconductor layer 220 may include Si. In some example embodiments, the sacrificial layer 242 may include a semiconductor material different from the semiconductor material of the semiconductor layer 220. In some example embodiments, the sacrificial layer 242 may include SiGe. In some example embodiments, each of the semiconductor layer 220 and the sacrificial layer 242 may include a single crystal semiconductor material. For example, the semiconductor layer 220 may include single crystal Si, and the sacrificial layer 242 may include single crystal SiGe.

[0097] Referring together to Figures 23A to 23G , a plurality of first trimming spaces TS1a are formed, and the plurality of first trimming spaces TS1a penetrate through the plurality of first insulating layers 210, the plurality of semiconductor layers 220, and the plurality of sacrificial layers 242, but are spaced apart from each other in a plan view. Two of the plurality of first trimming spaces TS1a may be arranged in a first horizontal direction (X direction), and the first trimming spaces TS1a may be arranged in rows in a second horizontal direction (Y direction). The substrate 110 may be exposed from the bottom surface of each of the plurality of first trimming spaces TS1a.

[0098] The horizontal widths and horizontal areas of two first trimming spaces TS1a arranged in a first horizontal direction (X direction) may be different from each other. In some example embodiments, among two first trimming spaces TS1a arranged in the first horizontal direction (X direction), the first trimming space TS1a on the right side in the first horizontal direction (X direction) may have a greater horizontal width than the first trimming space TS1a on the left side in the first horizontal direction (X direction). In some example embodiments, the horizontal widths of a plurality of first trimming spaces TS1a in a second horizontal direction (Y direction) may be substantially equal to each other.

[0099] Refer together Figures 24A to 24G , a portion of a plurality of sacrificial layers 242 is removed through a plurality of first trimming spaces TS1a to form a plurality of first expansion spaces ES1a in each of the plurality of sacrificial layers 242. For example, a portion of the sacrificial layer may be removed through an etching operation. Each of the plurality of first expansion spaces ES1a may be formed such that the plurality of first trimming spaces TS1a in each of the plurality of sacrificial layers 242 communicate with each other.

[0100] Refer together Figures 25A to 25G , a portion of each of a plurality of semiconductor layers 220 is removed to form a plurality of second expansion spaces ES2a in each of the plurality of semiconductor layers 220. For example, this portion of each of the plurality of semiconductor layers 220 may be removed through an etching operation. Each of the plurality of second expansion spaces ES2a may be formed such that two first trimming spaces TS1a adjacent to each other in the first horizontal direction (X direction) in each of the plurality of semiconductor layers 220 communicate with each other. In some example embodiments, the horizontal width of each of the plurality of second expansion spaces ES2a in the second horizontal direction (Y direction) may be greater than the horizontal width of each of the plurality of first trimming spaces TS1a in the second horizontal direction (Y direction).

[0101] Refer together Figures 26A to 26G , a second insulating layer 232 is provided to fill the first trimming spaces TS1a that are "on the left side in the first horizontal direction (X direction) and arranged in a row in the second horizontal direction (Y direction)" among the plurality of first trimming spaces TS1a and the spaces between the first trimming spaces TS1a. In a plan view, the second insulating layer 232 may overlap with the first trimming spaces TS1a that are "on the left side in the first horizontal direction (X direction) and arranged in a row in the second horizontal direction (Y direction)" among the plurality of first trimming spaces TS1a and may extend in the second horizontal direction (Y direction). The second insulating layer 232 may include an oxide. For example, the second insulating layer 232 may include silicon oxide.

[0102] Refer together Figures 27A to 27G, a gate dielectric film 272 is provided to cover the surfaces of the plurality of semiconductor layers 220 that are not covered by the plurality of sacrificial layers 242 and the second insulating layer 232. The gate dielectric film 272 may cover the upper surfaces of each of the plurality of semiconductor layers 220 and both sides of each of the plurality of semiconductor layers 220 in the second horizontal direction (Y direction). In some example embodiments, the gate dielectric film 272 may also cover the upper surfaces of the plurality of first insulating layers 210 that are not covered by the plurality of semiconductor layers 220, the plurality of sacrificial layers 242, and the second insulating layer 232.

[0103] Refer together to Figures 28A to 28G , a gate material layer 274P is provided to cover the gate dielectric film 272. The gate material layer 274P may cover the upper surfaces of each of the plurality of semiconductor layers 220 and both sides of each of the plurality of semiconductor layers 220 in the second horizontal direction (Y direction), wherein the gate dielectric film 272 is between the gate material layer 274P and "the upper surfaces of each of the plurality of semiconductor layers 220 and both sides of each of the plurality of semiconductor layers 220 in the second horizontal direction (Y direction)". In some example embodiments, the gate material layer 274P may also cover a part of the upper surface of the gate dielectric film 272 that covers the plurality of first insulating layers 210.

[0104] The gate material layer 274P may cover the semiconductor layer 220 disposed on one of the plurality of first insulating layers 210, but may not contact the lower surface of another first insulating layer 210 located above the semiconductor layer 220. For example, the gate material layer 274P is located between two first insulating layers 210 adjacent to each other in the vertical direction (Z direction), and the gate material layer 274P may have an upper surface at a vertical height lower than the lower surface of the upper first insulating layer 210, and thus may not contact the upper first insulating layer 210.

[0105] Refer together to Figures 29A to 29G , a part of the plurality of first insulating layers 210 located below the part of the semiconductor layer 220 covered by the gate dielectric film 272 and the gate material layer 274P and each of the plurality of first insulating layers 210 located below the gate dielectric film 272 and the gate material layer 274P is partially removed. For example, a part of each of the plurality of first insulating layers 210 may be removed by an etching operation. When a part of each of the plurality of first insulating layers 210 is removed, the lower surface of the gate dielectric film 272 and the lower surface of the part of the semiconductor layer 220 covered by the gate dielectric film 272 and the gate material layer 274P may be exposed.

[0106] Refer to Figures 30A to 30G, a back gate dielectric film 252 is formed below "the lower surface of the gate dielectric film 272 and the lower surface of the portion of the semiconductor layer 220 covered by the gate dielectric film 272 and the gate material layer 274P". The back gate dielectric film 252 can cover the lower surface of each of the plurality of semiconductor layers 220. In some example embodiments, the back gate dielectric film 252 can also cover the lower surface of the gate dielectric film 272.

[0107] Refer together to Figures 31A to 31G , a back gate material layer 254P is provided to cover the bottom of the back gate dielectric film 252. The back gate material layer 254P can cover the lower surface of the gate dielectric film 272 and the lower surface of the back gate dielectric film 252 located above the back gate material layer 254P, and the back gate dielectric film 252 covers the lower surface of the portion of the semiconductor layer 220 covered by the gate dielectric film 272 and the gate material layer 274P. However, the back gate material layer 254P may not be in contact with the gate material layer 274P located below the back gate material layer 254P. For example, the back gate material layer 254P has a lower surface at a vertical height higher than the upper surface of the gate material layer 274P located below the back gate material layer 254P, and thus may not be in contact with the gate material layer 274P located below the back gate material layer 254P.

[0108] Each of the gate dielectric film 272, the gate material layer 274P, the back gate dielectric film 252, and the back gate material layer 254P can include a first portion extending in the second horizontal direction (Y direction) and a second portion protruding from the first portion and extending in the first horizontal direction (X direction). The gate dielectric film 272, the gate material layer 274P, the back gate dielectric film 252, and the back gate material layer 254P can be stacked on top of each other in the vertical direction (Z direction).

[0109] Refer together to Figures 31A to 31G and Figures 32A to 32G , for each of the gate dielectric film 272, the gate material layer 274P, the back gate dielectric film 252, and the back gate material layer 254P, for example, by an etching operation, the second portion protruding from the first portion and extending in the first horizontal direction (X direction) is removed, and the first portion extending in the second horizontal direction (Y direction) is retained. The gate dielectric film 272 and the gate electrode film 274 as the first portion (i.e., the remaining portion of the gate material layer 274P) constitute the gate structure 270. The back gate dielectric film 252 and the back gate electrode film 254 as the first portion (i.e., the remaining portion of the back gate material layer 254P) constitute the back gate structure 250.

[0110] Multiple gate structures 270 and multiple back gate structures 250 may extend in a second horizontal direction (Y direction). The multiple back gate structures 250 and the multiple gate structures 270 may be alternately arranged in a vertical direction (Z direction) on the substrate 110.

[0111] Figures 33A to 33G is a view showing a semiconductor memory device 2 according to an exemplary embodiment. Specifically, Figure 33A is a view showing Figure 33D a horizontal cross-sectional view of a part of the semiconductor memory device 2 taken along a vertical height A, Figure 33B is a view showing Figure 33D a horizontal cross-sectional view of a part of the semiconductor memory device 2 taken along a vertical height B, Figure 33C is a view showing Figure 33D a horizontal cross-sectional view of a part of the semiconductor memory device 2 taken along a vertical height C, Figure 33D is a view showing Figure 33A a vertical cross-sectional view of a part of the semiconductor memory device 2 taken along a line D-D' of Figure 33E is a view showing Figure 33A a vertical cross-sectional view of a part of the semiconductor memory device 2 taken along a line E-E' of Figure 33F is a view showing Figure 33A a vertical cross-sectional view of a part of the semiconductor memory device 2 taken along a line F-F' of, and Figure 33G is a view showing Figure 33A a vertical cross-sectional view of a part of the semiconductor device 2 taken along a line G-G' in

[0112] Referring together to Figures 32A to 32G and Figures 33A to 33G , a stacked structure of the multiple first insulating layers 210, the multiple semiconductor layers 220, and the multiple sacrificial layers 242 is removed. The stacked structure of the multiple first insulating layers 210, the multiple semiconductor layers 220, and the multiple sacrificial layers 242 is disposed on both sides in a first horizontal direction (X direction) with respect to the multiple gate structures 270 and the multiple back gate structures 250. For example, the removal of the layers may be performed by an etching operation. While removing the stacked structure of the multiple first insulating layers 210, the multiple semiconductor layers 220, and the multiple sacrificial layers 242 disposed on both sides in the first horizontal direction (X direction) with respect to the multiple gate structures 270 and the multiple back gate structures 250, a portion of the multiple semiconductor layers 220 located between the multiple gate structures 270 and the multiple back gate structures 250 may also be removed together. The remaining portions of the semiconductor layers 220 may form multiple semiconductor patterns 220P. The multiple semiconductor patterns 220P may extend in the first horizontal direction (X direction) and be spaced apart from each other in each of the vertical direction (Z direction) and the second horizontal direction (Y direction).

[0113] In a first horizontal direction (X direction), a plurality of bit lines 280 are formed on one side of a plurality of semiconductor patterns 220P, a plurality of unit capacitors 300 are formed on the other side of the plurality of semiconductor patterns 220P, and a third fill insulating layer 290 surrounds the plurality of bit lines 280 and the plurality of unit capacitors 300. Accordingly, a semiconductor memory device 2 can be formed.

[0114] The plurality of bit lines 280 may extend in a vertical direction (Z direction) and be spaced apart from each other in a second horizontal direction (Y direction). Each of the plurality of bit lines 280 may be connected to one side of each of the semiconductor patterns 220P spaced apart from each other in the vertical direction (Z direction). The bit lines 280 may correspond to Figure 21 the bit lines BL shown in. The plurality of unit capacitors 300 may extend in the first horizontal direction (X direction) and be spaced apart from each other in each of the vertical direction (Z direction) and the second horizontal direction (Y direction). The plurality of unit capacitors 300 may be connected to the other side of the plurality of semiconductor patterns 220P. The bit lines 280, the semiconductor patterns 220P, and the unit capacitors 300 connected to each other in a plan view may be sequentially arranged in the first horizontal direction (X direction). The unit capacitors 300 may correspond to Figure 21 the unit capacitors CAP shown in.

[0115] The unit capacitor 300 may include a lower electrode layer, a capacitor dielectric film covering the lower electrode layer, and an upper electrode layer covering the capacitor dielectric film. The lower electrode layer is connected to the other side of the semiconductor pattern 220P and extends in the first horizontal direction (X direction). The lower electrode layer and the upper electrode layer of the unit capacitor 300 may respectively correspond to Figure 21 the first electrode and the second electrode of the unit capacitor CAP shown in. The capacitor dielectric film may be located between the lower electrode layer and the upper electrode layer. The semiconductor pattern 220P, the gate dielectric film 272, and the gate electrode film 274 may constitute Figure 21 the unit transistor CTR shown in.

[0116] Figure 34 and Figures 35A to 35D are partial enlarged views of a semiconductor memory device according to an exemplary embodiment.

[0117] Referring together to Figures 33A to 33G and Figure 34, the semiconductor memory device 2 may include a plurality of gate structures 270 extending in a second horizontal direction (Y direction), a plurality of back gate structures 250 extending in the second horizontal direction (Y direction), a plurality of bit lines 280 extending in a vertical direction (Z direction), and a plurality of semiconductor patterns 220P connected to the plurality of bit lines 280 and extending in a first horizontal direction (X direction). The semiconductor memory device 2 may include a plurality of unit capacitors 300. One end of the plurality of semiconductor patterns 220P is connected to the plurality of bit lines 280, and the other end of the plurality of semiconductor patterns 220P facing away from one end of the plurality of semiconductor patterns 220P is connected to the plurality of unit capacitors 300. The plurality of back gate structures 250 and the plurality of gate structures 270 may be alternately arranged on the substrate 110 in the vertical direction (Z direction).

[0118] The back gate structure 250 may cover one side surface of the semiconductor pattern 220P and the gate structure 270 may cover the remaining side surface of the semiconductor pattern 220P. For example, the back gate dielectric film 252 may be in contact with one side surface of the semiconductor pattern 220P, and the gate dielectric film 272 may be in contact with the remaining side surface of the semiconductor pattern 220P. For example, the back gate electrode film 254 may cover one side surface of the semiconductor pattern 220P, where the back gate dielectric film 252 is between the back gate electrode film 254 and one side surface of the semiconductor pattern 220P, and the gate electrode film 274 may cover the other side surface of the semiconductor pattern 220P, where the gate dielectric film 272 is between the gate electrode film 274 and the other side surface of the semiconductor pattern 220P.

[0119] For example, in a cross-section perpendicular to the direction in which the semiconductor pattern 220P extends (i.e., in the Y-Z cross-section perpendicular to the first horizontal direction (X direction)), the back gate structure 250 may cover one of the sides of the semiconductor pattern 220P, and the gate structure 270 may cover the remaining sides of the semiconductor pattern 220P except for one side of the semiconductor pattern 220P. For example, the lower surface of a semiconductor pattern 220P located above the back gate structure 250 may be in contact with the upper surface of the back gate structure 250. In addition, the remaining surfaces of a semiconductor pattern 220P (i.e., the upper surface of a semiconductor pattern 220P and the two side surfaces of a semiconductor pattern 220P in the second horizontal direction (Y direction)) may be in contact with a gate structure 270 located above the back gate structure 250.

[0120] Referring to Figure 35A , with Figure 34Compared with the semiconductor memory device 2 shown in [reference], the semiconductor memory device 2a may further include a sub-insulating layer 222. The sub-insulating layer 222 may be located between the back gate structure 250 and the semiconductor pattern 220P. For example, the back gate structure 250 and the semiconductor pattern 220P may be spaced apart from each other, and the sub-insulating layer 222 is between the back gate structure 250 and the semiconductor pattern 220P. The sub-insulating layer 222 may be formed by depositing an insulating material layer corresponding to the sub-insulating layer 222 on the lower portion of the semiconductor layer 220 during the process of forming Figures 22A to 22G the semiconductor layer 220 shown in [reference].

[0121] The semiconductor memory device 2a may include a semiconductor pattern 220P having a relatively small thickness due to the sub-insulating layer 222. In some exemplary embodiments, the semiconductor pattern 220P may have a thickness of about 5 nm or less. The semiconductor memory device 2a includes a semiconductor pattern 220P having a relatively small thickness, and thus, the occurrence of the floating body effect can be prevented to improve the operation reliability.

[0122] Referring to Figure 35B , compared with Figure 34 the semiconductor memory device 2 shown in [reference], the semiconductor memory device 2b may further include a sub-insulating layer 222a. The sub-insulating layer 222a may be located between the back gate structure 250 and the semiconductor pattern 220P. The sub-insulating layer 222a extends from the back gate structure 250 into the semiconductor pattern 220P, but may not extend to the gate structure 270. For example, the semiconductor pattern 220P may cover the upper surface of the sub-insulating layer 222a and the two side surfaces of the sub-insulating layer 222a in the second horizontal direction (Y direction). The sub-insulating layer 222a may be formed by depositing an insulating material layer corresponding to the sub-insulating layer 222a on the lower portion of the semiconductor layer 220 during the process of forming Figures 22A to 22G the semiconductor layer 220 shown in [reference].

[0123] The semiconductor memory device 2b may include a semiconductor pattern 220P having a relatively small thickness due to the sub-insulating layer 222a. In some exemplary embodiments, the semiconductor pattern 220P may have a thickness of about 5 nm or less between the sub-insulating layer 222a and the gate structure 270. The semiconductor memory device 2b includes a semiconductor pattern 220P having a relatively small thickness, and thus, the occurrence of the floating body effect can be prevented to improve the operation reliability.

[0124] Referring to Figure 35C , compared with Figure 34Compared with the semiconductor memory device 2 shown in [reference], the semiconductor memory device 2c may further include a sub-semiconductor layer 224. The sub-semiconductor layer 224 may be located between the back gate structure 250 and the semiconductor pattern 220P. For example, the back gate structure 250 and the semiconductor pattern 220P may be spaced apart from each other, and the sub-semiconductor layer 224 is between the back gate structure 250 and the semiconductor pattern 220P. The sub-semiconductor layer 224 may be formed by depositing a semiconductor material layer corresponding to the sub-semiconductor layer 224 on the lower portion of the semiconductor layer 220 during the process of forming the semiconductor layer 220 shown in [reference]. The sub-semiconductor layer 224 may include a semiconductor material different from that of the semiconductor pattern 220P. Figures 22A to 22G During the process of forming the semiconductor layer 220 shown in [reference], the sub-semiconductor layer 224 may be formed by depositing a semiconductor material layer corresponding to the sub-semiconductor layer 224 on the lower portion of the semiconductor layer 220. The sub-semiconductor layer 224 may include a semiconductor material different from that of the semiconductor pattern 220P.

[0125] In some example embodiments, the sub-semiconductor layer 224 may include a semiconductor material having a smaller bandgap than the bandgap of the semiconductor material of the semiconductor pattern 220P. For example, the sub-semiconductor layer 224 may include SiGe. When the semiconductor pattern 220P and the sub-semiconductor layer 224 are in contact with each other, the bandgap of the equilibrium band becomes smaller than the bandgap of the conduction band. Therefore, the movement of holes from the semiconductor pattern 220P to the sub-semiconductor layer 224 can be promoted, and the operation reliability of the semiconductor memory device 2c can be improved.

[0126] Referring to Figure 35D , Figure 34 Compared with the semiconductor memory device 2 shown in [reference], the semiconductor memory device 2d may further include a sub-semiconductor layer 224a. The sub-semiconductor layer 224a may be located between the back gate structure 250 and the semiconductor pattern 220P. The sub-semiconductor layer 224a extends from the back gate structure 250 into the semiconductor pattern 220P, but may not extend to the gate structure 270. For example, the semiconductor pattern 220P may cover the upper surface of the sub-semiconductor layer 224a and the two side surfaces of the sub-semiconductor layer 224a in the second horizontal direction (Y direction). The sub-semiconductor layer 224a may be formed by depositing a semiconductor material layer corresponding to the sub-semiconductor layer 224a on the lower portion of the semiconductor layer 220 during the process of forming the semiconductor layer 220 shown in [reference]. The sub-semiconductor layer 224a may include a semiconductor material different from that of the semiconductor pattern 220P. Figures 22A to 22G During the process of forming the semiconductor layer 220 shown in [reference], the sub-semiconductor layer 224a may be formed by depositing a semiconductor material layer corresponding to the sub-semiconductor layer 224a on the lower portion of the semiconductor layer 220. The sub-semiconductor layer 224a may include a semiconductor material different from that of the semiconductor pattern 220P.

[0127] In some example embodiments, the sub-semiconductor layer 224a may include a semiconductor material having a smaller bandgap than the bandgap of the semiconductor material of the semiconductor pattern 220P. For example, the sub-semiconductor layer 224a may include SiGe. When the semiconductor pattern 220P and the sub-semiconductor layer 224a are in contact with each other, the bandgap of the equilibrium band becomes smaller than the bandgap of the conduction band. Therefore, the movement of holes from the semiconductor pattern 220P to the sub-semiconductor layer 224a can be promoted, and the operation reliability of the semiconductor memory device 2d can be improved.

[0128] Figure 36 It is an equivalent circuit diagram showing a cell array of a semiconductor memory device 3 according to an exemplary embodiment.

[0129] Referring to Figure 36 , the cell array of the semiconductor memory device 3 according to the exemplary embodiment may include a plurality of sub-cell arrays SCA. The plurality of sub-cell arrays SCA may be arranged in a first horizontal direction (X direction). Each of the sub-cell arrays SCA may include a plurality of bit lines BL, a plurality of word lines WL, a plurality of back gate lines BG, and a plurality of cell transistors CTR. One cell transistor CTR may be located between one word line WL and one bit line BL.

[0130] The plurality of word lines WL may extend in a vertical direction (Z direction). The word lines WL in one sub-cell array SCA may be spaced apart from each other in a second horizontal direction (Y direction). The plurality of back gate lines BG may extend in a vertical direction (Z direction). The back gate lines BG in one sub-cell array SCA may be spaced apart from each other in a second horizontal direction (Y direction). The word lines WL and the back gate lines BG in one sub-cell array SCA may be spaced apart from each other in the second horizontal direction (Y direction) and extend parallel to each other in the vertical direction (Z direction). Each of the plurality of back gate lines BG may be located between a pair of adjacent word lines WL among the word lines WL. In one sub-cell array SCA, the number of word lines WL may be approximately twice the number of back gate lines BG. For example, the word lines WL and the back gate lines BG in one sub-cell array SCA may be configured such that two word lines WL among the word lines WL and one back gate line BG among the back gate lines BG are alternately arranged in the second horizontal direction (Y direction). In this regard, one back gate line BG among the back gate lines BG may be located between two word lines WL that are adjacent to each other in the second horizontal direction (Y direction) in one sub-cell array SCA. In addition, two word lines WL among the word lines WL may be arranged between two back gate lines BG that are adjacent to each other in the second horizontal direction (Y direction) in one sub-cell array SCA.

[0131] The plurality of bit lines BL may extend in the second horizontal direction (Y direction). The bit lines BL in one sub-cell array SCA may be spaced apart from each other in the vertical direction (Z direction).

[0132] The gate of the cell transistor CTR may be connected to the word line WL, and the source of the cell transistor CTR may be connected to the bit line BL. The cell transistor CTR may be connected to the cell capacitor CAP. The drain of the cell transistor CTR may be connected to the first electrode of the cell capacitor CAP, and the second electrode of the cell capacitor CAP may be connected to the ground line PP.

[0133] The semiconductor memory device 3 may include a plurality of sub - cell arrays SCA. Each of the plurality of sub - cell arrays SCA includes a plurality of memory cells MC, a plurality of bit lines BL, and a plurality of word lines WL. The plurality of memory cells MC are spaced apart from each other in the second horizontal direction (Y - direction) and the vertical direction (Z - direction) and are arranged in rows and columns. The plurality of bit lines BL are connected to the cell transistors CTR of the memory cells MC arranged in the second horizontal direction (Y - direction), extend in the second horizontal direction (Y - direction), and are spaced apart from each other in the vertical direction (Z - direction). The plurality of word lines WL extend in the vertical direction (Z - direction) and are spaced apart from each other in the second horizontal direction (Y - direction). The plurality of sub - cell arrays SCA may be arranged in the first horizontal direction (X - direction).

[0134] The first horizontal direction (X - direction), the second horizontal direction (Y - direction), and the vertical direction (Z - direction) may be referred to as the first direction, the second direction, and the third direction, respectively. The first direction, the second direction, and the third direction may be perpendicular to each other.

[0135] Figure 37 is a partial enlarged view of the semiconductor memory device 3 according to an exemplary embodiment.

[0136] Refer together to Figure 36 and Figure 37 The semiconductor memory device 3 may include a plurality of gate structures 270 extending in the vertical direction (Z - direction) on a substrate 110, a plurality of bit lines 280 extending in the second horizontal direction (Y - direction), and a plurality of semiconductor patterns 220P connected to the plurality of bit lines 280 and extending in the first horizontal direction (X - direction). The semiconductor memory device 3 may include a plurality of cell capacitors CAP. One end of the plurality of semiconductor patterns 220P is connected to the plurality of bit lines 280, and the other end of the plurality of semiconductor patterns 220P, which is opposite to one end of the plurality of semiconductor patterns 220P, is connected to the plurality of cell capacitors CAP. The semiconductor memory device 3 may further include a plurality of back - gate structures 250, and each of the plurality of back - gate structures 250 is located between two gate structures 270 that are adjacent to each other in the second horizontal direction (Y - direction) and extend in the vertical direction (Z - direction).

[0137] The back gate structure 250 may cover one side surface of the semiconductor pattern 220P and the gate structure 270 may cover the remaining side surface of the semiconductor pattern 220P. For example, the back gate dielectric film 252 may be in contact with one side surface of the semiconductor pattern 220P, and the gate dielectric film 272 may be in contact with the remaining side surface of the semiconductor pattern 220P. For example, the back gate electrode film 254 may cover one side surface of the semiconductor pattern 220P, where the back gate dielectric film 252 is between the back gate electrode film 254 and one side surface of the semiconductor pattern 220P, and the gate electrode film 274 may cover the other side surface of the semiconductor pattern 220P, where the gate dielectric film 272 is between the gate electrode film 274 and the other side surface of the semiconductor pattern 220P.

[0138] For example, in a cross-section perpendicular to the direction in which the semiconductor pattern 220P extends (i.e., in the Y-Z cross-section perpendicular to the first horizontal direction (X direction)), the back gate structure 250 may cover one of the sides of the semiconductor pattern 220P, and the gate structure 270 may cover the remaining sides of the semiconductor pattern 220P except for one side of the semiconductor pattern 220P. The back gate structure 250 may be in contact with each of two semiconductor patterns 220P adjacent to each other in the second horizontal direction (Y direction).

[0139] For example, in the Y-Z cross-section, the right side surface of one semiconductor pattern 220P located on the left side of the back gate structure 250 may be in contact with the left side surface of the back gate structure 250. In addition, the remaining surfaces of one semiconductor pattern 220P (i.e., the left side surface, the upper surface, and the lower surface of one semiconductor pattern 220P) may be in contact with one gate structure 270 located on the left side of the back gate structure 250. For example, the left side surface of another semiconductor pattern 220P located on the right side of the back gate structure 250 may be in contact with the right side surface of the back gate structure 250. In addition, the remaining surfaces of another semiconductor pattern 220P (i.e., the right side surface, the upper surface, and the lower surface of another semiconductor pattern 220P) may be in contact with another gate structure 270 located on the right side of the back gate structure 250. Therefore, the back gate structure 250 may be shared by one semiconductor pattern 220P and one gate structure 270 arranged on the left side of the back gate structure 250 and another semiconductor pattern 220P and another gate structure 270 arranged on the right side of the back gate structure 250.

[0140] Figure 38 is an equivalent circuit diagram showing a cell array of the semiconductor memory device 4 according to an exemplary embodiment.

[0141] The cell array of the semiconductor memory device 4 according to an exemplary embodiment may include a plurality of sub-cell arrays SCA. The plurality of sub-cell arrays SCA may be arranged in a first horizontal direction (X direction). Each of the sub-cell arrays SCA may include a plurality of bit lines BL, a plurality of word lines WL, a plurality of back gate lines BG, and a plurality of cell transistors CTR. One cell transistor CTR may be located between one word line WL and one bit line BL.

[0142] The plurality of word lines WL may extend in a vertical direction (Z direction). The word lines WL in one sub-cell array SCA may be spaced apart from each other in a second horizontal direction (Y direction). The plurality of back gate lines BG may extend in a vertical direction (Z direction). The back gate lines BG in one sub-cell array SCA may be spaced apart from each other in a second horizontal direction (Y direction). The word lines WL and the back gate lines BG in one sub-cell array SCA may be spaced apart from each other in the second horizontal direction (Y direction) and extend parallel to each other in the vertical direction (Z direction). In one sub-cell array SCA, the number of word lines WL may be equal to or substantially similar to the number of back gate lines BG. For example, the word lines WL and the back gate lines BG in one sub-cell array SCA may be alternately arranged in the second horizontal direction (Y direction). The bit lines BL in one sub-cell array SCA may be spaced apart from each other in the vertical direction (Z direction).

[0143] The gate of the cell transistor CTR may be connected to the word line WL, and the source of the cell transistor CTR may be connected to the bit line BL. The cell transistor CTR may be connected to the cell capacitor CAP. The drain of the cell transistor CTR may be connected to the first electrode of the cell capacitor CAP, and the second electrode of the cell capacitor CAP may be connected to the ground line PP.

[0144] The semiconductor memory device 4 may include a plurality of sub-cell arrays SCA, each of the plurality of sub-cell arrays SCA including a plurality of memory cells MC, a plurality of bit lines BL, and a plurality of word lines WL, the plurality of memory cells MC being spaced apart from each other in the second horizontal direction (Y direction) and the vertical direction (Z direction) and arranged in rows and columns, the plurality of bit lines BL being connected to the cell transistors CTR of the memory cells MC arranged in the second horizontal direction (Y direction), extending in the second horizontal direction (Y direction), and being spaced apart from each other in the vertical direction (Z direction), the plurality of word lines WL extending in the vertical direction (Z direction) and being spaced apart from each other in the second horizontal direction (Y direction). The plurality of sub-cell arrays SCA may be arranged in a first horizontal direction (X direction).

[0145] Figure 39 is a partial enlarged view of the semiconductor memory device 4 according to an exemplary embodiment.

[0146] Refer together to Figure 38 andFigure 39 The semiconductor memory device 4 may include a plurality of gate structures 270 extending in a vertical direction (Z direction) on a substrate 110, a plurality of back gate structures 250 extending in the vertical direction (Z direction), a plurality of bit lines 280 extending in a second horizontal direction (Y direction), and a plurality of semiconductor patterns 220P connected to the plurality of bit lines 280 and extending in a first horizontal direction (X direction). The semiconductor memory device 4 may include a plurality of cell capacitors CAP. One end of the plurality of semiconductor patterns 220P is connected to the plurality of bit lines 280, and the other end of the plurality of semiconductor patterns 220P, which faces away from one end of the plurality of semiconductor patterns 220P, is connected to the plurality of cell capacitors CAP. The plurality of back gate structures 250 and the plurality of gate structures 270 may be alternately arranged in the second horizontal direction (Y direction).

[0147] The back gate structure 250 may cover one side surface of the semiconductor pattern 220P and the gate structure 270 may cover the remaining side surface of the semiconductor pattern 220P. For example, the back gate dielectric film 252 may be in contact with one side surface of the semiconductor pattern 220P, and the gate dielectric film 272 may be in contact with the remaining side surface of the semiconductor pattern 220P. For example, the back gate electrode film 254 may cover one side surface of the semiconductor pattern 220P, where the back gate dielectric film 252 is between the back gate electrode film 254 and one side surface of the semiconductor pattern 220P, and the gate electrode film 274 may cover the other side surface of the semiconductor pattern 220P, where the gate dielectric film 272 is between the gate electrode film 274 and the other side surface of the semiconductor pattern 220P.

[0148] For example, in a cross-section perpendicular to the direction in which the semiconductor pattern 220P extends (i.e., in the Y-Z cross-section perpendicular to the first horizontal direction (X direction)), the back gate structure 250 may cover one of the edges of the semiconductor pattern 220P, and the gate structure 270 may cover the remaining edges of the semiconductor pattern 220P except for one edge of the semiconductor pattern 220P.

[0149] For example, the right side surface of one semiconductor pattern 220P located on the left side of the back gate structure 250 may be in contact with the left side surface of the back gate structure 250. In addition, the remaining surfaces of one semiconductor pattern 220P (i.e., the left side surface, the upper surface, and the lower surface of one semiconductor pattern 220P) may be in contact with one gate structure 270 located on the left side of the back gate structure 250.

[0150] Although aspects of the exemplary embodiments have been specifically shown and described, it will be understood that various changes in form and detail may be made therein without departing from the spirit and scope of the appended claims.

Claims

1. A semiconductor memory device, comprising: A semiconductor pattern extending in a first direction; a bit line extending in a second direction perpendicular to the first direction and connected to a first end of the semiconductor pattern in the first direction; a unit capacitor extending in the first direction and connected to a second end of the semiconductor pattern in the first direction; A gate structure extending in a third direction perpendicular to both the first direction and the second direction; as well as The back gate structure extends in the third direction. The semiconductor pattern is between the gate structure and the back gate structure, and The back gate structure covers one surface of the semiconductor pattern, and the gate structure covers the other surface of the semiconductor pattern.

2. The semiconductor memory device according to claim 1, wherein: The back gate structure covers one of the two surfaces of the semiconductor pattern in the second direction, and The gate structure covers the other of the two surfaces of the semiconductor pattern in the second direction and the two surfaces of the semiconductor pattern in the third direction.

3. The semiconductor memory device according to claim 2, wherein: The semiconductor pattern is one of a plurality of semiconductor patterns, the gate structure is one of a plurality of gate structures, and the back gate structure is one of a plurality of back gate structures, The semiconductor pattern, the gate structure and the back gate structure are spaced apart from each other in the second direction. wherein one back gate structure among the plurality of back gate structures is located between two gate structures among the plurality of gate structures that are adjacent to each other in the second direction in the second direction, and Wherein, two gate structures among the plurality of gate structures are arranged in the second direction between two back gate structures among the plurality of back gate structures that are adjacent to each other in the second direction.

4. The semiconductor memory device according to claim 3, wherein: The one back gate structure is shared by: A first semiconductor pattern among the plurality of semiconductor patterns located at one side of the one back gate structure in the second direction; A first gate structure among the plurality of gate structures located at the one side of the one back gate structure in the second direction; a second semiconductor pattern located at the other side of the one back gate structure in the second direction among the plurality of semiconductor patterns; as well as A second gate structure among the plurality of gate structures is located at the other side of the one back gate structure in the second direction.

5. The semiconductor memory device according to claim 4, wherein: The one back gate structure covers one surface of the first semiconductor pattern and one surface of the second semiconductor pattern facing each other in the second direction, The first gate structure covers another surface of the first semiconductor pattern in the second direction and two surfaces of the first semiconductor pattern in the third direction, and The second gate structure covers the other surface of the second semiconductor pattern in the second direction and two surfaces of the second semiconductor pattern in the third direction.

6. The semiconductor memory device according to claim 1, further comprising: The sub-insulating layer is between the semiconductor pattern and the back gate structure.

7. The semiconductor memory device according to claim 1, further comprising: a sub-insulating layer, located between the semiconductor pattern and the back gate structure, and extending from the back gate structure into the semiconductor pattern, The semiconductor pattern covers one of the two surfaces of the sub-insulating layer in the second direction and both surfaces of the sub-insulating layer in the third direction.

8. The semiconductor memory device according to claim 1, further comprising: a sub-semiconductor layer including a material different from that of the semiconductor pattern, The sub-semiconductor layer is between the semiconductor pattern and the back gate structure.

9. The semiconductor memory device according to claim 1, further comprising: a sub-semiconductor layer including a material different from that of the semiconductor pattern, The sub-semiconductor layer is between the semiconductor pattern and the back gate structure, and extends from the back gate structure into the semiconductor pattern, and The semiconductor pattern covers one of the two surfaces of the sub-semiconductor layer in the second direction and both surfaces of the sub-semiconductor layer in the third direction.

10. The semiconductor memory device according to claim 1, wherein: The semiconductor pattern is one of a plurality of semiconductor patterns, the gate structure is one of a plurality of gate structures, and the back gate structure is one of a plurality of back gate structures, The semiconductor pattern, the gate structure and the back gate structure are spaced apart from each other in the second direction. The plurality of back gate structures and the plurality of gate structures are alternately arranged in the second direction, Each of the plurality of back gate structures covers one of two surfaces of a corresponding semiconductor pattern among the plurality of semiconductor patterns in the second direction, and Each of the plurality of gate structures covers the other of the two surfaces of a corresponding semiconductor pattern among the plurality of semiconductor patterns in the second direction and both surfaces of the corresponding semiconductor pattern in the third direction.

11. A semiconductor memory device comprising: a plurality of semiconductor patterns, each of the plurality of semiconductor patterns extending in a first horizontal direction on a substrate, wherein the plurality of semiconductor patterns are spaced apart from each other in a second horizontal direction and a vertical direction perpendicular to the first horizontal direction; a plurality of bit lines extending in a vertical direction on the substrate, wherein the plurality of bit lines are spaced apart from each other in a second horizontal direction and connected to first ends of the plurality of semiconductor patterns in the first horizontal direction; a plurality of unit capacitors extending in a first horizontal direction on the substrate and connected to second ends of the plurality of semiconductor patterns in the first horizontal direction; a plurality of back gate structures extending in a second horizontal direction and covering one of the upper surface and the lower surface of the plurality of semiconductor patterns, wherein the plurality of back gate structures are spaced apart from each other in a vertical direction; and a plurality of gate structures extending in a second horizontal direction and covering the other of the upper surface and the lower surface of the plurality of semiconductor patterns and each of the two side surfaces of the plurality of semiconductor patterns in the second horizontal direction, Among them, the upper surface and lower surface of a back gate structure among the multiple back gate structures respectively cover the lower surface of the first semiconductor pattern and the upper surface of the second semiconductor pattern, the first semiconductor pattern is a semiconductor pattern among the multiple semiconductor patterns arranged above the one back gate structure, and the second semiconductor pattern is another semiconductor pattern among the multiple semiconductor patterns arranged below the one back gate structure.

12. The semiconductor memory device according to claim 11, wherein: The plurality of gate structures include: a first gate structure disposed above the first semiconductor pattern and a second gate structure disposed below the second semiconductor pattern, The first gate structure covers the upper surface of the first semiconductor pattern and two side surfaces of the first semiconductor pattern in the second horizontal direction. The second gate structure covers the lower surface of the second semiconductor pattern and two side surfaces of the second semiconductor pattern in the second horizontal direction.

13. The semiconductor memory device according to claim 11, wherein: Each of the plurality of back gate structures includes a back gate electrode film and a back gate dielectric film, the back gate dielectric film being between the back gate electrode film and the plurality of semiconductor patterns, Each of the plurality of gate structures includes a gate electrode film and a gate dielectric film, the gate dielectric film is between the gate electrode film and the plurality of semiconductor patterns, and A portion of the back gate dielectric film contacts a portion of the gate dielectric film.

14. The semiconductor memory device according to claim 11, wherein: The plurality of gate structures and the plurality of back gate structures are spaced apart from each other in a vertical direction, wherein two gate structures among the plurality of gate structures are arranged between two back gate structures among the plurality of back gate structures that are adjacent to each other in a vertical direction, and Among them, one back gate structure among the multiple back gate structures is located between two gate structures among the multiple gate structures that are adjacent to each other in the vertical direction, and wherein the one back gate structure is shared by two semiconductor patterns among the multiple semiconductor patterns that are respectively located above and below the one back gate structure.

15. The semiconductor memory device according to claim 11, further comprising: The sub-insulating layers are respectively arranged between the plurality of semiconductor patterns and the plurality of back gate structures covering the plurality of semiconductor patterns.

16. The semiconductor memory device according to claim 15, wherein: Each of the plurality of semiconductor patterns has a thickness less than 5 nm between the sub-insulating layer and the gate structure.

17. The semiconductor memory device according to claim 11, further comprising: a sub-semiconductor layer including a material different from that of the plurality of semiconductor patterns, The sub-semiconductor layers are respectively arranged between the plurality of semiconductor patterns and the plurality of back gate structures covering the plurality of semiconductor patterns.

18. The semiconductor memory device according to claim 17, wherein: The sub-semiconductor layer includes a semiconductor material having a band gap smaller than a band gap of a semiconductor material of the plurality of semiconductor patterns.

19. A semiconductor memory device comprising: a plurality of semiconductor patterns, each of the plurality of semiconductor patterns extending in a first horizontal direction on a substrate, wherein the plurality of semiconductor patterns are spaced apart from each other in a second horizontal direction and a vertical direction perpendicular to the first horizontal direction; a plurality of bit lines extending in a vertical direction on the substrate, wherein the plurality of bit lines are spaced apart from each other in a second horizontal direction and connected to first ends of the plurality of semiconductor patterns in the first horizontal direction; a plurality of unit capacitors extending in a first horizontal direction on the substrate and connected to second ends of the plurality of semiconductor patterns in the first horizontal direction; a plurality of back gate structures, each of the plurality of back gate structures extending in a second horizontal direction, wherein the plurality of back gate structures are spaced apart from each other in a vertical direction, each of the plurality of back gate structures comprising a back gate dielectric film and a back gate electrode film covering the back gate dielectric film, the back gate dielectric film covering one of an upper surface and a lower surface of a corresponding semiconductor pattern among the plurality of semiconductor patterns; and a plurality of gate structures, each of the plurality of gate structures extending in a second horizontal direction, wherein the plurality of gate structures are spaced apart from each other in a vertical direction, and each of the plurality of gate structures includes a gate dielectric film and a gate electrode film covering the gate dielectric film, the gate dielectric film covering the other of the upper surface and the lower surface of a corresponding semiconductor pattern among the plurality of semiconductor patterns and both side surfaces of the corresponding semiconductor pattern in the second horizontal direction, Among them, two gate structures among the multiple gate structures are between two semiconductor patterns among the multiple semiconductor patterns that are adjacent to each other in the vertical direction, and one back gate structure among the multiple back gate structures is between two semiconductor patterns among the multiple semiconductor patterns that are adjacent to each other in the vertical direction.

20. The semiconductor memory device according to claim 19, wherein: The back gate dielectric film and the gate dielectric film covering two semiconductor patterns adjacent to each other in the second horizontal direction among the plurality of semiconductor patterns are in contact with each other between the two semiconductor patterns adjacent to each other in the second horizontal direction.

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