Semiconductor device
By adopting a vertical channel transistor structure in DRAM devices, including plate electrodes, capacitor dielectric layer and cell plugs, the electrical connection path is optimized, and the problem of increased leakage current in DRAM devices is solved, which improves electrical performance and reduces the difficulty of the etching process.
Patent Information
- Application Number
- CN202411868033.8
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Priority Date
- 2023-12-29
- Filing Date
- 2024-12-18
- Publication Date
- 2025-07-01
AI Technical Summary
With the miniaturization of DRAM devices, the leakage current in the channel region gradually increases, and it is difficult for the prior art to effectively reduce the leakage current.
Using a vertical channel transistor structure, including a plate electrode, a capacitor dielectric layer and a cell plug, the electrical connection path is optimized to reduce leakage current by forming a plurality of vertical structures on the substrate.
By optimizing the electrical connection path, the leakage current of semiconductor devices is reduced, the electrical performance is improved, the risk of arc discharge is reduced, and the difficulty of etching process is simplified.
Smart Images
Figure CN120239270A_ABST
Abstract
Description
Technical Field
[0001] The inventive concept relates to a semiconductor device, and more particularly, to a semiconductor device including a vertical-channel transistor. Background Art
[0002] As semiconductor devices are scaled down, the size of dynamic random access memory (DRAM) devices is decreasing. In a DRAM device having a 1T-1C structure (where one transistor is connected to one capacitor), as the DRAM device is miniaturized, the leakage current passing through the channel region may gradually increase. To reduce such leakage current, a vertical-channel transistor including an oxide semiconductor material as a channel layer has been proposed. Summary of the Invention
[0003] The inventive concept provides a semiconductor device having excellent electrical properties.
[0004] According to an aspect of the inventive concept, there is provided a semiconductor device including: a peripheral circuit on a substrate; a capacitor structure on the peripheral circuit and including a plate electrode and a vertical structure extending in a vertical direction perpendicular to an upper surface of the substrate on the plate electrode, wherein the vertical structure includes a first electrode, a second electrode, and a capacitor dielectric layer between the first electrode and the second electrode; a cell transistor at a higher vertical level than the capacitor structure and electrically connected to the capacitor structure; a first cell plug extending in a vertical direction between the plate electrode and the peripheral circuit and adjacent to and electrically connected to a bottom surface of the plate electrode; and a second cell plug extending in a vertical direction between the cell transistor and the peripheral circuit, wherein the first cell plug includes a first end adjacent to the peripheral circuit and a second end opposite to the first end, and a width of the second end is greater than a width of the first end.
[0005] According to another aspect of the inventive concept, there is provided a semiconductor device including: a peripheral circuit on a substrate; a capacitor structure on the peripheral circuit and including a plate electrode and a plurality of vertical structures extending in a vertical direction perpendicular to an upper surface of the substrate on the plate electrode, wherein each of the plurality of vertical structures includes a first electrode, a second electrode, and a capacitor dielectric layer between the first electrode and the second electrode; a molded insulating layer on the plate electrode and including a plurality of openings extending in the vertical direction, wherein the plurality of vertical structures are respectively in the plurality of openings; an active semiconductor layer on the molded insulating layer and electrically connected to the second electrode; a word line on a sidewall of the active semiconductor layer; a bit line on an upper surface of the active semiconductor layer; a first cell plug extending in the vertical direction between the plate electrode and the peripheral circuit and adjacent to and electrically connected to a bottom surface of the plate electrode; and a second cell plug extending in the vertical direction between the word line and the peripheral circuit and electrically connecting the word line to the peripheral circuit.
[0006] According to another aspect of the inventive concept, there is provided a semiconductor device including: a peripheral circuit on a substrate; a capacitor structure on the peripheral circuit and including a plate electrode and a plurality of vertical structures extending in a vertical direction perpendicular to an upper surface of the substrate on the plate electrode, wherein each of the plurality of vertical structures includes a first electrode electrically connected to the plate electrode and extending in the vertical direction, a second electrode on a sidewall of the first electrode, and a capacitor dielectric layer between the first electrode and the second electrode; a molded insulating layer on the plate electrode and surrounding sidewalls of the plurality of vertical structures; an active semiconductor layer at a higher vertical level than the capacitor structure, extending in the vertical direction, and including a first end and a second end, wherein the first end is adjacent to and electrically connected to the second electrode; a word line on a sidewall of the active semiconductor layer; a bit line adjacent to the second end of the active semiconductor layer and electrically connected to the second end of the active semiconductor layer; a wiring layer at a higher vertical level than the bit line; a first cell plug extending in the vertical direction between the plate electrode and the peripheral circuit and adjacent to and electrically connected to a bottom surface of the plate electrode; a second cell plug extending in the vertical direction between the word line and the peripheral circuit and electrically connecting the word line to the peripheral circuit; a third cell plug extending in the vertical direction between the bit line and the peripheral circuit and electrically connecting the bit line to the peripheral circuit; and a peripheral plug extending in the vertical direction between the wiring layer and the peripheral circuit and electrically connecting the wiring layer to the peripheral circuit. BRIEF DESCRIPTION OF THE DRAWINGS
[0007] Embodiments of the inventive concept will be more clearly understood from the following detailed description in conjunction with the accompanying drawings, in which:
[0008] Figure 1 A perspective view of a semiconductor device according to an embodiment is shown;
[0009] Figure 2 Shows Figure 1 An enlarged layout of the cell array region;
[0010] Figure 3 Is a cross-sectional view of a semiconductor device taken along Figure 2 Line A1 - A1';
[0011] Figure 4 Is a cross-sectional view of a semiconductor device taken along Figure 2 Line A2 - A2';
[0012] Figure 5 Shows Figure 3 An enlarged view of region CX1;
[0013] Figure 6 Shows Figure 3 An enlarged view of region CX2;
[0014] Figure 7 And Figure 8 Is a cross-sectional view of a semiconductor device according to an embodiment;
[0015] Figure 9 Shows Figure 7 An enlarged view of region CX1;
[0016] Figure 10 Shows Figure 7 An enlarged view of region CX2;
[0017] Figure 11 Is a cross-sectional view of a semiconductor device according to an embodiment;
[0018] Figures 12 to 15 、 Figure 16A 、 Figure 16B 、 Figure 17A 、 Figure 17B 、 Figure 18 、 Figure 19A 、 Figure 19B 、 Figure 20A 、 Figure 20B 、 Figure 21A And Figure 21B Schematically shows a method of manufacturing a semiconductor device according to an embodiment; and
[0019] Figure 22 、 Figure 23 、 Figure 24A 、 Figure 24B 、 Figure 25A And Figure 25B Schematically shows a method of manufacturing a semiconductor device according to an embodiment. Detailed Description
[0020] Figure 1 A perspective view of a semiconductor device 100 according to an embodiment is shown. Figure 2 Shown is Figure 1 an enlarged layout of a cell array region MCA. Figure 3 is a cross-sectional view of the semiconductor device 100 taken along line Figure 2 A1 - A1' thereof. Figure 4 is a cross-sectional view of the semiconductor device 100 taken along line Figure 2 A2 - A2' thereof. Figure 5 is an enlarged view showing Figure 3 region CX1 thereof. Figure 6 is an enlarged view showing Figure 3 region CX2 thereof.
[0021] Referring to Figures 1 to 6 , the semiconductor device 100 may include a peripheral circuit region PCA and a cell array region MCA at a higher vertical level than the peripheral circuit region PCA.
[0022] In some embodiments, the cell array region MCA may be a memory cell region of a dynamic random access memory (DRAM) device, and the peripheral circuit region PCA may be a core region or a peripheral circuit region of the DRAM device. For example, the peripheral circuit region PCA may include peripheral circuit transistors 120 configured to transmit signals and / or power to a memory cell array included in the cell array region MCA. In an embodiment, the peripheral circuit transistors 120 may configure various circuits, such as a command decoder, control logic, an address buffer, a row decoder, a column decoder, a sense amplifier, and a data input / output circuit.
[0023] As Figure 2 shown, in the cell array region MCA, a plurality of word lines WL extending in a first horizontal direction X and a plurality of bit lines BL extending in a second horizontal direction Y may be arranged. At intersections where the plurality of word lines WL and the plurality of bit lines BL cross, a plurality of cell transistors CTR may be arranged. A plurality of vertical structures VS may be respectively arranged under the plurality of cell transistors CTR.
[0024] The word lines WL may include first word lines WL1 and second word lines WL2 alternately arranged in the second horizontal direction Y, and the cell transistors CTR may include first cell transistors CTR1 and second cell transistors CTR2 alternately arranged in the second horizontal direction Y. The first cell transistors CTR1 may be arranged adjacent to the first word lines WL1, and the second cell transistors CTR2 may be arranged adjacent to the second word lines WL2.
[0025] The first unit transistor CTR1 and the second unit transistor CTR2 may have a mirror-symmetric structure with respect to each other. For example, the first unit transistor CTR1 and the second unit transistor CTR2 may have a mirror-symmetric structure with respect to a center line between the first unit transistor CTR1 and the second unit transistor CTR2, and the center line extends in the first horizontal direction X.
[0026] In an embodiment, the width of the bit line BL may be 1F, the pitch of the bit line BL (i.e., the sum of the width and the gap) may be 2F, the pitch of the word line WL (i.e., the sum of the width and the gap) may be 2F, and the unit area for forming one unit transistor CTR may be 4F. 2 . Therefore, since the unit transistor CTR can be a cross-point type that requires a relatively small unit area, it can be advantageous for improving the integration of the semiconductor device 100.
[0027] The edge region EA may be located near the cell array region MCA. The edge region EA may be an area where electrical connection members for the word line WL and / or electrical connection members for the bit line BL can be arranged, and may be an area including electrical connection members for realizing electrical connection between the cell array region MCA and the peripheral circuit region PCA.
[0028] The substrate 110 may include silicon, such as single-crystalline silicon, polycrystalline silicon, or amorphous silicon. In other embodiments, the substrate 110 may include at least one selected from germanium (Ge), silicon germanium (SiGe), silicon carbide (SiC), gallium arsenide (GaAs), indium arsenide (InAs), and indium phosphide (InP). In some embodiments, the substrate 110 may include a conductive region, such as an impurity-doped well or an impurity-doped structure.
[0029] In the peripheral circuit region PCA, an active region AC may be defined in the substrate 110, and the peripheral circuit transistor 120 may be arranged at the active region AC of the substrate 110. The peripheral circuit transistor 120 may include a gate electrode 120G, a gate insulating layer 120I, and source / drain regions 120S. For example, the peripheral circuit transistor 120 may be electrically connected to the bit line BL or the word line WL through the peripheral circuit line 122 and the peripheral circuit contact 124.
[0030] The peripheral circuit insulating layer 126 may cover the peripheral circuit transistor 120, the peripheral circuit line 122, and the peripheral circuit contact 124 on the substrate 110. The peripheral circuit insulating layer 126 may include an oxide layer, a nitride layer, a low-k dielectric layer, or a combination thereof, and may have a stacked structure including a plurality of insulating layers.
[0031] The isolation insulating layer 128 may be disposed on the peripheral circuit insulating layer 126, and the capacitor structure CAP may be disposed on the isolation insulating layer 128. The capacitor structure CAP may have a metal-insulator-metal type capacitor configuration. The capacitor structure CAP may include a plate electrode PE and a plurality of vertical structures VS on the plate electrode PE.
[0032] In an embodiment, the plate electrode PE may have a planar shape extending in a first horizontal direction X and a second horizontal direction Y. In an embodiment, the plate electrode PE may include Si, SiGe, tungsten (W), tungsten nitride (WN), titanium (Ti), titanium nitride (TiN), or a combination thereof.
[0033] The first unit plug CC1 may be disposed between the plate electrode PE and the peripheral circuit line 122. The upper surface of the first unit plug CC1 may contact (and thus be adjacent to and electrically connected to) the bottom surface of the plate electrode PE, and the bottom surface of the first unit plug CC1 may contact the upper surface of the uppermost peripheral circuit line 122_U. The first unit plug CC1 may electrically connect the plate electrode PE to the peripheral circuit transistor 120 through the peripheral circuit line 122.
[0034] In an embodiment, the first unit plug CC1 may be located in a first unit plug hole CC1H that penetrates the isolation insulating layer 128. The first unit plug hole CC1H may be formed by a process of removing a portion of the isolation insulating layer 128 from the upper surface of the isolation insulating layer 128, and in an embodiment, the first unit plug hole CC1H may have inclined sidewalls such that the upper width of the first unit plug hole CC1H is greater than the bottom width of the first unit plug hole CC1H.
[0035] The first unit plug CC1 may include a first end CC1a disposed close to (i.e., adjacent to) the peripheral circuit transistor 120 (e.g., the first end CC1a that contacts the upper surface of the uppermost peripheral circuit line 122_U) and a second end CC1b opposite to the first end CC1a. The width of the second end CC1b of the first unit plug CC1 may be greater than the width of the first end CC1a of the first unit plug CC1. The first unit plug CC1 may thus taper towards the peripheral circuit in the peripheral circuit area PCA.
[0036] The vertical structure VS may extend on the plate electrode PE in the vertical direction Z. For example, each vertical structure VS may include a first electrode 142, a capacitor dielectric layer 144, and a second electrode 146. Each vertical structure VS may have a relatively high aspect ratio, and the height of the vertical structure VS in the vertical direction Z may be greater than the width of the vertical structure VS in the first horizontal direction X or the second horizontal direction Y.
[0037] The vertical structure VS can be surrounded by the capacitor-molded insulating layer 130. For example, the capacitor-molded insulating layer 130 can be disposed on the plate electrode PE and include a plurality of openings 130H that penetrate the capacitor-molded insulating layer 130 and extend in the vertical direction Z. The vertical structure VS can be respectively located in the openings 130H of the capacitor-molded insulating layer 130. Thus, the vertical structure VS can be arranged to extend in the vertical direction Z by penetrating the capacitor-molded insulating layer 130. The bottom surface of the capacitor-molded insulating layer 130 can be in contact with the upper surface of the plate electrode PE.
[0038] The first electrode 142 can be disposed on the inner wall of each opening 130H. The first electrode 142 can have a cylindrical shape with a closed bottom and extend in the vertical direction Z in each opening 130H. The bottom surface of the first electrode 142 can be in contact with the upper surface of the plate electrode PE.
[0039] The capacitor dielectric layer 144 can be disposed on the inner wall of each opening 130H (e.g., the inner side wall of the first electrode 142).
[0040] The second electrode 146 can be in the interior (e.g., the middle part) of each opening 130H (e.g., can fill the interior (e.g., the middle part) of each opening 130H), such that the capacitor dielectric layer 144 is disposed between the second electrode 146 and the first electrode 142. The bottom surface and side walls of the second electrode 146 can be surrounded by the capacitor dielectric layer 144, and the second electrode 146 can have a column (e.g., rectangular or cylindrical) shape that extends in the vertical direction Z. In a horizontal cross-section (i.e., the X-Y plane), the first electrode 142 can be annular and the second electrode 146 can have a circular shape. The annular horizontal cross-section of the first electrode 142 can surround (e.g., enclose) the circular horizontal cross-section of the second electrode 146.
[0041] Optionally, an etch stop layer 131 can be disposed on the upper surface of the capacitor-molded insulating layer 130, and the etch stop layer 131 can surround the upper part of the side wall of each vertical structure VS. In an embodiment, the capacitor dielectric layer 144 can extend from the inner wall of each opening 130H to the upper surface of the capacitor-molded insulating layer 130. As Figure 5 shown, the etch stop layer 131 can be disposed on the upper surface of the capacitor-molded insulating layer 130, and a part of the capacitor dielectric layer 144 can be disposed on the upper surface of the etch stop layer 131.
[0042] In an embodiment, the first electrode 142 may include Ti, TiN, tantalum (Ta), tantalum nitride (TaN), W, WN, titanium silicon nitride (TiSiN), tungsten silicon nitride (WSiN), polysilicon, SiGe, or a combination thereof. In an embodiment, the second electrode 146 may include Ti, TiN, Ta, TaN, W, WN, TiSiN, WSiN, polysilicon, or a combination thereof. In an embodiment, the capacitor dielectric layer 144 may include at least one material selected from hafnium oxide (HfO), hafnium silicate (HfSiO), hafnium oxynitride (HfON), hafnium silicon oxynitride (HfSiON), lanthanum oxide (LaO), lanthanum aluminum oxide (LaAlO), zirconium oxide (ZrO), zirconium silicate (ZrSiO), zirconium oxynitride (ZrON), zirconium silicon oxynitride (ZrSiON), tantalum oxide (TaO), titanium oxide (TiO), barium strontium titanate (BaSrTiO), barium titanate (BaTiO), lead zirconate titanate (PbZrTiO), strontium tantalum bismuthate (SrTaBiO), bismuth iron oxide (BiFeO), strontium titanate (SrTiO), yttrium oxide (YO), aluminum oxide (AlO), and lead scandium tantalum oxide (PbScTaO).
[0043] In an embodiment, the opening 130H (having a bottom that exposes the upper surface of the plate electrode PE) may be formed by penetrating the capacitor molding insulating layer 130, and the vertical structure VS may be formed by sequentially forming the first electrode 142, the capacitor dielectric layer 144, and the second electrode 146 in the opening 130H. During an etching process for removing a part of the capacitor molding insulating layer 130, a circuit path to the substrate 110 may be provided to the plate electrode PE through the first unit plug CC1 that is adjacent to and electrically connected to (e.g., contacts) the bottom surface of the plate electrode PE, and electrical damage (e.g., arc discharge) to the plate electrode PE that may occur due to the collision of plasma or ions used during the etching process may be prevented.
[0044] A plurality of landing pads LP may be respectively disposed on the plurality of vertical structures VS. Each landing pad LP may include Ti, TiN, Ta, TaN, W, WN, TiSiN, WSiN, polysilicon, or a combination thereof. A landing pad isolation insulating layer LPI surrounding the sidewalls of the landing pad LP may be disposed on the capacitor molding insulating layer 130.
[0045] The channel molding insulating layer 132 may be disposed on the landing pad LP and the landing pad isolation insulating layer LPI and include a plurality of molding openings 132H extending in a first horizontal direction X. A unit transistor CTR may be disposed in each molding opening 132H.
[0046] In an embodiment, the unit transistor CTR may include an active semiconductor layer AP, a gate insulating layer GI, and a word line WL disposed in each molding opening 132H.
[0047] In an embodiment, the active semiconductor layer AP may have a U-shaped vertical cross-section in each molding opening 132H. The active semiconductor layer AP may include a vertical extension portion (i.e., a vertical part) APV extending in the vertical direction Z and a horizontal extension portion (i.e., a horizontal part) APH integrally connected to the bottom of the vertical extension portion APV and extending in the second horizontal direction Y. For example, the vertical extension portion APV may be disposed on opposite (e.g., two) sidewalls of each molding opening 132H, and the horizontal extension portion APH may be disposed on the bottom of each molding opening 132H. The horizontal extension portion APH may be disposed to vertically overlap two landing pads LP arranged side by side in the second horizontal direction Y.
[0048] In an embodiment, the active semiconductor layer AP may include zinc tin oxide (Zn x Sn y O), indium zinc oxide (In x Zn y O), zinc oxide (ZnO x ), indium gallium zinc oxide (In x Ga y Zn z O), indium gallium silicon oxide (In x Ga y Si z O), indium tungsten oxide (In x W y O), indium oxide (In x O), tin oxide (Sn x O), titanium oxide (Ti x O), zinc oxynitride (Zn x ON z ), magnesium zinc oxide (Mg x Zn y O), zirconium indium zinc oxide (Zr x In y Zn z O), hafnium indium zinc oxide (Hf x In y Zn z O), tin indium zinc oxide (Sn x In y Zn z O), aluminum tin indium zinc oxide (Al x Sn y In z Zn a O), silicon indium zinc oxide (Six In y Zn z O), aluminum zinc tin oxide (Al x Zn y Sn z O), gallium zinc tin oxide (Ga x Zn y Sn z O), and zirconium zinc tin oxide (Zr x Zn y Sn z O) or at least one of them.
[0049] In an embodiment, the active semiconductor layer AP may include a first end connected to (e.g., in contact with and electrically connected to) the landing pad LP and a second end opposite to the first end. The first end may refer to the horizontally extending portion APH, and the second end may refer to the upper portion of the vertically extending portion APV. In an embodiment, the first end and the second end of the active semiconductor layer AP may also be doped with impurity ions, and the regions doped with impurity ions may be used as the source contact and the drain contact, respectively.
[0050] The gate insulating layer GI may be disposed on the sidewalls of the vertically extending portion APV and the upper surface of the horizontally extending portion APH of the active semiconductor layer AP.
[0051] In an embodiment, the gate insulating layer GI may include at least one selected from a ferroelectric material and a high-k dielectric material having a dielectric constant higher than that of silicon oxide. In an embodiment, the gate insulating layer GI may include at least one material selected from HfO, HfSiO, HfON, HfSiON, LaO, LaAlO, ZrO, ZrSiO, ZrON, ZrSiON, TaO, TiO, BaSrTiO, BaTiO, PbZrTiO, SrTaBiO, BiFeO, SrTiO, YO, AlO, and PbScTaO.
[0052] The word line WL may be disposed in each molding opening 132H of the channel molding insulating layer 132. The word line WL may be disposed on the sidewalls of the gate insulating layer GI. In an embodiment, the word line WL may include Ti, TiN, Ta, TaN, Mo, Ru, W, WN, TiSiN, WSiN, polysilicon, or a combination thereof. For example, in one molding opening 132H, two word lines WL may be spaced apart from each other and extend in the first horizontal direction X. For example, the first word line WL1 may be disposed on the first sidewall of the molding opening 132H, and the second word line WL2 may be spaced apart from the first word line WL1 on the second sidewall of the molding opening 132H.
[0053] In an embodiment, within a single molding opening 132H, the first buried insulating layer 152 may be disposed between two word lines WL in one molding opening 132H, and the second buried insulating layer 154 may be disposed on the two word lines WL and the first buried insulating layer 152.
[0054] A bit line BL extending in the second horizontal direction Y may be disposed on the unit transistor CTR. The bit line BL may be disposed at a higher vertical level relative to the upper surface of the substrate 110 than the capacitor structure CAP. In an embodiment, the bit line BL may be disposed on a second end portion of the active semiconductor layer AP (e.g., on an upper side of the vertically extending portion APV).
[0055] In an embodiment, the bit line BL may include Ti, TiN, Ta, TaN, Mo, Ru, W, WN, Co, Ni, TiSi, TiSiN, WSi, WSiN, TaSi, TaSiN, RuTiN, CoSi, NiSi, polysilicon, or a combination thereof.
[0056] In an embodiment, a shielding structure extending in the second horizontal direction Y may be additionally disposed between the bit lines BL. The shielding structure may include a conductive material, such as a metal. In an embodiment, the shielding structure may include a conductive material and have an air gap or void therein.
[0057] In the edge region EA, the buried insulating layer 134 may cover the capacitor structure CAP and the unit transistor CTR on the isolation insulating layer 128. The buried insulating layer 134 may have a height sufficient to cover the capacitor structure CAP, the unit transistor CTR, and the bit line BL. In an embodiment, the buried insulating layer 134 may include an oxide layer, a nitride layer, a low-k dielectric layer, or a combination thereof. In an embodiment, the buried insulating layer 134 may include a stacked structure including a plurality of insulating layers.
[0058] In an embodiment, a shielding structure extending in the second horizontal direction Y may be additionally disposed between the bit lines BL. The shielding structure may include a conductive material, such as a metal. In an embodiment, the shielding structure may include a conductive material and have an air gap or void therein. Optionally, in other embodiments, the air gap may be defined in the buried insulating layer 134 rather than in the shielding structure.
[0059] As Figure 2 and Figure 4As shown, in the edge region EA, the second unit plug CC2 can be arranged between the unit transistor CTR and the peripheral circuit line 122. For example, the upper surface of the second unit plug CC2 can contact the bottom surface of the word line WL, and the bottom surface of the second unit plug CC2 can contact the upper surface of the uppermost peripheral circuit line 122_U. The second unit plug CC2 can electrically connect the word line WL to the peripheral circuit transistor 120 through the peripheral circuit line 122.
[0060] In an embodiment, the second unit plug CC2 can be arranged in the second unit plug hole CC2H that penetrates the isolation insulating layer 128 and the buried insulating layer 134. The second unit plug hole CC2H can be formed by a process of removing a part of the buried insulating layer 134 and a part of the isolation insulating layer 128 from the upper surface of the buried insulating layer 134, and in an embodiment, the second unit plug hole CC2H can have inclined sidewalls such that the upper width of the second unit plug hole CC2H is greater than its bottom width.
[0061] The second unit plug CC2 can include a first end CC2a arranged close to (i.e., adjacent to) the peripheral circuit transistor 120 (for example, the first end CC2a that contacts the upper surface of the uppermost peripheral circuit line 122_U) and a second end CC2b opposite to the first end CC2a. The width of the second end CC2b of the second unit plug CC2 can be greater than the width of the first end CC2a of the second unit plug CC2.
[0062] In an embodiment, since the capacitor structure CAP is arranged between the unit transistor CTR and the peripheral circuit transistor 120, the height of the second unit plug CC2 in the vertical direction Z can be greater than the height of the capacitor structure CAP in the vertical direction Z (for example, the height of the vertical structure VS in the vertical direction Z). For example, the upper surface of the second unit plug CC2 can be at a higher vertical level than the upper surface of the vertical structure VS. In addition, the second unit plug CC2 can have a greater vertical length than the vertical structure VS.
[0063] As Figure 3 As shown, in the edge region EA, the third unit plug CC3 can be arranged between the bit line BL and the peripheral circuit line 122. For example, the upper surface of the third unit plug CC3 can contact the bottom surface of the bit line BL, and the bottom surface of the third unit plug CC3 can contact the upper surface of the uppermost peripheral circuit line 122_U. The third unit plug CC3 can electrically connect the bit line BL to the peripheral circuit transistor 120 through the peripheral circuit line 122.
[0064] In an embodiment, the third unit plug CC3 may be disposed in a third unit plug hole CC3H that penetrates the isolation insulating layer 128 and the buried insulating layer 134. The third unit plug hole CC3H may be formed by a process of removing a part of the buried insulating layer 134 and a part of the isolation insulating layer 128 from the upper surface of the buried insulating layer 134, and in an embodiment, the third unit plug hole CC3H may have inclined sidewalls such that the upper width of the third unit plug hole CC3H is greater than the bottom width of the third unit plug hole CC3H.
[0065] The third unit plug CC3 may include a first end CC3a (e.g., the first end CC3a that contacts the upper surface of the uppermost peripheral circuit line 122_U) disposed close to (i.e., adjacent to) the peripheral circuit transistor 120 and a second end CC3b opposite to the first end CC3a. The width of the second end CC3b of the third unit plug CC3 may be greater than the width of the first end CC3a of the third unit plug CC3.
[0066] In an embodiment, since the capacitor structure CAP is disposed between the bit line BL and the peripheral circuit transistor 120, the height of the third unit plug CC3 in the vertical direction Z may be greater than the height of the capacitor structure CAP in the vertical direction Z (e.g., the height of the vertical structure VS in the vertical direction Z).
[0067] The upper wiring layer 162 and the upper via 164 may be disposed on the upper surface of the buried insulating layer 134, and an upper insulating layer 166 may be disposed to cover the upper wiring layer 162 and the upper via 164. In an embodiment, each of the upper wiring layer 162 and the upper via 164 may have a multi-layer structure in which a second layer is disposed at a vertical level different from that of the first layer. In an embodiment, the upper surface of the lowermost layer in the upper wiring layer 162 may be coplanar with the upper surface of the buried insulating layer 134.
[0068] As Figure 3 shown, in the edge region EA, the peripheral plug PC1 may be disposed between the upper wiring layer 162 and the peripheral circuit line 122. For example, the upper surface of the peripheral plug PC1 may contact the bottom surface of the upper wiring layer 162, and the bottom surface of the peripheral plug PC1 may contact the upper surface of the uppermost peripheral circuit line 122_U. The peripheral plug PC1 may electrically connect the upper wiring layer 162 to the peripheral circuit transistor 120 through the peripheral circuit line 122.
[0069] In an embodiment, the peripheral plug PC1 may be disposed in a peripheral plug hole PC1H that penetrates the isolation insulating layer 128 and the buried insulating layer 134. The peripheral plug hole PC1H may be formed by a process of removing a part of the buried insulating layer 134 and a part of the isolation insulating layer 128 from the upper surface of the buried insulating layer 134, and in an embodiment, the peripheral plug hole PC1H may have inclined sidewalls such that the upper width of the peripheral plug hole PC1H is greater than the bottom width of the peripheral plug hole PC1H.
[0070] The peripheral plug PC1 may include a first end PC1a (e.g., the first end PC1a that contacts the upper surface of the uppermost peripheral circuit line 122_U) disposed close to (i.e., adjacent to) the first end of the peripheral circuit transistor 120 and a second end PC1b opposite to the first end PC1a. The width of the second end PC1b of the peripheral plug PC1 may be greater than the width of the first end PC1a of the peripheral plug PC1.
[0071] Generally, the peripheral circuit structure and the cell transistor are sequentially disposed on the substrate, and the capacitor structure is disposed on the cell transistor. A plurality of openings having a relatively high aspect ratio are formed in the molding insulating layer, and lower electrodes are formed in the openings. However, during the process of etching the openings having a high aspect ratio, the inclination of the openings may occur, resulting in misalignment (where the openings are misaligned on the corresponding landing pads / not aligned with the corresponding landing pads but aligned with another adjacent landing pad / aligned with another adjacent landing pad).
[0072] However, according to an embodiment, the opening 130H (having a bottom that exposes the upper surface of the plate electrode PE) may be formed by penetrating the capacitor molding insulating layer 130, and the vertical structure VS may be formed by sequentially forming a first electrode 142, a capacitor dielectric layer 144, and a second electrode 146 in the opening 130H. Therefore, since the plate electrode PE is exposed at the bottom of the opening 130H, it is not necessary to align the opening 130H with the landing pad, and thus defects caused by the inclination of the opening 130H can be prevented.
[0073] In addition, in the etching process for forming the opening 130H having a relatively high aspect ratio, a circuit path to the substrate 110 may be provided to the plate electrode PE through the first unit plug CC1 connected to the bottom surface of the plate electrode PE, and electrical damage (such as arc discharge) to the plate electrode PE that may occur due to the collision of plasma or ions used during the etching process can be prevented. Therefore, the semiconductor device 100 may have excellent electrical performance.
[0074] Figure 7 and Figure 8 is a cross-sectional view of the semiconductor device 100A according to an embodiment. Figure 9 is shownFigure 7 An enlarged view of region CX1. Figure 10 shows Figure 7 An enlarged view of region CX2.
[0075] Referring to Figures 7 to 10 , the capacitor structure CAP may include a plate electrode PEA and a vertical structure VSA. The vertical structure VSA may include a first electrode 142A including a plurality of openings 142H, a capacitor dielectric layer 144A disposed in the openings 142H of the first electrode 142A, and a plurality of second electrodes 146A disposed in the openings 142H of the first electrode 142A.
[0076] In an embodiment, the plate electrode PEA and the first electrode 142A may be integrally formed with each other. For example, the plate electrode PEA may include the same material as the first electrode 142A. In an embodiment, the plate electrode PEA and the first electrode 142A may include Si, SiGe, W, WN, Ti, TiN, or a combination thereof.
[0077] In an embodiment, the first electrode 142A may have a relatively large height, and an etching process for forming the plurality of openings 142H having a relatively high aspect ratio in the first electrode 142A may be performed. In this case, the openings 142H may be formed to a depth that does not completely penetrate the first electrode 142A, and a portion of the first electrode 142A located at a lower vertical level than the openings 142H may be referred to as the plate electrode PEA.
[0078] In an embodiment, the capacitor dielectric layer 144A may be conformally disposed on the inner walls of the openings 142H and also on the upper surface of the first electrode 142A. The second electrodes 146A may be disposed on the capacitor dielectric layer 144A within each opening 142H.
[0079] In an embodiment, in the etching process for forming the openings 142H having a relatively high aspect ratio, a circuit path to the substrate 110 may be provided to the plate electrode PEA through a first unit plug CC1 connected to the bottom surface of the plate electrode PEA, and electrical damage (such as arc discharge) to the plate electrode PEA, which may occur due to collisions of plasma or ions used during the etching process, may be prevented. Accordingly, the semiconductor device 100A may have excellent electrical performance.
[0080] Figure 11 is a cross-sectional view of a semiconductor device 100B according to an embodiment.
[0081] Referring to Figure 11, in each opening 132H of the trench-molded insulating layer 132, two active semiconductor layers AP may be spaced apart from each other in the second horizontal direction Y. Each of the two active semiconductor layers AP may have an L-shaped vertical cross-section and may have a mirror-symmetric structure with respect to each other; for example, the active semiconductor layer AP disposed on the first sidewall of each opening 132H may be spaced apart from the active semiconductor layer AP disposed on the second sidewall of each opening 132H, and the first buried insulating layer 152 may be disposed between one active semiconductor layer AP and the other active semiconductor layer AP.
[0082] Figures 12 to 15 , Figure 16A , Figure 16B , Figure 17A , Figure 17B , Figure 18 , Figure 19A , Figure 19B , Figure 20A , Figure 20B , Figure 21A and Figure 21B schematically shows a method of manufacturing a semiconductor device 100 according to an embodiment. Figures 12 to 15 , Figure 16A , Figure 17A , Figure 18 , Figure 19A , Figure 20A and Figure 20B are respectively cross-sectional views of the semiconductor device taken along the line A1-A1 of Figure 2 , Figure 16B is an enlarged view showing the region CX2 of Figure 16A , Figure 17B , Figure 19B , Figure 20B and Figure 21B are respectively cross-sectional views of the semiconductor device taken along the line A2-A2 of Figure 2 .
[0083] Referring to Figure 12 , an active region AC may be formed in the substrate 110, and the peripheral circuit transistors 120 may be formed at the active region AC. For example, the peripheral circuit transistors 120 may include gate electrodes 120G, gate insulating layers 120I, and source / drain regions 120S.
[0084] Then, peripheral circuit lines 122 and peripheral circuit contacts 124 electrically connected to the substrate 110 and the peripheral circuit transistors 120 may be formed, and a peripheral circuit insulating layer 126 covering the peripheral circuit lines 122 and the peripheral circuit contacts 124 may be formed on the substrate 110. The peripheral circuit insulating layer 126 may be formed using an oxide layer, a nitride layer, a low-k dielectric layer, or a combination thereof.
[0085] Referring toFigure 13 The isolation insulating layer 128 may be formed on the peripheral circuit insulating layer 126. The isolation insulating layer 128 may be formed using an oxide layer, a nitride layer, a low-k dielectric layer, or a combination thereof.
[0086] A mask pattern may be formed on the isolation insulating layer 128, and a portion of the isolation insulating layer 128 may be removed by using the mask pattern as an etching mask to form a first unit plug hole CC1H. The first unit plug hole CC1H may penetrate the isolation insulating layer 128, and the uppermost peripheral circuit line 122_U may be exposed at the bottom of the first unit plug hole CC1H.
[0087] In an embodiment, during the process of removing a portion of the isolation insulating layer 128, the upper portion of the first unit plug hole CC1H may be exposed to the etching atmosphere for a longer period of time. For example, the first unit plug hole CC1H may have slanted sidewalls such that the width of the upper portion of the first unit plug hole CC1H is greater than the width of the bottom portion of the first unit plug hole CC1H.
[0088] Then, the first unit plug CC1 may be formed by filling the interior of the first unit plug hole CC1H with a conductive material. The bottom surface of the first unit plug CC1 may be in contact with the uppermost peripheral circuit line 122_U.
[0089] In an embodiment, the first unit plug CC1 may include a first end CC1a disposed close to the peripheral circuit transistor 120 and a second end CC1b opposite the first end CC1a. The width of the second end CC1b of the first unit plug CC1 may be greater than the width of the first end CC1a of the first unit plug CC1.
[0090] Refer to Figure 14 The plate electrode PE may be formed on the isolation insulating layer 128 and the first unit plug CC1. In an embodiment, the plate electrode PE may include Si, SiGe, W, WN, Ti, TiN, or a combination thereof.
[0091] Then, the capacitor molding insulating layer 130 may be formed on the plate electrode PE. In an embodiment, the capacitor molding insulating layer 130 may be formed using silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof. In an embodiment, the capacitor molding insulating layer 130 may have a stacked structure that includes at least two molding layers and a support layer disposed between the at least two molding layers. The capacitor molding insulating layer 130 may have a relatively large height.
[0092] Refer to Figure 15, a mask pattern may be formed on the capacitor molded insulating layer 130, and a part of the capacitor molded insulating layer 130 may be removed by using the mask pattern as an etching mask, thereby forming a plurality of openings 130H.
[0093] The openings 130H may penetrate the capacitor molded insulating layer 130 and may be formed to a depth at which the upper surface of the plate electrode PE is exposed. The openings 130H may have a relatively high aspect ratio. In an embodiment, the process of forming the openings 130H may include any one of a plasma etching process, a reactive ion etching process, and a dry etching process.
[0094] In an embodiment, in the etching process for forming the openings 130H, a circuit path to the substrate 110 may be provided to the plate electrode PE through the first unit plug CC1 connected to the plate electrode PE, and electrical damage (such as arc discharge) to the plate electrode PE, which may occur due to the collision of plasma or ions used during the etching process, may be prevented.
[0095] In addition, in a semiconductor device according to a comparative example, a plurality of openings need to be aligned with the landing pads, and in this case, due to the inclination of the openings, defects such as connection or communication between the openings and adjacent landing pads may occur. Therefore, the difficulty of the process of aligning the openings with their corresponding landing pads may be high. However, in an embodiment, although the openings 130H are inclined during the etching process for forming the openings 130H, the upper surface of the plate electrode PE may be exposed at the bottom of the openings 130H, and thus, the difficulty of the etching process may be reduced.
[0096] Referring to Figure 16A and Figure 16B , a vertical structure VS may be formed in the openings 130H.
[0097] In an embodiment, the vertical structure VS may be formed by sequentially forming a first electrode 142, a capacitor dielectric layer 144, and a second electrode 146 in the openings 130H.
[0098] In an embodiment, an etch stop layer 131 may be additionally formed on the capacitor molded insulating layer 130, the first electrode 142 may be formed on the inner walls of the openings 130H and the upper surface of the capacitor molded insulating layer 130, and a part of the first electrode 142 (for example, the part of the first electrode 142 disposed on the upper surface of the capacitor molded insulating layer 130) may be removed by a planarization process until the upper surface of the etch stop layer 131 is exposed. Therefore, the first electrode 142 may have a cylindrical shape with a closed bottom, and the bottom surface of the first electrode 142 may contact the upper surface of the plate electrode PE.
[0099] Then, landing pads LP can be formed on the vertical structure VS, respectively. For example, a conductive layer can be formed on the capacitor molding insulating layer 130 to connect to the second electrode 146, and the conductive layer can be patterned to form landing pads LP respectively located on the second electrode 146.
[0100] Then, a landing pad isolation insulating layer LPI surrounding the sidewalls of the landing pads LP can be formed on the capacitor molding insulating layer 130.
[0101] Referring Figure 17A and Figure 17B , unit transistors CTR can be formed on the landing pads LP, respectively.
[0102] In an embodiment, a channel molding insulating layer 132 can be formed on the landing pads LP and the landing pad isolation insulating layer LPI, and then a part of the channel molding insulating layer 132 can be removed to form a plurality of molding openings 132H extending in the first horizontal direction X.
[0103] In each molding opening 132H, a unit transistor CTR including an active semiconductor layer AP, a gate insulating layer GI, and a word line WL can be formed. In an embodiment, the active semiconductor layer AP can have a U-shaped vertical cross-section and can include a horizontal extension APH ( Figure 5 ) contacting the landing pad LP and a vertical extension APV ( Figure 5 ) contacting the channel molding insulating layer 132. The gate insulating layer GI can be disposed on the upper surface of the horizontal extension APH of the active semiconductor layer AP and the sidewalls of the vertical extension APV. The word line WL can face the vertical extension APV of the active semiconductor layer AP, with the gate insulating layer GI therebetween.
[0104] In an embodiment, a buried insulating layer 134a can be formed on the isolation insulating layer 128 to cover the sidewalls of the plate electrode PE and the sidewalls of the channel molding insulating layer 132. The buried insulating layer 134a is a single layer, but according to requirements or design preferences, the buried insulating layer 134a can have a stacked structure including a plurality of insulating layers.
[0105] In an embodiment, before the process of forming the word line WL, a part of the buried insulating layer 134a and a part of the isolation insulating layer 128 can be removed to form a second unit plug hole CC2H, and a second unit plug CC2 filling the second unit plug hole CC2H can be formed.
[0106] For example, the upper surface of the second unit plug CC2 can contact the bottom surface of the word line WL, and the bottom surface of the second unit plug CC2 can contact the upper surface of the uppermost peripheral circuit line 122_U. The second unit plug CC2 can electrically connect the word line WL to the peripheral circuit transistor 120 through the peripheral circuit line 122.
[0107] In an embodiment, during the process of removing a part of the buried insulating layer 134a, the upper portion of the second unit plug hole CC2H can be exposed to the etching atmosphere for a longer period of time. For example, the second unit plug hole CC2H can have inclined sidewalls such that the upper width of the second unit plug hole CC2H is greater than the bottom width of the second unit plug hole CC2H.
[0108] The second unit plug CC2 can include a first end CC2a arranged close to the peripheral circuit transistor 120 and a second end CC2b opposite to the first end CC2a. The width of the second end CC2b of the second unit plug CC2 can be greater than the width of the first end CC2a of the second unit plug CC2.
[0109] Referring to Figure 18 , a part of the buried insulating layer 134a and a part of the isolation insulating layer 128 can be removed to form a third unit plug hole CC3H.
[0110] In an embodiment, during the process of removing a part of the buried insulating layer 134a, the upper portion of the third unit plug hole CC3H can be exposed to the etching atmosphere for a longer period of time. For example, the third unit plug hole CC3H can have inclined sidewalls such that the upper width of the third unit plug hole CC3H is greater than the bottom width of the third unit plug hole CC3H.
[0111] Referring to Figure 19A and Figure 19B , a third unit plug CC3 filling the third unit plug hole CC3H can be formed.
[0112] The third unit plug CC3 can include a first end CC3a arranged close to the peripheral circuit transistor 120 and a second end CC3b opposite to the first end CC3a. The width of the second end CC3b of the third unit plug CC3 can be greater than the width of the first end CC3a of the third unit plug CC3.
[0113] Then, a bit line BL can be formed on the cell transistor CTR. In the edge portion of the memory cell array, the bit line BL can be electrically connected to the third unit plug CC3. For example, the upper surface of the third unit plug CC3 can contact the bottom surface of the bit line BL. The third unit plug CC3 can electrically connect the bit line BL to the peripheral circuit transistor 120 through the peripheral circuit line 122.
[0114] With reference to Figure 20A and Figure 20B a buried insulating layer 134b covering the bit line BL can be formed on the buried insulating layer 134a, and a part of the buried insulating layer 134a, a part of the buried insulating layer 134b, and a part of the isolation insulating layer 128 can be removed to form a peripheral plug hole PC1H. The buried insulating layer 134a and the buried insulating layer 134b can be collectively referred to as a mask insulating layer 134.
[0115] Then, with reference to Figure 21A and Figure 21B a peripheral plug PC1 filling the peripheral plug hole PC1H can be formed.
[0116] The peripheral plug PC1 can electrically connect the upper wiring layer 162 ( Figure 3 ) to the peripheral circuit transistor 120 through the peripheral circuit line 122.
[0117] Returning to the reference Figure 3 and Figure 4 the upper wiring layer 162 and the upper via 164 can be formed on the buried insulating layer 134b, and an upper insulating layer 166 covering the upper wiring layer 162 and the upper via 164 can be formed.
[0118] The semiconductor device 100 can be completed by the above process.
[0119] According to an embodiment, in the etching process for forming the opening 130H having a relatively high aspect ratio, the plate electrode PE can be exposed at the bottom of the opening 130H, and thus, the difficulty of the process for forming the opening 130H can be reduced.
[0120] In addition, in the etching process, a circuit path to the substrate 110 can be provided to the plate electrode PE through the first unit plug CC1 connected to the bottom surface of the plate electrode PE, and an electrical damage (e.g., arc discharge) to the plate electrode PE, which may occur due to the collision of plasma or ions used during the etching process, can be prevented. Therefore, the semiconductor device 100 can have excellent electrical performance.
[0121] Figure 22 、 Figure 23 、 Figure 24A 、 Figure 24B 、 Figure 25A and Figure 25B schematically show a method of manufacturing a semiconductor device 100A according to an embodiment.
[0122] The peripheral circuit transistor 120 and the first unit plug CC1 can be formed on the substrate 110 by performing the processes described above with reference to Figure 12 and Figure 13 .
[0123] Referring to Figure 22 , the first electrode 142A may be formed on the first unit plug CC1 and the isolation insulating layer 128. The first electrode 142A may include Si, SiGe, W, WN, Ti, TiN, or a combination thereof.
[0124] Referring to Figure 23 , a mask pattern may be formed on the first electrode 142A, and a portion of the first electrode 142A may be removed by using the mask pattern as an etching mask to form an opening 142H.
[0125] The opening 142H may have a relatively high aspect ratio. In an embodiment, the process of forming the opening 142H may include any one of a plasma etching process, a reactive ion etching process, and a dry etching process.
[0126] The opening 142H may be formed to a depth that does not completely penetrate the first electrode 142A, and a portion of the first electrode 142A located at a lower vertical level than the opening 142H may be used as (and referred to as) a plate electrode PEA.
[0127] In an embodiment, in the process of forming the opening 142H, a circuit path to the substrate 110 may be provided through the first unit plug CC1 connected to the first electrode 142A or the plate electrode PEA, and electrical damage (such as an arc discharge) to the first electrode 142A or the plate electrode PEA that may occur due to collisions of plasma or ions used during the etching process may be prevented.
[0128] Referring to Figure 24A and Figure 24B , a capacitor dielectric layer 144A may be formed on the inner wall of the opening 142H. The capacitor dielectric layer 144A may be conformally disposed on the inner wall of the opening 142H to a thickness such that the interior of the opening 142H is not completely filled. The capacitor dielectric layer 144A may also be disposed on the upper surface of the first electrode 142A.
[0129] Then, a second electrode 146A may be formed in the opening 142H, respectively. The second electrode 146A may be formed in a column shape to fill the interior of the opening 142H.
[0130] Then, a landing pad LP may be formed on the second electrode 146A, and a landing pad isolation insulating layer LPI may be formed around the sidewall of the landing pad LP.
[0131] Referring to Figure 25A and Figure 25B, a unit transistor CTR may be formed on a landing pad LP, and a buried insulating layer 134a covering sidewalls of the vertical structure VSA may be formed. Further, a bit line BL may be formed on the unit transistor CTR. Further, by removing a part of the buried insulating layer 134a, a second unit plug CC2 connected to a word line WL may be formed, and a third unit plug CC3 connected to the bit line BL may be formed.
[0132] Return reference Figure 7 and Figure 8 , the semiconductor device 100A may be completed by forming a peripheral plug PC1, an upper wiring layer 162, an upper via 164, and an upper insulating layer 166.
[0133] According to an embodiment, in an etching process of forming an opening having a relatively high aspect ratio, since the plate electrode is exposed at the bottom of the opening, the difficulty of the process of forming the opening may be reduced. Further, during the etching process, a circuit path to the substrate may be provided to the plate electrode through a first unit plug connected to the bottom surface of the plate electrode, and electrical damage (such as arc discharge) to the plate electrode, which may occur due to collision of plasma or ions used during the etching process, may be prevented. Accordingly, the semiconductor device may have excellent electrical performance.
[0134] Although the inventive concept has been specifically shown and described with reference to embodiments thereof, it will be understood that various changes in form and detail may be made therein without departing from the scope of the appended claims.
[0135] This application is based on and claims priority to Korean Patent Application No. 10-2023-0197695, filed with the Korean Intellectual Property Office on December 29, 2023, the disclosure of which is incorporated herein by reference in its entirety.
Claims
1. A semiconductor device, comprising: Peripheral circuits, on the substrate; a capacitor structure on the peripheral circuit and comprising a plate electrode and a vertical structure extending on the plate electrode in a vertical direction perpendicular to an upper surface of the substrate, wherein the vertical structure comprises a first electrode, a second electrode, and a capacitor dielectric layer between the first electrode and the second electrode; a cell transistor at a higher vertical level than the capacitor structure and electrically connected to the capacitor structure; a first unit plug extending in the vertical direction between the plate electrode and the peripheral circuit and adjacent to and electrically connected to a bottom surface of the plate electrode; as well as a second cell plug extending in the vertical direction between the cell transistor and the peripheral circuit, wherein the first unit plug includes a first end adjacent to the peripheral circuit and a second end opposite to the first end, and The width of the second end of the first unit plug is greater than the width of the first end of the first unit plug.
2. The semiconductor device according to claim 1, wherein an upper surface of the second end portion of the first cell plug contacts the bottom surface of the plate electrode, wherein the second unit plug comprises a first end adjacent to the peripheral circuit and a second end opposite to the first end of the second unit plug, and The width of the second end of the second unit plug is greater than the width of the first end of the second unit plug.
3. The semiconductor device according to claim 1, wherein the unit transistor comprises: an active semiconductor layer extending in the vertical direction at a higher vertical level than the capacitor structure and comprising a first end and a second end, wherein the first end of the active semiconductor layer is adjacent to and electrically connected to the second electrode; and word lines on sidewalls of the active semiconductor layer, and The second cell plug is electrically connected to the word line.
4. The semiconductor device according to claim 3, wherein the active semiconductor layer includes a vertical portion extending in the vertical direction and a horizontal portion connected to the vertical portion and extending in the horizontal direction, wherein the horizontal portion includes the first end portion of the active semiconductor layer, wherein an upper portion of the vertical portion includes the second end portion of the active semiconductor layer, and The semiconductor device further includes a landing pad between a bottom surface of the horizontal portion and the second electrode.
5. The semiconductor device according to claim 3, further comprising: a bit line on the second end of the active semiconductor layer; and a third cell plug extending in the vertical direction between the bit line and the peripheral circuit and electrically connecting the bit line to the peripheral circuit, wherein the third unit plug includes a first end portion adjacent to the peripheral circuit and a second end portion opposite to the first end portion of the third unit plug, and The width of the second end portion of the third unit plug is greater than the width of the first end portion of the third unit plug.
6. The semiconductor device according to claim 1, further comprising: a wiring layer at a higher vertical level than the cell transistor; and a peripheral plug extending in the vertical direction between the wiring layer and the peripheral circuit and electrically connecting the wiring layer to the peripheral circuit, wherein the peripheral plug comprises a first end portion adjacent to the peripheral circuit and a second end portion opposite to the first end portion of the peripheral plug, and The width of the second end of the peripheral plug is greater than the width of the first end of the peripheral plug.
7. The semiconductor device according to claim 1, further comprising a mold insulating layer on the plate electrode and including a plurality of openings extending in the vertical direction, wherein the vertical structure is in each of the plurality of openings.
8. The semiconductor device according to claim 7, wherein the first electrode is on an inner wall of each of the plurality of openings and in contact with the mold insulating layer, wherein the capacitor dielectric layer is formed on an inner side wall of the first electrode and on an upper surface of the mold insulating layer in each of the plurality of openings, and Wherein the second electrode is within each of the plurality of openings.
9. The semiconductor device according to claim 7, wherein the cell transistor comprises an active semiconductor layer extending in the vertical direction at a higher vertical level than the capacitor structure and comprising a first end and a second end, wherein the first end of the active semiconductor layer is adjacent to and electrically connected to the second electrode, and The active semiconductor layer comprises zinc tin oxide (Zn x Sn y O), indium zinc oxide (In x Zn y O), zinc oxide (ZnO x ), Indium Gallium Zinc Oxide (In x Ga y Zn z O), Indium Gallium Silicon Oxide (In x Ga y Si z O), indium tungsten oxide (In x W y O), indium oxide (In x O), tin oxide (Sn x O), titanium oxide (Ti x O), zinc nitride (Zn x ON z )、Mg-Zn-Oxide(Mg x Zn y O), zirconium indium zinc oxide (Zr x In y Zn z O), hafnium indium zinc oxide (Hf x In y Zn z O), tin indium zinc oxide (Sn x In y Zn z O), aluminum tin indium zinc oxide (Al x Sn y In z Zn a O), silicon indium zinc oxide (Si x In y Zn z O), aluminum zinc tin oxide (Al x Zn y Sn z O), gallium zinc tin oxide (Ga x Zn y Sn z O) and zirconium zinc tin oxide (Zr x Zn y Sn z O) at least one. 10 . The semiconductor device according to claim 1 , wherein a height of the second cell plug in the vertical direction is greater than a height of the vertical structure in the vertical direction.
11. A semiconductor device comprising: Peripheral circuits, on the substrate; a capacitor structure on the peripheral circuit and comprising a plate electrode and a plurality of vertical structures extending on the plate electrode in a vertical direction perpendicular to an upper surface of the substrate, wherein each of the plurality of vertical structures comprises a first electrode, a second electrode, and a capacitor dielectric layer between the first electrode and the second electrode; a molded insulating layer on the plate electrode and including a plurality of openings extending in the vertical direction, wherein the plurality of vertical structures are respectively in the plurality of openings; an active semiconductor layer on the mold insulating layer and electrically connected to the second electrode; A word line on a sidewall of the active semiconductor layer; a bit line on the upper surface of the active semiconductor layer; a first unit plug extending in the vertical direction between the plate electrode and the peripheral circuit and adjacent to and electrically connected to a bottom surface of the plate electrode; as well as A second cell plug extends in the vertical direction between the word line and the peripheral circuit and electrically connects the word line to the peripheral circuit.
12. The semiconductor device according to claim 11, wherein the first unit plug includes a first end adjacent to the peripheral circuit and a second end opposite to the first end, and The width of the second end of the first unit plug is greater than the width of the first end of the first unit plug.
13. The semiconductor device according to claim 11, wherein the second unit plug includes a first end adjacent to the peripheral circuit and a second end opposite to the first end, and The width of the second end of the second unit plug is greater than the width of the first end of the second unit plug.
14. The semiconductor device according to claim 11, further comprising a third cell plug extending in the vertical direction between the bit line and the peripheral circuit and electrically connecting the bit line to the peripheral circuit, wherein the third unit plug includes a first end adjacent to the peripheral circuit and a second end opposite to the first end, and The width of the second end portion of the third unit plug is greater than the width of the first end portion of the third unit plug.
15. The semiconductor device according to claim 11, wherein the active semiconductor layer includes a vertical portion extending in the vertical direction and a horizontal portion connected to the vertical portion and extending in the horizontal direction, The semiconductor device further includes a landing pad between a bottom surface of the horizontal portion and the second electrode.
16. The semiconductor device according to claim 15, wherein in each of the plurality of openings of the mold insulating layer, the second electrode extends in the vertical direction, wherein in each of the plurality of openings in the mold insulating layer, the capacitor dielectric layer surrounds a side wall and a bottom surface of the second electrode, wherein in each of the plurality of openings in the mold insulating layer, the first electrode surrounds the sidewall and the bottom surface of the capacitor dielectric layer, wherein a bottom surface of the first electrode contacts an upper surface of the plate electrode, and The upper surface of the second electrode contacts the bottom surface of the landing pad.
17. The semiconductor device according to claim 16, wherein the first electrode has a circular horizontal cross-section, and The second electrode has a circular horizontal cross-section.
18. A semiconductor device comprising: Peripheral circuits, on the substrate; a capacitor structure on the peripheral circuit and comprising a plate electrode and a plurality of vertical structures extending on the plate electrode in a vertical direction perpendicular to an upper surface of the substrate, wherein each of the plurality of vertical structures comprises a first electrode electrically connected to the plate electrode and extending in the vertical direction, a second electrode on a sidewall of the first electrode, and a capacitor dielectric layer between the first electrode and the second electrode; molding an insulating layer on the plate electrode and around sidewalls of the plurality of vertical structures; an active semiconductor layer extending in the vertical direction at a higher vertical level than the capacitor structure and comprising a first end and a second end, wherein the first end is adjacent to and electrically connected to the second electrode; A word line on a sidewall of the active semiconductor layer; a bit line adjacent to and electrically connected to the second end of the active semiconductor layer; a wiring layer at a higher vertical level than the bit lines; a first unit plug extending in the vertical direction between the plate electrode and the peripheral circuit and adjacent to and electrically connected to a bottom surface of the plate electrode; a second cell plug extending in the vertical direction between the word line and the peripheral circuit and electrically connecting the word line to the peripheral circuit; a third cell plug extending in the vertical direction between the bit line and the peripheral circuit and electrically connecting the bit line to the peripheral circuit; as well as A peripheral plug extends in the vertical direction between the wiring layer and the peripheral circuit and electrically connects the wiring layer to the peripheral circuit.
19. The semiconductor device according to claim 18, wherein the first unit plug includes a first end portion adjacent to the peripheral circuit and a second end portion opposite to the first end portion of the first unit plug, wherein the width of the second end of the first unit plug is greater than the width of the first end of the first unit plug, wherein the peripheral plug comprises a first end portion adjacent to the peripheral circuit and a second end portion opposite to the first end portion of the peripheral plug, and The width of the second end of the peripheral plug is greater than the width of the first end of the peripheral plug.
20. The semiconductor device according to claim 18, wherein the second unit plug includes a first end adjacent to the peripheral circuit and a second end opposite to the first end of the second unit plug, wherein the width of the second end of the second unit plug is greater than the width of the first end of the second unit plug, wherein the third unit plug includes a first end portion adjacent to the peripheral circuit and a second end portion opposite to the first end portion of the third unit plug, and The width of the second end portion of the third unit plug is greater than the width of the first end portion of the third unit plug.