Three-dimensional memory

Abstract

The invention provides a three-dimensional memory which comprises a step structure, the step structure is provided with a plurality of steps, each step comprises at least one gate layer and at least one dielectric layer which are alternately stacked from top to bottom, the edge of at least one gate layer forms the top surface of the step, a conductive layer is formed on the top surface of the step, and the dielectric layer is formed on the top surface of the step. And the conductive layer is connected with a contact part. Compared with the prior art, due to the fact that the grid layer is covered with the conducting layer, the thickness of the grid layer is larger, the grid layer is not prone to being etched through, and the risk of etching punch-through is greatly reduced.

Description

[0001] This application is a divisional application of the patent application 201811108506.9 with the application date of September 21, 2018 and the invention title of "Three-Dimensional Memory". Technical Field

[0002] The present invention mainly relates to the field of semiconductor manufacturing, and particularly relates to a three-dimensional memory. Background Art

[0003] In order to overcome the limitations of two-dimensional storage devices, the industry has developed storage devices with a three-dimensional (3D) structure to increase the integration density by arranging memory cells three-dimensionally on a substrate.

[0004] In a three-dimensional storage device such as a 3D NAND flash memory, a storage array may include a core area and a staircase area. The staircase area is used to lead out contact portions for the gate layers in each layer of the storage array. These gate layers serve as word lines of the storage array and perform operations such as programming, erasing, and reading.

[0005] In the manufacturing process of 3D NAND flash memory, contact holes are etched on the staircase structures of each level in the staircase area, and then the contact holes are filled to lead out the electrical signals of the gate layers. In the actual production process, due to the large number of staircase layers in 3D-NAND flash memory, in the contact hole etching step, in order to ensure that the lower staircase can be successfully led out, the upper staircase is easily over-etched, resulting in punch through, causing short circuits between the gate metal layers and reducing the product yield.

[0006] To solve the above problems, multiple light irradiations and etching operations are often required to reduce the depth difference during each etching. Summary of the Invention

[0007] The technical problem to be solved by the present invention is a three-dimensional memory, which can overcome problems such as etching defects in the word line connection area, and there is no need to perform multiple light irradiations and etching.

[0008] To solve the above technical problem, the present invention provides a three-dimensional memory, including a staircase structure, the staircase structure having a plurality of steps, each step including at least one gate layer and at least one dielectric layer alternately stacked from top to bottom, the edge of at least one of the gate layers constituting the top surface of the step, a conductive layer being formed on the top surface of the step, and a contact portion being connected to the conductive layer.

[0009] In an embodiment of the present invention, the projections of the conductive layers of adjacent steps on the bottom surface of the stacked structure are connected end to end.

[0010] In an embodiment of the present invention, the conductive layer has the same material as the gate layer.

[0011] In one embodiment of the present invention, the materials of the conductive layer and the gate layer are both tungsten or cobalt.

[0012] In one embodiment of the present invention, the thickness of the conductive layer is 10 - 100 nm.

[0013] In one embodiment of the present invention, the method for forming the conductive layer on the top surface of the step is physical vapor deposition, metal sputtering or metal evaporation.

[0014] In one embodiment of the present invention, the stepped structure further includes a virtual channel hole penetrating through the stepped structure.

[0015] In one embodiment of the present invention, the method for connecting the contact part to the conductive layer includes: covering an insulating layer on the stepped structure, etching the insulating layer covered on the stepped structure, so as to form a plurality of contact holes exposing the gate layer on the top surfaces of each step of the stepped structure.

[0016] In one embodiment of the present invention, covering the insulating layer on the stepped structure further includes planarizing the insulating layer.

[0017] In one embodiment of the present invention, peripheral circuit devices are further included below the stepped structure.

[0018] Compared with the prior art, the present invention has the following advantages: The present invention provides a three-dimensional memory. The semiconductor device of the three-dimensional memory includes a core area and a stepped area. The stepped area has a stepped structure. The stepped structure has a plurality of steps. Each step includes at least one gate layer and at least one dielectric layer alternately stacked from top to bottom. The edge of at least one of the gate layers constitutes the top surface of the step. A conductive layer is formed on the top surface of the step, and a contact part is connected to the conductive layer. It can be seen that since the gate layer is covered with a conductive layer, the thickness of the gate layer is thicker and it is not easily etched through. Therefore, the risk of etching through is greatly reduced. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] To make the above objects, features and advantages of the present invention more obvious and understandable, the following detailed description of the specific embodiments of the present invention is provided in conjunction with the accompanying drawings, wherein:

[0020] Figure 1A-1F is a flowchart of a manufacturing method of a three-dimensional memory.

[0021] Figure 2A-2B is a schematic structural diagram of a three-dimensional memory.

[0022] Figure 3 is a flowchart of a manufacturing method of a three-dimensional memory according to an embodiment of the present invention.

[0023] Figure 4A-4E It is a cross-sectional schematic diagram of an exemplary process of a method for manufacturing a three-dimensional memory according to an embodiment of the present invention.

[0024] Figure 5A-5D It is an exemplary process of a planarization insulating layer according to an embodiment of the present invention.

[0025] Figure 6 It is a schematic structural diagram of a three-dimensional memory according to an embodiment of the present invention. Detailed implementation manners

[0026] To make the above objects, features and advantages of the present invention more obvious and understandable, the following detailed description of the specific implementation manners of the present invention is provided in conjunction with the accompanying drawings.

[0027] In the following description, many specific details are set forth to facilitate a thorough understanding of the present invention. However, the present invention may be implemented in other ways different from those described herein, and thus the present invention is not limited by the specific embodiments disclosed below.

[0028] As shown in the present application and the claims, unless the context clearly indicates otherwise, words such as "a", "an", "one" and / or "the" are not specifically singular and may also include the plural. Generally speaking, the terms "comprising" and "including" only indicate the inclusion of the clearly identified steps and elements, and these steps and elements do not constitute an exclusive list. The method or device may also include other steps or elements.

[0029] When detailing the embodiments of the present invention, for ease of explanation, the cross-sectional views showing the device structure will be enlarged locally out of proportion and the schematic diagrams are only examples and should not limit the scope of protection of the present invention here. In addition, in actual manufacturing, three-dimensional spatial dimensions of length, width and depth should be included.

[0030] For convenience of description, spatial relationship terms such as "beneath", "below", "lower", "under", "above", "on" etc. may be used herein to describe the relationship of one element or feature shown in the drawings with other elements or features. It will be understood that these spatial relationship terms are intended to include other directions of the device in use or operation in addition to the directions depicted in the drawings. For example, if the device in the drawings is flipped, the direction of the element described as "beneath" or "below" or "under" other elements or features will be changed to "above" the other elements or features. Thus, the exemplary terms "below" and "under" can include both upward and downward directions. The device may also have other orientations (rotated 90 degrees or in other directions), and thus the spatial relationship description terms used herein should be interpreted accordingly. In addition, it will also be understood that when a layer is referred to as being "between" two layers, it can be the only layer between the two layers, or there may be one or more intervening layers.

[0031] As introduced in the background art, in a three-dimensional storage device such as a 3D NAND flash memory, a storage array may include a core area and a stepped area. The stepped area is used to lead out contact portions for the gate layers in each layer of the storage array. These gate layers serve as word lines of the storage array and perform operations such as programming, erasing, and reading.

[0032] During the manufacturing process of 3D NAND flash memory, contact holes are etched on the stepped structures of each level of the stepped area, and then the contact holes are filled to lead out the electrical signals of the gate layer. In the actual production process, due to the large number of stepped layers in 3D-NAND flash memory, in the contact hole etching step, in order to ensure that the lower stepped layers can be successfully led out, the upper stepped layers are prone to over-etching (OverEtch), resulting in punch-through, causing short circuits between the gate metal layers and reducing the product yield.

[0033] Figure 1A-1F It is a flowchart of a manufacturing method for a three-dimensional memory. This manufacturing method mainly etches contact holes on each level of the stepped area. The process of forming the contact holes includes forming a stacked structure 110 having alternately stacked dummy gate layers 101 and dielectric layers 102 as shown in Figure 1A , forming a stepped structure at the edge of the stacked structure 110 as shown in Figure 1B , covering an insulating layer 103 on the stacked structure 110 as shown in Figure 1C , replacing the dummy gate layer 101 with a gate layer 104 as shown in Figure 1D , and finally forming contact holes 106 through an etching mask 105 and filling the contact holes 106 to form contact portions 107 as shown in Figure 1E and 1F respectively.

[0034] As Figure 1D shown, the gate layer 104 in the stepped area of this method is relatively thin and is prone to over-etching. As Figure 2A shown, due to the large depth difference during the etching of the contact holes 106, when the contact holes are just etched in place at the deepest part, the contact holes at the shallowest part will be etched through and cause a short circuit. In order to avoid over-etching of the contact holes at the shallowest part, the vertical through holes corresponding to the metal gate layers in different regions are usually etched in segments, as Figure 2B shown. This method requires multiple photolithography and etching steps, with high cost and time cost, seriously affecting the mass production rate, and the more layers the storage unit stack has, the more photolithography and etching processes are required.

[0035] Figure 3 It is a flowchart of a manufacturing method for a three-dimensional memory according to an embodiment of the present invention. Figure 4A-4EThis is a cross-sectional schematic diagram of an exemplary process of a method for manufacturing a three-dimensional memory according to an embodiment of the present invention. The following will refer to Figure 3-4E illustrate a method for manufacturing a three-dimensional memory according to this embodiment.

[0036] In step 302, a semiconductor structure is provided.

[0037] This semiconductor structure is at least a part of the structure that will be used in subsequent processes to finally form a three-dimensional storage device. The semiconductor structure may include an array region (array), and the array region may include a core region (core) and a stair-step region (stair step, SS). The core region is the region including memory cells, and the stair-step region is the region including word-line connection circuits. The stair-step region may be located on at least one side of the core region. Viewed from the vertical direction, the array region may have a substrate and a stacked structure. A trench hole array is formed on the stacked structure in the core region, and a dummy trench hole array may be formed on the stacked structure in the stair-step region. The stacked structure includes alternately stacked first material layers and second material layers, and a stair structure is formed at the edge. The stair structure has several layers of steps, and the edge of at least a part of the first material layer constitutes the top surface of the step. The first material layer may be a dummy gate layer or a gate layer. The second material layer may be a dielectric layer. For the sake of simplicity, in the following, an example will be given with the first material layer being a dummy gate layer and the second material layer being a dielectric layer.

[0038] In Figure 4A In the cross-sectional view of the illustrated semiconductor structure 400a, the semiconductor structure 400a may include a stacked structure 410. The stacked structure 410 may include alternately stacked dummy gate layers 410a and dielectric layers 410b. A stair structure is formed at the edge of the stacked structure 410. The stair structure may include several layers of steps, which depends on the number of layers of the three-dimensional storage device to be manufactured (such as 32 layers or 64 layers). Figure 4A Exemplarily shown in [the figure] are 3 steps 411, 412, and 413. Each step includes one or more dielectric layers and one or more dummy gate layers alternately stacked from top to bottom, that is, the dummy gate layers and the dielectric layers are alternately stacked, and the edge of at least one of the dummy gate layers constitutes the top surface of the step. Taking step 412 as an example, it includes a dummy gate layer 412a and a dielectric layer 412b alternately stacked from top to bottom, and the edge of the dummy gate layer 412a constitutes the top surface of the step. It can be understood that step 412 is not limited to the 2 layers exemplified here, but may have other numbers, such as 4 layers, 6 layers or more layers.

[0039] In an embodiment of the present invention, the semiconductor structure 400a may further include a virtual channel hole 420. The virtual channel hole 420 may be formed in the step region and / or the core region. The virtual channel hole 420 vertically penetrates the stacked structure of the semiconductor structure 400a, and is filled with, for example, an insulating material to provide support for the stacked structure. As an exemplary process for forming a virtual channel hole 420, a hard mask, an anti-reflective coating, and a photoresist may be sequentially covered on the stacked structure; then photolithography and etching are performed to form a virtual channel hole; the virtual channel hole is wet cleaned; and the virtual channel hole is filled with an insulating material, such as silicon oxide. The step of forming the virtual channel hole 420 on the stacked structure may be performed before the step structure is formed at the edge of the stacked structure. It is understood that the virtual channel hole 420 does not completely isolate the pseudo gate layer. The virtual channel hole 420 is only a hole-like structure that penetrates a portion of the cross-sectional area of ​​the pseudo gate layer. After the pseudo gate layer is replaced by the gate layer, the control signal can still be transmitted to the core region through the gate layer.

[0040] In an embodiment of the present invention, the material of the dummy gate layer 412 b may be silicon nitride, and the material of the dielectric layer 412 a may be silicon oxide, for example.

[0041] Although an exemplary composition of the initial semiconductor structure is described herein, it is understood that one or more features may be omitted from, replaced by, or added to this semiconductor structure. In addition, the materials of the various layers exemplified are merely exemplary, for example, the pseudo gate layer 412b and the dielectric layer 412a may also be other materials available in a charge storage type (CTF) three-dimensional NAND memory. For example, the pseudo gate layer 412b and the dielectric layer 412a may also be a combination of silicon oxide and (undoped) polysilicon or amorphous silicon, a combination of silicon oxide or silicon nitride and amorphous carbon, etc. For example, the step of forming a virtual channel hole 420 on the stacked structure may be omitted.

[0042] In step 304, at least a portion of at least one of the dielectric layers is removed by etching back.

[0043] In this step, in order to avoid short circuit connection between the conductive layers, at least a portion of at least one of the dielectric layers is removed, so that the side surface of at least one of the dielectric layers is concave relative to the pseudo gate layer thereon. The method of etching back to remove at least a portion of at least one of the dielectric layers may include wet etching, for example, using phosphoric acid as an etchant to etch at least a portion of at least one of the dielectric layers. The thickness of the etched dielectric layer may be the thickness of the dielectric layer in the stacked structure. The depth of etching may be half or less of the width of the virtual channel hole. In some embodiments of the present invention, the step of removing at least a portion of at least one of the dielectric layers may be omitted, and the conductive layer may be directly covered on the top surface of the step.

[0044] exist Figure 4BIn the cross-sectional view of the exemplary semiconductor structure 400b, a portion of the dielectric layer 412b is removed such that the side surface of the dielectric layer 412b is concave with respect to the dummy gate layer 412a thereon. The thickness of the etched dielectric layer 412b (in the vertical direction in the figure) is the thickness of the dielectric layer in the stacked structure. The etching depth (in the horizontal direction in the figure) is half of the width of the virtual channel hole 420. It can be understood that the etching depth can be other values, such as greater than or less than half of the width of the virtual channel hole 420.

[0045] In step 306, a conductive layer covering the top surface of the step and an insulating layer covering the conductive layer are formed.

[0046] In this step, a conductive layer covering the top surface of the step and an insulating layer covering the conductive layer are formed. The conductive layer covers the top surface of the step and is in contact with the dummy gate layer of the stepped structure in the stepped region. The material of the conductive layer can be various conductive materials. In some embodiments of the present invention, the material of the conductive layer is a metal material. Preferably, the material of the conductive layer can be the same as the material of the gate layer. For example, the materials of both the conductive layer and the gate layer are tungsten or cobalt. The method of forming the conductive layer covering the top surface of the step can be Physical Vapor Deposition (PVD), Metal Sputtering, Metal Evaporation, etc. The thickness and morphology of the conductive layer need to ensure that the two dielectric layers above and below it do not adhere. The projections of the conductive layers of adjacent steps are connected end to end on the bottom surface of the stacked structure, that is, the conductive layer is only formed on the horizontal plane and no conductive layer is formed on the side surface, and the adjacent conductive layers are still insulated from each other. The thickness of the conductive layer can be 10 - 100 nm. The morphology of the conductive layer can be flat. The width of the conductive layer can be approximately equal to the width of each step. In some embodiments of the present invention, after forming the conductive layer covering the top surface of the step, wet cleaning, cleaning of the back surface of the wafer and the side surface of the dielectric layer, etc. can also be included to remove a small amount of metal that may be contaminated, facilitating subsequent processes. After forming the conductive layer covering the top surface of the step, an insulating layer covering the conductive layer is formed on the conductive layer. The insulating layer covering the conductive layer includes a planarized insulating layer.

[0047] In Figure 4CIn the cross-section of the semiconductor structure 400c shown, the conductive layer 430 covers the top surface of the step and is in contact with the dummy gate layer of the stepped structure in the stepped region. The material of the conductive layer 430 can be various conductive materials. In some embodiments of the present invention, the material of the conductive layer 430 is a metal material. Preferably, the material of the conductive layer 430 can be the same as the material of the gate layer. For example, the materials of both the conductive layer 430 and the gate layer are tungsten or cobalt. The method of forming the conductive layer covering the top surface of the step can be Physical Vapor Deposition (PVD), Metal Sputtering, Metal Evaporation, etc. The projections of the conductive layers 430 of adjacent steps are connected end to end on the bottom surface of the stacked structure 410, that is, the conductive layer 430 is only formed on the horizontal plane and no conductive layer 430 is formed on the side. The adjacent conductive layers 430 are still insulated from each other. The thickness and morphology of the conductive layer 430 need to ensure that the two dielectric layers above and below it do not adhere. The thickness of the conductive layer 430 can be 50 - 200 nm. The morphology of the conductive layer can be flat. The width of the conductive layer 430 is approximately equal to the width of each step. After forming the conductive layer 430 covering the top surface of the step, wet cleaning, backside cleaning of the wafer and side cleaning of the dielectric layer, etc. can also be included to remove a small amount of metal that may be contaminated, facilitating subsequent processes.

[0048] In Figure 4D In the cross-section of the semiconductor structure 400d shown, after forming the conductive layer 430 covering the top surface of the step, an insulating layer 440 covering the conductive layer 430 is formed on the conductive layer 430. The insulating layer 440 covering the conductive layer 430 includes a planarized insulating layer 440.

[0049] In step 308, a contact structure is formed that passes through the insulating layer and connects to the conductive layer.

[0050] In this step, a contact structure is formed that passes through the insulating layer and connects to the conductive layer. The step of forming the contact structure that passes through the insulating layer and connects to the conductive layer includes etching the insulating layer on the stepped structure to form a plurality of contact holes exposing the gate layer on the top surfaces of the respective steps of the stepped structure at one time, and filling the contact holes to form the contact structure. An insulating material can be first covered on the stepped structure, and then contact holes vertically penetrating the stepped region can be formed by etching in a conventional manner. The contact holes will vertically penetrate the insulating material from the upper surface to reach the first material layer at the top of each stepped structure.

[0051] The method of forming the contact holes is, for example, etching or other known methods, which are not limited herein.

[0052] The first material layer can be a dummy gate layer or a gate layer, and the second material layer can be a dielectric layer. If the first material layer is a gate layer, a contact structure can be directly formed; if the first material layer is a dummy gate layer, the dummy gate layer needs to be replaced with a gate layer. The method of replacing the dummy gate layer with a gate layer includes removing the dummy gate layer to form a gap between the dielectric layers, and forming a gate layer in the gap. The method of removing the dummy gate layer includes wet etching. The etching solution for wet etching can be phosphoric acid. After the dummy gate is removed, a gap is formed between the dielectric layers. A gate layer material is filled into the gap to form a gate layer in the gap. The materials of the gate layer include but are not limited to tungsten and cobalt. Before the steps of removing the dummy gate layer to form a gap between the dielectric layers and forming a gate layer in the gap, a channel hole (Channel Hole, CH) can also be formed in the core region. The method of forming a channel hole in the core region is well known in the art and will not be described in detail here.

[0053] In Figure 4E In the cross-sectional view of the exemplary semiconductor structure 400e shown, an insulating material 440 is covered on each stepped structure, and contact holes are respectively formed through the insulating material 440 to reach the gate layers of each stepped structure. After that, a contact structure 470 can be formed by filling a metal material into the contact holes to provide a conduction path for the gate layers of each stepped structure. The material of the contact structure 470 can be tungsten or cobalt. It can be seen that since a conductive layer is covered on the gate layer, the thickness of the gate layer is thicker and it is not easily etched through, so the risk of etching through is greatly reduced.

[0054] Here, a flowchart is used to illustrate the operations performed by the method according to an embodiment of the present application. It should be understood that the previous operations do not necessarily need to be precisely executed in sequence. On the contrary, various steps can be processed in reverse order or simultaneously. At the same time, other operations can be added to these processes, or one or several operations can be removed from these processes. For example, step 304 can be omitted. After providing the semiconductor structure, a conductive layer covering the top surface of the step and an insulating layer covering the conductive layer can be directly formed.

[0055] For the semiconductor structure formed in the above embodiment, after subsequent conventional steps, a three-dimensional memory device can be obtained. Here, a three-dimensional memory according to an embodiment of the present invention is described with reference to the semiconductor structure formed in this embodiment.

[0056] Figure 5A-5D An exemplary process of planarizing an insulating layer according to an embodiment of the present invention is shown.

[0057] In Figure 5A In the cross-section of the semiconductor structure 500a shown, an insulating layer material 540 is filled into the stepped area, and the core area will also be filled with the insulating layer material 540, resulting in the overall height of the core area being relatively high, forming a high platform with a protruding middle part.

[0058] In Figure 5B In the cross-section of the semiconductor structure 500b shown, before Chemical Mechanical Polishing (CMP), a protective layer 550 can be covered on the surface of the insulating layer 540. The material of the protective layer 550 can be silicon nitride. It can be understood that if the chemical mechanical polishing process is controlled well enough, the protective layer 550 may not be needed. The stepped surface of the core region is also covered with a conductive layer 530, which can serve as a barrier layer for the core region.

[0059] In Figure 5C In the cross-section of the semiconductor structure 500c shown, dry etching is performed on the insulating layer 540 of the core region. As an example, dry etching can be to sequentially cover a hard mask layer, an anti-reflection coating, and a photoresist on the insulating layer, then expose to open the hard mask layer, remove most of the insulating layer in the core region, and stop at the conductive layer 530 that serves as a barrier layer in the core region. In some embodiments of the present invention, the anti-reflection coating material can be silicon oxynitride. In some embodiments of the present invention, after dry etching the insulating layer 540 of the core region, wet cleaning can also be included to facilitate subsequent processes.

[0060] In Figure 5D In the cross-section of the semiconductor structure 500d shown, mechano-chemical polishing is performed, with the core region staying on the conductive layer 430 and the stepped region staying on the protective layer 450. Subsequently, wet etching is performed to remove the protective layer 450 on the surface of the stepped region and the conductive layer 430 on the surface of the core region.

[0061] Thus far, a planarized surface of the insulating layer is formed, and the planarized surface stays above the pseudo-gate layer in the core region.

[0062] Figure 6 Shows a partial structure of a three-dimensional memory 600 according to an embodiment of the present invention. As Figure 6 shown, the three-dimensional memory 600 includes a core region and a stepped region. The stepped region has a stepped structure, the stepped structure has a plurality of steps, each step (such as 611) includes at least one gate layer (such as 611a) and at least one dielectric layer (such as 611b) stacked alternately from top to bottom, the edge of at least one of the gate layers constitutes the top surface of the step, a conductive layer (such as 611c) is formed on the top surface of the step, and a contact portion (such as 620) is connected to the conductive layer.

[0063] In an embodiment of the present invention, the projections of the conductive layers (such as 611c) of adjacent steps are connected end to end on the bottom surface of the stacked structure. In an embodiment of the present invention, the conductive layer (such as 611c) and the gate layer (such as 611a) are made of the same material. In an embodiment of the present invention, the conductive layer (such as 611c) and the gate layer (such as 611a) are both made of tungsten or cobalt. In an embodiment of the present invention, the thickness of the conductive layer (such as 611c) is 10 - 100 nm. In an embodiment of the present invention, the method for forming the conductive layer (such as 611c) on the top surface of the step is physical vapor deposition, metal sputtering or metal evaporation. In an embodiment of the present invention, the stepped structure further includes a virtual channel hole 640 penetrating the stepped structure. In an embodiment of the present invention, the method for connecting the contact part (such as 620) on the conductive layer (such as 611c) includes: covering an insulating layer 630 on the stepped structure, etching the insulating layer 630 covered on the stepped structure to form a plurality of contact holes (not shown in the figure) exposing the gate layer (such as 611a) on the top surfaces of each step of the stepped structure. In an embodiment of the present invention, covering the insulating layer 630 on the stepped structure further includes planarizing the insulating layer 630. In an embodiment of the present invention, peripheral circuit devices (not shown in the figure) are further included below the stepped structure.

[0064] Other details of this embodiment can be referred to the previous manufacturing method and will not be elaborated here.

[0065] This embodiment of the present invention provides a semiconductor structure, including a core area and a stepped area. The stepped area has a stepped structure with multiple steps. Each step includes at least one gate layer and at least one dielectric layer stacked alternately from top to bottom. The edge of at least one of the gate layers constitutes the top surface of the step. A conductive layer is formed on the top surface of the step, and a contact part is connected to the conductive layer. It can be seen that since the gate layer is covered with a conductive layer, the thickness of the gate layer becomes thicker and it is not easily etched through. Therefore, the risk of etching through is greatly reduced.

[0066] Although the present invention has been described with reference to the current specific embodiments, those of ordinary skill in the art should recognize that the above embodiments are only used to illustrate the present invention. Various equivalent changes or substitutions can be made without departing from the spirit of the present invention. Therefore, as long as the changes and modifications of the above embodiments are within the scope of the spirit of the present invention, they will fall within the scope of the claims of this application.

Claims

1. A three-dimensional memory includes a stepped structure and an insulating layer disposed on the stepped structure. The stepped structure has a plurality of steps, and each step includes at least one gate layer and at least one dielectric layer stacked alternately. The edge of at least one of the gate layers constitutes the top surface of the step. A conductive layer is formed on the top surface of the step, the side surface of the step is in contact with the insulating layer, and a contact portion is connected to the conductive layer. The conductive layer has the same material as the gate layer, the thickness of the conductive layer is 10 - 100 nm, the stepped structure further includes a hole-like structure penetrating the stepped structure along a first direction. The hole-like structure includes an end portion away from the contact portion, and the end portion protrudes from the stepped structure. The hole-like structure is filled with an insulating material, and at least part of the insulating material is in contact with the gate layer.

2. The three-dimensional memory according to claim 1, wherein The material of the insulating material includes silicon oxide, and the insulating material provides support for the stepped structure.

3. The three-dimensional memory according to claim 1, wherein The materials of the conductive layer and the gate layer are both tungsten or cobalt.

4. The three-dimensional memory according to claim 1, wherein, Along a second direction intersecting with the first direction, at least one of the contact portions is disposed between two of the hole-like structures.

5. The three-dimensional memory according to claim 1, wherein At least part of the hole-like structure is located on one side of the stepped structure along the first direction.

6. The three-dimensional memory according to claim 1, wherein The hole-like structure is a columnar support structure.

7. The three-dimensional memory according to claim 1, characterized in that Peripheral circuit devices are further included below the stepped structure.

8. The three-dimensional memory according to claim 1, wherein The thickness of the conductive layer is less than the thickness of the dielectric layer.

9. A three-dimensional memory includes a stepped structure and an insulating layer disposed on the stepped structure. The stepped structure has a plurality of steps, and each step includes at least one gate layer and at least one dielectric layer stacked alternately. The edge of at least one of the gate layers constitutes the top surface of the step. A conductive layer is formed on the top surface of the step, the side surface of the step is in contact with the insulating layer, and a contact portion is connected to the conductive layer. The conductive layer has the same material as the gate layer, the thickness of the conductive layer is 10 - 100 nm, and the thickness of the conductive layer is less than the thickness of the dielectric layer.

10. The three-dimensional memory according to claim 9, wherein The stepped structure further includes a hole-like structure penetrating the stepped structure along a first direction. The hole-like structure includes an end portion away from the contact portion, and the end portion protrudes from the stepped structure. The hole-like structure is filled with an insulating material, and at least part of the insulating material is in contact with the gate layer.

11. The three-dimensional memory according to claim 10, wherein The material of the insulating material includes silicon oxide, and the insulating material provides support for the stepped structure.

12. The three-dimensional memory according to claim 10, wherein Along a second direction intersecting with the first direction, at least one of the contact portions is disposed between two of the hole-like structures.

13. The three-dimensional memory according to claim 10, wherein At least part of the hole-like structure is located on one side of the stepped structure along the first direction.

14. The three-dimensional memory according to claim 10, wherein, The hole-like structure is a columnar support structure.

15. The three-dimensional memory according to claim 1, wherein The materials of the conductive layer and the gate layer are both tungsten or cobalt.

16. The three-dimensional memory according to claim 1, wherein Peripheral circuit devices are further included below the stepped structure.

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