Semiconductor device

Abstract

A semiconductor device includes: a peripheral circuit structure; and a cell structure including: gate electrodes extending in a first direction and spaced apart from each other in a second direction, where the gate electrodes define a channel hole extending in the second direction; the channel layer comprises a first region and a second region; a common source layer electrically connected to the second region of the channel layer; the upper insulating layer is arranged on the common source electrode layer, and the upper insulating layer, the common source electrode layer and the second area of the channel layer define a back grid electrode hole extending in the second direction; a back gate insulating layer on the channel hole and the back gate hole; and a back gate electrode in the channel hole and the back gate hole and on the back gate insulating layer.

Description

Cross - reference to Related Applications

[0001] This application claims priority based on and claims the benefit of Korean Patent Application No. 10 - 2023 - 0197697, filed with the Korean Intellectual Property Office on December 29, 2023, the entire disclosure of which is incorporated herein by reference. Technical Field

[0002] The present disclosure relates to a semiconductor device, and more particularly, to a semiconductor device having memory strings arranged in a vertical direction. Background Art

[0003] In an electronic system that requires data storage, a semiconductor device capable of storing a large amount of data is desired. As a method of increasing the data storage capacity of a semiconductor device, a semiconductor device including three - dimensionally arranged memory cells instead of two - dimensionally arranged memory cells has been proposed. In addition, a semiconductor device has been proposed in which a part of the semiconductor device is formed on a first substrate, another part of the semiconductor device is formed on a second substrate, and the first substrate and the second substrate are bonded to each other. Summary of the Invention

[0004] The present disclosure provides a semiconductor device having excellent operating characteristics and improved integration.

[0005] The object of the present disclosure is not limited to the above - mentioned object, and other objects not mentioned will be clearly understood by those skilled in the art from the following description.

[0006] According to one aspect of the present disclosure, there is provided a semiconductor device including: a peripheral circuit structure; and a cell structure on the peripheral circuit structure, wherein the cell structure includes: gate electrodes extending in a first direction and spaced apart from each other in a second direction intersecting the first direction, wherein the gate electrodes define channel holes extending in the second direction; a channel layer including a first region in the channel holes and a second region extending from the first region in the second direction; a common source layer electrically connected to the second region of the channel layer; an upper insulating layer on the common source layer, wherein the upper insulating layer, the common source layer, and the second region of the channel layer define a back - gate hole extending in the second direction; a back - gate insulating layer on the inner walls of the channel holes and the back - gate hole and extending in the second direction; and a back - gate electrode in the channel holes and the back - gate hole and on the back - gate insulating layer.

[0007] According to another aspect of the present disclosure, a semiconductor device is provided, including: a peripheral circuit structure; and a cell structure on the peripheral circuit structure, wherein the cell structure includes: gate electrodes extending in a first direction and spaced apart from each other in a second direction intersecting the first direction, wherein the gate electrodes define channel holes extending in the second direction; a channel layer including a first region in the channel holes and a second region extending from the first region in the second direction; a common source layer electrically connected to the second region of the channel layer; an upper insulating layer on the common source layer, wherein the upper insulating layer, the common source layer, and the second region of the channel layer define a back gate hole including a first back gate hole and a second back gate hole, the first back gate hole being defined by a part of the upper insulating layer and a first part of the common source layer, and the second back gate hole being defined by a second part of the common source layer and the second region of the channel layer; a back gate insulating layer on inner walls of the channel holes and inner walls of the back gate holes and extending in the second direction; a back gate electrode in the channel holes and the back gate holes and on the back gate insulating layer; and an insulating spacer on an inner wall of the first back gate hole.

[0008] According to another aspect of the present disclosure, a semiconductor device is provided, including: a peripheral circuit structure; and a cell structure on the peripheral circuit structure, wherein the cell structure includes: gate electrodes extending in a first direction and spaced apart from each other in a second direction intersecting the first direction, wherein the gate electrodes define channel holes extending in the second direction; a channel structure including a back gate insulating layer, a back gate electrode, and a channel layer between the back gate insulating layer and the back gate electrode, the channel layer including a first region in the channel holes and a second region extending from the first region in the second direction; a common source layer electrically connected to the second region of the channel layer; an upper conductive layer on the common source layer; an upper insulating layer on the upper conductive layer, wherein the upper insulating layer, the upper conductive layer, the common source layer, and the second region of the channel layer define a back gate hole including a first back gate hole and a second back gate hole, the first back gate hole being defined by a part of the upper insulating layer, a part of the upper conductive layer, and a first part of the common source layer, and the second back gate hole being defined by a second part of the common source layer and the second region of the channel layer; a back gate contact extending into the upper insulating layer and electrically connected to the back gate electrode; and a common source contact extending into the upper insulating layer and electrically connected to the common source layer, wherein the back gate insulating layer extends in the second direction and is on inner walls of the back gate holes, and wherein the back gate electrode extends in the second direction, on the back gate insulating layer, and in the back gate holes. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Embodiments will be understood more clearly from the following detailed description in conjunction with the accompanying drawings, in which:

[0010] Figure 1is a block diagram of a semiconductor device according to an embodiment;

[0011] Figure 2 is a circuit diagram of a memory block according to an embodiment;

[0012] Figure 3 is a perspective view of a representative configuration of a semiconductor device according to an embodiment;

[0013] Figure 4 is a plan layout diagram of a semiconductor device;

[0014] Figure 5 is Figure 4 an enlarged layout diagram of region A of

[0015] Figure 6 is a cross-sectional view of the Figure 5 semiconductor device taken along line B-B';

[0016] Figure 7 is Figure 6 an enlarged view of region CX1 of

[0017] Figure 8 is a cross-sectional view of a semiconductor device according to an embodiment;

[0018] Figure 9 is Figure 8 an enlarged view of region CX2 of

[0019] Figure 10 、 Figure 11 、 Figure 12 、 Figure 13 、 Figure 14 、 Figure 15 、 Figure 16 、 Figure 17 、 Figure 18 、 Figure 19 、 Figure 20 、 Figure 21 and Figure 22 is a cross-sectional view showing a method of manufacturing a semiconductor device according to an embodiment;

[0020] Figure 23 is a schematic diagram of a data storage system including a semiconductor device according to an embodiment;

[0021] Figure 24 is a schematic perspective view of a data storage system including a semiconductor device according to an embodiment; and

[0022] Figure 25 is a schematic cross-sectional view of a semiconductor package according to an embodiment. Detailed Description

[0023] To clarify the present disclosure, parts irrelevant to the description will be omitted, and throughout the specification, the same elements or equivalents will be denoted by the same reference numerals. In addition, since the dimensions and thicknesses of the constituent members shown in the drawings are arbitrarily given for better understanding and easy description, the present disclosure is not limited to the dimensions and thicknesses shown. In the drawings, the thicknesses of layers, films, panels, regions, etc. are exaggerated for clarity. In the drawings, the thicknesses of some layers and regions are overly shown for better understanding and easy description.

[0024] It will be understood that when an element (e.g., a layer, film, region, or substrate) is referred to as being "on" another element, the element can be directly on the other element or there can also be intervening elements. In contrast, when an element is referred to as being "directly on" another element, there are no intervening elements. In addition, for ease of description, spatial relative terms (e.g., "below", "beneath", "under", "above", "on", etc.) may be used herein to describe the relationship of one element or feature to another element or feature as shown in the drawings. It will be understood that the spatial relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation shown in the drawings.

[0025] Furthermore, unless explicitly described to the contrary, the word "comprising" and variations such as "containing" or "including" will be understood to mean including the stated elements but not excluding any other elements. As used herein, the singular forms "a", "an", and "the" are intended to also include the plural forms unless the context clearly dictates otherwise. The term "and / or" includes any and all combinations of one or more of the associated listed items. The term "connected" may be used herein to refer to physical and / or electrical connections, and may refer to direct or indirect physical and / or electrical connections.

[0026] Hereinafter, embodiments will be described in detail with reference to the drawings. The same reference numerals are used for the same components in the drawings, and repeated descriptions thereof are omitted.

[0027] Figure 1 is a block diagram of a semiconductor device 10 according to an embodiment.

[0028] Referring to Figure 1 , the semiconductor device 10 may include a memory cell array 20 and a peripheral circuit 30. The memory cell array 20 may include a plurality of memory cell blocks BLK1, BLK2, ……, BLKn. Each of the plurality of memory cell blocks BLK1, BLK2, ……, BLKn may include a plurality of memory cells. The plurality of memory cell blocks BLK1, BLK2, ……, BLKn may be connected to the peripheral circuit 30 through bit lines BL, word lines WL, string selection lines SSL, and ground selection lines GSL.

[0029] The peripheral circuit 30 may include a row decoder 32, a page buffer 34, a data input / output (I / O) circuit 36, and a control logic 38. Although Figure 1 not shown, the peripheral circuit 30 may further include an input / output interface, column logic, a voltage generator, a pre-decoder, a temperature sensor, a command decoder, an address decoder, an amplifier circuit, etc.

[0030] The memory cell array 20 may be connected to the page buffer 34 through bit lines BL, and may be connected to the row decoder 32 through word lines WL, string select lines SSL, and ground select lines GSL. In the memory cell array 20, each memory cell among the multiple memory cells included in each of the multiple memory cell blocks BLK1, BLK2, ……, BLKn may be a flash memory cell. The memory cell array 20 may include a three-dimensional memory cell array. The three-dimensional memory cell array may include multiple NAND strings, and each NAND string may include multiple memory cells connected to multiple word lines WL stacked vertically on a substrate.

[0031] The peripheral circuit 30 may receive an address ADDR, a command CMD, and a control signal CTRL from outside the semiconductor device 10, and may send data DATA to a device outside the semiconductor device 10 and receive data DATA from a device outside the semiconductor device 10.

[0032] The row decoder 32 may select at least one of the multiple memory cell blocks BLK1, BLK2, ……, BLKn in response to an address ADDR from outside, and may select the word lines WL, string select lines SSL, and ground select lines GSL of the selected memory cell block. The row decoder 32 may send a voltage for performing a memory operation to the word lines WL of the selected memory cell block.

[0033] The page buffer 34 may be connected to the memory cell array 20 through bit lines BL. In a programming operation, the page buffer 34 may operate as a write driver to apply a voltage to the bit lines BL according to data DATA to be stored in the memory cell array 20, and in a read operation, the page buffer 34 may operate as a sense amplifier to read data DATA stored in the memory cell array 20. The page buffer 34 may operate according to a control signal PCTL provided from the control logic 38.

[0034] The data input / output circuit 36 can be connected to the page buffer 34 through a plurality of data lines DL. In a programming operation, the data input / output circuit 36 can receive data DATA from a memory controller (not shown), and can provide the programming data DATA to the page buffer 34 based on the column address C_ADDR provided from the control logic 38. In a read operation, the data input / output circuit 36 can provide the read data DATA stored in the page buffer 34 to the memory controller based on the column address C_ADDR provided from the control logic 38.

[0035] The data input / output circuit 36 can send an address or a command input to the data input / output circuit 36 to the control logic 38 or the row decoder 32. The peripheral circuit 30 can also include an electrostatic discharge (ESD) circuit and a pull-up / pull-down driver.

[0036] The control logic 38 can receive a command CMD and a control signal CTRL from the memory controller. The control logic 38 can provide the row address R_ADDR to the row decoder 32, and can provide the column address C_ADDR to the data input / output circuit 36. The control logic 38 can generate various internal control signals used in the semiconductor device 10 in response to the control signal CTRL. For example, the control logic 38 can adjust the voltage levels provided to the word line WL and the bit line BL when performing a memory operation (e.g., a programming operation or an erase operation).

[0037] Figure 2 is a circuit diagram of a memory cell block BLK according to an embodiment.

[0038] Referring to Figure 2 , the memory cell array MCA can include: memory cell strings MCS11, MCS12, MCS13, MCS21, MCS22, MCS23, MCS31, MCS32, MCS33; word lines WL1, WL2, WL3, WL4, WL5, WL6, WL7, WL8; ground selection lines GSL1, GSL2, GSL3; string selection lines SSL1, SSL2, SSL3; and a common source line CSL.

[0039] Memory cell strings MCS11, MCS21, and MCS31 can be disposed between a first bit line BL1, a first back gate line BGL1, and a common source line CSL. Memory cell strings MCS12, MCS22, and MCS32 can be disposed between a second bit line BL2, a second back gate line BGL2, and the common source line CSL. And memory cell strings MCS13, MCS23, and MCS33 can be disposed between a third bit line BL3, a third back gate line BGL3, and the common source line CSL. Each memory cell string (e.g., MCS11) can include a string select transistor SST, a plurality of memory cells MCT1 to MCT8, and a ground select transistor GST that are connected in series with each other.

[0040] The string select transistor SST can be connected to corresponding string select lines SSL1 to SSL3. The plurality of memory cells MCT1 to MCT8 can be respectively connected to corresponding word lines WL1 to WL8. The ground select transistor GST can be connected to corresponding ground select lines GSL1 to GSL3. The string select transistor SST can be connected to the corresponding first bit line BL1 to third bit line BL3, and the ground select transistor GST can be connected to the common source line CSL.

[0041] In some embodiments, word lines (e.g., WL1) disposed at the same height can be commonly connected to each other, the string select lines SSL1 to SSL3 can be separated from each other, and the ground select lines GSL1 to GSL3 can also be separated from each other. Although Figure 2 three string select lines SSL1 to SSL3 are shown sharing a word line disposed at the same height, the present disclosure is not limited thereto. For example, two string select lines can share a word line disposed at the same height. As another example, four string select lines can share a word line disposed at the same height.

[0042] Figure 3 is a perspective view of a representative configuration of a semiconductor device 100 according to an embodiment. Figure 4 is a plan layout view of the semiconductor device 100, and Figure 5 is Figure 4 an enlarged layout view of region A of Figure 6 is along Figure 5 a cross-sectional view of the semiconductor device 100 taken along line B - B'. Figure 7 is Figure 6 an enlarged view of region CX1 of

[0043] Referring to Figures 3 to 7 , the semiconductor device 100 can include a cell structure CS and a peripheral circuit structure PS that overlap each other in the vertical direction Z. The cell structure CS can include referring to Figure 1The described memory cell array 20, and the peripheral circuit structure PS may include reference Figure 1 to the described peripheral circuit 30.

[0044] The cell structure CS may include a plurality of memory cell blocks BLK1, BLK2, ……, BLKn. Each of the plurality of memory cell blocks BLK1, BLK2, ……, BLKn may include three-dimensionally arranged memory cells.

[0045] The peripheral circuit structure PS may include peripheral circuit transistors 60TR arranged on the substrate 50 and a peripheral circuit wiring structure 70. An active region AC may be defined in the substrate 50 by a device isolation layer 52, and a plurality of peripheral circuit transistors 60TR may be formed on the active region AC. Each of the plurality of peripheral circuit transistors 60TR may include a peripheral circuit gate 60G and source / drain regions 62 disposed in portions of the substrate 50 on both sides of the peripheral circuit gate 60G.

[0046] The substrate 50 may include a semiconductor material, for example, a Group-IV semiconductor, a Group-III-V compound semiconductor, or a Group-II-VI oxide semiconductor. For example, the Group-IV semiconductor may include silicon (Si), germanium (Ge), or silicon-germanium. The substrate 50 may be provided as a bulk wafer or an epitaxial layer. In some embodiments, the substrate 50 may include a silicon-on-insulator (SOI) substrate or a germanium-on-insulator (GeOI) substrate.

[0047] The peripheral circuit wiring structure 70 may include a plurality of peripheral circuit contacts 72 and a plurality of peripheral circuit wiring layers 74. An interlayer insulating layer 80 may be disposed on the substrate 50, and the interlayer insulating layer 80 covers or overlaps the peripheral circuit transistors 60TR and the peripheral circuit wiring structure 70. Each of the plurality of peripheral circuit wiring layers 74 may have a multi-layer structure including a plurality of metal layers disposed at different vertical levels. A connection pad 90 may be disposed on the interlayer insulating layer 80, and the peripheral circuit structure PS and the cell structure CS may be electrically connected and bonded to each other through the connection pad 90.

[0048] The cell structure CS may include a cell region MCR, a connection region CON, and a peripheral circuit connection region PCR. The cell region MCR may be a region in which a cell block BLK including a plurality of memory cell strings extending in the vertical direction Z is arranged. In the cell region MCR, a common source layer 110, a plurality of gate electrodes 120, and a channel structure 130 may be arranged. The channel structure 130 may penetrate or extend into the gate electrode 120 in the vertical direction Z, and the channel structure 130 may be connected to the common source layer 110. In the connection region CON, an extension portion 120E, a pad portion 120P, and a first plug CP1 may be arranged. The extension portion 120E and the pad portion 120P are connected to the plurality of gate electrodes 120. The first plug CP1 penetrates or extends into the extension portion 120E and the pad portion 120P and is electrically connected to the pad portion 120P. In the peripheral circuit connection region PCR, a second plug CP2 extending in the vertical direction Z and electrically connected to the peripheral circuit wiring structure 70 may be arranged.

[0049] The cell structure CS may include a first surface CS_1 connected to the peripheral circuit structure PS and a second surface CS_2 opposite to the first surface CS_1. Figure 6 It is shown that the first surface CS_1 of the cell structure CS is arranged on the lower side of the cell structure CS, and the second surface CS_2 of the cell structure CS is arranged on the upper side of the cell structure CS. Herein, for convenience, as Figure 6 shown, arranging close to the first surface CS_1 of the cell structure CS is referred to as being arranged at the first vertical level, and arranging close to the second surface CS_2 of the cell structure CS is referred to as being arranged at a second vertical level higher than or greater than the first vertical level.

[0050] The gate electrodes 120 may be arranged separately from each other in the vertical direction Z in the cell region MCR, and the gate electrodes 120 may be alternately arranged with the molding insulating layer 122. The gate electrodes 120 may extend into the connection region CON, and the portion of the gate electrode 120 arranged in the connection region CON may be referred to as the extension portion 120E. Each extension portion 120E may have a horizontal length that gradually increases toward the second surface CS_2 of the cell structure CS (i.e., in the Figure 6 upward direction in). Each extension portion 120E may have a stepped shape, and the pad portion 120P may be connected to the end of the extension portion 120E. The thickness of each pad portion 120P in the vertical direction Z may be greater than the thickness of each extension portion 120E in the vertical direction Z.

[0051] Each gate electrode 120 may include a buried conductive layer and a conduction blocking layer that at least partially surrounds top, bottom, and side surfaces of the buried conductive layer. For example, the buried conductive layer may include a metal (e.g., tungsten, nickel, cobalt, or tantalum), a metal silicide (e.g., tungsten silicide, nickel silicide, cobalt silicide, or tantalum silicide), doped polysilicon, or a combination thereof. In some embodiments, the conduction blocking layer may include titanium nitride, tantalum nitride, tungsten nitride, or a combination thereof.

[0052] In some embodiments, the gate electrode 120 may correspond to a ground selection line GSL1 to GSL3, a word line WL1 to WL8, and at least one string selection line SSL1 to SSL3 connected to the memory cell strings MCS11 to MCS33 (see Figure 2 ). For example, the uppermost gate electrode 120 among the gate electrodes 120 may be used as the ground selection line GSL1 to GSL3, the lowermost two gate electrodes 120 among the gate electrodes 120 may be used as the string selection lines SSL1 to SSL3, and the remaining gate electrodes 120 among the gate electrodes 120 may be used as the word lines WL1 to WL8. Accordingly, memory cell strings MCS11 to MCS33 in which the ground selection transistor GST, the string selection transistor SST, and the memory cells MCT1 to MCT8 therebetween are connected in series may be provided. In some embodiments, at least one gate electrode 120 may be used as a dummy word line, but the present disclosure is not limited thereto.

[0053] The stack separation insulating layer WLI may be disposed in the stack separation opening WLH that penetrates the gate electrode 120 and the molding insulating layer 122 or extends into the gate electrode 120 and the molding insulating layer 122 and extends in the vertical direction Z. The stack separation insulating layer WLI may have a top surface disposed at a vertical level higher than the uppermost gate electrode 120 among the gate electrodes 120 and may protrude or extend upward with respect to the uppermost gate electrode 120 among the gate electrodes 120. In some embodiments, the gate electrodes 120 disposed between a pair of stack separation openings WLH may form one memory cell block BLK. Further, in one memory cell block BLK, at least one gate electrode 120 (e.g., the lowermost gate electrode 120 among the gate electrodes 120) may be divided into two gate electrodes 120 through the string separation opening SSLH. The string separation insulating layer SSLI may be disposed in the string separation opening SSLH.

[0054] The stack insulating layer 124 may be disposed to at least partially surround the gate electrode 120, the extension portion 120E, and the pad portion 120P in the connection region CON and the peripheral circuit connection region PCR. In a plan view, the stack insulating layer 124 may be disposed to surround the gate electrode 120 and may have a top surface disposed at the same level as the uppermost gate electrode 120 among the gate electrodes 120 in the peripheral circuit connection region PCR.

[0055] The channel structure 130 may be disposed in the channel hole 130H that penetrates the gate electrode 120 and the molded insulating layer 122 or extends into the gate electrode 120 and the molded insulating layer 122 and extends in the vertical direction. The channel structure 130 may include a gate insulating layer 132, a channel layer 134, a back gate insulating layer 136, a drain region 138, and a back gate electrode 131. The gate insulating layer 132, the channel layer 134, the back gate insulating layer 136, and the back gate electrode 131 may be sequentially disposed on the inner wall of the channel hole 130H.

[0056] In some embodiments, the back gate insulating layer 136 may cover the inner wall of the channel layer 134 or overlap with the inner wall of the channel layer 134 in the channel hole 130H, and may protrude or extend in the vertical direction to cover the inner wall of the back gate hole or overlap with the inner wall of the back gate hole. In addition, the back gate electrode 131 may protrude or extend in the vertical direction to cover the back gate insulating layer 136 or overlap with the back gate insulating layer 136 and fill the back gate hole or be in the back gate hole. The back gate electrode 131 may cover the inner wall of the back gate insulating layer 136 or overlap with the inner wall of the back gate insulating layer 136 in the channel hole 130H, and may protrude or extend in the vertical direction to cover the back gate insulating layer 136 or overlap with the back gate insulating layer 136 in the back gate hole. The structures of the back gate insulating layer 136 and the back gate electrode 131 are described in detail below.

[0057] The drain region 138 electrically connected to the channel layer 134 may be disposed at one end of the channel structure 130. The drain region 138 may be connected to the bit line contact portion BLC, and the channel layer 134 may be electrically connected to the bit line BL through the drain region 138 and the bit line contact portion BLC.

[0058] In some embodiments, the channel layer 134 may include a first region 134a and a second region 134b. The first region 134a of the channel layer 134 may refer to the region disposed in the channel hole 130H, and the second region 134b of the channel layer 134 may refer to the region connected to the first region 134a and disposed at a higher vertical level than the etch stop layer 112. For example, the first region 134a may refer to the portion of the channel layer 134 disposed at the same vertical level as the gate electrode 120 and at least partially surrounded by the gate electrode 120. In this case, the horizontal width of the second region 134b may be greater than the horizontal width of the first region 134a.

[0059] The side surface and the top surface of the channel layer 134 may not be covered by or may not overlap with the gate insulating layer 132 in the second region 134b. The common source layer 110 may be connected to a part of the side surface and the top surface of the channel layer 134 in the second region 134b. A part of the top surface of the channel layer 134 may be penetrated by the back gate hole in the second region 134b, or the back gate hole may extend into a part of the top surface of the channel layer 134 in the second region 134b.

[0060] In some embodiments, the back gate hole may include a first back gate hole 131H and a second back gate hole 132H. The first back gate hole 131H may penetrate a part of the upper insulating layer 142 and the common source layer 110 or may extend into a part of the upper insulating layer 142 and the common source layer 110. The second back gate hole 132H may be disposed at the bottom of the first back gate hole 131H. The second back gate hole 132H may penetrate the common source layer 110 and the top surface of the second region 134b of the channel layer 134, or may extend into the common source layer 110 and the top surface of the second region 134b of the channel layer 134. In this case, the horizontal width of the first back gate hole 131H may be greater than the horizontal width of the second back gate hole 132H.

[0061] In some embodiments, the back gate insulating layer 136 may be disposed on the inner walls of the channel hole 130H and the back gate hole and may extend in the vertical direction. The back gate insulating layer 136 may cover or may overlap with the inner wall of the channel layer 134. Specifically, the back gate insulating layer 136 may be disposed in the first region 134a and the second region 134b of the channel layer 134. The back gate insulating layer 136 may be disposed on the inner walls of the first back gate hole 131H and the second back gate hole 132H. The back gate insulating layer 136 disposed in the channel hole 130H and the back gate hole may be formed as a single body. In some embodiments, the back gate insulating layer 136 may include silicon oxide, hafnium oxide, aluminum oxide, zirconium oxide, tantalum oxide, etc.

[0062] In some embodiments, the back gate electrode 131 may cover or may overlap with the back gate insulating layer 136 to fill the channel hole 130H and the back gate hole or may be in the channel hole 130H and the back gate hole. The back gate electrode 131 may extend in the vertical direction Z in the channel hole 130H and the back gate hole. The back gate insulating layer 136 may be disposed on the side wall of the back gate electrode 131. The back gate electrode 131 may be electrically insulated from the channel layer 134 and the common source layer 110 by the back gate insulating layer 136 disposed between the back gate electrode 131 and each of the channel layer 134 and the common source layer 110.

[0063] The bottom surface of the back gate electrode 131 may be covered by or overlap with the back gate insulating layer 136 at one end of the channel structure 130, and the back gate insulating layer 136 may be disposed between the bottom surface of the back gate electrode 131 and the drain region 138. The top surface of the back gate electrode 131 may not be covered by or overlap with the back gate insulating layer 136, and the back gate contact portion 144 may be disposed on the top surface of the back gate electrode 131.

[0064] In some embodiments, the back gate electrode 131 may include a first portion 131A, a second portion 131B, and a third portion 131C. The first portion 131A may be disposed in a first region 134a of the channel layer 134. The first portion 131A of the back gate electrode 131 may have a shape in which the width increases toward the peripheral circuit structure PS.

[0065] The second portion 131B may be connected to the first portion 131A in the vertical direction and may be disposed in a second region 134b of the channel layer 134. In some embodiments, the horizontal width of the second portion 131B may be greater than the horizontal width of the first portion 131A.

[0066] The third portion 131C may be connected to the second portion 131B in the vertical direction and may be disposed in the back gate hole. In some embodiments, the third portion 131C of the back gate electrode 131 may have a shape in which the horizontal width increases in the vertical direction away from the peripheral circuit structure PS. In this case, the horizontal width of the back gate electrode 131 disposed in the first back gate hole 131H may be greater than the horizontal width of the back gate electrode 131 disposed in the second back gate hole 132H.

[0067] In some embodiments, the first portion 131A, the second portion 131B, and the third portion 131C of the back gate electrode 131 may include the same material. In addition, the first portion 131A, the second portion 131B, and the third portion 131C may be formed as a single body (e.g., the first portion 131A, the second portion 131B, and the third portion 131C of the back gate electrode 131 are integral). For example, the back gate electrode 131 may include a doped polysilicon layer, but the present disclosure is not limited thereto. When performing a data write operation, read operation, or erase operation on the memory cells MCT1 to MCT8 (see Figure 2 ), a specific voltage (or signal) may be applied to the back gate electrode 131 through the first back gate line BGL1 to the third back gate line BGL3 (see Figure 2 ).

[0068] The gate insulating layer 132 may have a structure including a tunneling dielectric layer, a charge storage layer, and a blocking dielectric layer in sequence on the outer wall of the channel layer 134.

[0069] The tunneling dielectric layer may include silicon oxide, hafnium oxide, aluminum oxide, zirconium oxide, tantalum oxide, etc. The charge storage layer may be a region that stores electrons that have passed through the tunneling dielectric layer from the channel layer 134, and may include silicon nitride, boron nitride, silicon boron nitride, or impurity-doped polysilicon. The blocking dielectric layer may include silicon oxide, silicon nitride, or a metal oxide having a dielectric constant higher than that of silicon oxide. The metal oxide may include hafnium oxide, aluminum oxide, zirconium oxide, tantalum oxide, or a combination thereof.

[0070] In some embodiments, the gate insulating layer 132 may include a ferroelectric dielectric material. For example, the charge storage layer may include a metal oxide having ferroelectric material characteristics. For example, the charge storage layer may include a ferroelectric material capable of storing data through a hysteresis behavior caused by a voltage applied to the charge storage layer. In some embodiments, the charge storage layer may include at least one of hafnium oxide, zirconium oxide, and hafnium zirconium oxide.

[0071] The etch stop layer 112 may be disposed on the uppermost gate electrode 120 in the gate electrode 120, and the etch stop layer 112 may include polysilicon. In some embodiments, the etch stop layer 112 may be omitted.

[0072] The common source layer 110 may be connected to the second region 134b of the channel layer 134 on the etch stop layer 112, and may be conformally formed to cover the top surface of the stacked isolation insulating layer WLI or overlap with the top surface of the stacked isolation insulating layer WLI. In a plan view, the common source layer 110 may be disposed above the entire cell region MCR.

[0073] In some embodiments, the common source layer 110 may cover a part of the top surface and side surface of the channel layer 134 or overlap with a part of the top surface and side surface of the channel layer 134. In addition, the common source layer 110 may cover a part of the side surface of the back gate insulating layer 136 or overlap with a part of the side surface of the back gate insulating layer 136. Since the first back gate hole 131H penetrates a part of the common source layer 110 or extends into a part of the common source layer 110, and the second back gate hole 132H penetrates the common source layer 110 or extends into the common source layer 110, the common source layer 110 may include a first protrusion 110a. In a plan view, the first protrusion 110a may have a shape that horizontally protrudes toward the second back gate hole 132H.

[0074] In some embodiments, the common source layer 110 may cover a part of the top surface and the side surface of the channel layer 134 or overlap with a part of the top surface and the side surface of the channel layer 134. In addition, the common source layer 110 may cover the top surface of the gate insulating layer 132 or overlap with the top surface of the gate insulating layer 132. Since the second region 134b of the channel layer 134 is arranged to protrude or extend from the etch stop layer 112, the common source layer 110 may include a second protrusion 110b. In a plan view, the second protrusion 110b may have a shape that horizontally protrudes toward the channel layer 134. Since the common source layer 110 includes the first protrusion 110a and the second protrusion 110b, a sufficient contact area may be ensured between the common source layer 110 and the channel layer 134.

[0075] In some embodiments, an upper conductive layer 110M may be disposed on the top surface of the common source layer 110. The upper conductive layer 110M may include a metal nitride (e.g., titanium nitride, tantalum nitride, or tungsten nitride), a metal (e.g., tungsten, molybdenum, chromium, nickel, cobalt, or tantalum), a metal silicide (e.g., tungsten silicide, nickel silicide, cobalt silicide, or tantalum silicide), or a combination thereof. In some embodiments, the upper conductive layer 110M may be formed as a stacked structure including two or more layers of different materials. In this case, the first back gate via 131H may penetrate a part of the upper insulating layer 142, the upper conductive layer 110M, and the common source layer 110 or extend into a part of the upper insulating layer 142, the upper conductive layer 110M, and the common source layer 110, and may extend in the vertical direction Z.

[0076] In some embodiments, the first end CP1x of the first plug CP1 may be arranged adjacent to the peripheral circuit structure PS, and the second end CP1y of the first plug CP1 may be arranged opposite to the first end CP1x. The first plug CP1 may have an inclined sidewall such that the width of the first end CP1x is greater than the width of the second end CP1y.

[0077] In some embodiments, the first plug CP1 may include a metal (e.g., tungsten, nickel, cobalt, or tantalum), a metal nitride (e.g., titanium nitride, tantalum nitride, or tungsten nitride), a metal silicide (e.g., tungsten silicide, nickel silicide, cobalt silicide, or tantalum silicide), doped polysilicon, or a combination thereof.

[0078] In the peripheral circuit connection region PCR, a second plug CP2 may be arranged to penetrate the stacked insulating layer 124 or extend into the stacked insulating layer 124. The shape and the constituent material of the second plug CP2 may be similar to those of the first plug CP1.

[0079] The connection via 152, the connection wiring layer 154, and the interlayer insulating layer 156 that at least partially surrounds the connection via 152 and the connection wiring layer 154 may be disposed between the stacked insulating layer 124 and the peripheral circuit structure PS. Each of the connection via 152 and the connection wiring layer 154 may be formed as a multi-layer to be disposed at multiple vertical levels, and the bit line BL, the first plug CP1, and the second plug CP2 may be electrically connected to the peripheral circuit structure PS through the connection pad 90.

[0080] The upper insulating layer 142 may be disposed on the upper conductive layer 110M. The upper insulating layer 142 may have a flat top surface that penetrates the unit region MCR and the connection region CON. The upper insulating layer 142 may be disposed to cover the top surface of the upper conductive layer 110M and the top surface of the first plug CP1 or overlap with the top surface of the upper conductive layer 110M and the top surface of the first plug CP1.

[0081] The back gate contact portion 144 may penetrate the upper insulating layer 142 or extend into the upper insulating layer 142. The back gate contact portion 144 may be disposed at a position vertically overlapping each channel structure 130. For example, as Figure 6 shown, the back gate contact portion 144 may be disposed to be offset in the first horizontal direction X and the second horizontal direction Y. In some embodiments, a spacer that at least partially surrounds the sidewall of the back gate contact portion 144 may also be included. The end of the back gate contact portion 144 may be at least partially surrounded by the back gate electrode 131. For example, the third portion 131C of the back gate electrode 131 may at least partially surround the back gate contact portion 144. The top surface of the back gate contact portion 144 may be disposed at the same vertical level as the top surface of the upper insulating layer 142.

[0082] The common source contact portion 146 may penetrate the upper insulating layer 142 or extend into the upper insulating layer 142, but may not penetrate the upper conductive layer 110M and the common source layer 110 or extend into the upper conductive layer 110M and the common source layer 110. The common source contact portion 146 may be disposed at a position vertically overlapping the stacked separation opening WLH or the stacked separation insulating layer WLI. For example, as Figure 6 shown, the common source contact portion 146 may be arranged in a line in the first horizontal direction X. In some embodiments, a spacer that at least partially surrounds the sidewall of the common source contact portion 146 may also be included. The top surface of the common source contact portion 146 may be disposed at the same vertical level as the top surface of the upper insulating layer 142.

[0083] In some embodiments, each of the back gate contact 144 and the common source contact 146 may include a metal (e.g., tungsten, nickel, cobalt, or tantalum), a metal nitride (e.g., titanium nitride, tantalum nitride, or tungsten nitride), a metal silicide (e.g., tungsten silicide, nickel silicide, cobalt silicide, or tantalum silicide), or a combination thereof.

[0084] The first post-wiring layer 164 and the second post-wiring layer 166 may be disposed on the upper insulating layer 142. The first post-wiring layer 164 may be electrically connected to the back gate contact 144, and the second post-wiring layer 166 may be disposed separately from the first post-wiring layer 164 in a horizontal direction and may be electrically connected to the common source contact 146. For example, as Figure 6 shown, the second post-wiring layer 166 may be disposed at a position vertically overlapping the stack separation opening WLH and may be electrically connected to the common source layer 110 through the common source contact 146. The first post-wiring layer 164 may be disposed in a region between two adjacent stack separation openings WLH (i.e., disposed at a position vertically overlapping the channel structure 130). The first post-wiring layer 164 may be commonly electrically connected to the back gate electrodes 131 of a plurality of channel structures 130 disposed between two adjacent stack separation openings WLH (or between two adjacent stack separation insulating layers WLI).

[0085] The passivation layer 162 may be disposed on the first post-wiring layer 164 and the second post-wiring layer 166, and the opening OP of the passivation layer 162 may be disposed to expose at least one of a part of the top surface of the first post-wiring layer 164 and a part of the top surface of the second post-wiring layer 166. The first post-wiring layer 164 may be configured to apply a back gate voltage from an external connection terminal to the back gate electrode 131 in the channel structure 130 through the back gate contact 144, and / or the first post-wiring layer 164 may be electrically connected to the peripheral circuit structure PS through the second plug CP2 (see Figure 5 ). The second post-wiring layer 166 may be configured to apply a common source voltage from an external connection terminal to the common source layer 110 through the common source contact 146, and / or the second post-wiring layer 166 may be electrically connected to the peripheral circuit structure PS through the second plug CP2 (see Figure 5 ).

[0086] According to an embodiment, the back gate electrode 131 may be included in the channel structure 130. For example, when the back gate electrode 131 is included in the channel structure 130, for a programming operation, a back gate voltage may be applied to the back gate electrode 131, a programming voltage may be applied to the selected word line, and a relatively low (e.g., 0V) pass voltage may be applied to the unselected word lines. Accordingly, compared with a semiconductor device according to a comparative example in which a relatively high pass voltage is applied to the unselected word lines, an interference phenomenon of storing data in the unselected memory cells may be prevented or reduced.

[0087] In addition, since the process of forming the back gate electrode 131 is performed after the peripheral circuit structure PS is bonded to the cell structure CS, the risk of defects occurring in the back gate electrode 131 during the bonding process may be eliminated or reduced.

[0088] Figure 8 is a cross-sectional view of a semiconductor device 100B according to an embodiment.

[0089] Figure 9 is Figure 8 an enlarged view of the region CX2 of.

[0090] In Figure 8 and Figure 9 the configuration of the semiconductor device 100B of, reference numerals identical to those of the semiconductor device 100 of Figures 1 to 7 represent the same components. Accordingly, the description will focus on the differences from the semiconductor device 100 of Figures 1 to 7 to describe Figure 8 and Figure 9 the semiconductor device 100B of.

[0091] In some embodiments, the semiconductor device 100B of the present disclosure may further include an insulating spacer 143. The insulating spacer 143 may cover the inner wall of the first back gate hole 131H or overlap with the inner wall of the first back gate hole 131H. Specifically, the insulating spacer 143 may cover a part of the sidewall and the bottom surface of the first back gate hole 131H or overlap with a part of the sidewall and the bottom surface of the first back gate hole 131H. The insulating spacer 143 may be disposed between the back gate insulating layer 136 and the upper insulating layer 142. In this case, the insulating spacer 143 may include at least one of silicon nitride, silicon oxide, and silicon oxynitride.

[0092] In some embodiments, the insulating spacer 143 may be disposed on a part of the first protrusion 110a of the common source layer 110. Since the insulating spacer 143 is disposed on a part of the first protrusion 110a, the insulation performance between the back gate electrode 131 and the common source layer 110 can be improved. Since the back gate insulating layer 136 and the insulating spacer 143 are disposed in a bilayer structure between the back gate electrode 131 and the common source layer 110, the breakdown voltage performance between the back gate electrode 131 and the common source layer 110 can be improved. In addition, since the insulating spacer 143 is disposed around the relatively thin second back gate hole 132H, the structural stability can be improved.

[0093] Figures 10 to 22 is a cross-sectional view showing a method of manufacturing a semiconductor device 100 according to an embodiment.

[0094] Referring to Figure 10 , a buffer insulating layer 220 may be formed on the cell substrate 210, and a part of the cell substrate 210 and the buffer insulating layer 220 may be removed to form an opening 230H and a landing pad opening 232H. Thereafter, a sacrificial layer 230 may be formed in the opening 230H, and a landing pad portion CP1P may be formed in the landing pad opening 232H.

[0095] In some embodiments, a metal (e.g., tungsten, nickel, cobalt, or tantalum), a metal nitride (e.g., titanium nitride, tantalum nitride, or tungsten nitride), a metal silicide (e.g., tungsten silicide, nickel silicide, cobalt silicide, or tantalum silicide), or a combination thereof may be used to form each of the sacrificial layer 230 and the landing pad portion CP1P. In some embodiments, the same material may be used to form the sacrificial layer 230 and the landing pad portion CP1P, but in other embodiments, different materials may be used to form the sacrificial layer 230 and the landing pad portion CP1P.

[0096] Thereafter, an etch stop layer 112 covering the sacrificial layer 230 and the landing pad portion CP1P or overlapping with the sacrificial layer 230 and the landing pad portion CP1P may be formed on the buffer insulating layer 220.

[0097] Referring to Figure 11 , a gate electrode 120 and a molding insulating layer 122 may be alternately formed in the cell region MCR and the connection region CON, and an extension portion 120E and a pad portion 120P connected to the gate electrode 120 may be formed in the connection region CON. In addition, a channel structure 130 penetrating the gate electrode 120 or extending into the gate electrode 120 and extending in the vertical direction Z, and a bit line BL connected to the channel structure 130 may be formed in the cell region MCR.

[0098] In some embodiments, in the process of forming the channel structure 130, a molded stack alternately including a sacrificial layer (not shown) and a molded insulating layer 122 may be formed on the etch stop layer 112 in the cell region MCR and the connection region CON, and a channel hole 130H penetrating the molded stack or extending into the molded stack may be formed in the cell region MCR. The channel hole 130H may be formed to penetrate the etch stop layer 112 or extend into the etch stop layer 112, and expose the top surface of the sacrificial layer 230 disposed in the opening 230H (see Figure 10 ).

[0099] Thereafter, the sacrificial layer 230 may be removed, a gate insulating layer 132, a channel layer 134, and a channel insulating layer 131P may be sequentially formed on the inner wall of the channel hole 130H and the inner wall of the opening 230H, and a drain region 138 may be formed at the entrance of the channel hole 130H.

[0100] In some embodiments, the opening 230H may be formed to have a horizontal width larger than that of the channel hole 130H, and correspondingly, the portion of the channel insulating layer 131P disposed in the opening 230H may be formed to have a horizontal width larger than that of the portion of the channel insulating layer 131P disposed in the channel hole 130H. Herein, the portion of the channel insulating layer 131P disposed in the opening 230H is referred to as an extended portion 131T.

[0101] In addition, a first plug CP1 penetrating the extended portion 120E and the pad portion 120P or extending into the extended portion 120E and the pad portion 120P may be formed in the connection region CON. In some embodiments, a first plug hole CP1H penetrating the molded stack or extending into the molded stack may be formed in the connection region CON. The top surface of the contact pad portion CP1P may be exposed at the bottom of the first plug hole CP1H. Thereafter, the portion of the sacrificial layer (not shown) exposed on the sidewall of the first plug hole CP1H may be removed by lateral etching, and an insulating pattern 126 may be formed in the region where the sacrificial layer (not shown) has been removed. Thereafter, the first plug CP1 may be formed in the first plug hole CP1H.

[0102] Referring to Figure 12 , a connection via 152 and a connection wiring layer 154 electrically connected to the bit line BL and the first plug CP1, and an interlayer insulating layer 156 may be formed. A connection pad 90_U may be formed on the top surface of the interlayer insulating layer 156.

[0103] Referring to Figure 13, the peripheral circuit structure PS can be fabricated. The peripheral circuit structure PS may include peripheral circuit transistors 60TR disposed on a substrate 50 and a peripheral circuit wiring structure 70. An active region AC may be defined in the substrate 50 by a device isolation layer 52, and a plurality of peripheral circuit transistors 60TR may be formed on the active region AC. Each of the plurality of peripheral circuit transistors 60TR may include a peripheral circuit gate 60G and source / drain regions 62 disposed in portions of the substrate 50 on both sides of the peripheral circuit gate 60G.

[0104] Thereafter, the peripheral circuit structure PS can be attached to the cell structure CS. The peripheral circuit structure PS and the cell structure CS can be attached to each other via connection pads 90 and interlayer insulating layers 80 and 156 using a metal-oxide hybrid bonding method, but the present disclosure is not limited thereto.

[0105] Thereafter, the structure in which the peripheral circuit structure PS and the cell structure CS are attached to each other can be flipped such that the cell substrate 210 (see Figure 12 ) faces upward, and the cell substrate 210 can be removed. The cell substrate 210 can be removed by a grinding process and a subsequent etching process, and in this case, the buffer insulating layer 220 (see Figure 12 ) can be exposed.

[0106] Thereafter, the buffer insulating layer 220 can also be removed, and the top surface of the etch stop layer 112 can be exposed. As the buffer insulating layer 220 is removed, the protruding region 130y of the channel structure 130 and the second end CP1y of the first plug CP1 can protrude or extend onto the top surface of the etch stop layer 112. As the cell substrate 210 and the buffer insulating layer 220 are removed, the upper side of the stacked isolation insulating layer WLI can also be exposed and protrude or extend above the etch stop layer 112.

[0107] A portion of the gate insulating layer 132 exposed to the protruding region 130y of the channel structure 130 can be removed to expose a second region 134b of the channel layer 134. A process of removing the gate insulating layer 132 can be performed until the top surface of the etch stop layer 112 is exposed.

[0108] In some embodiments, the gate insulating layer 132 may be disposed at a level lower than the second region 134b of the channel layer 134, and the upper side of the gate insulating layer 132 can be removed such that the top surface and a part of the sidewall of the channel layer 134 are exposed. The gate insulating layer 132 can be removed, and the second region 134b of the channel layer 134 can be exposed at a vertical level higher than the etch stop layer 112.

[0109] Referring to Figure 14, a common source layer 110 can be formed in the cell region MCR, the connection region CON, and the peripheral circuit connection region PCR. Polysilicon can be used to form the common source layer 110. For example, polysilicon doped with n-type impurities can be used to form the common source layer 110. In the cell region MCR, the common source layer 110 can be conformally formed on the exposed top surfaces of the etch stop layer 112 and the channel layer 134. In the connection region CON, the common source layer 110 can cover or overlap with the second end CP1y of the first plug CP1.

[0110] In some embodiments, an upper conductive layer 110M can be formed on the top surface of the common source layer 110. The upper conductive layer 110M can include metal nitrides (e.g., titanium nitride, tantalum nitride, or tungsten nitride), metals (e.g., tungsten, molybdenum, chromium, nickel, cobalt, or tantalum), metal silicides (e.g., tungsten silicide, nickel silicide, cobalt silicide, or tantalum silicide), or combinations thereof. In some embodiments, the upper conductive layer 110M can be formed as a stacked structure including two or more layers of different materials.

[0111] Referring to Figure 15 , portions of the common source layer 110, the upper conductive layer 110M, and the etch stop layer 112 disposed in the connection region CON and the peripheral circuit connection region PCR can be removed.

[0112] In some embodiments, a mask pattern can be formed on the upper conductive layer 110M in the cell region MCR, and by using the mask pattern as an etch mask, portions of the common source layer 110, the upper conductive layer 110M, and the etch stop layer 112 disposed in the connection region CON and the peripheral circuit connection region PCR can be removed. As the portions of the common source layer 110, the upper conductive layer 110M, and the etch stop layer 112 disposed in the connection region CON and the peripheral circuit connection region PCR are removed, the second end CP1y of the first plug CP1 and the topmost molded insulating layer 122 in the molded insulating layer 122 can be exposed again.

[0113] Thereafter, in the cell region MCR, the connection region CON, and the peripheral circuit connection region PCR, an upper insulating layer 142 can be formed on the upper conductive layer 110M and the topmost molded insulating layer 122 in the molded insulating layer 122. The upper insulating layer 142 can be formed to a height large enough such that the upper insulating layer 142 covers or overlaps with both the upper conductive layer 110M and the second end CP1y of the first plug CP1 and has a flat top surface.

[0114] Referring to Figure 16, a mask pattern can be formed on the upper insulating layer 142, and by using the mask pattern as an etching mask, a part of the upper insulating layer 142, a part of the upper conductive layer 110M, and a part of the common source layer 110 can be removed to form the first back gate hole 131H.

[0115] In some embodiments, the first back gate hole 131H can be formed at a position overlapping the channel structure 130 in the vertical direction. In the process of forming the first back gate hole 131H, a part of the upper conductive layer 110M and a part of the common source layer 110 can be removed, so that a part of the upper conductive layer 110M and a part of the common source layer 110 are exposed.

[0116] Referring to Figure 17 , an insulating spacer 143 covering the sidewall of the first back gate hole 131H and the top surface of the upper insulating layer 142 or overlapping the sidewall of the first back gate hole 131H and the top surface of the upper insulating layer 142 can be formed. The insulating spacer 143 can conformally cover the first back gate hole 131H and the upper insulating layer 142 or overlap the first back gate hole 131H and the upper insulating layer 142. The insulating spacer 143 can be formed to cover the exposed portions of the upper conductive layer 110M and the common source layer 110 or overlap the exposed portions of the upper conductive layer 110M and the common source layer 110.

[0117] Referring to Figure 18 , the portion of the insulating spacer 143 covering the bottom of the first back gate hole 131H or overlapping the bottom of the first back gate hole 131H can be removed to form the second back gate hole 132H. In the process of forming the second back gate hole 132H, a part of the common source layer 110, a part of the channel layer 134, and a part of the channel insulating layer 131P can be removed. A part of the second region 134b of the channel layer 134 arranged in the protruding region 130y of the channel structure 130 can be removed, and the top surface of the extended portion 131T of the channel insulating layer 131P can be exposed.

[0118] In some embodiments, in Figures 16 to 18 the process of forming the first back gate hole 131H and the second back gate hole 132H in, the first protrusion 110a of the common source layer 110 described above can be formed.

[0119] Referring to Figure 19, the filled trench hole 130H or the trench insulating layer 131P in the trench hole 130H can be removed. By removing the filled trench hole 130H or the trench insulating layer 131P in the trench hole 130H, a back gate via BGH can be formed. As the back gate via BGH is formed, the top surface of the drain region 138 can be exposed. The trench insulating layer 131P exposed through the first back gate hole 131H and the second back gate hole 133H can be removed by an etching process. As the trench insulating layer 131P is removed, the sidewalls of the channel layer 134 can be exposed.

[0120] Referring to Figure 20 , the sidewalls of the first back gate hole 131H and the top surface of the upper insulating layer 142 or the insulating spacer 143 overlapping with the sidewalls of the first back gate hole 131H and the top surface of the upper insulating layer 142 can be removed. By removing the insulating spacer 143, the sidewalls of the first back gate hole 131H and the top surface of the upper insulating layer 142 can be exposed again.

[0121] In some embodiments, the process of removing the sidewalls of the first back gate hole 131H and the top surface of the upper insulating layer 142 or the insulating spacer 143 overlapping with the sidewalls of the first back gate hole 131H and the top surface of the upper insulating layer 142 can be omitted. When the insulating spacer 143 is not removed, the semiconductor device 100 can be substantially the same as the semiconductor device 100B described with reference to Figure 8 and Figure 9 . Except for the process of removing the insulating spacer 143, the semiconductor device 100B described with reference to Figures 10 to 22 can be manufactured in substantially the same manner as the semiconductor device 100 described with reference to Figure 8 and Figure 9 .

[0122] Referring to Figure 21 , an initial back gate insulating layer 136P and an initial back gate electrode BGP can be sequentially formed to fill or be in the back gate via BGH. The initial back gate insulating layer 136P can conformally cover the inner walls of the channel layer 134, the inner walls of the second back gate hole 132H, the inner walls of the first back gate hole 131H, and the top surface of the upper insulating layer 142, or overlap with the inner walls of the channel layer 134, the inner walls of the second back gate hole 132H, the inner walls of the first back gate hole 131H, and the top surface of the upper insulating layer 142. The initial back gate electrode BGP can conformally cover the inner walls and the top surface of the initial back gate insulating layer 136P or overlap with the inner walls and the top surface of the initial back gate insulating layer 136P.

[0123] Referring to Figure 22, a part of the initial back gate insulating layer 136P and the initial back gate electrode BGP can be removed, and the back gate insulating layer 136 and the back gate electrode 131 can be formed. The initial back gate insulating layer 136P covering or overlapping with the upper insulating layer 142 and the initial back gate electrode BGP can be removed by a chemical mechanical polishing (CMP) process.

[0124] In some embodiments, the back gate insulating layer 136 disposed in the channel hole 130H and the back gate hole can be formed as a single body. In addition, the first part 131A, the second part 131B, and the third part 131C of the back gate electrode 131 can include the same material. In addition, the first part 131A, the second part 131B, and the third part 131C can be formed as a single body. Since the first part 131A, the second part 131B, and the third part 131C are formed as a single body, an interface may not be formed between the first part 131A, the second part 131B, and the third part 131C.

[0125] Thereafter, referring again to Figure 6 , the first post-wiring layer 164 and the second post-wiring layer 166 can be formed on the upper insulating layer 142. The first post-wiring layer 164 can be electrically connected to the back gate contact portion 144, and the second post-wiring layer 166 can be electrically connected to the common source contact portion 146. For example, the first post-wiring layer 164 and the second post-wiring layer 166 can be arranged separately from each other in the horizontal direction.

[0126] Thereafter, a passivation layer 162 covering or overlapping with the first post-wiring layer 164 and the second post-wiring layer 166 can be formed on the upper insulating layer 142, and an opening OP can be formed in the passivation layer 162 to expose the top surfaces of the first post-wiring layer 164 and the second post-wiring layer 166.

[0127] Figure 23 is a schematic diagram of a data storage system 1000 including a semiconductor device according to an embodiment.

[0128] Referring to Figure 23 , the data storage system 1000 can include at least one semiconductor device 1100 and a storage controller 1200 electrically connected to the semiconductor device 1100. For example, the data storage system 1000 can be a solid state drive (SSD) device, a universal serial bus (USB), a computing system, a medical device, or a communication device including at least one semiconductor device 1100.

[0129] The semiconductor device 1100 can be a non-volatile semiconductor device. For example, the semiconductor device 1100 can be one including reference to Figures 1 to 9One of the described semiconductor devices 10, 100, and 100B, a NAND flash semiconductor device. The semiconductor device 1100 may include a first structure 1100F and a second structure 1100S on the first structure 1100F. The first structure 1100F may be a peripheral circuit structure including a row decoder 1110, a page buffer 1120, and a logic circuit 1130.

[0130] The second structure 1100S may be a memory cell structure including the following: bit lines BL, a common source line CSL, a plurality of word lines WL, a first string selection line UL1 and a second string selection line UL2, a first ground selection line LL1 and a second ground selection line LL2, and a plurality of memory cell strings CSTR between the bit lines BL and the common source line CSL.

[0131] In the second structure 1100S, each of the plurality of memory cell strings CSTR may include ground selection transistors LT1 and LT2 adjacent to the common source line CSL, string selection transistors UT1 and UT2 adjacent to the bit lines BL, and a plurality of memory cell transistors MCT between the ground selection transistors LT1 and LT2 and the string selection transistors UT1 and UT2. The number of ground selection transistors LT1 and LT2 and the number of string selection transistors UT1 and UT2 may be modified differently according to embodiments.

[0132] In some embodiments, the first ground selection line LL1 and the second ground selection line LL2 may be respectively connected to the gate electrodes of the ground selection transistors LT1 and LT2. The word lines WL may be connected to the gate electrodes of the memory cell transistors MCT. The first string selection line UL1 and the second string selection line UL2 may be respectively connected to the gate electrodes of the string selection transistors UT1 and UT2.

[0133] The common source line CSL, the first ground selection line LL1 and the second ground selection line LL2, the plurality of word lines WL, and the first string selection line UL1 and the second string selection line UL2 may be connected to the row decoder 1110. The plurality of bit lines BL may be electrically connected to the page buffer 1120.

[0134] The semiconductor device 1100 may communicate with the memory controller 1200 through an input / output pad 1101 electrically connected to the logic circuit 1130. The input / output pad 1101 may be electrically connected to the logic circuit 1130.

[0135] The memory controller 1200 may include a processor 1210, a NAND controller 1220, and a host interface (I / F) 1230. In some embodiments, the data storage system 1000 may include a plurality of semiconductor devices 1100, and in this case, the memory controller 1200 may control the plurality of semiconductor devices 1100.

[0136] The processor 1210 may control the overall operation of the data storage system 1000 including the storage controller 1200. The processor 1210 may operate according to specific firmware and may access the semiconductor device 1100 by controlling the NAND controller 1220. The NAND controller 1220 may include a NAND interface 1221 that processes communication with the semiconductor device 1100. Through the NAND interface 1221, control commands for controlling the semiconductor device 1100, data of a plurality of memory cell transistors MCT to be written to the semiconductor device 1100, and data to be read from the plurality of memory cell transistors MCT of the semiconductor device 1100 may be transmitted, etc. The host interface 1230 may provide a communication function between the data storage system 1000 and an external host. When a control command is received from the external host through the host interface 1230, the processor 1210 may control the semiconductor device 1100 in response to the control command.

[0137] Figure 24 FIG. 4 is a schematic perspective view of a data storage system 2000 including a semiconductor device according to an embodiment.

[0138] Referring to Figure 24 FIG. 5, the data storage system 2000 according to an embodiment may include a main substrate 2001, a storage controller 2002 mounted on the main substrate 2001, at least one semiconductor package 2003, and a dynamic random access memory (DRAM) 2004. The semiconductor package 2003 and the DRAM 2004 may be connected to the storage controller 2002 through a plurality of wiring patterns 2005 formed on the main substrate 2001.

[0139] The main substrate 2001 may include a connector 2006 that includes a plurality of pins coupled to an external host. The number and arrangement of the plurality of pins in the connector 2006 may vary according to the communication interface between the data storage system 2000 and the external host. In some embodiments, the data storage system 2000 may communicate with the external host according to any one of interfaces (e.g., USB, Peripheral Component Interconnect Express (PCI-Express), Serial Advanced Technology Attachment (SATA), and M-Phy for Universal Flash Storage (UFS)). In some embodiments, the data storage system 2000 may operate with power supplied from the external host via the connector 2006. The data storage system 2000 may further include a power management integrated circuit (PMIC) that distributes the power supplied from the external host to the storage controller 2002 and the semiconductor package 2003.

[0140] The storage controller 2002 may write data to or read data from the semiconductor package 2003 and may improve the operation speed of the data storage system 2000.

[0141] The DRAM 2004 can be a buffer memory for reducing the speed difference between the semiconductor package 2003 as a data storage space and an external host. The DRAM 2004 included in the data storage system 2000 can operate as a cache memory and can provide a space for temporarily storing data in the control operation of the semiconductor package 2003. When the DRAM 2004 is included in the data storage system 2000, in addition to the NAND controller for controlling the semiconductor package 2003, the storage controller 2002 can also include a DRAM controller for controlling the DRAM 2004.

[0142] The semiconductor package 2003 can include a first semiconductor package 2003a and a second semiconductor package 2003b that are separated from each other. Each of the first semiconductor package 2003a and the second semiconductor package 2003b can be a semiconductor package including a plurality of semiconductor chips 2200. Each of the first semiconductor package 2003a and the second semiconductor package 2003b can include a package substrate 2100, a plurality of semiconductor chips 2200 on the package substrate 2100, an adhesive layer 2300 on the bottom surface of each of the plurality of semiconductor chips 2200, a connection structure 2400 for electrically connecting the plurality of semiconductor chips 2200 to the package substrate 2100, and a molding layer 2500 covering or overlapping the plurality of semiconductor chips 2200 and the connection structure 2400 on the package substrate 2100.

[0143] The package substrate 2100 can be a printed circuit board including a plurality of package upper pads 2130. Each of the plurality of semiconductor chips 2200 can include input / output pads 2210. The input / output pads 2210 can correspond to Figure 23 the input / output pads 1101. Each of the plurality of semiconductor chips 2200 can include at least one of the semiconductor devices 10, 100, and 100B described with reference to Figures 1 to 9 this specification.

[0144] In some embodiments, the connection structure 2400 may be a bonding wire that electrically connects the input / output pad 2210 to the package upper pad 2130. Accordingly, in the first semiconductor package 2003a and the second semiconductor package 2003b, the plurality of semiconductor chips 2200 may be electrically connected to each other by a bonding wire method and may be electrically connected to the package upper pads 2130 of the package substrate 2100. In some embodiments, in the first semiconductor package 2003a and the second semiconductor package 2003b, the plurality of semiconductor chips 2200 may be electrically connected to each other by a connection structure including through-silicon vias (TSVs) instead of the bonding wire type connection structure 2400.

[0145] In some embodiments, the memory controller 2002 and the plurality of semiconductor chips 2200 may be included in one package. In some embodiments, the memory controller 2002 and the plurality of semiconductor chips 2200 may be mounted on a separate insertion substrate different from the main substrate 2001 and may be connected to each other by wirings formed on the insertion substrate.

[0146] Figure 25 is a schematic cross-sectional view of a semiconductor package 2003 according to an embodiment. Figure 25 is along Figure 24 The cross-sectional view of the semiconductor package 2003 taken along the line II-II'.

[0147] Referring to Figure 25 , in the semiconductor package 2003, the package substrate 2100 may be a printed circuit board. The package substrate 2100 may include: a package substrate body 2120; a plurality of package upper pads 2130 (see Figure 24 ), arranged on the top surface of the package substrate body 2120; a plurality of lower pads 2125, arranged on the bottom surface of the package substrate body 2120 or exposed through the bottom surface of the package substrate body 2120; and a plurality of internal wirings 2135, electrically connecting the plurality of package upper pads 2130 (see Figure 24 ) to the plurality of lower pads 2125 in the package substrate body 2120. As Figure 24 shown, the plurality of package upper pads 2130 may be electrically connected to the plurality of connection structures 2400. As Figure 25 shown, the plurality of lower pads 2125 may be connected to the Figure 24 A plurality of wiring patterns 2005 on the main substrate 2001 of the data storage system 2000 shown through a plurality of conductive bumps 2800. Each of the plurality of semiconductor chips 2200 may include at least one of the semiconductor devices 10, 100, and 100B described with reference to Figures 1 to 9 .

[0148] Although the present disclosure has been specifically shown and described with reference to embodiments thereof, it should be understood that various changes in form and detail may be made therein without departing from the spirit and scope of the appended claims.

Claims

1. A semiconductor device, comprising: Peripheral circuit structure; as well as Unit structure, on the peripheral circuit structure, Wherein, the unit structure comprises: gate electrodes extending in a first direction and spaced apart from each other in a second direction intersecting the first direction, wherein the gate electrodes define channel holes extending in the second direction; a channel layer including a first region in the channel hole and a second region extending from the first region in the second direction; a common source layer electrically connected to the second region of the channel layer; an upper insulating layer on the common source layer, wherein the upper insulating layer, the common source layer and the second region of the channel layer define a back gate hole extending in the second direction; a back gate insulating layer on the inner wall of the channel hole and the inner wall of the back gate hole and extending in the second direction; and A back gate electrode is in the channel hole and the back gate hole and on the back gate insulating layer.

2. The semiconductor device according to claim 1, further comprising: a back gate contact extending into the upper insulating layer and electrically connected to the back gate electrode; as well as A common source contact extends into the upper insulating layer and is electrically connected to the common source layer.

3. The semiconductor device according to claim 1, wherein The back gate electrode comprises: A first portion on the first region of the channel layer; a second portion electrically connected to the first portion and on the second region of the channel layer; and A third portion is electrically connected to the second portion and is in the back gate hole.

4. The semiconductor device according to claim 3, wherein: The first portion, the second portion, and the third portion of the back gate electrode include the same material and are integral.

5. The semiconductor device according to claim 3, wherein: The back gate hole comprises: a first back gate hole defined by a portion of the upper insulating layer and a first portion of the common source layer; and a second back gate hole defined by a second portion of the common source layer and the second region of the channel layer, The width of the third portion of the back gate electrode in the first back gate hole along the first direction is greater than the width of the third portion of the back gate electrode in the second back gate hole along the first direction.

6. The semiconductor device according to claim 5, wherein: The common source layer includes a protrusion extending in the first direction toward the second back gate hole.

7. The semiconductor device according to claim 3, wherein: The width of the third portion of the back-gate electrode in the first direction increases as the third portion of the back-gate electrode extends in the second direction relative to the peripheral circuit structure.

8. The semiconductor device according to claim 1, wherein The back gate insulating layer is on an inner wall of the first region of the channel layer and an inner wall of the second region of the channel layer.

9. The semiconductor device according to claim 1, wherein: A width of the second region of the channel layer in the first direction is greater than a width of the first region of the channel layer in the first direction.

10. The semiconductor device according to claim 1, further comprising: An upper conductive layer is between the common source layer and the upper insulating layer.

11. A semiconductor device comprising: Peripheral circuit structure; as well as Unit structure, on the peripheral circuit structure, Wherein, the unit structure comprises: gate electrodes extending in a first direction and spaced apart from each other in a second direction intersecting the first direction, wherein the gate electrodes define channel holes extending in the second direction; a channel layer including a first region in the channel hole and a second region extending from the first region in the second direction; a common source layer electrically connected to the second region of the channel layer; an upper insulating layer on the common source layer, wherein the upper insulating layer, the common source layer, and the second region of the channel layer define a back gate hole, the back gate hole comprising a first back gate hole and a second back gate hole, the first back gate hole being defined by a portion of the upper insulating layer and a first portion of the common source layer, and the second back gate hole being defined by a second portion of the common source layer and the second region of the channel layer; a back gate insulating layer, on the inner wall of the channel hole and the inner wall of the back gate hole, and extending in the second direction; a back gate electrode in the channel hole and the back gate hole and on the back gate insulating layer; and An insulating spacer is on the inner wall of the first back gate hole.

12. The semiconductor device according to claim 11, further comprising: a back gate contact extending into the upper insulating layer and electrically connected to the back gate electrode; as well as A common source contact extends into the upper insulating layer and is electrically connected to the common source layer.

13. The semiconductor device according to claim 11, wherein The back gate electrode comprises: A first portion on the first region of the channel layer; a second portion electrically connected to the first portion of the back gate electrode and on the second region of the channel layer; and a third portion electrically connected to the second portion of the back gate electrode and in the back gate hole, The first part, the second part and the third part comprise the same material and are integral.

14. The semiconductor device according to claim 11, wherein The insulating spacer is on a bottom surface of the first back gate hole.

15. The semiconductor device according to claim 11, wherein A width of the first back gate hole in the first direction is greater than a width of the second back gate hole in the first direction.

16. The semiconductor device according to claim 11, wherein The common source layer includes a protrusion extending in the first direction toward the second back gate hole.

17. The semiconductor device according to claim 11, further comprising: An upper conductive layer is between the common source layer and the upper insulating layer.

18. A semiconductor device comprising: Peripheral circuit structure; as well as Unit structure, on the peripheral circuit structure, Wherein, the unit structure comprises: gate electrodes extending in a first direction and spaced apart from each other in a second direction intersecting the first direction, wherein the gate electrodes define channel holes extending in the second direction; a channel structure comprising a back gate insulating layer, a back gate electrode, and a channel layer between the back gate insulating layer and the back gate electrode, the channel layer comprising a first region in the channel hole and a second region extending from the first region in the second direction; a common source layer electrically connected to the second region of the channel layer; an upper conductive layer, on the common source layer; an upper insulating layer on the upper conductive layer, wherein the upper insulating layer, the upper conductive layer, the common source layer, and the second region of the channel layer define a back gate hole, the back gate hole comprising a first back gate hole and a second back gate hole, the first back gate hole being defined by a portion of the upper insulating layer, a portion of the upper conductive layer, and a first portion of the common source layer, and the second back gate hole being defined by a second portion of the common source layer and the second region of the channel layer; a back gate contact extending into the upper insulating layer and electrically connected to the back gate electrode; and a common source contact extending into the upper insulating layer and electrically connected to the common source layer, Wherein, the back gate insulating layer extends in the second direction and is on the inner wall of the back gate hole, and The back gate electrode extends in the second direction, is on the back gate insulating layer, and is in the back gate hole.

19. The semiconductor device according to claim 18, further comprising: An insulating spacer is on the inner wall of the first back gate hole.

20. The semiconductor device according to claim 18, wherein The common source layer includes a protrusion extending in the first direction toward the second back gate hole.

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