Semiconductor device and radiation detection apparatus

Abstract

The invention relates to a semiconductor device and a radiation detection apparatus. Provided is a highly reliable semiconductor device for a radiation detection device. The semiconductor device has: a semiconductor layer provided on an insulating surface; a first gate electrode provided on the semiconductor layer and facing the semiconductor layer; a first insulating layer that is provided between the semiconductor layer and the first gate electrode, covers a pattern end portion of the semiconductor layer, and includes silicon oxide; a second insulating layer that is provided on the first insulating layer between the semiconductor layer and the first gate electrode, has a planar view shape common to the first gate electrode, and contains a first metal oxide; and a third insulating layer that is provided on the second insulating layer between the semiconductor layer and the first gate electrode, has a planar view shape common to the first gate electrode, and contains silicon nitride.

Description

Technical Field

[0001] One embodiment of the present invention relates to a semiconductor device and a radiation detection device. In particular, one embodiment of the present invention relates to a radiation detection device including a semiconductor device using an oxide semiconductor as a channel. Background Art

[0002] In recent years, the development of semiconductor devices using an oxide semiconductor as a channel instead of amorphous silicon, low-temperature polycrystalline silicon, and single-crystalline silicon has been continuously advanced (for example, Patent Document 1). A semiconductor device using an oxide semiconductor as a channel can be formed with a simple structure and by a low-temperature process in the same manner as a semiconductor device using amorphous silicon as a channel. It is known that a semiconductor device using an oxide semiconductor as a channel has a higher mobility than a semiconductor device using amorphous silicon as a channel.

[0003] In order to make a semiconductor device using an oxide semiconductor as a channel operate stably, it is important to supply oxygen to the oxide semiconductor layer in the manufacturing process of the semiconductor device to reduce oxygen vacancies formed in the oxide semiconductor layer. As one method of supplying oxygen to the oxide semiconductor layer, for example, a technique of forming an insulating layer covering the oxide semiconductor layer under conditions where the insulating layer contains more oxygen is disclosed.

[0004] Prior Art Documents

[0005] Patent Documents

[0006] Patent Document 1: Japanese Unexamined Patent Application Publication No. 2021-141338 Summary of the Invention

[0007] Problems to be Solved by the Invention

[0008] However, an insulating layer formed under conditions where it contains more oxygen contains many defects. Under its influence, characteristic variations of the semiconductor device in a reliability test are considered to occur due to holes being trapped by these defects. If a semiconductor device having hole traps is used for a radiation detection device, characteristic variations of the semiconductor device occur due to holes generated by the radiation being trapped. Suppression of such characteristic variations is required.

[0009] One problem of one embodiment of the present invention is to realize a highly reliable semiconductor device for a radiation detection device.

[0010] Means for Solving the Problems

[0011] One embodiment of the present invention relates to a semiconductor device having: a semiconductor layer provided on an insulating surface; a first gate electrode provided on the semiconductor layer and opposed to the semiconductor layer; a first insulating layer provided between the semiconductor layer and the first gate electrode, covering the pattern end of the semiconductor layer and containing silicon oxide; a second insulating layer provided on the first insulating layer between the semiconductor layer and the first gate electrode, having a top view shape common to the first gate electrode and containing a first metal oxide; and a third insulating layer provided on the second insulating layer between the semiconductor layer and the first gate electrode, having a top view shape common to the first gate electrode and containing silicon nitride. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Figure 1 It is a cross-sectional view showing an outline of a radiation detection device according to an embodiment of the present invention.

[0013] Figure 2 It is a circuit diagram showing an outline of a radiation detection device according to an embodiment of the present invention.

[0014] Figure 3 It is a cross-sectional view of a semiconductor device according to an embodiment of the present invention.

[0015] Figure 4 It is a cross-sectional view of a semiconductor device according to a comparative example and its electrical characteristics.

[0016] Figure 5 It is a cross-sectional view of a semiconductor device according to a comparative example and its electrical characteristics.

[0017] Figure 6 It is a cross-sectional view of a semiconductor device according to a comparative example and its electrical characteristics.

[0018] Figure 7 It is a cross-sectional view of a semiconductor device according to a comparative example and its electrical characteristics.

[0019] Figure 8 It is a cross-sectional view of a semiconductor device according to a comparative example and its electrical characteristics.

[0020] Figure 9 It is a cross-sectional view of a semiconductor device according to an embodiment of the present invention and its electrical characteristics.

[0021] Figure 10 It is a graph showing the results of a radiation reliability test of a semiconductor device according to an embodiment of the present invention.

[0022] Figure 11 It is a cross-sectional view showing a manufacturing method of a semiconductor device according to an embodiment of the present invention.

[0023] Figure 12 It is a cross-sectional view showing a method of manufacturing a semiconductor device according to an embodiment of the present invention.

[0024] Figure 13 It is a cross-sectional view showing a method of manufacturing a semiconductor device according to an embodiment of the present invention.

[0025] Figure 14 It is a cross-sectional view showing a method of manufacturing a semiconductor device according to an embodiment of the present invention.

[0026] Figure 15 It is a cross-sectional view showing a method of manufacturing a semiconductor device according to an embodiment of the present invention.

[0027] Figure 16 It is a cross-sectional view showing a method of manufacturing a semiconductor device according to an embodiment of the present invention.

[0028] Figure 17 It is a cross-sectional view showing a method of manufacturing a semiconductor device according to an embodiment of the present invention.

[0029] Figure 18 It is a cross-sectional view showing a method of manufacturing a semiconductor device according to an embodiment of the present invention.

[0030] Description of Reference Numerals

[0031] 10: Radiation detection device, 20: Semiconductor device, 30: Pixel, 100: Substrate, 105: Gate electrode, 109: Gate control line, 110: Gate insulating layer, 120: Gate insulating layer, 130, 150, 160: Insulating layer, 140: Oxide semiconductor layer, 161, 163: Opening, 200: Source / drain electrode, 201: Source electrode, 203: Drain electrode, 208: Conductive layer, 209: Wiring, 210: Light-shielding layer, 220: Connection wiring, 230: Insulating layer, 231: Opening, 300: Photoelectric conversion layer, 309: Wiring, 310: Lower electrode, 320: Upper electrode, 330, 340: Insulating layer, 331, 341: Opening, 350, 360: Wiring, 400: Wavelength conversion layer, 500: Charge amplifier circuit, 510, 520, 530: Gate insulating layer, 540: Gate electrode, PR: Photoresist Detailed Description of the Invention

[0032] Hereinafter, each embodiment of the present invention will be described with reference to the accompanying drawings. The following disclosure is merely an example. Constitutions that can be easily conceived by those skilled in the art by appropriately changing the constitution of the embodiment while maintaining the gist of the invention are of course included in the scope of the present invention. Regarding the drawings, in order to make the description clearer, the width, thickness, shape, etc. of each part may be schematically shown as compared with the actual mode. However, the illustrated shape is merely an example and does not limit the interpretation of the present invention. In this specification and each figure, the same reference numerals are given to the same constitutions as those described in the accompanying drawings that have already appeared, and the detailed description may be appropriately omitted.

[0033] In each embodiment of the present invention, the direction from the substrate toward the oxide semiconductor layer is referred to as up or above. Conversely, the direction from the oxide semiconductor layer toward the substrate is referred to as down or below. Thus, for the sake of convenience in explanation, statements such as above or below are used for explanation, but for example, the vertical relationship between the substrate and the oxide semiconductor layer may be arranged in a direction different from that shown in the figure. In the following description, for example, the expression such as the oxide semiconductor layer on the substrate is merely used to explain the vertical relationship between the substrate and the oxide semiconductor layer as described above, and other members may be arranged between the substrate and the oxide semiconductor layer. Above or below means the stacking order in a structure in which multiple layers are stacked. In the case of a first member above a transistor, it may also be a positional relationship where the transistor and the first member do not overlap in a top view. On the other hand, in the case of a first member vertically above a transistor, it means a positional relationship where the transistor and the first member overlap in a top view.

[0034] In this specification, unless otherwise explicitly stated, expressions such as "α includes A, B, or C", "α includes any one of A, B, and C", and "α includes one selected from the group consisting of A, B, and C" do not exclude the case where α includes multiple combinations of A to C. In addition, the above expressions do not exclude the case where α includes other elements.

[0035] It should be noted that the following embodiments can be combined with each other as long as there is no technical contradiction.

[0036] [1. Configuration of Radiation Detection Device 10]

[0037] Use Figure 1 And Figure 2 The configuration of a radiation detection device 10 according to an embodiment of the present invention will be described. Figure 1 is a cross-sectional view showing an outline of a radiation detection device according to an embodiment of the present invention. Figure 2 is a circuit diagram showing an outline of a radiation detection device according to an embodiment of the present invention.

[0038] As Figure 1 shown, the radiation detection device 10 is disposed above the substrate 100. The radiation detection device 10 includes a semiconductor device 20, a photoelectric conversion layer 300, and a wavelength conversion layer 400. In addition to the above-described components, the radiation detection device 10 further includes a light-shielding layer 210, connection wirings 220, an insulating layer 230, a lower electrode 310, an upper electrode 320, insulating layers 330, 340, and wirings 350, 360. The detailed structure of the semiconductor device 20 will be described later.

[0039] The uppermost layer of the semiconductor device 20 is an insulating layer 160. The light-shielding layer 210 is disposed above the insulating layer 160. The light-shielding layer 210 is disposed in a region that overlaps, in a plan view, an oxide semiconductor layer 140 that forms a channel of the semiconductor device 20. In a plan view, the light-shielding layer 210 is disposed so as to cover at least the oxide semiconductor layer 140 in the channel region. The connection wiring 220 is disposed above the insulating layer 160 and is connected to the semiconductor device 20. As will be described in detail later, the connection wiring 220 is connected to a source electrode 201 of the semiconductor device 20.

[0040] An insulating layer 230 is disposed above the insulating layer 160, the light-shielding layer 210, and the connection wiring 220. The insulating layer 230 covers the pattern ends of the light-shielding layer 210 and the pattern ends of the connection wiring 220. The insulating layer 230 alleviates the step difference formed by the semiconductor device 20, the light-shielding layer 210, and the connection wiring 220. The insulating layer 230 can be referred to as a planarization layer. As the insulating layer 230, an organic insulating layer is used. An opening 231 is provided in the insulating layer 230. The opening 231 reaches the connection wiring 220.

[0041] A lower electrode 310 is disposed above the insulating layer 230 and inside the opening 231. The lower electrode 310 is in contact with the connection wiring 220 at the bottom of the opening 231. A photoelectric conversion layer 300 and an upper electrode 320 are disposed above the lower electrode 310. That is, the photoelectric conversion layer 300 is connected to the semiconductor device 20 via the lower electrode 310 and the connection wiring 220. The photoelectric conversion layer 300 includes an N-type semiconductor layer, a P-type semiconductor layer, and an intrinsic semiconductor layer. The intrinsic semiconductor layer is disposed between the N-type semiconductor layer and the P-type semiconductor layer. One of the N-type semiconductor layer and the P-type semiconductor layer is in contact with the lower electrode 310, and the other is in contact with the upper electrode 320.

[0042] The photoelectric conversion layer 300 has the function of converting light energy into electric energy. When light energy is absorbed by the intrinsic semiconductor layer of the photoelectric conversion layer 300, the semiconductor is photoexcited to generate pairs of electrons and holes. The generated electrons and holes flow to the lower electrode 310 and the upper electrode 320 via the N-type semiconductor layer and the P-type semiconductor layer. By detecting the current generated by the electrons and holes generated by photoexcitation, the intensity of the light irradiated onto the photoelectric conversion layer 300 can thus be detected.

[0043] An insulating layer 330 is provided above the upper electrode 320. An opening 331 is provided in the insulating layer 330. The opening 331 reaches the upper electrode 320. An insulating layer 340 is provided above the insulating layer 330. An opening 341 is provided in the insulating layer 340. In a plan view, the opening 341 is larger than the opening 331. The opening 341 reaches the upper electrode 320 and a part of the insulating layer 330. As the insulating layer 330, an inorganic insulating layer is used. As the insulating layer 340, an organic insulating layer is used. The insulating layer 330 has a shape that reflects the step difference formed by the lower electrode 310, the photoelectric conversion layer 300, and the upper electrode 320. On the other hand, the insulating layer 340 alleviates this step difference. That is, the insulating layer 340 is a planarization layer.

[0044] A wiring 360 is provided in a region above the insulating layer 340 and not overlapping with the photoelectric conversion layer 300 in a plan view. A wiring 350 is provided above the insulating layer 340, above the wiring 360, and inside the opening 341. The wiring 350 is connected to the upper electrode 320 at the bottom of the opening 341.

[0045] Details will be described later. In order for the visible light emitted from the wavelength conversion layer 400 to efficiently reach the photoelectric conversion layer 300, a transparent conductive layer is used as the upper electrode 320 and the wiring 350. On the other hand, the wiring 360 is an opaque metal layer. The resistance of the metal layer used as the wiring 360 is lower than the resistance of the transparent conductive layer used as the wiring 350. However, as the wiring 360, a transparent conductive layer can also be used.

[0046] The wavelength conversion layer 400 is provided above the wiring 350 so as to face the photoelectric conversion layer 300. The wavelength conversion layer 400 can be adhered to the wiring 350 and the insulating layer 340 through an adhesive layer, or the positional relationship between the wavelength conversion layer 400 and the wiring 350 and the insulating layer 340 can be fixed through other fixing members. The wavelength conversion layer 400 has the function of converting radiation into visible light. For example, the wavelength conversion layer 400 includes a phosphor that absorbs X-rays, α-rays, or γ-rays and emits visible light. The wavelength conversion layer 400 can be referred to as a scintillator.

[0047] When radiation is incident on the wavelength conversion layer 400 from above, the radiation is converted into visible light by the wavelength conversion layer 400. By making the converted visible light incident on the photoelectric conversion layer 300, light energy is converted into electric energy, and the converted electric energy is detected as a current. Since there is a correlation between the intensity of the radiation incident on the wavelength conversion layer 400 and the detected current, the intensity of the radiation can be evaluated based on the magnitude of this current.

[0048] As Figure 2 shown, pixels 30 are arranged in a matrix in the radiation detection device 10. The pixel 30 includes a semiconductor device 20 and a photoelectric conversion layer 300. The gate electrode of the semiconductor device 20 is connected to the gate control line 109. The source electrode 201 of the semiconductor device 20 is connected to the cathode of the photoelectric conversion layer 300. The anode of the photoelectric conversion layer 300 is connected to the wiring 309. The drain electrode 203 of the semiconductor device 20 is connected to the wiring 209. The wiring 209 is connected to the charge amplifier circuit 500.

[0049] As described above, the radiation incident on the wavelength conversion layer 400 is converted into visible light, and this visible light is converted into electric energy by the photoelectric conversion layer 300. Here, by supplying a bias voltage to the wiring 309 connected to the pixel 30 that detects the radiation, and supplying a signal that controls the semiconductor device 20 to the on state to the gate control line 109 connected to this pixel 30, this electric energy is detected as a current flowing in the semiconductor device 20. The current flowing in the semiconductor device 20 is supplied to the charge amplifier circuit 500 via the wiring 209. And, it is converted from a charge signal into a voltage signal by the charge amplifier circuit 500, and the voltage signal is output to the outside. Through the above operations, the intensity of the radiation irradiated on the pixel 30 can be evaluated.

[0050] As Figure 1 shown, ideally, all of the radiation incident from above is absorbed by the wavelength conversion layer 400, but in reality, a part of the radiation passes through the wavelength conversion layer 400. In addition, ideally, the radiation that has passed through the wavelength conversion layer 400 is blocked by the light shielding layer 210, but in reality, the radiation bypasses the light shielding layer 210 due to reflection by other components and reaches the oxide semiconductor layer 140. If the radiation is incident on the oxide semiconductor layer 140, electron-hole pairs are generated in the oxide semiconductor layer 140. When there are hole traps formed in the oxide insulating layer adjacent to the oxide semiconductor layer 140, the generated holes are trapped in this oxide insulating layer. Under its influence, there may sometimes be a problem that the electrical characteristics of the semiconductor device 20 shift in the negative direction.

[0051] [2. Structure of the semiconductor device 20]

[0052] Use Figure 3 The configuration of the semiconductor device 20 included in the radiation detection device 10 according to an embodiment of the present invention will be described. Figure 3 It is a cross-sectional view of the semiconductor device according to an embodiment of the present invention.

[0053] As Figure 3 shown, the semiconductor device 20 is disposed on a substrate 100 having an insulating surface. The semiconductor device 20 includes a gate electrode 105, gate insulating layers 110, 120, an insulating layer 130, an oxide semiconductor layer 140, gate insulating layers 510, 520, 530, a gate electrode 540, insulating layers 150, 160, a source electrode 201, and a drain electrode 203. The semiconductor device 20 is a transistor using the oxide semiconductor layer 140 as a channel. Depending on the polarity of the transistor, the circuit configuration, or the potential of each node, the source electrode and the drain electrode of the aforementioned transistor may be swapped. When the source electrode 201 and the drain electrode 203 are not particularly distinguished, they are sometimes collectively referred to as the source / drain electrode 200. The semiconductor device 20 may also be a transistor using a semiconductor other than an oxide semiconductor as a channel.

[0054] In the present embodiment, as the semiconductor device 20, a double-gate transistor in which a gate electrode 105 is provided below the oxide semiconductor layer 140 and a gate electrode 540 is provided above the oxide semiconductor layer 140 will be described. However, the semiconductor device 20 may also be a bottom-gate transistor having only the gate electrode 105, or a top-gate transistor having only the gate electrode 540.

[0055] The gate electrode 105 is disposed on the substrate 100. The gate electrode 105 faces the oxide semiconductor layer 140. The gate insulating layers 110, 120 are provided between the gate electrode 105 and the oxide semiconductor layer 140. If the above configuration is described in another way, it can be said that the gate electrode 105 is provided between the substrate 100 and the oxide semiconductor layer 140. It can be said that the gate insulating layer 110 is provided between the gate electrode 105 and the oxide semiconductor layer 140. It can be said that the gate insulating layer 120 is provided between the gate insulating layer 110 and the oxide semiconductor layer 140. Details will be described later. In the present embodiment, the gate insulating layer 110 contains silicon nitride. The gate insulating layer 120 contains silicon oxide. Sometimes the gate electrode 105 is referred to as the "second gate electrode". Sometimes the gate insulating layer 110 is referred to as the "fourth insulating layer". Sometimes the gate insulating layer 120 is referred to as the "fifth insulating layer".

[0056] The gate insulating layers 110 and 120 have a stacked structure. The insulating layer 130 is disposed on the gate insulating layer 120. In other words, the insulating layer 130 is disposed between the gate insulating layer 120 and the oxide semiconductor layer 140. The insulating layer 130 contains a metal oxide. Sometimes the insulating layer 130 is referred to as the "sixth insulating layer". Sometimes the metal oxide contained in the insulating layer 130 is referred to as the "second metal oxide".

[0057] The oxide semiconductor layer 140 is disposed on the insulating layer 130. The insulating layer 130 and the oxide semiconductor layer 140 have a common top view shape. That is, the ends of the insulating layer 130 and the ends of the oxide semiconductor layer 140 substantially coincide.

[0058] Here, the "common top view shape" means that multiple layers each have substantially the same pattern when viewed from above. For example, in the case of etching different multiple layers, there is a case where a tapered shape is formed at the pattern ends of each of the multiple layers due to etching. In this case, since the pattern of the upper layer is smaller than the pattern of the lower layer, these patterns are not exactly the same. However, even in such a case, it is said that the pattern of the upper layer and the pattern of the lower layer have a common top view shape.

[0059] The gate insulating layer 510 is disposed on the oxide semiconductor layer 140 and on the gate insulating layer 120 exposed from the oxide semiconductor layer 140. The gate insulating layer 510 is formed from the upper surface of the oxide semiconductor layer 140 across the pattern end of the oxide semiconductor layer 140 to the upper surface of the gate insulating layer 120. On the gate insulating layer 510, the gate insulating layers 520 and 530 and the gate electrode 540 are sequentially disposed.

[0060] In other words for the above-described configuration, the gate electrode 540 is disposed on the oxide semiconductor layer 140 and faces the oxide semiconductor layer 140. The gate insulating layer 510 is disposed between the oxide semiconductor layer 140 and the gate electrode 540. The gate insulating layer 510 covers the pattern end of the oxide semiconductor layer 140. Details will be described later. In the present embodiment, the gate insulating layer 510 contains silicon oxide. Sometimes the gate electrode 540 is referred to as the "first gate electrode". Sometimes the gate insulating layer 510 is referred to as the "first insulating layer".

[0061] The gate insulating layers 520 and 530 and the gate electrode 540 have a common top view shape. That is, the ends of the gate insulating layer 520, the ends of the gate insulating layer 530, and the ends of the gate electrode 540 substantially coincide. In the D1 direction connecting the source electrode 201 and the drain electrode 203, the lengths of the gate insulating layers 520 and 530 and the gate electrode 540 are smaller than the length of the gate electrode 105.

[0062] If the above configuration is described in another way, the gate insulating layers 520 and 530 are provided above the gate insulating layer 510 between the oxide semiconductor layer 140 and the gate electrode 540. The gate insulating layer 530 is provided above the gate insulating layer 520. Details will be described later. In this embodiment, the gate insulating layer 520 contains a metal oxide. The gate insulating layer 530 contains silicon nitride. Sometimes the gate insulating layer 520 is referred to as the "second insulating layer". Sometimes the gate insulating layer 530 is referred to as the "third insulating layer". Sometimes the metal oxide contained in the gate insulating layer 520 is referred to as the "first metal oxide".

[0063] The insulating layers 150 and 160 are provided above the gate electrode 540 and the gate insulating layer 510. The insulating layers 150 and 160 have a stacked structure. The insulating layer 160 is provided above the insulating layer 150. The insulating layers 150 and 160 cover the gate electrode 540. In other words, the insulating layers 150 and 160 cover the pattern ends of the gate electrode 540. The insulating layer 150 is an insulating layer containing silicon nitride. The insulating layer 160 is an insulating layer containing silicon oxide. Sometimes the insulating layer 150 is referred to as the "seventh insulating layer". Sometimes the insulating layer 160 is referred to as the "eighth insulating layer".

[0064] Openings 161 and 163 are provided in the insulating layers 150 and 160 and the gate insulating layer 510. The openings 161 and 163 reach the oxide semiconductor layer 140. A source electrode 201 is provided above the insulating layer 160 and inside the opening 161. A drain electrode 203 is provided above the insulating layer 160 and inside the opening 163. The source electrode 201 and the drain electrode 203 are respectively connected to the oxide semiconductor layer 140 at the bottoms of the openings 161 and 163. The source electrode 201 is connected to Figure 1 the connection wiring 220 shown.

[0065] The film thickness of the gate insulating layer 110 is, for example, 50 nm or more and 500 nm or less, 50 nm or more and 400 nm or less, 50 nm or more and 300 nm or less, 50 nm or more and 150 nm or less, or 50 nm or more and 100 nm or less. The film thickness of the gate insulating layer 120 is, for example, 10 nm or more and 200 nm or less, or 10 nm or more and 100 nm or less. The total film thickness of the gate insulating layers 110 and 120 is, for example, 100 nm or more and 700 nm or less, 100 nm or more and 500 nm or less, 100 nm or more and 400 nm or less, 100 nm or more and 250 nm or less, 100 nm or more and 200 nm or less, or 100 nm or more and 150 nm or less.

[0066] The film thicknesses of the insulating layer 130 and the gate insulating layer 520 are, for example, 1 nm or more and 20 nm or less, or 1 nm or more and 10 nm or less. In the present embodiment, alumina is used as the insulating layer 130 and the gate insulating layer 520. Alumina has high gas barrier properties against gases such as oxygen or hydrogen. The term "barrier property" means the function of suppressing the permeation of gases such as oxygen or hydrogen through alumina. That is, even if gases such as oxygen or hydrogen are released from the layer below the alumina film, the gases will not move to the layer above the alumina film. Or, even if gases such as oxygen or hydrogen are released from the layer above the alumina film, the gases will not move to the layer below the alumina film.

[0067] The film thickness of the oxide semiconductor layer 140 is 10 nm or more and 50 nm or less, 10 nm or more and 40 nm or less, or 10 nm or more and 30 nm or less. The film thicknesses of the insulating layers 150 and 160 are 50 nm or more and 300 nm or less, 60 nm or more and 200 nm or less, or 70 nm or more and 150 nm or less.

[0068] The film thickness of the gate insulating layer 510 is, for example, 50 nm or more and 200 nm or less, or 50 nm or more and 100 nm or less. By making the thickness of the gate insulating layer 510 within the above range, the reliability of the semiconductor device 20 against visible light and radiation is improved as described later.

[0069] The film thickness of the gate insulating layer 530 is, for example, 50 nm or more and 300 nm or less, 50 nm or more and 200 nm or less, or 50 nm or more and 100 nm or less. By making the thickness of the gate insulating layer 530 within the above range, the withstand voltage of the gate insulating layer required for the semiconductor device 20 against the applied voltage can be ensured.

[0070] [3. Materials of the components of the radiation detection device 10]

[0071] [3-1. Substrate]

[0072] As the substrate 100, a rigid substrate having light transmissivity such as a glass substrate, a quartz substrate, or a sapphire substrate can be used. When it is necessary for the substrate 100 to have flexibility, a resin-containing substrate such as a polyimide substrate, an acrylic substrate, a silicone substrate, or a fluororesin substrate is used as the substrate 100. When a resin-containing substrate is used as the substrate 100, in order to improve the heat resistance of the substrate 100, impurities may be introduced into the above resin. As the substrate 100, a semiconductor substrate such as a silicon substrate, a silicon carbide substrate, or a compound semiconductor substrate, or a conductive substrate such as a stainless steel substrate that does not have light transmissivity can also be used.

[0073] [3-2. Conductive layers such as electrodes and wirings]

[0074] As the gate electrodes 105, 540, source / drain electrodes 200, light-shielding layer 210, connection wirings 220, lower electrodes 310, and wirings 360, common metal materials are used. For example, as the above components, for example, aluminum (Al), titanium (Ti), chromium (Cr), cobalt (Co), nickel (Ni), molybdenum (Mo), hafnium (Hf), tantalum (Ta), tungsten (W), bismuth (Bi), silver (Ag), copper (Cu), and their alloys or compounds are used. As the above electrodes and wirings, the above materials can be used in a single-layer form or in a stacked form. When it is not necessary for the light-shielding layer 210 to have conductivity, a black resin can also be used as the light-shielding layer 210.

[0075] As the upper electrodes 320 and wirings 350, transparent conductive layers are used. As the transparent conductive layer, a mixture of indium oxide and tin oxide (ITO) and a mixture of indium oxide and zinc oxide (IZO) can also be used. As the transparent conductive layer, materials other than the above can also be used.

[0076] [3-3. Insulating Layer]

[0077] As the gate insulating layers 110, 120, 510, 530, insulating layers 150, 160, 330, common insulating materials are used. For example, as the gate insulating layers 120, 510, and insulating layer 160, silicon oxide (SiO x ), silicon oxynitride (SiO x N y ), aluminum oxide (AlO x ), aluminum oxynitride (AlO x N y ) and other oxygen-containing inorganic insulating layers are used. As the gate insulating layers 110, 530, and insulating layer 150, silicon nitride (SiN x ), silicon oxynitride (SiN x O y ), aluminum nitride (AlN x ), aluminum oxynitride (AlN x O y ) and other nitrogen-containing inorganic insulating layers are used. However, as the gate insulating layers 110 and insulating layer 150, oxygen-containing inorganic insulating layers as described above can also be used. As the gate insulating layers 120 and insulating layer 160, nitrogen-containing inorganic insulating layers as described above can also be used.

[0078] As the gate insulating layer 510, an insulating layer having a function of releasing oxygen by heat treatment is used. That is, as the gate insulating layer 510, an oxide insulating layer containing an excessive amount of oxygen is used. The temperature of the heat treatment for the gate insulating layer 510 to release oxygen is, for example, 600°C or lower, 500°C or lower, 450°C or lower, or 400°C or lower. That is, the gate insulating layer 510 releases oxygen at the heat treatment temperature in the manufacturing process of the semiconductor device 20 when a glass substrate is used as the substrate 100, for example.

[0079] As the gate insulating layer 120, an insulating layer with few defects is used. For example, when comparing the oxygen composition ratio in the gate insulating layer 120 with the oxygen composition ratio in an insulating layer having the same composition as the gate insulating layer 120 (hereinafter referred to as "other insulating layer"), the oxygen composition ratio in the gate insulating layer 120 is closer to the stoichiometric ratio of the insulating layer than the oxygen composition ratio in the other insulating layer. Specifically, when silicon oxide (SiO x ) is used for each of the gate insulating layer 120 and the gate insulating layer 510, the oxygen composition ratio in the silicon oxide used as the gate insulating layer 120 is closer to the stoichiometric ratio of silicon oxide than the oxygen composition ratio in the silicon oxide used as the gate insulating layer 510. For example, as the gate insulating layer 120, a layer in which no defects are observed when evaluated by electron spin resonance (ESR) method can also be used.

[0080] The above-mentioned SiO x N y and AlO x N y are silicon compounds and aluminum compounds containing nitrogen (N) in a ratio less than that of oxygen (x > y). SiN x O y and AlN x O y are silicon compounds and aluminum compounds containing oxygen in a ratio less than that of nitrogen (x > y).

[0081] As the insulating layers 230 and 340, an organic insulating layer is used. For example, as the organic insulating layer, polyimide resin, acrylic resin, epoxy resin, silicone resin, fluororesin, and siloxane resin are used.

[0082] As the insulating layers 130 and 520, a metal oxide mainly composed of aluminum is used. For example, as the insulating layers 130 and 520, aluminum oxide (AlO x ) and aluminum oxynitride (AlO x N y) and other inorganic insulating layers. "The insulating layers 130 and 520 mainly composed of aluminum" means that the ratio of aluminum contained in the insulating layers 130 and 520 is 1% or more of the entire metal oxide layer. The ratio of aluminum contained in the insulating layers 130 and 520 can also be 5% or more and 70% or less, 10% or more and 60% or less, or 30% or more and 50% or less of the entire metal oxide layer. The above ratios can be mass ratios or weight ratios.

[0083] [3-4. Oxide semiconductor layer]

[0084] As the oxide semiconductor layer 140, an oxide semiconductor containing two or more metals including indium (In) is used. For example, as the oxide semiconductor layer 140, an oxide semiconductor containing indium (In), gallium (Ga), zinc (Zn), and oxygen (O) can also be used. For example, as the oxide semiconductor layer 140, an oxide semiconductor having a composition ratio of In:Ga:Zn:O = 1:1:1:4 can also be used. However, the oxide semiconductor containing In, Ga, Zn, and O used in this embodiment is not limited to the above composition. As this oxide semiconductor, an oxide semiconductor having a composition different from the above can also be used. For example, in order to improve the mobility, an oxide semiconductor layer with a larger ratio of In than the above can be used. On the other hand, in order to increase the band gap to reduce the influence caused by light irradiation, an oxide semiconductor layer with a larger ratio of Ga than the above can be used.

[0085] For example, as the oxide semiconductor layer 140 with a larger ratio of In than the above, an oxide semiconductor layer in which the ratio of indium element in the oxide semiconductor layer 140 to all metal elements is 50% or more by atomic ratio can also be used. As the oxide semiconductor layer 140, in addition to indium, gallium (Ga), zinc (Zn), aluminum (Al), hafnium (Hf), yttrium (Y), zirconium oxide (Zr), and lanthanide elements can also be used. As the oxide semiconductor layer 140, other elements other than the above can also be used.

[0086] As the oxide semiconductor layer 140, other elements can also be added to the oxide semiconductor containing In, Ga, Zn, and O. For example, metal elements such as Al and Sn can be added. In addition to the above oxide semiconductors, an oxide semiconductor containing In and Zn (IZO), an oxide semiconductor containing In, Sn, and Zn (ITZO), an oxide semiconductor containing In, Sn, Ga, and Zn (ITGZO), an oxide semiconductor containing In and Ga (IGO), etc. can also be used as the oxide semiconductor layer 140.

[0087] When the ratio of indium element is large, the oxide semiconductor layer 140 is likely to crystallize. As described above, by using a material in which the ratio of indium element to all metal elements in the oxide semiconductor layer 140 is 50% or more, an oxide semiconductor layer 140 having a polycrystalline structure can be easily obtained. As other metal elements other than indium, it is preferable that the oxide semiconductor layer 140 contains gallium. Gallium belongs to Group 13 elements like indium. Therefore, the crystallinity of the oxide semiconductor layer 140 is not hindered by gallium, and the oxide semiconductor layer 140 has a polycrystalline structure.

[0088] As described above, when the ratio of indium element to all metal elements in the oxide semiconductor layer 140 is 50% or more, the oxide semiconductor layer 140 has a polycrystalline structure having translucency and including a plurality of crystal grains. Details will be described later. By using Poly-OS (Poly-crystalline Oxide Semiconductor) technology, an oxide semiconductor layer 140 having a polycrystalline structure can be formed. Hereinafter, the configuration of the oxide semiconductor layer 140 will be described. Sometimes, an oxide semiconductor having a polycrystalline structure is referred to as Poly-OS.

[0089] The crystal grain diameter of the crystal grains included in Poly-OS is, for example, 0.1 μm or more, 0.3 μm or more, or 0.5 μm or more. The crystal grain diameter of the crystal grains can be obtained, for example, by using cross-sectional SEM observation, cross-sectional TEM observation, or electron backscattered diffraction (EBSD) method.

[0090] As described above, since the crystal grain diameter of the crystal grains included in Poly-OS is 0.1 μm or more, in the oxide semiconductor layer 140 having a film thickness of 10 nm or more and 30 nm or less, there is a region including only one crystal grain in the film thickness direction.

[0091] The oxide semiconductor layer 140 can be formed by a sputtering method. The composition of the oxide semiconductor layer 140 formed by the sputtering method depends on the composition of the sputtering target. Even when the oxide semiconductor layer 140 has a polycrystalline structure, the composition of the sputtering target is substantially the same as the composition of the oxide semiconductor layer 140. In this case, the composition of the metal elements in the oxide semiconductor layer 140 can be determined based on the composition of the metal elements in the sputtering target.

[0092] In the case where the oxide semiconductor layer 140 has a polycrystalline structure, an X-ray Diffraction (XRD) method can also be used to determine the composition of the oxide semiconductor layer. Specifically, the composition of the metal elements in the oxide semiconductor layer can be determined based on the crystal structure and lattice constant of the oxide semiconductor layer obtained by the XRD method. In addition, the composition of the metal elements in the oxide semiconductor layer 140 can also be determined using fluorescence X-ray analysis or Electron Probe Micro Analyzer (EPMA) analysis, etc. However, since the oxygen element contained in the oxide semiconductor layer 140 varies depending on the sputtering process conditions, etc., it is sometimes impossible to determine by the above methods.

[0093] [3-5.Poly-OS Technology]

[0094] The Poly-OS contained in the oxide semiconductor layer can be formed using sputtering and heat treatment. Here, the method for forming the oxide semiconductor layer will be described.

[0095] First, the oxide semiconductor layer is formed by sputtering. The formed oxide semiconductor layer has an amorphous structure. Here, the amorphous structure refers to a structure in which there is no long-range ordered structure and no periodic lattice arrangement can be seen. For example, when using the XRD method to observe an oxide semiconductor layer having an amorphous structure, no specific peak based on the crystal structure can be obtained in the diffraction pattern. It should be noted that an oxide semiconductor layer having an amorphous structure sometimes has a short-range ordered structure in a minute region. However, such an oxide semiconductor layer can be classified as an oxide semiconductor layer having an amorphous structure because it does not exhibit the characteristics of Poly-OS.

[0096] In the Poly-OS technology, the oxide semiconductor layer is formed at a low temperature. For example, the temperature of the substrate on which the oxide semiconductor layer is formed is 150 °C or lower, preferably 100 °C or lower, more preferably 50 °C or lower. If the temperature of the substrate during the formation of the oxide semiconductor layer is high, microcrystals are likely to be generated in the formed oxide semiconductor. The oxygen partial pressure in the chamber during film formation is 1% or more and 10% or less, preferably 1% or more and 5% or less, more preferably 2% or more and 4% or less. If the oxygen partial pressure is high, microcrystals are generated in the oxide semiconductor layer due to the excessive oxygen contained in the oxide semiconductor. On the other hand, under the condition that the oxygen partial pressure is less than 1%, the composition of oxygen in the oxide semiconductor layer becomes non-uniform, and an oxide semiconductor layer containing a large amount of microcrystals or an oxide semiconductor layer that does not crystallize even after heat treatment is formed.

[0097] Next, the oxide semiconductor layer formed by sputtering is heat-treated. The heat treatment is carried out in the atmosphere, and the atmosphere of the heat treatment is not limited to this. The temperature of the heat treatment is 300°C or higher and 500°C or lower, preferably 350°C or higher and 450°C or lower. The time of the heat treatment is 15 minutes or longer and 120 minutes or shorter, preferably 30 minutes or longer and 60 minutes or shorter. By performing the heat treatment, the oxide semiconductor layer having an amorphous structure is crystallized to form an oxide semiconductor layer containing Poly-OS.

[0098] [4. Electrical Characteristics of Semiconductor Device 20]

[0099] Figures 4 to 8 is a cross-sectional view of a semiconductor device according to a comparative example and its electrical characteristics. Figure 9 is a cross-sectional view of a semiconductor device according to an embodiment of the present invention and its electrical characteristics. In Figures 4 to 9 it shows the structure and electrical characteristics of the semiconductor device whose electrical characteristics have been evaluated together. Using Figures 4 to 9 it explains the effects obtained by the structure according to the present embodiment with reference to the cross-sectional structures and electrical characteristics of the semiconductor devices according to the comparative example and the present embodiment respectively.

[0100] Figures 4 to 9 The measurement conditions of the electrical characteristics shown are as follows. The vertical axis of each electrical characteristic is the drain current value (Id [A]), and the horizontal axis is the gate voltage value (Vg [V]).

[0101] · Size of channel region CH: W / L = 4.5 μm / 3.0 μm

[0102] · Source-drain voltage: 0.1 V (dashed line), 10 V (solid line)

[0103] · Gate voltage: -15 V to +15 V

[0104] · Measurement environment: room temperature, dark room

[0105] [4-1. Conventional Semiconductor Device]

[0106] Figure 4 A conventional semiconductor device and its electrical characteristics are shown as a comparative example. Figure 4 The semiconductor device 20V shown is similar to Figure 3 the semiconductor device 20 shown. However, in the semiconductor device 20V, a member equivalent to the gate insulating layers 520 and 530 of the semiconductor device 20 is not provided, and the gate electrode 540V is in contact with the gate insulating layer 510V. The electrical characteristics of the semiconductor device 20V are good. However, for the semiconductor device 20V, for example, the threshold variation is large in a radiation irradiation test using X-rays.

[0107] It is known that the threshold change in the radiation irradiation test is caused by holes generated in the oxide semiconductor layer 140V by radiation irradiation being trapped by hole traps in the oxide insulating layer adjacent to the oxide semiconductor layer 140V. Therefore, in order to improve the tolerance of the semiconductor device 20V to the radiation irradiation test, it is necessary to reduce the film thickness of the gate insulating layer 510V.

[0108] However, in the structure of the semiconductor device 20V, when the film thickness of the gate insulating layer 510V is small, not only is the breakdown voltage of the gate insulating layer 510V low, but it is also difficult to adjust the impurity implantation process for making the oxide semiconductor layer 140V in the source and drain regions that do not overlap with the gate electrode 540V in a plan view have a low resistance. By thinning the gate insulating layer 510V and adding an insulating layer containing silicon nitride between the gate insulating layer 510V and the gate electrode 540V, the above problems can be solved.

[0109] [4-2. Semiconductor device with a silicon nitride layer added to the gate insulating layer]

[0110] Figure 5 The semiconductor device 20W and its electrical characteristics are shown as a comparative example. In the semiconductor device 20W, different from the existing semiconductor device 20V, a gate insulating layer 530W containing silicon nitride is provided between the gate insulating layer 510W and the gate electrode 540W. As Figure 5 shown, in the semiconductor device 20W, the gate insulating layer 530W, like the gate insulating layer 510W, not only lies under the gate electrode 540W but also extends to the outside of the pattern of the oxide semiconductor layer 140W. The electrical characteristics of the semiconductor device 20W are poor, and the semiconductor device 20W does not have the function of a switching element (it will not become an off state).

[0111] Since silicon nitride contains a large amount of hydrogen, hydrogen diffuses into the oxide semiconductor layer 140W during the formation of the gate insulating layer 530W and during the heat treatment after the formation of the gate insulating layer 530W. If hydrogen reaches the oxide semiconductor layer 140W, the oxide semiconductor layer 140W is N-type doped under the reducing action of hydrogen. As a result, as Figure 5 shown, the semiconductor device 20W does not have a switching function. Especially in the semiconductor device 20W, since the gate insulating layer 530W is formed over the entire surface, a large amount of hydrogen diffuses into the oxide semiconductor layer 140W.

[0112] As described above, the reason why the semiconductor device 20W does not have a switching function is that hydrogen contained in silicon nitride diffuses into the oxide semiconductor layer 140W, resulting in N-type formation of the oxide semiconductor layer 140W. Therefore, by reducing the amount of hydrogen diffusing into the oxide semiconductor layer 140W, the above problem can be suppressed. Since the gate insulating layer 530W only needs to be provided between the gate insulating layer 510W and the gate electrode 540W, by removing the gate insulating layer 530W other than between the gate insulating layer 510W and the gate electrode 540W, the amount of hydrogen can be reduced.

[0113] [4-3. Semiconductor device in which a silicon nitride layer is patterned according to a gate electrode]

[0114] Figure 6 The semiconductor device 20X and its electrical characteristics are shown as a comparative example. In the semiconductor device 20X, different from the Figure 5 shown semiconductor device 20W, the gate insulating layer 530X in the region that does not overlap with the gate electrode 540X in a plan view is removed. As Figure 6 shown, in the semiconductor device 20X, the gate insulating layer 530X is only provided between the gate insulating layer 510X and the gate electrode 540X, and the gate insulating layer 530X is not provided in the region that does not overlap with the gate electrode 540X in a plan view. The electrical characteristics of the semiconductor device 20X are poor, and the semiconductor device 20X does not have the function of a switching element (it will not become an off state).

[0115] Figure 7 The semiconductor device 20Y and its electrical characteristics are shown as a comparative example. The semiconductor device 20Y is different from the Figure 5 shown semiconductor device 20W in that the gate insulating layers 510Y and 530Y in the regions that do not overlap with the gate electrode 540Y in a plan view are removed. As Figure 7 shown, in the semiconductor device 20Y, the two square gate insulating layers 510Y and 530Y form the same pattern as the gate electrode 540Y. The electrical characteristics of the semiconductor device 20Y are poor, and the semiconductor device 20Y does not have the function of a switching element (it will not become an off state).

[0116] As described above, in the case where only the gate insulating layer 530X is removed or both the gate insulating layers 510Y and 530Y are removed in a region that does not overlap with the gate electrodes 540X and 540Y when viewed from above, the N-type conversion of the oxide semiconductor layers 140X and 140Y cannot be suppressed. Here, since a metal oxide mainly composed of aluminum can suppress the diffusion of hydrogen, for example, by providing the above-described metal oxide between the gate insulating layer 530X and the gate insulating layer 510X, the N-type conversion of the oxide semiconductor layers 140X and 140Y can be suppressed.

[0117] [4-4. Semiconductor device having an aluminum oxide layer provided between a silicon nitride layer and a silicon oxide layer]

[0118] Figure 8 The semiconductor device 20Z and its electrical characteristics are shown as a comparative example. In the semiconductor device 20Z, different from the semiconductor device 20X shown Figure 6 a gate insulating layer 520Z containing a metal oxide mainly composed of aluminum is provided between the gate insulating layer 510Z and the gate insulating layer 530Z. In the present embodiment, an example in which alumina is used as the metal oxide will be described. As Figure 8 shown, in the semiconductor device 20Z, the gate insulating layer 520Z, like the gate insulating layer 530Z, is not only located under the gate electrode 540Z but also extends to the outside of the pattern of the oxide semiconductor layer 140Z. The electrical characteristics of the semiconductor device 20Z are different from the respective electrical characteristics of the semiconductor devices 20W to 20Y and have a function as a switching element (capable of switching between a conductive state and a cutoff state). On the other hand, in the semiconductor device 20Z, there is a problem of low on-current.

[0119] Details will be described later. In the semiconductor device 20Z, in order to reduce the resistance of the oxide semiconductor layer 140Z in the source region and the drain region, a process of implanting impurities into the oxide semiconductor layer 140 is performed. By implanting the impurities, oxygen vacancies are formed in the oxide semiconductor layer 140Z. It is known that hydrogen diffuses from the insulating layer 150Z with respect to the oxygen vacancies, thereby realizing the low resistance of the oxide semiconductor layer 140Z.

[0120] On the other hand, in Figure 8In the structure of the semiconductor device 20Z shown, a gate insulating layer 520Z (aluminum oxide) is provided over the entire surface under the insulating layer 150Z. Since aluminum oxide inhibits the diffusion of hydrogen, the diffusion of hydrogen contained in the insulating layer 150Z into the oxide semiconductor layer 140Z is suppressed. As a result, even if oxygen vacancies are formed in the oxide semiconductor layer 140Z by impurity implantation, hydrogen does not diffuse into the oxygen vacancies. Therefore, the oxide semiconductor layer 140Z in the source region and the drain region is not made low-resistance. As a result, as Figure 8 shown, in some semiconductor devices 20Z, there is a problem of low on-current.

[0121] In view of the above results, as Figure 9 shown, in the semiconductor device 20 according to the present embodiment, the gate insulating layer 520 in the source region and the drain region is removed so that hydrogen contained in the insulating layer 150 can diffuse into the oxide semiconductor layer 140 to make the oxide semiconductor layer 140 in the source region and the drain region low-resistance. As a result, the decrease in the on-current confirmed in Figure 8 is eliminated, and the semiconductor device 20 has a function as a good switching element.

[0122] [5. Radiation tolerance of semiconductor device 20]

[0123] Figure 10 is a graph showing the results of a radiation reliability test of a semiconductor device according to an embodiment of the present invention. Figure 10 The reliability test shown is the result of an X-ray irradiation test. Figure 10 The graph shown represents the amount of change in the threshold voltage Vth obtained from the electrical characteristics before and after X-ray irradiation.

[0124] The conditions of the X-ray irradiation test are as follows.

[0125] · Size of channel region: W / L = 4.5 μm / 3.0 μm

[0126] · Number of evaluation transistors: 4

[0127] · X-ray irradiation device: MBR-1520R-3 (manufactured by Hitachi Energy Solutions Co., Ltd.)

[0128] · X-ray irradiation conditions: 90 Gy (continuous irradiation at 20 mA)

[0129] · X-ray irradiation conditions: Filter Al = 1 mm

[0130] Figure 10 The vertical axis (ΔVth@90Gy) of is the amount of change in the threshold voltage Vth before and after X-ray irradiation. In Figure 10In this case, the semiconductor device involved in the embodiment is Figure 3 the semiconductor device 20 shown. The film thicknesses of the gate insulating layer 510 (silicon oxide) and the gate insulating layer 530 (silicon nitride) of the semiconductor device 20 are both 50 nm. The semiconductor device involved in the comparative example is Figure 4 the semiconductor device 20V shown. The film thickness of the gate insulating layer 510V (silicon oxide) of the semiconductor device 20V is 75 nm.

[0131] As Figure 10 shown, the threshold change before and after the X-ray irradiation test of the semiconductor device 20 involved in the embodiment is smaller than that of the semiconductor device 20V involved in the comparative example. The reason for this result is that due to the difference in the film thicknesses of the gate insulating layer 510 and the gate insulating layer 510V, the amount of hole traps contained in the gate insulating layer 510 in the embodiment is less than the amount of hole traps contained in the gate insulating layer 510V in the comparative example.

[0132] [6. Manufacturing Method of Semiconductor Device 20]

[0133] Use Figures 11 to 18 to describe the manufacturing method of the semiconductor device according to an embodiment of the present invention. Figures 11 to 18 is a cross-sectional view showing the manufacturing method of the semiconductor device according to an embodiment of the present invention. In the following description of the manufacturing method, the manufacturing method of the semiconductor device 20 using silicon nitride as the gate insulating layers 110, 530, using silicon oxide as the gate insulating layers 120, 510, and using aluminum oxide as the insulating layer 130 and the gate insulating layer 520 will be described.

[0134] As Figure 11 shown, a gate electrode 105 is formed as a bottom gate on the substrate 100, and gate insulating layers 110, 120 are formed on the gate electrode 105. Silicon nitride is formed as the gate insulating layer 110. Silicon oxide is formed as the gate insulating layer 120. The gate insulating layers 110, 120 are formed by CVD (Chemical Vapor Deposition) method.

[0135] By using silicon nitride as the gate insulating layer 110, the gate insulating layer 110 can block impurities diffusing from the substrate 100 side toward the oxide semiconductor layer 140, for example.

[0136] An insulating layer 130 and an oxide semiconductor layer 140 are formed over the gate insulating layer 120. Aluminum oxide is used as the insulating layer 130. The oxide semiconductor layer 140 is formed in contact with the insulating layer 130. The insulating layer 130 and the oxide semiconductor layer 140 are formed by sputtering or atomic layer deposition (ALD: Atomic Layer Deposition).

[0137] A resist mask is formed over the oxide semiconductor layer 140, and the insulating layer 130 and the oxide semiconductor layer 140 are etched using the resist mask. As the etching of the oxide semiconductor layer 140, wet etching or dry etching can be used. As the wet etching, an acidic etchant can be used for etching. For example, as the etchant, an etching solution containing phosphoric acid as a main component or hydrofluoric acid can be used.

[0138] After that, the patterned oxide semiconductor layer 140 is used as a mask to etch the insulating layer 130. As the etching of the insulating layer 130, wet etching or dry etching can be used. For example, as the wet etching, diluted hydrofluoric acid (DHF) is used. As described above, by etching the insulating layer 130 using the oxide semiconductor layer 140 as a mask, the photolithography process can be omitted.

[0139] As described above, a gate insulating layer 510 is formed over the patterned insulating layer 130 and oxide semiconductor layer 140. Silicon oxide is formed as the gate insulating layer 510. The gate insulating layer 510 is formed by CVD. For example, as the gate insulating layer 510, in order to form an insulating layer with fewer defects as described above, the gate insulating layer 510 can also be formed at a film formation temperature of 350 °C or higher.

[0140] In the present embodiment, a configuration in which the insulating layer 130 is provided under the oxide semiconductor layer 140 is illustrated, but the insulating layer 130 can also be omitted.

[0141] As Figure 12 shown, a gate insulating layer 520 is formed over the gate insulating layer 510. The gate insulating layer 520 is formed by sputtering. Due to the film formation of the gate insulating layer 520, oxygen and the process gas used in the sputtering method are injected into the gate insulating layer 510. As the process gas in the sputtering method, argon is often used. Therefore, argon may be contained in the gate insulating layer 510.

[0142] As Figure 13 shown, a gate insulating layer 530 is formed over the gate insulating layer 520. Silicon nitride is formed as the gate insulating layer 530. The gate insulating layer 530 is formed by CVD.

[0143] As Figure 14As shown, a conductive layer is formed over the gate insulating layer 530, and a photoresist PR is formed over the conductive layer. The conductive layer and the gate insulating layer 530 are etched using the photoresist PR as a mask. The gate electrode 540 is formed by this etching.

[0144] For example, in the case where an alloy of molybdenum and tungsten (MoW) is used as the gate electrode 540, dry etching using SF6 and O2 as process gases is used for etching MoW. This dry etching has a high etching rate for silicon nitride but a low etching rate for aluminum oxide. Thus, as Figure 14 shown, the gate electrode 540 and the gate insulating layer 530 are etched together using the photoresist PR as a mask, and the gate insulating layer 520 functions as a stopper for this etching.

[0145] As the gate electrode 540, in addition to a single layer of MoW, a stack of titanium (lower layer) and MoW (upper layer) can also be used. As the gate electrode 540, materials other than MoW can be used in a single-layer form, or materials other than MoW can be used in a stacked form. The conductive layer constituting the gate electrode 540 is formed by sputtering.

[0146] As Figure 15 shown, the gate insulating layer 520 is etched using the photoresist PR, the gate electrode 540, and the gate insulating layer 530 as masks. By this etching, a configuration in which the pattern ends of the gate electrode 540, the gate insulating layer 530, and the gate insulating layer 520 are aligned with each other is obtained. That is, by the above-described etching, a configuration in which the gate insulating layer 520 has a top view shape common to the gate electrode 540 and the gate insulating layer 530 is obtained.

[0147] In the case where MoW is used as the gate electrode 540, the etching of the gate insulating layer 520 can be performed in a state where the photoresist PR is formed, or can be performed in a state where the photoresist PR is removed.

[0148] As Figure 16 shown, after removing the photoresist PR, ion implantation is performed on the oxide semiconductor layer 140. As Figure 16 shown, since the gate insulating layer 510 is formed over the oxide semiconductor layer 140, ions that have passed through the gate insulating layer 510 are implanted into the oxide semiconductor layer 140. However, since the implanted ions are blocked by the gate electrode 540, ions are not implanted into the oxide semiconductor layer 140 in a region that overlaps the gate electrode 540 in a top view.

[0149] For example, boron (B) is implanted into the oxide semiconductor layer 140 as an impurity element by ion implantation. However, instead of boron, other impurity elements such as phosphorus (P) can also be implanted into the oxide semiconductor layer 140.

[0150] Through the above-described ion implantation, impurity elements are implanted into the oxide semiconductor layer 140 in the source region and the drain region. In the oxide semiconductor layer 140 in the source region and the drain region, oxygen defects are formed by the implantation of the impurity elements. By capturing hydrogen in the oxygen defects, the oxide semiconductor layer 140 in the source region and the drain region is made to have a low resistance.

[0151] In the oxide semiconductor layer 140 including Poly-OS, even in the source region and the drain region where impurity elements are implanted, the oxide semiconductor layer 140 sometimes has crystallinity. This is also one of the characteristics of Poly-OS. In this case, the crystal structures of the source region and the drain region are the same as the crystal structure of the channel region that overlaps with the gate electrode 540 in a top view.

[0152] As Figure 17 shown, an insulating layer 150 and an insulating layer 160 are formed as an interlayer film on the gate insulating layer 510 and the gate electrode 540. The insulating layers 150 and 160 are formed by CVD method. As the insulating layer 150, silicon nitride is formed, and as the insulating layer 160, silicon oxide is formed. The materials used as the insulating layers 150 and 160 are not limited to the above.

[0153] As Figure 18 shown, openings 161 and 163 are formed in the insulating layers 150 and 160 and the gate insulating layer 510. The openings 161 and 163 are formed so as to expose the oxide semiconductor layer 140, respectively. A conductive layer 208 is formed on the insulating layer 160 and inside the openings 161 and 163, and the conductive layer 208 is patterned, whereby a source electrode 201 and a drain electrode 203 are formed as Figure 3 shown.

[0154] Each of the embodiments described above as embodiments of the present invention can be implemented by appropriately combining them as long as they are not contradictory to each other. In addition, a solution obtained by a person skilled in the art by appropriately adding, deleting, or changing the design of the constituent elements or a solution obtained by adding, omitting, or changing the conditions of the process based on the semiconductor device and the radiation detection device of each embodiment is also included in the scope of the present invention as long as it has the gist of the present invention.

[0155] Even if there are other effects different from the effects brought about by the solutions of the above-described embodiments, if they are clearly known from the description of this specification or can be easily predicted by a person skilled in the art, they are of course also understood to be the effects brought about by the present invention.

Claims

1. A semiconductor device comprising: a semiconductor layer disposed on the insulating surface; A first gate electrode, disposed on the semiconductor layer and opposite to the semiconductor layer; a first insulating layer, which is disposed between the semiconductor layer and the first gate electrode, covers the pattern end of the semiconductor layer and comprises silicon oxide; a second insulating layer, which is disposed on the first insulating layer between the semiconductor layer and the first gate electrode, has a common top-view shape with the first gate electrode, and includes a first metal oxide; and The third insulating layer is provided on the second insulating layer between the semiconductor layer and the first gate electrode, has a plan view shape common to that of the first gate electrode, and includes silicon nitride.

2. The semiconductor device according to claim 1, further comprising: A second gate electrode disposed between the insulating surface and the semiconductor layer; and A fourth insulating layer is disposed between the second gate electrode and the semiconductor layer.

3. The semiconductor device according to claim 1, wherein The semiconductor layer includes an oxide semiconductor.

4. The semiconductor device according to claim 1, wherein The semiconductor layer includes an oxide semiconductor having a polycrystalline structure.

5. The semiconductor device according to claim 1, further comprising: a second gate electrode disposed between the insulating surface and the semiconductor layer; a fourth insulating layer, disposed between the second gate electrode and the semiconductor layer, and comprising silicon nitride; a fifth insulating layer disposed between the fourth insulating layer and the semiconductor layer and comprising silicon oxide; and a sixth insulating layer, disposed between the fifth insulating layer and the semiconductor layer, and comprising a second metal oxide, The semiconductor layer includes an oxide semiconductor having a polycrystalline structure.

6. The semiconductor device according to claim 5, wherein: The first metal oxide and the second metal oxide are metal oxides containing aluminum as a main component.

7. The semiconductor device according to claim 6, wherein: The thickness of the second insulating layer is greater than or equal to 1 nm and less than or equal to 20 nm.

8. The semiconductor device according to claim 5, wherein: The thickness of the first insulating layer is not less than 50 nm and not more than 200 nm. The thickness of the third insulating layer is greater than or equal to 50 nm and less than or equal to 300 nm.

9. The semiconductor device according to claim 5, further comprising: a seventh insulating layer, which is disposed on the first gate electrode, covers a pattern end portion of the first gate electrode, and comprises silicon nitride; and The eighth insulating layer is disposed on the seventh insulating layer and comprises silicon oxide.

10. A radiation detection device comprising: The semiconductor device according to any one of claims 1 to 9; a photoelectric conversion layer connected to the semiconductor device; and A wavelength conversion layer is disposed opposite to the photoelectric conversion layer and emits visible light based on the irradiated radiation.

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