Image sensor and forming method thereof

Abstract

Some embodiments relate to an image sensor device comprising: a photodetector; the pixel circuit comprises a floating diffusion node and an output node; a pass transistor electrically coupled from the floating diffusion node to the photodetector; a source follower transistor including a gate electrode electrically coupled to the floating diffusion node; a row selection transistor electrically coupled from the source / drain region of the source follower transistor to the output node; and a capacitor electrically coupled from the output node to the floating diffusion node. The embodiment of the invention also relates to a method for forming the image sensor device.

Description

Technical Field

[0001] Embodiments of the present application relate to an image sensor and a method of forming the same. Background Art

[0002] Integrated circuits (ICs) with image sensors are used in various modern electronic devices, such as cameras and mobile phones. Types of image sensors include, for example, complementary metal oxide semiconductor (CMOS) image sensors and charge-coupled device (CCD) image sensors. Compared with CCD image sensors, CMOS image sensors are becoming increasingly popular due to low power consumption, small size, fast data processing, direct output of data, and low manufacturing cost. Summary of the Invention

[0003] According to one aspect of embodiments of the present application, there is provided an image sensor device, including: a photodetector; and a pixel circuit, including: a floating diffusion node and an output node; a transfer transistor electrically coupled from the floating diffusion node to the photodetector; a source follower transistor including a gate electrode electrically coupled to the floating diffusion node; a row selection transistor electrically coupled from a source / drain region of the source follower transistor to the output node; and a capacitor electrically coupled from the output node to the floating diffusion node.

[0004] According to another aspect of embodiments of the present application, there is provided an image sensor device, including: a source follower transistor and a row selection transistor located on a first substrate, wherein the row selection transistor is electrically coupled from the source follower transistor to the output node; a photodetector and a floating diffusion node located in a second substrate; a transfer transistor located on the second substrate and electrically coupled from the photodetector to the floating diffusion node; a first interconnect structure and a second interconnect structure located between the first substrate and the second substrate; and a bonding structure located between the first interconnect structure and the second interconnect structure, wherein the bonding structure includes a bonding electrode and a shielding electrode surrounding the bonding electrode; wherein the first interconnect structure electrically couples the shielding electrode to the output node, and wherein the second interconnect structure electrically couples the bonding electrode to the floating diffusion node.

[0005] According to another aspect of an embodiment of the present application, a method of forming an image sensor device is provided, including: forming an output stage on a first substrate, the output stage including a row selection transistor electrically coupled from a source follower transistor to an output node; forming a first interconnect structure above the output stage, wherein the first interconnect structure includes a first conductive path electrically coupled to a gate electrode of the source follower transistor and a second conductive path electrically coupled to the output node; forming a first bonding layer above the first interconnect structure, wherein the first bonding layer includes a bonding electrode and a shielding electrode surrounding the bonding electrode, and wherein the shielding electrode is formed to be electrically coupled to the second conductive path; forming a photodetector in a second substrate; forming a transfer transistor above the second substrate, wherein the transfer transistor is electrically coupled from the photodetector to a floating diffusion node; forming a second interconnect structure above the transfer transistor, the second interconnect structure including a third conductive path electrically coupled to the floating diffusion node; and bonding the second interconnect structure to the first interconnect structure through the first bonding layer, wherein the bonding electrically couples the first conductive path and the third conductive path together through the bonding electrode. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Aspects of the present invention are best understood from the following detailed description when read with the accompanying drawings. It should be noted that, in accordance with standard practice in the industry, various components are not drawn to scale. In fact, for clarity of discussion, the dimensions of various components may be arbitrarily increased or decreased.

[0007] Figure 1A 、 Figure 1B and Figure 1C FIGS. show circuit schematics of some embodiments of an image sensor having a capacitor between an output node and a floating diffusion node.

[0008] Figure 2 FIG. shows a cross-sectional view of an output stage of some embodiments of an image sensor having a capacitor between an output node and a floating diffusion node.

[0009] Figure 3 FIGS. show circuit schematics of some embodiments of an image sensor having a capacitor between an output node and a floating diffusion node (wherein a plurality of photodetectors are coupled to the floating diffusion node).

[0010] Figure 4 FIG. shows a cross-sectional view of some embodiments of an image sensor having a shielding structure and a metal bonding pad with a capacitor configured to be coupled between an output node and a floating diffusion node.

[0011] Figure 5A and Figure 5B FIGS. show top views of some embodiments of a plurality of shielding structures and metal bonding pads in a pixel circuit array.

[0012] Figures 6 - 18 A series of cross-sectional views showing some embodiments of a method of forming an image sensor having a capacitor between an output node and a floating diffusion node to which a plurality of photodetectors are coupled.

[0013] Figure 19 A flowchart showing some embodiments of a method of forming an image sensor having a capacitor between an output node and a floating diffusion node. DETAILED DESCRIPTION

[0014] The present invention provides many different embodiments or examples for implementing different features of the present invention. Specific examples of components and arrangements will be described below to simplify the present invention. Of course, these are only examples and are not intended to be limiting. For example, in the following description, forming a first component above or on a second component may include embodiments where the first component and the second component are in direct contact, and may also include embodiments where additional components are formed between the first component and the second component such that the first component and the second component may not be in direct contact. Also, the present invention may repeat reference numerals and / or letters in various examples. This repetition is for the sake of brevity and clarity, but does not itself indicate a relationship between the various embodiments and / or configurations being discussed.

[0015] In addition, for ease of description, spatial relationship terms such as "below", "beneath", "lower", "above", "upper", etc. may be used herein to describe the relationship of one element or component to another element or component as shown in the figures. Spatial relationship terms are intended to include different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatial relationship descriptors used herein may be interpreted accordingly.

[0016] It should be understood that in this written description and the following claims, the words "first", "second", "third", etc. are only general identifiers used for ease of description to distinguish different elements of one figure or a series of figures. These words themselves do not imply any chronological order or structural proximity of these elements, and are not intended to describe corresponding elements in different shown embodiments and / or unshown embodiments. For example, a "first dielectric layer" associated with a first figure may not necessarily correspond to a "first dielectric layer" associated with another figure, and may not necessarily correspond to a "first dielectric layer" in an unshown embodiment.

[0017] The image sensor includes a pixel array having a plurality of photodetectors and a plurality of pixel circuits coupled to the photodetectors. The plurality of pixel circuits include a floating diffusion node, a transfer transistor extending between the floating diffusion node and the photodetector, a reset transistor having a source / drain terminal coupled to the floating diffusion node, and an output stage coupled to the floating diffusion node. The output stage includes a source follower transistor having a gate electrode coupled to the floating diffusion node, and further includes a row selection transistor having a first source / drain terminal coupled to the source / drain terminal of the source follower transistor. The output node is located at the second source / drain terminal of the row selection transistor. The plurality of pixel circuits are organized into a plurality of rows and columns, and the output nodes of each column of the plurality of pixel circuits are coupled together by output lines.

[0018] In some embodiments, the image sensor spans multiple substrates bonded together by a bonding layer. The reset transistor and the output stage are located on a first substrate. The photodetector and the floating diffusion node are located within a second substrate coupled to the first substrate through the first bonding layer. The floating diffusion node is coupled to the output stage through a metal bonding pad within the first bonding layer. A shielding structure is also located within the first bonding layer and continuously surrounds the metal bonding pad.

[0019] The total parasitic capacitance C at the output line tot is the sum of the pixel parasitic capacitance values C js between the output nodes of the plurality of pixel circuits coupled to the output line. The total capacitance C tot increases the RC delay of the image sensor. The increase in the RC delay results in a longer time required to transfer a signal from the pixel circuit to the image signal processor (ISP) circuit. Due to the total capacitance C tot , the image sensor gain in a low information environment (e.g., when imaging an area with less light using a conversion gain circuit) is also reduced. The RC delay further results in a reduction in the image sensor bandwidth. Therefore, a method for mitigating the total capacitance C tot is needed.

[0020] The present disclosure provides a capacitor between the output node and the floating diffusion node. Applying Miller's theorem to the capacitor, an output stage with a gain less than one causes the capacitance C H of the capacitor seen from the output node to appear negative. Therefore, the combination of the pixel parasitic capacitance values C js and C H is less than the individual pixel parasitic capacitance value C jsApplying this result to the pixel circuit coupled to the output line results in a reduced sensed capacitance seen from the output of the circuit. This reduction in the sensed capacitance reduces the RC delay of the image sensor and increases the gain and the bandwidth of the image sensor in low-information applications (e.g., for imaging regions with low light amounts). The increase in gain in low-information applications results in an increase in the dynamic range of the image sensor, thereby improving the quality of the images produced by the image sensor.

[0021] Figure 1A 、 Figure 1B and Figure 1C Circuit schematics 100a, 100b, 100c showing some embodiments of an image sensor having a capacitor between an output node and a floating diffusion node.

[0022] A photodetector 102 is coupled to a pixel circuit 104. The pixel circuit 104 includes a floating diffusion node 106, a transfer transistor 108 extending between the floating diffusion node 106 and the photodetector 102, a reset transistor 110 having a source / drain terminal 112 coupled to the floating diffusion node 106, and an output stage 114 coupled to the floating diffusion node 106. The output stage 114 includes a source follower transistor 116 and a row select transistor 120. The source follower transistor has a first gate electrode 118 coupled to the floating diffusion node 106, and the row select transistor has a first source / drain terminal 122 coupled to a second source / drain terminal 124 of the source follower transistor 116. A third source / drain terminal 126 of the source follower transistor is coupled to a voltage supply rail Vdd. An output node 128 is coupled to a fourth source / drain terminal 130 of the row select transistor 120. An output line 140 is coupled to the output node 128, and a row select line 142 is coupled to the gate electrode of the row select transistor 120.

[0023] The output node 128 has a parasitic capacitance C js , which is represented by a first capacitor 132. A second capacitor 134 is coupled between the output node 128 and the floating diffusion node 106 and has a capacitance C H . The capacitance C H and the parasitic capacitance C js both affect the sensed capacitance at the output node 128. The sensed capacitance caused by the second capacitor 134 depends on the ratio of the voltage at the output node 128 to the voltage at the floating diffusion node 106. The ratio of the voltage at the output node to the voltage at the floating diffusion node 106 can also be expressed as the gain of the output stage 114.

[0024] When the gain of the output stage 114 is greater than one (e.g., when the voltage at the output node 128 is greater than the voltage at the floating diffusion node 106), the sensed capacitance of the second capacitor 134 is positive, and the total sensed capacitance at the output node is greater than the parasitic capacitance Cjs When the gain of the output stage 114 is less than one (e.g., when the voltage at the output node 128 is less than the voltage at the floating diffusion node 106), the sensing capacitance of the second capacitor 134 is negative, and the total sensing capacitance at the output node is less than the parasitic capacitance C js Provides a 128 capacitance at the output node (for more details, see Figure 1B ). The total capacitance C sensed at the output node 128 tot The reduction in reduces the RC delay in the image sensor, thereby increasing the gain in low information applications. As the time constant of the pixel array is reduced, the gain is increased, thereby increasing the signal amplitude range available within the measurement time range and the bandwidth of the image sensor (e.g., by reducing the time constant, reducing the minimum measurement time range to transfer the signal from the pixel circuit to the ISP circuit). The increase in gain in low information applications results in an increase in the dynamic range of the image sensor and improves the quality of the image produced by the image sensor.

[0025] like Figure 1B The circuit diagram 100b shows a circuit diagram of a Figure 1A The circuit diagram 100a is equivalent to the circuit shown in the circuit diagram 100a. The second capacitor (see Figure 1A 134) can be considered as a third capacitor 136 coupled between the floating diffusion node 106 and ground, and a fourth capacitor 138 coupled between the output node 128 and ground. This results in a circuit in which, for each pixel circuit 104 in the plurality of pixel circuits coupled to the output line 140, the perceived capacitance at the output node 128 can be determined by adding the capacitance of the first capacitor 132 to the capacitance of the fourth capacitor 138. The capacitance C4 of the fourth capacitor 138 can be based on the second capacitor (see Figure 1A 134) Capacitor C H , determined by using Miller's theorem (substituting the impedance of the second capacitor for the initial impedance Z of Miller's theorem and substituting the impedance of the fourth capacitor for the output impedance Z2 of Miller's theorem):

[0026]

[0027] Where k is the ratio of the voltage at the output node 128 to the voltage at the floating diffusion node 106 (eg, the gain of the output stage 114). Equation (1) can be simplified and solved for C4 to yield equation (2) as shown below:

[0028]

[0029] As shown in equation (2), when k is greater than 1, multiply the capacitance C H The factor of C4 is positive, which leads to C4 being positive. In addition, when k is less than 1, multiplying the capacitance CH The factor of C4 is obtained as negative, resulting in C4 being negative. Since Figure 1B in the equivalent circuit shown, the first capacitor 132 (representing parasitic capacitance C js ) and the fourth capacitor 138 are in parallel. Therefore, by finding the sum of all capacitances coupled to the output node 128, the total sensed capacitance at the output node 128 can be obtained. In Figure 1B the pixel circuit shown, when k is less than 1, the sum of the parasitic capacitance C js and the capacitance C4 is less than the parasitic capacitance C js , resulting in a decrease in the sensed capacitance at the output node 128.

[0030] As shown in Figure 1C the circuit schematic 100c, a plurality of pixel circuits 145 are organized into a plurality of rows 146, 148 and columns 150, 152. The first row selection line 142a is coupled to the gate electrode 144 of the row selection transistor 120 in the first row 146 of the pixel circuits. The second row selection line 142b is coupled to the gate electrode 144 of the row selection transistor 120 in the second row 148 of the pixel circuits. The first output line 140a is coupled to the output node 128 of the first column 150 of the pixel circuits. The second output line 140b is coupled to the output node 128 of the second column 152 of the pixel circuits.

[0031] The sensed capacitance at the first output line 140a is affected by the parasitic capacitance C js and the capacitance C H of each pixel circuit in the first column 150. The total capacitance C tot sensed on the output line can be found by finding the sum of the parasitic capacitance and the capacitance C4, where the equivalent circuit shown in Figure 1B is used to replace the pixel circuit 104 in Figure 1C . The total capacitance C tot can be obtained by the following equation 3:

[0032]

[0033] where n is the total number of pixel circuits in the first column 150. For example, when the output stage gain of the pixel circuit is 0.9, one-ninth of the capacitance C tot is subtracted from the total capacitance C H sensed at the first output line 140a. The gain of the capacitance C H and the capacitors of each pixel circuit 104 in the first column 150 are also included in C tot .

[0034] Figure 2 FIG. 200 shows a cross-sectional view of the output stage of some embodiments of an image sensor having a capacitor between the output node and the floating diffusion node.

[0035] Parasitic capacitance C js (represented by the first capacitor 132) is located between the fourth source / drain terminal 130 of the row selection transistor and the body region of the first substrate 202. The first electrode 204 of the second capacitor 134 is coupled to the fourth source / drain terminal 130 through the first contact 206. The interconnect structure 208 further extends between and is electrically coupled to the first electrode 204 and the first contact 206, thereby coupling the first electrode 204 to the output node 128. The second electrode 210 of the second capacitor 134 is coupled to the first gate electrode 118 of the source follower transistor 116 through the interconnect structure 208 and the second contact 212, wherein the second electrode 210 is coupled to the floating diffusion node (see Figure 1A 106). The interconnect structure 208 includes one or more wire layers and one or more via layers, forming a first conduction path 214 between the first gate electrode 118 and the second electrode 210 and a second conduction path 216 between the fourth source / drain terminal 130 and the first electrode 204. The interconnect structure 208 is surrounded by a plurality of interlayer dielectric layers 218. The first insulating layer 220 surrounds the first and second electrodes 204, 210 of the second capacitor 134.

[0036] Figure 3 A circuit schematic 300 showing some embodiments of an image sensor having a capacitor between the output node and the floating diffusion node (wherein a plurality of photodetectors are coupled to the floating diffusion node).

[0037] In some embodiments, the pixel circuit 104 is formed on a plurality of different chips bonded together. In some embodiments, the reset transistor 110, the source follower transistor 116, and the row selection transistor 120 are located on the first chip 306. The plurality of photodetectors 302 are coupled to the floating diffusion node 106 through a plurality of transfer transistors 304 on the second chip 308. The ISP circuit 310 is located on the third chip 312. The row selection line 142 and the output line 140 are located within the first chip 306. The output node 128 is located on the first chip 306 and is electrically coupled to the third chip 312. In some embodiments, the first electrode 204 and the second electrode 210 of the second capacitor 134 are located in the bonding layer between the second chip 308 and the first chip 306.

[0038] Figure 4 A cross-sectional view 400 showing some embodiments of an image sensor having a shielding structure and a metal bonding pad with a capacitor configured to be coupled between the output node and the floating diffusion node.

[0039] In some embodiments, the first interconnect structure 208 is located on a first side 202a of the first substrate 202 and includes a first conductive path 214. The first conductive path 214 electrically couples a first gate electrode 118 of the source follower transistor 116 to a second electrode 210 of the second capacitor 134. The first conductive path 214 is also electrically coupled to a source / drain terminal 112 of the reset transistor 110 and the conversion gain circuit 402. The first conductive path 214 is coupled to the floating diffusion node 106. The conversion gain circuit 402 includes one or more semiconductor devices configured to increase the conversion gain of the pixel circuit in a low information environment (e.g., imaging regions with a light level below a specified threshold).

[0040] The first conductive path 214 is coupled to a third conductive path 404 in a second interconnect structure 406 on the second chip 308. A first bonding layer 408 of the first chip 306 and a second bonding layer 411 of the second chip 308 mechanically couple the first chip 306 to the second chip 308. The second electrode 210 includes a combination of a first metal bonding pad 405a in a first plurality of metal bonding pads 405 in the first bonding layer 408 and a second metal bonding pad 415a in a second plurality of metal bonding pads 415 in the second bonding layer 411. The second metal bonding pad 415a is coupled to the first metal bonding pad 405a at a first bonding interface 421. The second electrode 210 electrically couples the first conductive path 214 to the third conductive path 404. The second electrode 210 is also referred to as a bonding electrode. Additionally, a first insulating layer 220 of the first bonding layer 408 is mechanically coupled to a second insulating layer 423 of the second bonding layer 411. The second interconnect structure 406 further includes one or more additional conductive paths 416 coupled to a plurality of transfer transistors 304. Separate conductive paths 416 of the plurality of transfer transistors 304 coupled to the floating diffusion node 106 cause charge to be transferred from each of the plurality of photodetectors 302 during operation such that charge from each photodetector can be individually transferred to the pixel circuit 104.

[0041] The second conductive path 216 extends from the fourth source / drain terminal 130 of the row select transistor 120 to the first electrode 204. In some embodiments, the second conductive path 216 is the same as the output node 128. In some embodiments, the first electrode 204 surrounds the second electrode 210, increasing the surface area of the second capacitor 134 and isolating the second electrode 210 from the electric fields caused by the other metal bonding pads in the first plurality of metal bonding pads 405. The first electrode 204 includes a combination of the first shielding structure 407a of the first plurality of shielding structures 407 and the second shielding structure 413a of the second plurality of shielding structures 413. The first electrode 204 is also referred to as a shielding electrode. The first shielding structure 407a is mechanically coupled to the second shielding structure 413a of the second plurality of shielding structures 413 at the first bonding interface 421. The second shielding structure 413a has the same layout as the first shielding structure 407a (e.g., having the same length and width, and the same distance between the inner sidewalls) to enhance the bonding strength at the first bonding interface 421. The combination of the first bonding layer 408 and the second bonding layer results in an increase in the surface area of the inner sidewall of the first electrode 204 and the outer sidewall of the second electrode 210. The increased surface area increases the capacitance of the second capacitor 134 without increasing the area used by the second capacitor 134 within the first or second interconnect structures 208, 406. That is, the thicknesses of the first electrode 204 and the second electrode 210 are greater than the second thickness of the wire layer of the interconnect structure, resulting in a capacitance between the first electrode and the second electrode that is greater than the capacitance between wires having the same layout as the first electrode 204 and the second electrode 210.

[0042] The second conductive path 216 is also electrically coupled to the ISP circuit 310 on the third chip 312. The ISP circuit 310 is configured to process signals from a plurality of pixel circuits in the image sensor (see Figure 1CThe ISP circuit 310 receives signals passed to it by, for example, the image sensor 145), and combines the signals into an image. The ISP circuit 310 includes one or more correlated double sampling (CDS) circuits, analog-to-digital converter (ADC) circuits, and amplifier circuits. One or more through-substrate vias (TSVs) 410 couple the first interconnect structure 208 to a third interconnect structure 412 on a second side 202b of the first substrate 202 opposite the first side 202a. In some embodiments, the third interconnect structure 412 includes one or more wire layers and one or more via layers, which are electrically coupled to the third chip 312 through a third bonding layer 409. The third bonding layer 409 includes a third plurality of metal bonding pads 414 and a third insulating layer 425. The third bonding layer 409 is electrically coupled to a fourth bonding layer 417 of the third chip 312 at a second bonding interface 426. A fourth plurality of metal bonding pads 419 are mechanically and electrically coupled to the third plurality of metal bonding pads 414. Additionally, a fourth insulating layer 427 is mechanically coupled to the third insulating layer 425. The third plurality of metal bonding pads 414 and the fourth plurality of metal bonding pads 419 electrically couple the third interconnect structure 412 to the ISP circuit 310.

[0043] A plurality of photodetectors 302 are located within the second substrate 418. A plurality of deep trench isolation (DTI) structures 420 extend around the plurality of photodetectors and isolate them from each other. A plurality of color filters 422 and microlenses 424 are located above the photodetectors 302 such that incident light is filtered and directed to the photodetectors 302 before entering the second substrate 418.

[0044] Figure 5A and Figure 5B Top views 500a, 500b showing some embodiments of a plurality of shielding structures and metal bonding pads in a pixel circuit array.

[0045] As Figure 5A shown in the top view 500a, the first bonding layer 408 includes a first insulating layer 220 that surrounds a first plurality of metal bonding pads 405 including the first metal bonding pad 405a and a first plurality of shielding structures 407 including the first shielding structure 407a. In some embodiments, the first plurality of metal bonding pads 405 are each surrounded by the first plurality of shielding structures 407. For example, in an image sensor having four pixel circuits, the first metal bonding pad 405a is surrounded by the first shielding structure 407a, the second metal bonding pad 405b is continuously surrounded by the second shielding structure 407b, the third metal bonding pad 405c is continuously surrounded by the third shielding structure 407c, and the fourth metal bonding pad 405d is continuously surrounded by the fourth shielding structure 407d. The number of metal bonding pads in the first plurality of metal bonding pads 405 is equal to the number of shielding structures in the first plurality of shielding structures 407.

[0046] AsFigure 5B As shown in the top view 500b, in other embodiments, the number of metal bonding pads in the first plurality of metal bonding pads 405 is greater than the number of shielding structures in the first plurality of shielding structures 407. The shielding structures surround more than one metal bonding pad within a column of the plurality of metal bonding pads. For example, in an image sensor having four pixel circuits, the first metal bonding pad 405a and the second metal bonding pad 405b in the first column 150 are continuously surrounded by the first shielding structure 407a, while the third metal bonding pad 405c and the fourth metal bonding pad 405d in the second column 152 are surrounded by the second shielding structure 407b. The output nodes of the plurality of pixel circuits in the first column 150 (see Figure 1C 128 in Figure 1C are coupled together through output lines (see Figure 1C 140 in Figure 1A . Since the output nodes (see Figure 1B 128 in Figure 5B are also coupled to the shielding structures of the first plurality of shielding structures 407 in the first column 150, the electrically coupled shielding structures shown in

[0047] Figures 6 - 18 can be replaced by the shielding structures shown in Figures 6 - 18 without changing the electrical coupling of the circuit. Using the shielding structures as shown in

[0048] reduces the footprint of the shielding structures (for example, the lateral area of the shielding structures can be reduced). By removing portions of the shielding structures between the metal bonding pads, the metal bonding pads can be placed closer together, thereby reducing the footprint of the pixel circuits. Figure 6As shown in the cross-sectional view 600, the third interconnect structure 412 is formed on the second side 202b of the first substrate 202 as part of the first chip 306. The third interconnect structure 412 includes one or more wire layers and one or more via layers that form conductive paths above the first substrate 202. In addition, a plurality of interlayer dielectric layers 218 are formed between the wire layers and via layers of the third interconnect structure 412. In some embodiments, the third interconnect structure 412 includes a conductive material such as copper, aluminum, tungsten, a conductive metal alloy, etc. In some embodiments, the plurality of interlayer dielectric layers 218 are or include an insulating material such as silicon dioxide (SiO2), silicon nitride (Si3N4), etc. The third interconnect structure 412 is formed using one or more of physical vapor deposition (PVD), atomic layer deposition (ALD), chemical vapor deposition (CVD), damascene process, dual damascene process, etc.

[0049] As Figure 7 shown in the cross-sectional view 700, in some embodiments, a third bonding layer 409 is formed on the third interconnect structure 412. The third bonding layer 409 includes a third insulating layer 425 and a third plurality of metal bonding pads 414. In some embodiments, the third plurality of metal bonding pads 414 are or include one or more of aluminum, copper, aluminum copper, etc. In some embodiments, the third insulating layer 425 is or includes one or more of silicon dioxide (SiO2), silicon nitride (Si3N4), etc. The third insulating layer 425 is formed using one or more of PVD, ALD, CVD, etc. The third plurality of metal bonding pads 414 are formed using one or more of PVD, ALD, CVD, damascene process, etc. In some embodiments, the third plurality of metal bonding pads 414 and the underlying contact layer are formed simultaneously using a dual damascene process.

[0050] As Figure 8 shown in the cross-sectional view 800, the ISP circuit 310 is formed on the third chip 312, and the third chip 312 is bonded to the first chip 306 at the third bonding layer 409. The ISP circuit 310 includes one or more correlated double sampling (CDS) circuits, analog-to-digital converter (ADC) circuits, and amplifier circuits, and the amplifier circuits include one or more transistors, passive circuit components, or other circuit components. Forming the ISP circuit 310 includes using one or more of PVD, ALD, CVD, and implantation processes, etc. to form transistors and circuit elements, and using one or more of PVD, ALD, CVD, damascene process, etc. to form overlying interconnect structures to form conductive paths between circuit components and transistors.

[0051] In some embodiments, the third chip 312 is coupled to the first chip 306 by forming a fourth bonding layer 417 on the third chip 312 before bonding the third chip 312 to the third bonding layer 409. The fourth insulating layer 427 is dielectrically bonded to the third insulating layer 425, and the fourth plurality of metal bonding pads 419 are bonded to the third plurality of metal bonding pads 414. The combination of dielectric-dielectric bonding between the insulating layers and metal-metal bonding between the metal bonding pads demonstrates a hybrid bonding at the second bonding interface 426. The dielectric-dielectric bonding between the insulating layers and the metal-metal bonding between the metal bonding pads are formed at the second bonding interface 426 by performing a pressure treatment to first bond the fourth insulating layer 427 to the third insulating layer 425 and then annealing to strengthen the bond between the third and fourth insulating layers 425, 427 and to form the bond between the third and fourth plurality of metal bonding pads 414, 419. In other embodiments, instead of using hybrid bonding to bond the first chip 306 to the third chip 312, a different method of bonding the first chip 306 to the third chip 312 is performed.

[0052] As Figure 9 shown in cross-sectional view 900 of FIG. 900, a plurality of front-end-of-line (FEOL) circuit components 902 are formed on the first side 202a of the first substrate 202. The plurality of FEOL circuit components 902 include reset transistors 110 of a plurality of pixel circuits, components of the conversion gain circuit 402, source follower transistors 116, and row selection transistors 120. In some embodiments, the plurality of FEOL circuit components 902 formed within the image sensor are a plurality of metal-oxide-semiconductor field-effect transistor (MOSFET) devices. In some embodiments, the plurality of FEOL circuit components 902 are formed using one or more PVD, ALD, CVD, or implantation processes.

[0053] As Figure 10 shown in cross-sectional view 1000 of FIG. 1000, contacts 1002 are formed above the first side of the first substrate 202, including a first contact 206 and a second contact 212, and an overlying wire layer 1004. The first contact 206 is coupled to the fourth source / drain terminal 130 of the row selection transistor 120, and the second contact 212 is coupled to the first gate electrode 118 of the source follower transistor 116. The contacts 1002 are coupled to the plurality of FEOL circuit components 902 to connect them to a first interconnect structure to be formed subsequently (see Figure 11In addition, a TSV 410 is formed to couple the fourth source / drain terminal 130 of the row selection transistor 120 (through the overlying wire layer 1004) to the third interconnect structure 412 and the ISP circuit 310. In some embodiments, one or more of etching, CVD, ALD, PVD, and planarization (e.g., chemical mechanical planarization) processes are used to form the contacts 1002, the TSV, and the overlying wire layer 1004. In some embodiments, the contacts 1002 and the overlying wire layer 1004 are formed simultaneously.

[0054] As Figure 11 shown in the cross-sectional view 1100 of, the first interconnect structure 208 is formed above the contacts 1002. The first interconnect structure 208 includes a plurality of wire layers and a plurality of via layers, which are arranged to form at least a first conduction path 214 and a second conduction path 216. The first conduction path 214 electrically couples the first gate electrode 118 of the source follower transistor 116, the source / drain terminal of the reset transistor 110, and the transistors of the conversion gain circuit 402, and extends to the uppermost wire layer of the first interconnect structure. The second conduction path 216 is coupled to the fourth source / drain terminal 130 of the row selection transistor 120 and the ISP circuit 310, and extends to the uppermost wire layer of the first interconnect structure 208. In some embodiments, the overlying wire layer (see Figure 10 1004 of) is part of the first interconnect structure 208.

[0055] As Figure 12 shown in the cross-sectional view 1200 of, the first bonding layer 408 is formed above and coupled to the first interconnect structure 208. The first bonding layer 408 includes a first insulating layer 220, a first plurality of metal bonding pads 405 (including the second electrode 210), and a first plurality of shielding structures 407 (including the first electrode 204), as Figure 5A and Figure 5B shown in the top layout of. The spacing between the first plurality of metal bonding pads 405 and the first plurality of shielding structures 407 forms a plurality of capacitors including the second capacitor 134. The capacitance of the plurality of capacitors is based on the distance between the opposing faces of the first plurality of metal bonding pads 405 (e.g., the outer sidewalls of the first plurality of metal bonding pads 405) and the first plurality of shielding structures 407 (e.g., the inner sidewalls of the first plurality of shielding structures 407) and the surface area of the opposing faces of the first plurality of metal bonding pads 405 and the first plurality of shielding structures 407. When the second bonding layer (see Figure 4 411 of) is bonded to the first bonding layer 408 (see Figure 16 ), the surface area of the opposing faces increases. The first plurality of shielding structures 407 are coupled to the output node 128 of the pixel circuit (see Figure 1A104). The first plurality of metal bonding pads 405 are coupled to the source follower transistor 116 through the first conductive path 214.

[0056] The first plurality of metal bonding pads 405 are or include one or more of aluminum, copper, aluminum copper, etc. The first insulating layer 220 is or includes one or more of silicon dioxide (SiO2), silicon nitride (Si3N4), etc. The first insulating layer 220 is formed using one or more of PVD, ALD, CVD, etching, etc. The first plurality of metal bonding pads 405 are formed using one or more of PVD, ALD, CVD, damascene process, etc. In some embodiments, the first plurality of metal bonding pads 405 and the underlying contact layer are formed using a dual damascene process simultaneously.

[0057] As Figure 13 As shown in the cross-sectional view 1300 of, a plurality of transfer transistors 304, a plurality of photodetectors 302, and a floating diffusion node 106 are formed on the second substrate 418 of the second chip 308. The floating diffusion node 106 and the plurality of photodetectors 302 are formed using an implantation process to implant an n-type dopant into the second substrate 418. In some embodiments, the plurality of transfer transistors 304 are formed using one or more of PVD, ALD, CVD, and etching processes.

[0058] As Figure 14 As shown in the cross-sectional view 1400 of, a second interconnect structure 406 is formed above the second substrate 418. The second interconnect structure 406 forms a third conductive path 404 coupled to the floating diffusion node 106 and an additional conductive path coupled to the gate electrodes of the transfer transistors 304. The second interconnect structure 406 includes a plurality of wire layers and a plurality of via layers. A plurality of interlayer dielectric layers 218 surround the second interconnect structure 406 and are formed between the respective wire layers. In some embodiments, the second interconnect structure 406 includes a conductive material such as copper, aluminum, aluminum copper, tungsten, a conductive metal alloy, etc. In some embodiments, the plurality of interlayer dielectric layers 218 are or include an insulating material such as silicon dioxide (SiO2), silicon nitride (Si3N4), etc. The second interconnect structure 406 is formed using one or more of PVD, ALD, CVD, damascene process, dual damascene process, etc.

[0059] As Figure 15As shown in the cross-sectional view 1500, in some embodiments, a second bonding layer 411 is formed above a second interconnect structure 406 on a second chip 308. The second bonding layer 411 includes a second insulating layer 423 having the same material as the first insulating layer 220, a second plurality of shielding structures 413 including the same material as the first plurality of shielding structures 407, and a second plurality of metal bonding pads 415 including the same material as the first plurality of metal bonding pads 405. The second plurality of metal bonding pads 415 are arranged to meet and couple with the exposed surfaces of the first plurality of metal bonding pads 405 during the bonding process described below (see Figure 16 ). The second plurality of shielding structures 413 are arranged to meet and couple with the exposed surfaces of the first plurality of shielding structures 407 during the bonding process described below (see Figure 16 ). In some embodiments, the second plurality of metal bonding pads 415 have the same top geometry as the first plurality of metal bonding pads (see Figure 4 of 405), wherein the second plurality of shielding structures 413 have the same top geometry as the first plurality of shielding structures (see Figure 4 of 407). In other embodiments, the second bonding layer 411 is omitted.

[0060] As Figure 16 shown in the cross-sectional view 1600, a plurality of DTI structures 420 are formed in a second substrate 418 around the plurality of photodetectors 302. In some embodiments, the plurality of DTI structures 420 are formed using one or more of PVD, ALD, CVD, or etching processes. In some embodiments, the plurality of DTI structures 420 are formed after the second chip 308 is bonded to the first chip 306 (e.g., after the step shown in Figure 17 ).

[0061] As Figure 17 shown in the cross-sectional view 1700, the second chip 308 is bonded to the first chip 306 such that a third conduction path 404 is electrically coupled to the first conduction path 214 through the first plurality of metal bonding pads 405 (including the second electrode 210) and the second plurality of metal bonding pads 415. The second chip 308 is bonded to the first chip 306 using a combination of dielectric-dielectric bonding between insulating layers and metal-metal bonding between metal bonding pads. The second insulating layer 423 and the first insulating layer 220 are bonded together by pressure treatment and subsequent annealing. In addition, during the pressure treatment and subsequent annealing, the first plurality of metal bonding pads 405 are bonded to the second plurality of metal bonding pads 415, and the first plurality of shielding structures 407 are bonded to the second plurality of shielding structures 413. Bonding the first bonding layer 408 to the second bonding layer 411 results in an increased area of the second capacitor 134, thereby increasing the capacitance of the second capacitor 134.

[0062] As Figure 18 As shown in cross-sectional view 1800, in some embodiments, a plurality of color filters 422 and a plurality of microlenses 424 are formed on a second substrate 418 above the photodetectors 302. In some embodiments, the plurality of color filters 422 and the plurality of microlenses 424 are formed before the second chip 308 is bonded to the first chip 306, and then the plurality of photodetectors 302 and the plurality of DTI structures 420 are formed. In some embodiments, the plurality of color filters 422 and the plurality of microlenses 424 are centered on each of the photodetectors in the plurality of photodetectors, such that the plurality of microlenses 424 direct light to the photodetectors 302. In other embodiments, the plurality of microlenses 424 are offset from the center of each photodetector based on the position of each photodetector in the photodetector array. For example, in some embodiments, each photodetector near the center of the photodetector array will have a microlens closer to the center of each photodetector, while each photodetector near the outer edge of the array will have a microlens that is more offset from the center of each photodetector to more effectively bend the incident light to each photodetector.

[0063] Figure 19 Flowchart 1900 showing some embodiments of a method of forming an image sensor having a capacitor between an output node and a floating diffusion node. Although the method and other methods shown and / or described herein are shown as a series of acts or events, it should be understood that the present disclosure is not limited to the order or acts shown. Thus, in some embodiments, the acts may be performed in an order different from that shown, and / or the acts may be performed simultaneously. Additionally, in some embodiments, the acts or events shown may be subdivided into multiple acts or events, which may be performed at separate times or simultaneously with other acts or sub-acts. In some embodiments, some of the acts or events shown may be omitted, and other acts or events not shown may be included.

[0064] At 1902, an output stage is formed on a first substrate, and the output stage includes a row selection transistor electrically coupled to an output node from a source follower transistor. For example, an example of a diagram illustrating this step can be found in Figure 9 In.

[0065] At 1904, a first interconnect structure is formed above the output stage, wherein the first interconnect structure includes a first conductive path electrically coupled to the gate electrode of the source follower transistor and a second conductive path electrically coupled to the output node. For example, an example of a diagram illustrating this step can be found in Figures 10 - 11 In.

[0066] At 1906, a first bonding layer is formed over the first interconnect structure, wherein the first bonding layer includes a bonding electrode and a shielding electrode surrounding the bonding electrode, and wherein the shielding electrode is formed to be electrically coupled to a second conduction path. For example, an example of a diagram illustrating this step can be found in Figure 12 In

[0067] At 1908, a photodetector is formed in the second substrate. For example, an example of a diagram illustrating this step can be found in Figure 13 In

[0068] At 1910, a transfer transistor is formed over the second substrate, wherein the transfer transistor is electrically coupled from the photodetector to a floating diffusion node. For example, an example of a diagram illustrating this step can be found in Figure 13 In

[0069] At 1912, a second interconnect structure is formed over the transfer transistor, the second interconnect structure including a third conduction path electrically coupled to the floating diffusion node. For example, an example of a diagram illustrating this step can be found in Figures 13 - 14 In

[0070] At 1914, the second interconnect structure is bonded to the first interconnect structure through the first bonding layer, wherein the bonding electrically couples the first and third conduction paths together through the bonding electrode. For example, an example of a diagram illustrating this step can be found in Figure 17 In

[0071] Some embodiments relate to an image sensor, comprising: a photodetector; and a pixel circuit, comprising: a floating diffusion node and an output node; a transfer transistor electrically coupled from the floating diffusion node to the photodetector; a source follower transistor comprising a gate electrode electrically coupled to the floating diffusion node; a row selection transistor electrically coupled from a source / drain region of the source follower transistor to the output node; and a capacitor electrically coupled from the output node to the floating diffusion node. In some embodiments, the image sensor further comprises: a first integrated circuit (IC) chip accommodating the photodetector, the floating diffusion node, and the transfer transistor; and a second IC chip joined to the first IC chip at an interface and accommodating the source follower transistor, the row selection transistor, and the output node, wherein the capacitor comprises respective electrodes at the interface. In some embodiments, the interface comprises a metal-metal interface and a dielectric-dielectric interface. In some embodiments, the image sensor further comprises a third IC chip joined to the second IC chip and separated from the first IC chip by the second IC chip, wherein the third IC chip comprises an image signal processor electrically coupled to the output node. In some embodiments, the capacitor comprises a first electrode and a second electrode electrically coupled to the output node and the floating diffusion node, respectively, and the first electrode extends around the second electrode in a closed path. In some embodiments, the photodetector and the pixel circuit form a pixel that repeats in a plurality of rows and a plurality of columns, and the image sensor further comprises: an output line extending along a first column among the plurality of columns and electrically coupled to the output nodes of each pixel in the first column. In some embodiments, the source follower transistor has a gain less than 1.

[0072] Other embodiments relate to an image sensor including: a source follower transistor and a row selection transistor located on a first substrate, wherein the row selection transistor is electrically coupled from the source follower transistor to an output node; a photodetector and a floating diffusion node located in a second substrate; a transfer transistor located on the second substrate and electrically coupled from the photodetector to the floating diffusion node; a first interconnect structure and a second interconnect structure located between the first substrate and the second substrate; and a bonding structure located between the first and second interconnect structures, wherein the bonding structure includes a shielding electrode and a bonding electrode surrounding the shielding electrode; wherein the first interconnect structure electrically couples the shielding electrode to the output node, and wherein the second interconnect structure electrically couples the bonding electrode to the floating diffusion node. In some embodiments, the first interconnect structure includes a plurality of wire layers and a plurality of via layers alternately stacked from the bonding structure toward the first substrate, and wherein the thickness of the shielding electrode is greater than the thickness of the wire layers in the plurality of wire layers. In some embodiments, the bonding electrode and the shielding electrode form a capacitor to cancel the parasitic capacitance at the output node. In some embodiments, the image sensor further includes: a plurality of pixels in a plurality of rows and a plurality of columns, wherein the plurality of pixels includes a first pixel partially formed by a photodetector, a row selection transistor, and a source follower transistor, and wherein the bonding structure includes a plurality of bonding electrodes including bonding electrodes individually for the plurality of pixels. In some embodiments, the shielding electrode extends in a closed path around the bonding electrode to separate the bonding electrode from each other bonding electrode in the plurality of bonding electrodes. In some embodiments, the first pixel is located in a first column of the plurality of columns, and wherein the shielding electrode extends in a closed path around the plurality of bonding electrodes corresponding to the pixels in the first column.

[0073] Some embodiments relate to a method of forming an image sensor, comprising: forming an output stage on a first substrate, the output stage including a row selection transistor electrically coupled from a source follower transistor to an output node; forming a first interconnect structure over the output stage, wherein the first interconnect structure includes a first conductive path electrically coupled to a gate electrode of the source follower transistor and a second conductive path electrically coupled to the output node; forming a first bonding layer over the first interconnect structure, the first bonding layer including a bonding electrode and a shielding electrode surrounding the bonding electrode, the shielding electrode being formed to be electrically coupled to the second conductive path; forming a photodetector in a second substrate; forming a transfer transistor over the second substrate, the transfer transistor being electrically coupled from the photodetector to a floating diffusion node; forming a second interconnect structure over the transfer transistor, the second interconnect structure including a third conductive path electrically coupled to the floating diffusion node; and bonding the second interconnect structure to the first interconnect structure through the first bonding layer, the bonding electrically coupling the first and third conductive paths together through the bonding electrode. In some embodiments, the bonding electrode and the shielding electrode form a capacitor electrically coupled from the output node to the floating diffusion node. In some embodiments, the method further comprises: forming a second bonding layer over the second interconnect structure, wherein the second bonding layer includes an additional bonding electrode and an additional shielding electrode, wherein the additional bonding electrode is electrically coupled to the third conductive path, and wherein during bonding the second interconnect structure to the first interconnect structure, the additional bonding electrode and the additional shielding electrode are respectively bonded to the bonding electrode and the shielding electrode. In some embodiments, the additional bonding electrode has the same top geometry as the bonding electrode, and wherein the additional shielding electrode has the same top geometry as the shielding electrode. In some embodiments, the method further comprises forming a conversion gain circuit simultaneously with forming the output stage, the conversion gain circuit including a first conversion gain transistor, wherein the first conductive path is electrically coupled to a gate electrode of the first conversion gain transistor. In some embodiments, the method further comprises: forming a third interconnect structure on a back side of the first substrate, wherein the output stage and the first interconnect structure are formed on a front side of the first substrate, opposite to the back side of the first substrate; and forming a through-substrate via (TSV) extending through the first substrate to the third interconnect structure, wherein the first interconnect structure is formed to be electrically coupled to the TSV. In some embodiments, the method further comprises bonding an integrated circuit (IC) chip to the third interconnect structure on the back side of the first substrate, wherein the IC chip includes image signal processing circuitry.

[0074] It should be understood that, in this written description and the following claims, the terms "first", "second", "third", etc. are merely general identifiers used for convenience of description to distinguish different elements of one figure or a series of figures. These terms do not themselves imply any chronological order or structural proximity of these elements and are not intended to describe corresponding elements in different illustrated embodiments and / or embodiments not shown. For example, a "first dielectric layer" associated with a first figure may not necessarily correspond to a "first dielectric layer" associated with another figure and may not necessarily correspond to a "first dielectric layer" in an embodiment not shown.

[0075] The components of several embodiments have been described above so that those skilled in the art can better understand the various embodiments of the present invention. Those skilled in the art should understand that it is easy to use the present invention as a basis to design or change other processes and structures to achieve the same purpose and / or realize the same advantages as the embodiments introduced in the present invention. Those skilled in the art should also realize that these equivalent structures do not depart from the spirit and scope of the present invention, and various changes, substitutions, and alterations can be made without departing from the spirit and scope of the present invention.

Claims

1. An image sensor device, comprising: Photodetectors; and A pixel circuit, comprising: floating diffusion node and output node; a transfer transistor electrically coupled from the floating diffusion node to the photodetector; a source follower transistor including a gate electrode electrically coupled to the floating diffusion node; a row select transistor electrically coupled from a source / drain region of the source follower transistor to the output node; and A capacitor is electrically coupled from the output node to the floating diffusion node.

2. The image sensor device according to claim 1, further comprising: a first integrated circuit chip housing the source follower transistor, the row select transistor, and the output node; as well as A second chip is bonded to the first chip at an interface and accommodates the photodetector, the floating diffusion node, and the transfer transistor, wherein the capacitor includes respective electrodes at the interface.

3. The image sensor device according to claim 2, wherein: The interfaces include metal-metal interfaces and dielectric-dielectric interfaces.

4. The image sensor device according to claim 2, further comprising: A third chip is bonded to the first chip and separated from the second chip by the first chip, wherein the third chip includes an image signal processor electrically coupled to the output node.

5. The image sensor device according to claim 1, wherein: The capacitor includes a first electrode and a second electrode electrically coupled to the output node and the floating diffusion node, respectively, and wherein the first electrode extends around the second electrode in a closed path.

6. The image sensor device according to claim 1, wherein: The photodetector and the pixel circuit form pixels, the pixels are repeated in a plurality of rows and columns, and wherein the device further comprises: An output line extends along a first column of the plurality of columns and is electrically coupled to an output node of each pixel in the first column.

7. The image sensor device according to claim 1, wherein: The gain of the source follower transistor is less than 1.

8. An image sensor device, comprising: a source follower transistor and a row select transistor on a first substrate, wherein the row select transistor is electrically coupled from the source follower transistor to an output node; A photodetector and a floating diffusion node are located in the second substrate; a transfer transistor disposed on the second substrate and electrically coupled from the photodetector to the floating diffusion node; A first interconnect structure and a second interconnect structure are located between the first substrate and the second substrate; and a bonding structure located between the first interconnect structure and the second interconnect structure, wherein the bonding structure includes a bonding electrode and a shielding electrode surrounding the bonding electrode; Wherein the first interconnect structure electrically couples the shield electrode to the output node, and wherein the second interconnect structure electrically couples the bond electrode to the floating diffusion node.

9. The image sensor device according to claim 8, wherein: The first interconnect structure includes a plurality of wire layers and a plurality of via layers alternately stacked from the bonding structure toward the first substrate, and wherein a thickness of the shielding electrode is greater than a thickness of a wire layer among the plurality of wire layers.

10. A method of forming an image sensor device, comprising: forming an output stage on a first substrate, the output stage including a row select transistor electrically coupled from a source follower transistor to an output node; forming a first interconnect structure over the output stage, wherein the first interconnect structure includes a first conductive path electrically coupled to a gate electrode of the source follower transistor and a second conductive path electrically coupled to the output node; forming a first bonding layer over the first interconnect structure, wherein the first bonding layer includes a bonding electrode and a shielding electrode surrounding the bonding electrode, and wherein the shielding electrode is formed to be electrically coupled to the second conductive path; forming a photodetector in a second substrate; forming a transfer transistor over the second substrate, wherein the transfer transistor is electrically coupled from the photodetector to a floating diffusion node; forming a second interconnect structure over the pass transistor, the second interconnect structure comprising a third conductive path electrically coupled to the floating diffusion node; and The second interconnect structure is bonded to the first interconnect structure through the first bonding layer, wherein the bonding electrically couples the first conductive path and the third conductive path together through the bonding electrode.

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