Back contact battery and preparation method thereof

Abstract

The embodiment of the invention relates to the photovoltaic field, and provides a back contact cell and a preparation method thereof, and the preparation method of the back contact cell comprises the steps: providing a substrate; forming a tunneling oxide layer and an intrinsic crystalline silicon layer; forming a first silicon oxide layer on the surface of the intrinsic crystalline silicon layer on the second region and the spacer region; carrying out first doping treatment on the intrinsic crystalline silicon layer on the first region, so that the intrinsic crystalline silicon layer on the first region is converted into a first doped conductive layer containing a first doping element; removing the first silicon oxide layer; forming a second silicon dioxide layer on the first doped conductive layer and the surface of the intrinsic crystalline silicon layer on the spacer region; performing second doping treatment on the intrinsic crystalline silicon layer on the second region, so that the intrinsic crystalline silicon layer on the second region is converted into a second doped conductive layer containing a second doping element; and removing the second silicon dioxide layer. According to the embodiment of the invention, the performance and preparation efficiency of the back contact battery can be improved at least, and the problem of high preparation process difficulty caused by laser treatment is avoided.

Description

Technical Field

[0001] Embodiments of the present disclosure relate to the field of photovoltaics, and in particular, to a back-contact battery and a method for manufacturing the same. Background Art

[0002] As fossil energy is gradually depleted, solar cells, as a new energy alternative, are being used more and more widely. A solar cell is a device that converts the light energy of the sun into electrical energy. The solar cell utilizes the photovoltaic effect to generate carriers, and then uses electrodes to extract the carriers, thereby facilitating the effective utilization of electrical energy.

[0003] Current solar cells mainly include IBC (Interdigitated BackContact) cells, TOPCON (Tunnel Oxide Passivated Contact) cells, PERC cells (Passivated emitter and real cell), and heterojunction cells, etc.

[0004] However, in the methods for manufacturing back-contact batteries in related technologies, laser treatment is included, resulting in a relatively high manufacturing process difficulty for back-contact batteries and relatively low performance of the manufactured back-contact batteries. Summary of the Invention

[0005] Embodiments of the present disclosure provide a back-contact battery and a method for manufacturing the same, which can at least improve the performance and manufacturing efficiency of the back-contact battery and avoid the problem of relatively high manufacturing process difficulty caused by laser treatment.

[0006] According to some embodiments of the present disclosure, on the one hand, a method for manufacturing a back contact battery provided by the embodiments of the present disclosure includes: providing a substrate having opposite first and second surfaces, wherein the second surface includes a first region, a second region, and a spacer region located between the first region and the second region; sequentially forming a tunneling oxide layer and an intrinsic crystalline silicon layer on the second surface of the substrate; forming a first silicon oxide layer on the surfaces of the intrinsic crystalline silicon layer on the second region and the spacer region; using the first silicon oxide layer as a first mask layer to perform a first doping process on the intrinsic crystalline silicon layer on the first region, so that the intrinsic crystalline silicon layer on the first region is converted into a first doped conductive layer containing a first doping element, and forming a first doped silicon glass layer on the surface of the first doped conductive layer facing away from the tunneling oxide layer; removing the first silicon oxide layer and the first doped silicon glass layer; forming a second silicon oxide layer on the surface of the first doped conductive layer and the intrinsic crystalline silicon layer on the spacer region; using the second silicon oxide layer as a second mask layer to perform a second doping process on the intrinsic crystalline silicon layer on the second region, so that the intrinsic crystalline silicon layer on the second region is converted into a second doped conductive layer containing a second doping element, and forming a second doped silicon glass layer on the surface of the second doped conductive layer facing away from the tunneling oxide layer, wherein the second doping element has a different conductivity type from the first doping element; removing the second silicon oxide layer and the second doped silicon glass layer.

[0007] In some embodiments, the method for forming the intrinsic crystalline silicon layer includes: forming the intrinsic crystalline silicon layer in an amorphous state on the surface of the tunneling oxide layer facing away from the second surface; using a first thermal oxidation process to form the first silicon oxide layer, and when performing the first thermal oxidation process, the intrinsic crystalline silicon layer is converted from the amorphous state to the polycrystalline state.

[0008] In some embodiments, forming the first silicon oxide layer on the surfaces of the intrinsic crystalline silicon layer on the second region and the spacer region includes: forming the first silicon oxide layer on the surface of the intrinsic crystalline silicon layer facing away from the tunneling oxide layer; forming a first organic mask layer on the surface of the first silicon oxide layer on the second region and the spacer region facing away from the tunneling oxide layer; using a first acidic solution to remove the first silicon oxide layer on the first region; using a first basic solution to remove the first organic mask layer.

[0009] In some embodiments, forming the second silicon oxide layer on the first doped conductive layer and the surface of the intrinsic crystalline silicon layer located on the spacer region includes: forming the second silicon oxide layer on the surfaces of the intrinsic crystalline silicon layer and the first doped conductive layer facing away from the tunneling oxide layer; forming a second organic mask layer on the surface of the second silicon oxide layer on the first region and the spacer region facing away from the tunneling oxide layer; removing the second silicon oxide layer on the second region using a second acidic solution; and removing the second organic mask layer using a second alkaline solution.

[0010] In some embodiments, the method of forming the first silicon oxide layer includes a first thermal oxidation process. The process temperature of the first thermal oxidation process is 600°C to 800°C, the oxygen flow rate introduced in the first thermal oxidation process is 1500 sccm to 8000 sccm, and the process duration of the first thermal oxidation process is 500 s to 3000 s. The method of forming the second silicon oxide layer includes a second thermal oxidation process. The process temperature of the second thermal oxidation process is 600°C to 800°C, the oxygen flow rate introduced in the second thermal oxidation process is 1500 sccm to 8000 sccm, and the process duration of the second thermal oxidation process is 500 s to 3000 s.

[0011] In some embodiments, the thickness of the first organic mask layer is 5 μm to 20 μm. The method of forming the first organic mask layer includes printing and spraying. The thickness of the second organic mask layer is 5 μm to 20 μm. The method of forming the second organic mask layer includes printing and spraying.

[0012] In some embodiments, the mass concentration of the first alkaline solution is 2% to 5%, and the process temperature for etching with the first alkaline solution is 15°C to 40°C. The mass concentration of the second alkaline solution is 2% to 5%, and the process temperature for etching with the second alkaline solution is 15°C to 40°C.

[0013] In some embodiments, the first acidic solution is hydrofluoric acid with a mass concentration of 3% to 10%, and the process temperature for etching with the first acidic solution is 15°C to 40°C. The second acidic solution is hydrofluoric acid with a mass concentration of 3% to 10%, and the process temperature for etching with the second acidic solution is 15°C to 40°C.

[0014] In some embodiments, the thickness of the first silicon oxide layer is 10 nm to 40 nm. The thickness of the second silicon oxide layer is 10 nm to 40 nm.

[0015] According to some embodiments of the present disclosure, on the other hand, an embodiment of the present disclosure further provides a back-contact battery, including: a substrate having opposite first and second surfaces, the second surface including a first region, a second region, and a spacer region located between the first region and the second region; a tunneling oxide layer located on the second surface; a first doped conductive layer located on the first region and on the surface of the tunneling oxide layer facing away from the second surface, the first doped conductive layer including a first doping element; a second doped conductive layer located on the second region and on the surface of the tunneling oxide layer facing away from the second surface, the second doped conductive layer including a second doping element, the second doping element having a different conductivity type from the first doping element; and an intrinsic crystalline silicon layer located on the spacer region and between the first doped conductive layer and the second doped conductive layer.

[0016] The technical solutions provided by the embodiments of the present disclosure have at least the following advantages:

[0017] In the method for manufacturing a back-contact battery, by using a first silicon oxide layer as a mask layer for the first doping process and a second silicon oxide layer as a mask layer for the second doping process, the first doped conductive layer and the second doped conductive layer in the back-contact battery are formed. In the above steps, there is no need to use laser treatment for local film opening in the related art, so the problem of high manufacturing process difficulty caused by laser treatment can be avoided.

[0018] In addition, before the first doping process, a first silicon oxide layer is formed on the spacer region, and before the second doping process, a second silicon oxide layer is formed on the spacer region. The first silicon oxide layer and the second silicon oxide layer can also be used to protect the tunneling oxide layer and the intrinsic crystalline silicon layer on the spacer region, that is, when forming the first doped conductive layer and the second doped conductive layer, the tunneling oxide layer and the intrinsic crystalline silicon layer for isolating the first doped conductive layer and the second doped conductive layer are formed synchronously, which can improve the isolation effect between the first doped conductive layer and the second doped conductive layer, thereby improving the performance of the back-contact battery.

[0019] In addition, the method for manufacturing a back-contact battery provided by the embodiments of the present disclosure retains the tunneling oxide layer and the intrinsic crystalline silicon layer initially formed on the spacer region of the second surface of the substrate as an isolation structure between the first doped conductive layer and the second doped conductive layer, without introducing additional process steps to form an isolation structure between the first doped conductive layer and the second doped conductive layer, which can reduce the production process of the back-contact battery and improve the manufacturing efficiency of the back-contact battery. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] One or more embodiments are exemplarily illustrated by the pictures in the corresponding drawings. These exemplary illustrations do not constitute a limitation on the embodiments. Unless otherwise stated, the figures in the drawings do not constitute a scale limitation. To more clearly illustrate the technical solutions in the embodiments of the present disclosure or in the prior art, the drawings required to be used in the embodiments will be briefly introduced below. Obviously, the drawings in the following description are only some embodiments of the present disclosure. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0021] Figures 1 to 6 It is a schematic structural diagram corresponding to each step in the preparation method of a back-contact battery in the related art.

[0022] Figure 7 It is a schematic flow diagram of a preparation method of a back-contact battery provided by an embodiment of the present disclosure.

[0023] Figures 8 to 19 It is a schematic partial sectional structural diagram corresponding to each step in the preparation method of a back-contact battery provided by an embodiment of the present disclosure. Detailed implementation manners

[0024] Figures 1 to 6 It is a schematic structural diagram corresponding to each step in the preparation method of a back-contact battery in the related art. Among them, Figure 4 The arrow in indicates the area of the second laser treatment.

[0025] The preparation method of the back-contact battery in the related art includes the following steps: Refer to Figure 1 , provide a substrate 100, the substrate 100 has opposite first surface 110 and second surface 120, and the second surface 120 includes a first region 130, a second region 140, and a spacer region 150 located between the first region 130 and the second region 140; form a first tunneling oxide layer 101 and a first amorphous silicon layer in sequence on the second surface 120 of the substrate 100, and the first tunneling oxide layer 101 is located between the substrate 100 and the first amorphous silicon layer.

[0026] Continue to refer to Figure 1 , perform boron doping treatment on the first amorphous silicon layer to convert the first amorphous silicon layer into a boron-doped polysilicon layer 102, and form a layer of boron-containing silicon oxide layer, also known as BSG (Boron Silicate Glass) layer 112, on the surface of the boron-doped polysilicon layer 102 facing away from the first tunneling oxide layer 101.

[0027] Combined with reference to Figure 1 and Figure 2, the BSG layer 112 on the spacer 150 and the second region 140 is removed by using a first laser treatment, and the boron-doped polysilicon layer 102 and the first tunneling oxide layer 101 on the spacer 150 and the second region 140 are removed by etching with a first alkaline solution. Among them, when etching with the first alkaline solution, the BSG layer 112 on the first region 130 can serve as a protective layer for the first tunneling oxide layer 101 and the boron-containing polysilicon layer on the first region 130, and the first alkaline solution will only etch the boron-doped polysilicon layer 102 and the first tunneling oxide layer 101 on the spacer 150 and the second region 140 that are not protected by the BSG layer 112.

[0028] Reference Figure 3 , a second tunneling oxide layer 103 and a second amorphous silicon layer are sequentially deposited on the second surface 120 of the substrate 100. The second amorphous silicon layer is subjected to a phosphorus doping treatment to convert the second amorphous silicon layer into a phosphorus-doped polysilicon layer 104, and a layer of phosphorus-containing silicon oxide layer, also known as a PSG (PhosphoSilicate Glass) layer 114, is formed on the surface of the phosphorus-doped polysilicon layer 104 facing away from the second tunneling oxide layer 103.

[0029] Combined with reference Figures 3 to 5 , the PSG layer 114 on the first region 130 and the spacer 150 is removed by using a second laser treatment, and the phosphorus-doped polysilicon layer 104 and the second tunneling oxide layer 103 on the first region 130 and the spacer 150 are removed by using a second alkaline solution. Among them, when etching with the second alkaline solution, the PSG layer 114 on the second region 140 can serve as a protective layer for the second tunneling oxide layer 103 and the phosphorus-containing polysilicon layer on the second region 140, and the second alkaline solution will only etch the phosphorus-doped polysilicon layer 104 and the second tunneling oxide layer 103 on the spacer 150 and the second region 140 that are not protected by the PSG layer 114.

[0030] Combined with reference Figure 5 and Figure 6 , the BSG layer 112 on the first region 130 and the PSG layer 114 on the second region 140 are removed by etching with HF acid, completing the preparation of the first tunneling oxide layer 101 and the boron-doped polysilicon layer 102 on the first region 130 of the back contact battery, as well as the second tunneling oxide layer 103 and the phosphorus-doped polysilicon layer 104 on the second region 140, and forming a spacer 150 between the first region 130 and the second region 140 to prevent the phosphorus-doped polysilicon layer 104 and the boron-doped polysilicon layer 102 from making electrical contact.

[0031] In the preparation method of the back-contact battery in the related art, it is necessary to first use the first laser treatment and combine it with the etching of the first alkaline solution to remove the first tunneling oxide layer 101 and the boron-doped polysilicon layer 102 on the spacer 150 and the second region 140. In the subsequent steps, the second laser treatment and the etching with the second alkaline solution are used to remove the second tunneling oxide layer 103 and the boron-doped polysilicon layer 102 on the first region 130 and the spacer, so as to complete the preparation of the first tunneling oxide layer 101 and the boron-doped polysilicon layer 102 on the first region 130 of the back-contact battery, as well as the second tunneling oxide layer 103 and the phosphorus-doped polysilicon layer 104 on the second region 140, and form the spacer 150 located between the first region 130 and the second region 140.

[0032] In the above steps, if the first laser treatment is over-etched, although it can ensure the complete removal of the BSG layer on the spacer and the second region, it will damage the spacer with a certain thickness, as well as the boron-doped polysilicon layer and the first tunneling oxide layer on the second region. As a result, when etching with the first alkaline solution, it will damage the substrate of the spacer and the second region, affecting the performance of the back-contact battery. If the thickness of the etched film layer by the first laser treatment is too small, it is easy to leave part of the BSG layer. The remaining BSG layer will cause the boron-doped polysilicon layer and the phosphorus-doped polysilicon in the finally manufactured back-contact battery to be in electrical contact, resulting in leakage or hot spot effects, etc., which will also affect the performance of the back-contact battery. That is to say, the process of the first laser treatment is more difficult, resulting in a poor performance of the prepared back-contact battery.

[0033] Similarly, if the second laser treatment is over-etched, although it can ensure the complete removal of the PSG layer on the spacer and the first region, it will damage the spacer with a certain thickness, as well as the phosphorus-doped polysilicon layer and the second tunneling oxide layer on the first region. As a result, when etching with the second alkaline solution, it will damage the substrate of the spacer, affecting the performance of the back-contact battery. If the thickness of the etched film layer by the second laser treatment is too small, it is easy to leave part of the PSG layer. The remaining PSG layer will cause the phosphorus-doped polysilicon layer and the phosphorus-doped polysilicon in the finally manufactured back-contact battery to be in electrical contact, resulting in leakage or hot spot effects, etc., which will also affect the performance of the back-contact battery. That is to say, the process of the second laser treatment is more difficult, resulting in a poor performance of the prepared back-contact.

[0034] In summary, the preparation method of the back-contact battery in the related art uses laser treatment, resulting in a greater difficulty in the preparation process of the back-contact battery, and the performance of the prepared back-contact battery needs to be improved.

[0035] To this end, embodiments of the present disclosure provide a back-contact battery and a method for manufacturing the same. In the method for manufacturing the back-contact battery, a first silicon oxide layer is used as a mask layer for the first doping process, and a second silicon oxide layer is used as a mask layer for the second doping process to form a first doped conductive layer and a second doped conductive layer in the back-contact battery. In the above steps, there is no need to use laser treatment for local film opening in the related art, so the problem of high manufacturing process difficulty caused by laser treatment can be avoided.

[0036] In addition, before the first doping process, a first silicon oxide layer is formed on the spacer region. Before the second doping process, a second silicon oxide layer is formed on the spacer region. The first silicon oxide layer and the second silicon oxide layer can also be used to protect the tunneling oxide layer and the polysilicon layer on the spacer region. That is, when the first doped conductive layer and the second doped conductive layer are formed, the tunneling oxide layer and the polysilicon layer for isolating the first doped conductive layer and the second doped conductive layer are synchronously formed, which can improve the isolation effect between the first doped conductive layer and the second doped conductive layer, thereby improving the performance of the back-contact battery.

[0037] In the method for manufacturing the back-contact battery provided by the embodiments of the present disclosure, the tunneling oxide layer and the intrinsic crystalline silicon layer initially formed on the spacer region of the second side of the substrate are retained as the isolation structure between the first doped conductive layer and the second doped conductive layer. There is no need to introduce additional process steps to form the isolation structure between the first doped conductive layer and the second doped conductive layer, which can reduce the production process of the back-contact battery and improve the manufacturing efficiency of the back-contact battery.

[0038] In the description of the embodiments of the present disclosure, technical terms such as "first" and "second" are only used to distinguish different objects, and cannot be understood as indicating or implying relative importance or implicitly indicating the quantity, specific order or primary-secondary relationship of the indicated technical features. In the description of the embodiments of the present disclosure, the meaning of "a plurality" is more than two, unless otherwise specifically and clearly defined.

[0039] Referring to "embodiments" herein means that the specific features, structures or characteristics described in connection with the embodiments may be included in at least one embodiment of the present disclosure. The phrase appears in various places in the specification and does not necessarily refer to the same embodiment, nor is it an independent or alternative embodiment mutually exclusive with other embodiments. Those skilled in the art will explicitly and implicitly understand that the embodiments described herein may be combined with other embodiments.

[0040] In the description of the embodiments of the present disclosure, the term "and / or" is merely a description of the association relationship of the associated objects, indicating that there can be three relationships. For example, A and / or B can mean: A exists, both A and B exist, and B exists. In addition, the character " / " in this article generally represents an "or" relationship between the associated objects before and after.

[0041] In the description of the embodiments of the present disclosure, the term "plurality" means two or more (including two). Similarly, "multiple groups" means two or more groups (including two groups), and "multiple pieces" means two or more pieces (including two pieces).

[0042] In the description of the embodiments of the present disclosure, the orientation or positional relationship indicated by technical terms such as "center", "longitudinal", "transverse", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", "axial", "radial", "circumferential", etc. is based on the orientation or positional relationship shown in the drawings. It is only for the convenience of describing the embodiments of the present disclosure and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation. Therefore, it should not be construed as a limitation on the embodiments of the present disclosure.

[0043] In the description of the embodiments of the present disclosure, unless otherwise clearly specified and limited, technical terms such as "installation", "connection", "coupling", "fixation", etc. should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or integrated; it can also be a mechanical connection or an electrical connection; it can be directly connected or indirectly connected through an intermediate medium, and it can be the communication inside two elements or the interaction relationship between two elements. For those of ordinary skill in the art, the specific meanings of the above terms in the embodiments of the present disclosure can be understood according to specific circumstances.

[0044] In the corresponding drawings of the embodiments of the present disclosure, for better understanding and convenience of description, the thickness and area of the layer are enlarged. When describing a component (such as a layer, a film, a region, or a substrate) on or on the surface of another component, the component can be "directly" on the surface of the other component, or there can be a third component between the two components. On the contrary, when describing a component on the surface of another component or when a surface of a component forms or is provided with another component, it means that there is no third component between the two components. In addition, when describing a component "substantially" formed on another component, it means that the component is not formed on the entire surface (or the front surface) of the other component, nor on a partial edge of the entire surface.

[0045] In the description of the embodiments of the present disclosure, when a certain component "includes" another component, unless otherwise specified, other components are not excluded, and other components may further be included. In addition, when a component such as a layer, film, region, or plate is referred to as being "on / located on" another component, it may be "directly on" the other component (i.e., located on the surface of the other component with no other components therebetween), or there may be other components therebetween. In addition, when a layer, film, region, plate, etc. is "directly located on" another component, or when a layer, film, region, plate, etc. is located on the surface of another component, it means that no other components are located therebetween.

[0046] The following will elaborate on the embodiments of the present disclosure in conjunction with the accompanying drawings. However, those of ordinary skill in the art can understand that in the embodiments of the present disclosure, many technical details are presented to enable readers to better understand the present disclosure. However, even without these technical details and various changes and modifications based on the following embodiments, the technical solutions claimed in the present disclosure can still be implemented.

[0047] Figure 7 It is a schematic flow chart of a preparation method of a back contact battery provided for an embodiment of the present disclosure. Figures 8 to 19 It is a schematic partial cross-sectional structure diagram corresponding to each step in the preparation method of the back contact battery provided for an embodiment of the present disclosure.

[0048] Refer to Figure 7 , the preparation method of the back contact battery at least includes the following steps:

[0049] Refer to Figure 8 and Figure 9 , step S1, provide a substrate 200, the substrate 200 has opposite first surface 210 and second surface 220, the second surface 220 includes a first region 230, a second region 240, and a spacer region 250 located between the first region 230 and the second region 240; step S2, sequentially form a tunneling oxide layer 201 and an intrinsic crystalline silicon layer 202 on the second surface 220 of the substrate 200.

[0050] Step S3, form a first silicon oxide layer 203 on the surface of the intrinsic crystalline silicon layer 202 on the second region 240 and the spacer region 250.

[0051] Step S4, refer to Figures 10 to 12 , using the first silicon oxide layer 203 as a first mask layer, perform a first doping process on the intrinsic crystalline silicon layer 202 located on the first region 230, so that the intrinsic crystalline silicon layer 202 located on the first region 230 is converted into a first doped conductive layer 212 containing a first doping element, and form a first doped silicon glass layer (not shown) on the surface of the first doped conductive layer 212 facing away from the tunneling oxide layer 201.

[0052] Step S5, refer toFigure 13 , remove the first silicon oxide layer 203 and the first doped silicon glass layer.

[0053] Step S6, refer to Figure 14 , form a second silicon oxide layer 204 on the surface of the first doped conductive layer 212 and the intrinsic crystalline silicon layer 202 located on the spacer region 250.

[0054] Step S7, refer to Figures 15 to 17 , using the second silicon oxide layer 204 as the second mask layer, perform a second doping process on the intrinsic crystalline silicon layer 202 located on the second region 240, so that the intrinsic crystalline silicon layer 202 located on the second region 240 is converted into a second doped conductive layer 222 containing a second doping element, and form a second doped silicon glass layer (not shown) on the surface of the second doped conductive layer 222 facing away from the tunneling oxide layer 201, wherein the second doping element has a different conductivity type from the first doping element.

[0055] Step S8, refer to Figure 18 and Figure 19 , remove the second silicon oxide layer 204 and the second doped silicon glass layer.

[0056] Among them, the first silicon oxide layer 203 formed on the spacer region 250 on the second surface 220 of the substrate 200 in step S3 can play a diffusion protection role in step S4, that is, the first doping element introduced by the first doping process will only be incorporated into the intrinsic crystalline silicon layer 202 on the first region 230, and will not be incorporated into the intrinsic crystalline silicon layer 202 on the second region 240 and the spacer region 250. Similarly, the second silicon oxide layer 204 formed in step S6 can play a diffusion protection role in step S7, that is, the second doping element introduced by the second doping process will only be incorporated into the intrinsic crystalline silicon layer 202 on the second region 240, and will not be incorporated into the first doped conductive layer 212 on the first region 230 and the intrinsic crystalline silicon layer 202 on the spacer region 250.

[0057] The tunneling oxide layer 201 and the intrinsic crystalline silicon layer 202 formed on the spacer region 250 on the second surface 220 of the substrate 200 in step S2, under the protection of the first silicon oxide layer 203 and the second silicon oxide layer 204, serve as an isolation structure between the first doped conductive layer 212 and the second doped conductive layer 222. There is no need to introduce additional process steps to form an isolation structure between the first doped conductive layer 212 and the second doped conductive layer 222, which can reduce the production process of the back contact battery and improve the preparation efficiency of the back contact battery. In addition, using the tunneling oxide layer 201 and the intrinsic crystalline silicon layer 202 as the isolation structure between the first doped conductive layer 212 and the second doped conductive layer 222 can improve the isolation effect between the first doped conductive layer 212 and the second doped conductive layer 222, thereby improving the performance of the back contact battery.

[0058] In addition, in the method for manufacturing a back-contact battery provided by the embodiments of the present disclosure, the first silicon oxide layer 203 is used as a mask layer (or diffusion protection layer) for the first doping process, and the second silicon oxide layer 204 is used as a mask layer (or diffusion protection layer) for the second doping process to form the first doped conductive layer 212 and the second doped conductive layer 222 in the back-contact battery. In the above steps, there is no need to use local film opening by laser treatment in the related art, so the problem of high manufacturing process difficulty caused by laser treatment can be avoided.

[0059] The embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings.

[0060] Continuing to refer to Figure 9 , in some embodiments, in step S1, the material of the substrate 200 may be an elemental semiconductor material. Specifically, the elemental semiconductor material is composed of a single element, for example, it may be silicon or germanium. Among them, the elemental semiconductor material may be in a single crystal state, a polycrystalline state, an amorphous state, or a microcrystalline state (a state with both single crystal and amorphous states is called a microcrystalline state). For example, silicon may be at least one of single crystal silicon, polycrystalline silicon, amorphous silicon, or microcrystalline silicon. In other embodiments, the material of the substrate 200 may also be a compound semiconductor material. Common compound semiconductor materials include, but are not limited to, silicon germanide, silicon carbide, gallium arsenide, indium gallium, perovskite, cadmium telluride, copper indium selenide, and other materials. Subsequently, an exemplary description will be given with the material of the substrate 200 being silicon.

[0061] In some embodiments, the substrate 200 may be an N-type semiconductor substrate doped with an N-type doping element. In some examples, the N-type doping element may be at least one of group V elements such as phosphorus (P), bismuth (Bi), antimony (Sb), or arsenic (As); the P-type semiconductor substrate is doped with a P-type element, and the P-type doping element may be at least one of group III elements such as boron (B), aluminum (Al), gallium (Ga), or indium (In).

[0062] The substrate 200 has opposite first surface 210 and second surface 220. In some embodiments, the back-contact battery is a single-sided battery, then the first surface 210 of the substrate 200 may be used as the light-receiving surface for receiving incident light, and the second surface 220 is used as the backlight surface. In some embodiments, the back-contact battery is a double-sided battery, then both the first surface 210 and the second surface 220 of the substrate 200 may be used as light-receiving surfaces and can be used to receive incident light. It can be understood that the backlight surface referred to in the embodiments of the present application can also receive incident light, but the degree of receiving incident light is weaker than that of the light-receiving surface, so it is defined as the backlight surface.

[0063] In some embodiments, the texturing process can be performed on at least one surface of the first surface 210 or the second surface 220 of the substrate 200 to form a textured surface on at least one surface of the first surface 210 or the second surface 220 of the substrate 200. In this way, the absorption and utilization rate of the incident light by the first surface 210 and the second surface 220 of the substrate 200 can be enhanced.

[0064] In some embodiments, the textured surface can be a pyramid textured surface. As a common textured surface, the pyramid textured surface not only reduces the reflectivity of the surface of the substrate 200, but also forms an optical trap, enhances the absorption effect of the substrate 200 on the incident light, and improves the photoelectric conversion efficiency of the back-contact battery.

[0065] Specifically, if the back-contact battery is a single-sided battery, a textured surface can be formed on the light-receiving surface of the substrate 200, for example, it can be a pyramid textured surface. The backlight surface of the substrate 200 can also be a polished surface, that is, the backlight surface of the substrate 200 is flatter than the light-receiving surface. It should be noted that for a single-sided battery, a textured surface can also be formed on both the light-receiving surface and the backlight surface of the substrate 200.

[0066] If the back-contact battery is a double-sided battery, textured surfaces can be formed on both the light-receiving surface and the backlight surface of the substrate.

[0067] The first region 230 of the substrate 200 is used to form the tunneling oxide layer 201 and the first doped conductive layer 212 subsequently. The second region 240 of the substrate 200 is used to form the tunneling oxide layer 201 and the second doped conductive layer 222 subsequently. The spacer region 250 of the substrate 200 is used to isolate the first doped conductive layer 212 and the second doped conductive layer 222.

[0068] It can be understood that Figures 8 to 19 only the case where the second surface 220 includes a first region 230, a second region 240, and a spacer region 250 is shown in the figure. In fact, the second surface 220 of the back-contact battery includes a plurality of first regions and second regions arranged alternately in the first direction, and the spacer region is located between the first region and the second region.

[0069] The tunneling oxide layer 201 can provide a good passivation effect for the substrate 200.

[0070] The tunneling oxide layer 201 located in the first region 230 can also enable majority carriers to tunnel into the subsequently formed first doped conductive layer 212 while blocking the recombination of minority carriers, helping the first doped conductive layer 212 to complete the collection of majority carriers and improving the performance of the back contact battery. The tunneling oxide layer 201 located in the second region 240 can also enable majority carriers to tunnel into the subsequently formed second doped conductive layer 222 while blocking the recombination of minority carriers, helping the second doped conductive layer 222 to complete the collection of majority carriers and improving the performance of the back contact battery. The tunneling oxide layer 201 located in the spacer region 250 can achieve electrical isolation between the first doped conductive layer 212 and the second doped conductive layer 222.

[0071] The material of the tunneling oxide layer 201 can be silicon oxide.

[0072] The method for forming the tunneling oxide layer 201 can be a thermal oxidation process or a chemical vapor deposition method, etc.

[0073] The intrinsic crystalline silicon layer 202 located on the first region 230 is used for subsequent first doping treatment to form the first doped conductive layer 212; the intrinsic crystalline silicon layer 202 located on the second region 240 is used for subsequent second doping treatment to form the second doped conductive layer 222. The intrinsic crystalline silicon layer 202 located in the spacer region 250 is used to isolate the first doped conductive layer 212 and the second doped conductive layer 222.

[0074] Reference Figure 9 , in some embodiments, the method for forming the intrinsic crystalline silicon layer 202 includes: forming an amorphous intrinsic crystalline silicon layer 202 on the surface of the tunneling oxide layer 201 facing away from the second surface 220; using a first thermal oxidation process to form a first silicon oxide layer 203, and when performing the first thermal oxidation process, the intrinsic crystalline silicon layer 202 is converted from the amorphous state to the polycrystalline state.

[0075] The method for forming the amorphous intrinsic crystalline silicon layer 202 can be chemical vapor deposition.

[0076] When using the first thermal oxidation process to prepare the first silicon oxide layer 203, a high-temperature environment and an oxygen-containing atmosphere will be provided to form the first silicon oxide. Under the action of the high-temperature environment, the intrinsic crystalline silicon layer 202 will be converted from the amorphous state to the polycrystalline state.

[0077] In step S3, reference Figures 9 to 11, in some embodiments, a first silicon oxide layer 203 is formed on the surface of the intrinsic crystalline silicon layer 202 on the second region 240 and the spacer region 250, including: forming the first silicon oxide layer 203 on the surface of the intrinsic crystalline silicon layer 202 facing away from the tunneling oxide layer 201; forming a first organic mask layer 206 on the surface of the first silicon oxide layer 203 on the second region 240 and the spacer region 250 facing away from the tunneling oxide layer 201; removing the first silicon oxide layer 203 on the first region 230 using a first acidic solution; removing the first organic mask layer 206 using a first alkaline solution.

[0078] The first silicon oxide layer 203 can play a role in diffusion protection in step S4, that is, the first doping element introduced by the first doping process will only be incorporated into the intrinsic crystalline silicon layer 202 on the first region 230, rather than into the intrinsic crystalline silicon layer 202 on the second region 240 and the spacer region 250.

[0079] The preparation of the first silicon oxide layer 203 and the conversion of the intrinsic crystalline silicon layer 202 from the amorphous state to the polycrystalline state can be completed simultaneously by using the first thermal oxidation process.

[0080] In some embodiments, the process temperature of the first thermal oxidation process is 600°C to 800°C, such as 600°C, 650°C, 700°C, 750°C or 800°C, etc.; the oxygen flow rate introduced in the first thermal oxidation process is 1500 sccm to 8000 sccm, such as 1500 sccm, 2000 sccm, 4000 sccm, 5000 sccm, 6000 sccm or 8000 sccm, etc.; the process duration of the first thermal oxidation process is 500 s to 3000 s, such as 500 s, 1000 s, 1500 s, 2000 s, 2500 s or 3000 s, etc. When the process temperature, oxygen flow rate and process duration of the first thermal oxidation process are within the above ranges, the intrinsic crystalline silicon layer 202 can be converted from the amorphous state to the polycrystalline state while forming the first silicon oxide layer 203 that can be used to protect the spacer region 250 and the second region 240.

[0081] In some embodiments, the thickness of the first silicon oxide layer 203 is 10 nm to 40 nm, such as 10 nm, 15 nm, 20 nm, 25 nm, 30 nm, 35 nm or 40 nm. When the thickness of the first silicon oxide layer 203 is within the above range, it can ensure that the first silicon oxide layer 203 protects the intrinsic crystalline silicon layer 202 on the spacer region 250 and the second region 240 while avoiding the problem of increased cost caused by the excessive thickness of the first silicon oxide layer 203.

[0082] A first organic mask layer 206 is formed on the surface of the first silicon oxide layer 203 on the second region 240 and the spacer region 250, facing away from the surface of the tunneling oxide layer 201. The first organic mask layer 206 can serve as a protective layer for the first silicon oxide layer 203 on the second region 240 and the spacer region 250. Utilizing the acid-resistant and alkali-sensitive characteristics of the first organic mask layer 206, when etching with the first acidic solution subsequently, the first silicon oxide layer 203 on the second region 240 and the spacer region 250 will not be damaged by the first acidic solution because it is protected by the first organic mask layer 206, while the first silicon oxide layer 203 on the first region 230 will be removed under the action of the first acidic solution; subsequently, the acid-resistant and alkali-sensitive characteristics of the first organic mask layer 206 are also utilized to remove the first organic mask layer 206 on the second region 240 and the spacer region 250 using the first alkaline solution.

[0083] The material of the first organic mask layer 206 can be paraffin wax, beeswax, polymethyl methacrylate, polyimide (PI), polystyrene (PS), etc.

[0084] In some embodiments, the thickness of the first organic mask layer 206 is 5 μm to 20 μm, such as 5 μm, 8 μm, 10 μm, 15 μm, 18 μm or 20 μm. When the thickness of the first organic mask layer 206 is within the above range, it can provide sufficient protection for the first silicon oxide layer 203 on the second region 240 and the spacer region 250, and can also avoid the problem of too high preparation cost caused by the too thick first organic mask layer 206.

[0085] In some embodiments, the method for forming the first organic mask layer 206 includes a printing method and a spraying method. The first organic mask layer 206 can be locally formed using the printing method or the spraying method. Such a preparation method is relatively simple and is beneficial to improving the preparation efficiency of the back contact battery.

[0086] In some embodiments, the first acidic solution is hydrofluoric acid with a mass concentration of 3% to 10%, such as the mass concentration can be 3%, 4%, 5%, 6%, 8%, 9% or 10%; the process temperature for etching with the first acidic solution is 15°C to 40°C, such as 15°C, 20°C, 25°C, 30°C, 35°C, 40°C. When the mass concentration of the first acidic solution is within the above range and the process temperature is within the above range, it can ensure that while the first acidic solution effectively removes the first silicon oxide layer 203 on the first region 230, it basically does not damage the first organic mask layer 206 on the second region 240 and the spacer region 250.

[0087] In some embodiments, the mass concentration of the first alkaline solution is 2% to 5%, such as 2%, 3%, 4%, or 5%; the process temperature for etching with the first alkaline solution is 15°C to 40°C, such as 15°C, 20°C, 25°C, 30°C, 35°C, 40°C. When the mass concentration of the first alkaline solution is within the above range and the process range is within the above range, it can ensure that while the first alkaline solution removes the first organic mask layer 206, it will basically not react with the intrinsic silicon layer 202 on the first region 230. In this way, it is possible to avoid additional damage to the intrinsic silicon layer 202 on the first region 230 caused by removing the first organic mask layer 206, which may affect the performance of the back contact battery, thus being beneficial to improving the reliability of preparing the back contact battery.

[0088] The first alkaline solution can be sodium hydroxide, potassium hydroxide, etc.

[0089] Reference Figure 12 , in step S4, the first silicon oxide layer 203 serves as the first mask layer, and a first doping process is performed on the intrinsic silicon layer 202 located on the first region 230, so that the intrinsic silicon layer 202 located on the first region 230 is converted into a first doped conductive layer 212 containing a first doping element, and a first doped silicon glass layer is formed on the surface of the first doped conductive layer 212 facing away from the tunneling oxide layer 201.

[0090] The first doping process can be a high-temperature diffusion method, an ion implantation method, a laser doping method, etc.

[0091] Under the protection of the first silicon oxide layer 203, for the intrinsic silicon layer 202 on the second region 240 and the spacer region 250, the first doping element introduced by the first doping process will only be incorporated into the intrinsic silicon layer 202 on the first region 230, converting the intrinsic silicon layer 202 on the first region 230 into the first doped conductive layer 212.

[0092] The first doping element can be a P-type element or an N-type element.

[0093] The tunneling oxide layer 201 and the first doped conductive layer 212 on the first region 230 can passivate the second surface 220, reduce surface recombination, improve the carrier lifetime, and thus enhance the open-circuit voltage and overall efficiency of the battery.

[0094] The first doped silicon glass layer can be a phosphosilicate glass layer or a borosilicate glass layer. The "boron" or "phosphorus" therein depends on the doping element during the first doping process. For example, if the doping element is boron, the first doped silicon glass layer is a borosilicate glass layer.

[0095] Reference Figure 12 and Figure 13, in step S5, the method for removing the first silicon oxide layer 203 and the first doped silicon glass layer on the second region 240 and the spacer region 250 may be: using 3% - 10% hydrofluoric acid, for example, the mass concentration may be 3%, 4%, 5%, 6%, 8%, 9% or 10%; the process temperature for etching with the first acidic solution is 15°C - 40°C, for example, 15°C, 20°C, 25°C, 30°C, 35°C, 40°C.

[0096] Reference Figure 14 and Figure 16 , in step S6, forming a second silicon oxide layer 204 on the surface of the first doped conductive layer 212 and the intrinsic crystalline silicon layer 202 located on the spacer region 250 includes: forming the second silicon oxide layer 204 on the surfaces of the intrinsic crystalline silicon layer 202 and the first doped conductive layer 212 facing away from the tunneling oxide layer 201; forming a second organic mask layer 216 on the surface of the second silicon oxide layer 204 on the first region 230 and the spacer region 250 facing away from the tunneling oxide layer 201; using a second acidic solution to remove the second silicon oxide layer 204 on the second region 240; using a second basic solution to remove the second organic mask layer 216.

[0097] The method for forming the second silicon oxide layer 204 includes a second thermal oxidation process. The process temperature of the second thermal oxidation process is 600°C - 800°C, for example, 600°C, 650°C, 700°C, 750°C or 800°C, etc.; the oxygen flow rate introduced in the second thermal oxidation process is 1500 sccm - 8000 sccm, for example, 1500 sccm, 2000 sccm, 4000 sccm, 5000 sccm, 6000 sccm or 8000 sccm, etc.; the process duration of the second thermal oxidation process is 500 s - 3000 s, for example, 500 s, 1000 s, 1500 s, 2000 s, 2500 s or 3000 s, etc. When the process temperature, oxygen flow rate and process duration of the second thermal oxidation process are within the above ranges, the second silicon oxide layer 204 that can be used to protect the spacer region 250 and the first region 230 can be formed.

[0098] In some embodiments, the thickness of the second silicon oxide layer 204 is 10 nm - 40 nm, for example, 10 nm, 15 nm, 20 nm, 25 nm, 30 nm, 35 nm or 40 nm. When the thickness of the second silicon oxide layer 204 is within the above range, the second silicon oxide layer 204 can protect the first doped conductive layer 212 and the intrinsic crystalline silicon layer 202 on the spacer region 250 while avoiding the problem of increased cost caused by an overly thick second silicon oxide layer 204.

[0099] A second organic mask layer 216 is formed on the surface of the second silicon oxide layer 204 on the first region 230 and the spacer region 250. The second organic mask layer 216 can serve as a protective layer for the second silicon oxide layer 204 on the first region 230 and the spacer region 250. Utilizing the acid-resistant but alkali-sensitive property of the second organic mask layer 216, when etching with a second acidic solution in a subsequent step, the second silicon oxide layer 204 on the first region 230 and the spacer region 250 will not be damaged by the second acidic solution because it is protected by the second organic mask layer 216, while the second silicon oxide layer 204 on the second region 240 will be removed under the action of the second acidic solution; subsequently, the acid-resistant but alkali-sensitive property of the second organic mask layer 216 is also utilized to remove the second organic mask layer 216 on the first region 230 and the spacer region 250 using a second alkaline solution.

[0100] The material of the second organic mask layer 216 can be paraffin wax, beeswax, polymethyl methacrylate, polyimide (PI), polystyrene (PS), etc.

[0101] The thickness of the second organic mask layer is 5 μm to 20 μm, such as 5 μm, 8 μm, 10 μm, 15 μm, 18 μm or 20 μm. When the thickness of the second organic mask layer 216 is within the above range, it can provide sufficient protection for the second silicon oxide layer 204 on the first region 230 and the spacer region 250, and can also avoid the problem of excessive preparation cost caused by the over-thickness of the second organic mask layer 216.

[0102] The method for forming the second organic mask layer 216 includes a printing method and a spraying method. The second organic mask layer 216 can be locally formed using the printing method or the spraying method. Such a preparation method is relatively simple and is beneficial to improving the preparation efficiency of the back-contact battery.

[0103] In some embodiments, the second acidic solution is hydrofluoric acid with a mass concentration of 3% to 10%, for example, the mass concentration can be 3%, 4%, 5%, 6%, 8%, 9% or 10%; the process temperature for etching with the second acidic solution is 15°C to 40°C, such as 15°C, 20°C, 25°C, 30°C, 35°C, 40°C. When the mass concentration of the second acidic solution is within the above range and the process temperature is within the above range, it can ensure that the second acidic solution effectively removes the second silicon oxide layer 204 on the second region 240 while basically not damaging the second organic mask layer 216 on the first region 230 and the spacer region 250.

[0104] In some embodiments, the mass concentration of the second alkaline solution is 2% to 5%, such as 2%, 3%, 4%, or 5%; the process temperature for etching with the second alkaline solution is 15°C to 40°C, such as 15°C, 20°C, 25°C, 30°C, 35°C, 40°C. When the mass concentration of the second alkaline solution is within the above range and the process range is within the above range, it can be ensured that while the second alkaline solution removes the second organic mask layer 216, it will basically not react with the first doped conductive layer 212. In this way, it is possible to avoid the situation where the removal of the second organic mask layer 216 causes additional damage to the first doped conductive layer 212 and affects the performance of the back contact battery, thereby improving the reliability of fabricating the back contact battery.

[0105] The second alkaline solution can be sodium hydroxide, potassium hydroxide, etc.

[0106] Reference Figure 17 , in step S7, using the second silicon oxide layer 204 as the second mask layer, the intrinsic crystalline silicon layer 202 located on the second region 240 is subjected to a second doping process, so that the intrinsic crystalline silicon layer 202 located on the second region 240 is converted into a second doped conductive layer 222 containing a second doping element, and a second doped silicon glass layer is formed on the surface of the second doped conductive layer 222 facing away from the tunneling oxide layer 201, wherein the second doping element has a different conductivity type from the first doping element.

[0107] The second doping process can be a high-temperature diffusion method, an ion implantation method, a laser doping method, etc.

[0108] Under the protection of the second silicon oxide layer 204, the first conductive layer on the first region 230 and the intrinsic crystalline silicon layer 202 on the spacer region 250, the second doping element introduced by the second doping process will only be incorporated into the intrinsic crystalline silicon layer 202 on the second region 240, converting the intrinsic crystalline silicon layer 202 on the second region 240 into the second doped conductive layer 222.

[0109] The second doping element has a different conductivity type from the first doping element. Specifically, the first doping element is one of a P-type element and an N-type element, and the second doping element is the other of a P-type element and an N-type element.

[0110] The tunneling oxide layer 201 and the second doped conductive layer 222 on the second region 240 can passivate the second surface 220, reduce surface recombination, increase the carrier lifetime, and thus improve the open-circuit voltage and overall efficiency of the battery.

[0111] The second doped silicon back layer can be a phosphosilicate glass layer or a borosilicate glass layer. The "boron" or "phosphorus" therein depends on the doping element during the second doping process. For example, if the doping element is phosphorus, the first doped silicon glass layer is a phosphosilicate glass layer.

[0112] ReferenceFigure 17 and Figure 18 In step S8, the method for removing the second silicon oxide layer 204 and the second doped silicon glass layer on the first region 230 and the spacer region 250 may be as follows: using 3% to 10% hydrofluoric acid, for example, the mass concentration may be 3%, 4%, 5%, 6%, 8%, 9% or 10%; the process temperature for etching with the second acidic solution is 15°C to 40°C, for example, 15°C, 20°C, 25°C, 30°C, 35°C, 40°C.

[0113] Reference Figure 19 In some embodiments, the method for preparing the back contact battery may further include: forming a first passivation layer 207 on the first surface 210, and forming a second passivation layer 217 on the surfaces of the first doped conductive layer 212, the second doped conductive layer 222 and the intrinsic crystalline silicon layer 202 that are away from the tunneling oxide layer 201.

[0114] The first passivation layer 207 can play a good passivation role on the substrate 200. The first passivation layer 207 can also have a good antireflection effect, reducing the reflection of the incident light by the first surface 210 of the substrate 200 and improving the utilization rate of the incident light by the substrate 200.

[0115] The material of the first passivation layer 207 may be at least one of silicon oxide, aluminum oxide, silicon nitride or silicon oxynitride.

[0116] The method for forming the first passivation layer 207 may be chemical vapor deposition.

[0117] The second passivation layer 217 can play a good passivation role on the substrate 200. For example, it can perform better chemical passivation on the dangling bonds of the second surface 220, saturate the dangling bonds of the substrate 200, reduce the defect state density of the substrate 200, and inhibit the carrier recombination of the substrate 200.

[0118] The material of the second passivation layer 217 may be at least one of silicon oxide, aluminum oxide, silicon nitride or silicon oxynitride.

[0119] The method for forming the second passivation layer 217 may be chemical vapor deposition.

[0120] Continue to refer to Figure 19 In some embodiments, the method for preparing the back contact battery may further include: printing a metal paste on the surface of the passivation layer on the second surface 220 by screen printing to form a first electrode 208 in electrical contact with the first doped conductive layer 212, and a second electrode 218 in electrical contact with the second doped conductive layer 222.

[0121] In some embodiments, the metal paste may include at least one of silver, aluminum, copper, tin, gold, lead or nickel.

[0122] The metal paste is subjected to a sintering process. In some embodiments, the metal paste contains materials with high corrosive components such as glass. Thus, during the sintering process, the corrosive components will corrode the passivation layer, a portion of the first doped conductive layer 212, and a portion of the second doped conductive layer 222, thereby allowing the metal paste to penetrate into the passivation layer and a portion of the first doped conductive layer 212 and a portion of the second doped conductive layer 222 to form a first electrode 208 electrically contacting the first doped conductive layer 212 and a second electrode 218 electrically contacting the second doped conductive layer 222.

[0123] Table 1 is a comparison table of the performance parameters of the solar cell prepared by the embodiment of the present disclosure and the performance parameters of the solar cell prepared by using related technologies.

[0124] Table 1

[0125] Uoc Isc FF Irev Eff Comparative example 740 mV 14.6A 83.0 0.8A 26.81％ Embodiment of the present disclosure 743 mV 14.6A 83.0 0.3A 26.91％

[0126] Among them, the comparative example is the performance parameters of the back contact battery prepared by laser technology in the related art (for details, please refer to the above comparative example). Figures 1 to 6 The corresponding preparation method of the back contact battery in the related technology). Uoc is the open-circuit voltage, which refers to the voltage difference between the positive and negative electrodes of the photovoltaic cell when there is no external load, that is, in an open circuit state. Isc is the short-circuit current, which refers to the current passing through the photovoltaic cell when the photovoltaic cell is in a short-circuit state (the external load resistance is zero). FF is the fill factor, which is an important parameter for measuring the output characteristics of photovoltaic cells. It is equal to the ratio of the maximum output power of the photovoltaic cell to the product of the open-circuit voltage and the short-circuit current, reflecting the efficiency of the photovoltaic cell in actual work. Irev is the reverse current, which refers to the current passing through the cell when the photovoltaic cell is in a reverse bias state. Under normal circumstances, reverse current should be avoided when the photovoltaic cell is working normally, because it will cause the battery to heat up, reduce efficiency or even be damaged. Eff is the conversion efficiency, which refers to the efficiency of photovoltaic cells in converting solar energy into electrical energy. It is usually expressed as a percentage and is one of the key indicators for measuring the performance of photovoltaic cells.

[0127] It can be seen from Table 1 that the preparation method of the embodiment of the present disclosure effectively improves the open circuit voltage of the back contact battery and reduces the reverse current of the back contact battery, so that the photoelectric conversion efficiency of the back contact battery is improved.

[0128] Correspondingly, another aspect of the embodiments of the present disclosure further provides a back contact battery prepared by the preparation method of the back contact battery according to any one of the foregoing embodiments. It should be noted that for the same or corresponding parts as those in the foregoing embodiments, reference may be made to the corresponding descriptions in the foregoing embodiments, which will not be elaborated below.

[0129] Reference Figure 18 Or Figure 19 , the back contact battery includes: a substrate 200, a tunneling oxide layer 201, a first doped conductive layer 212, a second doped conductive layer 222, and an intrinsic crystalline silicon layer 202. The substrate 200 has opposite first and second surfaces 210 and 220. The second surface 220 includes a first region 230, a second region 240, and a spacer region 250 located between the first region 230 and the second region 240. The tunneling oxide layer 201 is located on the second surface 220. The first doped conductive layer 212 is located on the first region 230 and on the surface of the tunneling oxide layer 201 facing away from the second surface 220. The first doped conductive layer 212 contains a first doping element. The second doped conductive layer 222 is located on the second region 240 and on the surface of the tunneling oxide layer 201 facing away from the second surface 220. The second doped conductive layer 222 includes a second doping element, and the second doping element has a different conductivity type from the first doping element. The intrinsic crystalline silicon layer 202 is located on the spacer region 250 and between the first doped conductive layer 212 and the second doped conductive layer 222.

[0130] Those of ordinary skill in the art can understand that the above-described embodiments are specific embodiments for implementing the present disclosure. In actual applications, various changes can be made in form and details without departing from the spirit and scope of the present disclosure. Any person skilled in the art can make various modifications and changes without departing from the spirit and scope of the present disclosure. Therefore, the protection scope of the present disclosure should be subject to the scope defined by the claims.

Claims

1. A method for preparing a back contact battery, characterized in that: include: Providing a substrate, the substrate having a first side and a second side opposite to each other, the second side comprising a first region, a second region, and a spacer region between the first region and the second region; forming a tunneling oxide layer and an intrinsic crystalline silicon layer in sequence on the second surface of the substrate; forming a first silicon oxide layer on the surface of the intrinsic crystalline silicon layer on the second region and the spacer region; Using the first silicon oxide layer as a first mask layer, performing a first doping treatment on the intrinsic crystalline silicon layer located on the first region, so that the intrinsic crystalline silicon layer located on the first region is converted into a first doped conductive layer containing a first doping element, and forming a first doped silicon glass layer on a surface of the first doped conductive layer away from the tunnel oxide layer; removing the first silicon oxide layer and the first doped silicon glass layer; forming a second silicon oxide layer on the surface of the first doped conductive layer and the intrinsic crystalline silicon layer located on the spacer region; Using the second silicon oxide layer as a second mask layer, performing a second doping treatment on the intrinsic crystalline silicon layer located on the second region, so that the intrinsic crystalline silicon layer located on the second region is converted into a second doped conductive layer containing a second doping element, and forming a second doped silicon glass layer on a surface of the second doped conductive layer away from the tunnel oxide layer, wherein the second doping element has a different conductivity type from the first doping element; The second silicon oxide layer and the second doped silicon glass layer are removed.

2. The method for preparing a back contact battery according to claim 1, characterized in that: The method for forming the intrinsic crystalline silicon layer includes: forming the intrinsic crystalline silicon layer in an amorphous silicon state on the surface of the tunneling oxide layer away from the second surface; using a first thermal oxidation process to form the first silicon oxide layer, and when performing the first thermal oxidation process, the intrinsic crystalline silicon layer is converted from the amorphous silicon state to a polycrystalline silicon state.

3. The method for preparing a back contact battery according to claim 2, characterized in that: Forming the first silicon oxide layer on the surface of the intrinsic crystalline silicon layer on the second region and the spacer region comprises: forming the first silicon oxide layer on a surface of the intrinsic crystalline silicon layer away from the tunnel oxide layer; forming a first organic mask layer on a surface of the first silicon oxide layer on the second region and the spacer region facing away from the tunnel oxide layer; Using a first acidic solution to etch and remove the first silicon oxide layer on the first region; The first organic mask layer is removed by etching using a first alkaline solution.

4. The method for preparing a back contact battery according to claim 3, characterized in that: The second silicon oxide layer is formed on the surface of the first doped conductive layer and the intrinsic crystalline silicon layer located on the spacer region, comprising: forming a second silicon oxide layer on the intrinsic crystalline silicon layer and the surface of the first doped conductive layer away from the tunnel oxide layer; forming a second organic mask layer on a surface of the second silicon oxide layer on the first region and the spacer region facing away from the tunnel oxide layer; Using a second acidic solution to etch and remove the second silicon oxide layer on the second region; The second organic mask layer is removed by etching using a second alkaline solution.

5. The method for preparing a back contact battery according to claim 4, characterized in that: The process temperature of the first thermal oxidation process is 600° C. to 800° C., and the oxygen flow rate introduced in the first thermal oxidation process is 1500 sccm to 8000 sccm. The process duration of the first thermal oxidation process is 500s to 3000s; The method for forming the second silicon oxide layer includes a second thermal oxidation process, the process temperature of the second thermal oxidation process is 600°C to 800°C, the oxygen flow rate introduced in the second thermal oxidation process is 1500sccm to 8000sccm, and the process time of the second thermal oxidation process is 500s to 3000s.

6. The method for preparing a back contact battery according to claim 4, characterized in that: The thickness of the first organic mask layer is 5 μm to 20 μm; the method of forming the first organic mask layer includes a printing method and a spraying method; The thickness of the second organic mask layer is 5 μm to 20 μm; Methods for forming the second organic mask layer include printing and spraying.

7. The method for preparing a back contact battery according to claim 4, characterized in that: The mass concentration of the first alkaline solution is 2% to 5%, and the etching process temperature of the first alkaline solution is 15°C to 40°C; the mass concentration of the second alkaline solution is 2% to 5%, and the etching process temperature of the second alkaline solution is 15°C to 40°C.

8. The method for preparing a back contact battery according to claim 4, characterized in that: The first acidic solution is hydrofluoric acid with a mass concentration of 3% to 10%, and the etching process temperature of the first acidic solution is 15°C to 40°C; the second acidic solution is hydrofluoric acid with a mass concentration of 3% to 10%, and the etching process temperature of the second acidic solution is 15°C to 40°C.

9. The method for preparing a back contact battery according to any one of claims 1 to 8, characterized in that: The thickness of the first silicon oxide layer is 10 nm to 40 nm; the thickness of the second silicon oxide layer is 10 nm to 40 nm.

10. A back contact battery, characterized in that: include: A substrate having a first side and a second side opposite to each other, wherein the second side includes a first region, a second region, and a spacer region between the first region and the second region; a tunneling oxide layer, wherein the tunneling oxide layer is located on the second surface; a first doped conductive layer, the first doped conductive layer being located on the first region and on a surface of the tunneling oxide layer facing away from the second surface, the first doped conductive layer comprising a first doping element; a second doped conductive layer, the second doped conductive layer being located on the second region and on a surface of the tunneling oxide layer facing away from the second surface, the second doped conductive layer comprising a second doping element, and the second doping element and the first doping element have a different conductivity type; An intrinsic crystalline silicon layer is located on the spacer and between the first doped conductive layer and the second doped conductive layer.

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