Burr reduction in phase shifters

Abstract

Methods and apparatus for reducing glitches in phase shifters implementing high isolation switches are disclosed. When transitioning from one phase shift to another, such glitches may occur at the output of the phase shifter. The disclosed method implements a delay in each step of phase shifter conversion. Exemplary embodiments for implementing single-pole multi-throw are provided, and exemplary performance of the disclosed methods is also presented. The described method is also applicable to multi-stage attenuators.

Description

[0001] Cross - reference to related applications

[0002] This application claims priority to U.S. Patent Application No. 17 / 933,230, filed on September 19, 2022, the content of which is incorporated herein by reference in its entirety. Technical field

[0003] The present disclosure relates to phase shifters, and more particularly, to methods and apparatuses for reducing glitches in a phase shifter when switching from one phase shift to another in a phase shifter implementing a high - isolation switch. Background art

[0004] A phase shifter can be implemented using high - isolation switches. FIG. 1A shows a prior - art phase shifter (100A) that includes single - pole four - throw (SP4T) switches (SW1, SW2) having throw terminals (1, ……, 4) and (1', ……, 4'), respectively. The two switches are connected to each other through paths (101, ……, 104). Each path has a different phase shift, and by selectively switching from one path to another, the phase shift between the input terminal (IN) and the output terminal (OUT) can be changed. Control voltages (V11, V12) and (V21, V22) control the states of the switches (SW1, SW2), respectively, to determine which path will connect the input terminal (IN) to the output terminal (OUT). Generally, a phase shifter path (101, ……, 104) can be implemented using a transmission line or an LC circuit (i.e., an inductor and a capacitor) or any other method to generate a unique desired phase shift on each path. The illustrated phase shifter can be similarly implemented using switches having any number of throws (e.g., SP2T, SP8T, etc.).

[0005] The phase shifter as described above often has a glitch problem when switching from one path to another. Glitches cause undesired and sudden amplitude, frequency, and phase changes at the output of the phase shifter, thereby preventing the user from transmitting data. FIG. 1B shows a diagram (100B) illustrating the glitch problem as described above. Curve (105) represents an example of the variation of the signal amplitude at the output terminal (OUT) in FIG. 1A with time. In this example, a transition from one phase shift to another is triggered at time (T1), and undesired amplitude glitches occur between times (T1) and (T4).

[0006] Figure 1CShows a prior art phase shifter (100C) implementing a first set of switches (110) and a second set of switches (120). The phase shifter (100C) includes paths (P1, P2), each path selectively coupling an input terminal (IN) to an output terminal (OUT). Each shown set of switches includes series switches and shunt switches. For example, the first set of switches (110) includes series switches (S11, S21) and shunt switches (S12, S22). Similarly, the second set of switches (120) includes series switches (S13, S23) and shunt switches (S14, S24). The above shunt switches are implemented for further isolation. Any path (P1, P2) corresponding to a desired phase shift can be selected by controlling the states of the series switches and shunt switches within these sets of switches (110, 120). In Figure 1C the example shown, path (P1) is in an active state and path (P2) is in an inactive state. In other words, the series switches (S11, S13) are turned on (closed), and the series switches (S21, S23) are turned off (open). Additionally, and for further isolation, the shunt switches (S12, S14) are turned off (open), and the shunt switches (S22, S24) are turned on (closed).

[0007] Hereinafter, more details regarding the potential root causes of phase shifter glitches as previously described will be provided. For illustrative purposes, a phase shifter having the same structure as the phase shifter (100C) in Figure 1C will be considered, although the problem is the same in phase shifters implementing switches with any number of throws.

[0008] Figures 2A to 2C Shows a first example of prior art steps for converting a phase shifter (200) from one phase shift to another, e.g., switching from path (P1) to path (P2). In the first step ( Figure 2A ), path (P1) is in an active state and path (P2) is in an inactive state. In other words, switches (S11, S13, S22, S24) are turned on (closed) and switches (S12, S14, S21, S23) are turned off (open). In the second step ( Figure 2B ), the series switches (S11, S13) are turned off, the shunt switches (S12, S14) are turned on, and the shunt switches (S22, S24) are turned off. In the third step ( Figure 2C ), switches (S21, S23) are turned on. In the third step, path (P2) is in an active state and path (P1) is in an inactive state, and the conversion has now occurred. As in Figure 2BAs can be seen, during the second step, both paths (P1, P2) are in an inactive state, and the input terminal (IN) and the output terminal (OUT) are decoupled, resulting in a glitch at the output terminal (OUT) during the third step. In this first example, the cause of the glitch problem is that the series switch in the second path (P2) turns on after the series switch in the path (P1) turns off.

[0009] Figures 2D to 2F A second example of the steps of the prior art for converting a phase shifter (200) from one phase shift to another, for example, switching from path (P1) to path (P2), is shown. During the first step ( Figure 2D ), path (P1) is in an active state and path (P2) is in an inactive state. In other words, switches (S11, S13, S22, S24) are turned on (closed) and switches (S12, S14, S21, S23) are turned off (open). During the second step ( Figure 2E ), the shunt switches (S12, S14) are turned on. During the third step ( Figure 2F ), the series switches (S11, S13) are turned off, the series switches (S21, S23) are turned on, and the shunt switches (S22, S24) are turned off. As Figure 2E shown, during the second step, path (P1) is shorted to ground, resulting in a glitch at the output terminal (OUT) during this step. The cause of this glitch is that, in this example, the shunt switches (S12, S14) turn on faster than the series switches (S11, S13) turn off, resulting in the shorting of path (P1) to ground.

[0010] Figures 2G to 2J A third example of the steps of the prior art for converting a phase shifter (200) from one phase shift to another, for example, switching from path (P1) to path (P2), is shown. During the first step ( Figure 2G ), path (P1) is in an active state and path (P2) is in an inactive state. In other words, switches (S11, S13, S22, S24) are turned on (closed) and switches (S12, S14, S21, S23) are turned off (open). During the second step ( Figure 2H ), the shunt switches (S12, S14) are turned on. During the third step ( Figure 2I ), the series switches (S11, S13) and the shunt switches (S22, S24) are turned off. During the fourth step ( Figure 2J ), the series switches (S21, S23) are turned on. In this step, path (P1) is in an inactive state and path (P2) is in an active state, and the conversion from path (P1) to path (P2) has occurred. As Figure 2HAs shown, during the second step, path (P1) is shorted to ground, and this is the first cause of the glitch appearing at the output terminal (OUT). In addition, during the third step, both paths (P1, P2) are in an inactive state, and thus, the terminals (IN, OUT) are decoupled. This is the second cause of the glitch appearing at the output terminal (OUT). Similarly, as in the second example described above, the reason for the path being shorted to ground in the second step is that the shunt switches (S12, S14) turn on faster than the series switches (S11, S13) turn off. In addition, similar to the first example, the decoupling of the input terminal (IN) and the output terminal (OUT) during the second step is due to the series switch in the second path (P2) turning on slower than the series switch in path (P1) turning off.

[0011] In view of the above, there is a need for methods and devices for overcoming the above-mentioned glitch problems in phase shifters that implement high isolation switches. Summary of the Invention

[0012] The disclosed methods and devices solve the glitch problems as described above.

[0013] According to a first aspect of the present disclosure, there is provided a phase shifter comprising: a first terminal and a second terminal; a first phase shift element and a second phase shift element; a control circuit; wherein the control circuit is configured to: in a first step: couple a first end of the first phase shift element to the first terminal and couple a second end of the first phase shift element to the second terminal; decouple the first end and the second end of the first phase shift element from ground; decouple a first end of the second phase shift element from the first terminal and decouple a second end of the second phase shift element from the second terminal; couple the first end and the second end of the phase shift element to ground; in a second step: decouple the first end and the second end of the second phase shift element from ground; in a third step delayed by a duration of a first delay: couple the first end of the second phase shift element to the first terminal and couple the second end of the second phase shift element to the second terminal; in a fourth step delayed by a duration of a second delay: decouple the first end of the first phase shift element from the first terminal and decouple the second end of the first phase shift element from the second terminal; and in a fifth step delayed by a duration of a third delay: couple the first end and the second end of the first phase shift element to ground.

[0014] According to a second aspect of the present disclosure, an attenuator is provided, which includes: a first terminal and a second terminal; a first attenuation element and a second attenuation element; a control circuit; wherein the control circuit is configured to: in a first step: couple a first end of the first attenuation element to the first terminal and couple a second end of the first phase attenuation to the second terminal; decouple the first end and the second end of the first attenuation element from the ground; decouple a first end of the second attenuation element from the first terminal and decouple a second end of the second attenuation element from the second terminal; couple the first end and the second end of the attenuation element to the ground; in a second step: decouple the first end and the second end of the second attenuation element from the ground; in a third step after a duration of a first delay: couple a first end of the second attenuation element to the first terminal and couple a second end of the second attenuation element to the second terminal; in a fourth step after a duration of a second delay: decouple a first end of the first attenuation element from the first terminal and decouple a second end of the first phase attenuation from the second terminal; and in a fifth step after a duration of a third delay: couple the first end and the second end of the first attenuation element to the ground.

[0015] According to a third aspect of the present disclosure, a method for reducing glitches at an output terminal of a phase shifter when switching from a first phase shift to a second phase shift is disclosed. The phase shifter includes: a first terminal and a second terminal; a first phase shift element and a second phase shift element; a control circuit; the method includes: in a first step: couple a first end of the first phase shift element to the first terminal and couple a second end of the first phase shift element to the second terminal; decouple the first end and the second end of the first phase shift element from the ground; decouple a first end of the second phase shift element from the first terminal and decouple a second end of the second phase shift element from the second terminal; couple the first end and the second end of the phase shift element to the ground; in a second step: decouple the first end and the second end of the second phase shift element from the ground; in a third step after a duration of a first delay: couple a first end of the second phase shift element to the first terminal and couple a second end of the second phase shift element to the second terminal; in a fourth step after a duration of a second delay: decouple a first end of the first phase shift element from the first terminal and decouple a second end of the first phase shift element from the second terminal; and in a fifth step after a duration of a third delay: couple the first end and the second end of the first phase shift element to the ground.

[0016] According to a fourth aspect of the present disclosure, a method of transitioning from one phase shift to another in a phase shifter, the phase shifter comprising: a first terminal and a second terminal; a control circuit; N selectively switchable phase shift elements, each phase shift element: when switched in, couples an input terminal to an output terminal, and when switched out, decouples from the first terminal and the second terminal; the method comprising: in a first step, starting with the i-th phase shift element switched in and the remaining phase shift elements among the phase shift elements switched out, continuously switching out the i-th phase shift element and switching in the (i + 1)-th phase shift element recursively, where the (i + 1)-th phase shift element serves as the phase shift element to be switched in in the next iteration, until the j-th shift element is switched in, and where: i is an integer selected from 1, 2, ……, N - 2, and j is an integer selected from i + 2, ……, N; the combination of switching out the i-th phase shift element and switching in the (i + 1)-th phase shift element comprises: in a second step: decoupling the first end and the second end of the (i + 1)-th phase shift element from ground; in a third step after a duration of a first delay: coupling the first end of the (i + 1)-th phase shift element to the first terminal and coupling the second end of the (i + 1)-th phase shift element to the second terminal; in a fourth step after a duration of a second delay: decoupling the first end of the i-th phase shift element from the first terminal and decoupling the second end of the i-th phase shift element from the second terminal; and in a fifth step after a duration of a third delay: coupling the first end and the second end of the i-th phase shift element to ground.

[0017] Other aspects of the present disclosure are provided in the description, drawings, and claims of this application. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] FIG. 1A shows a prior art phase shifter.

[0019] FIG. 1B shows a prior art figure illustrating a glitch problem.

[0020] Figure 1C A prior art phase shifter is shown.

[0021] Figures 2A to 2C A first example of the steps of a prior art of transitioning a phase shifter from one phase shift to another is shown.

[0022] Figures 2D to 2F A second example of the steps of a prior art of transitioning a phase shifter (200) from one phase shift to another is shown.

[0023] Figures 2G to 2J A first example of the steps of a prior art of transitioning a phase shifter (200) from one phase shift to another is shown.

[0024] Figures 3A to 3EIllustrates exemplary steps of converting a phase shifter from one phase shift to another according to an embodiment of the present disclosure.

[0025] Figures 3F to 3G Represents exemplary performance of a phase shifter conversion from one phase shift to another according to an embodiment of the present disclosure.

[0026] Figure 4 Illustrates a prior art phase shifter having multiple phase shift paths.

[0027] Figures 5A to 5E Illustrates exemplary steps of converting a multi - stage attenuator from one attenuation to another according to an embodiment of the present disclosure.

[0028] Figures 6A to 6C Illustrates exemplary steps of converting a multi - stage attenuator from one attenuation to another according to another embodiment of the present invention.

[0029] Figure 7 Illustrates an exemplary circuit for implementing a phase shifter control method according to an embodiment of the present disclosure.

[0030] Like reference numerals and names in the various figures represent like elements. Detailed Description

[0031] According to the teachings of the present disclosure, various time delays can be implemented at different steps when a phase shifter is converted from one phase shift to another. As will be described by way of exemplary embodiments, the implementation of such time delays will help to overcome the glitch problems described previously.

[0032] Figures 3A to 3E Illustrates exemplary steps of converting a phase shifter (300) from one phase shift to another according to an embodiment of the present disclosure. Such a conversion occurs when the phase shifter (300) switches from path (P1) to path (P2). The phase shifter (300) is the same as Figure 1C the phase shifter (100C) in. During the first step ( Figure 3A ), path (P1) is active and path (P2) is inactive. In the second step ( Figure 3B ), the shunt switches (S22, S24) are turned off. During the third step ( Figure 3C ) performed after the second step, the series switches (S21, S23) are turned on. After the third step, and during the fourth step ( Figure 3D) During this period, the series switches (S11, S13) are turned off. During the fifth step after the fourth step, the shunt switches (S12, S14) are turned on. After this step, the conversion is completed. In other words, the conversion process starts from the non-active path first, where first the shunt switch or multiple shunt switches are turned off, and then the series switch or multiple series switches are turned on. Then, in the initially active path, the series switch is turned off, and then the shunt switch or multiple shunt switches of the initially active path are turned on. By implementing the proper sequence of controlling the states of the respective switches by introducing activation / deactivation delays, problems such as short-circuiting the active path to ground or having both paths in a non-active state simultaneously, as previously described, can be reduced. This will result in a significant reduction in glitches at the output terminals. According to an embodiment of the present disclosure, the switches (S11, S12) can be part of a first single-pole N-throw (SPNT), the switches (S13, S14) can be part of a second SPNT, the switches (S21, S22) can be part of a third SPNT, and the switches (S23, S24) can be part of a fourth SPNT.

[0033] Referring to Figures 3A to 3E , according to an embodiment of the present disclosure, assuming that the second step is executed at time zero, then the third, fourth, and fifth steps are delayed by their respective time delays, ΔT1 < ΔT2 < ΔT3. An exemplary numerical distribution of such a delay sequence ΔT1 / ΔT2 / ΔT3 is 200 ns / 300 ns / 650 ns, or 100 ns / 200 ns / 550 ns. Generally, the delay duration can vary according to the size of the switches and the charge / discharge time constants of the gate terminals of the devices implemented as series switches or shunt switches. In other words, the delay sequence depends on the speed at which the series switches and shunt switches perform the switching.

[0034] Figures 3F to 3G represents the performance of the phase shifter conversion method as disclosed above. Figure 3F shows a curve (305F) representing the variation of the glitch amplitude with time at the output terminal when the phase shifter is switched from one phase shift to another before applying the teachings of the present disclosure. Figure 3G shows the same result of applying the method disclosed above, i.e., curve (305G). It can be seen from such a curve that there is a significant reduction in the glitch amplitude.

[0035] Referring to the previously discussed Figure 3C, it is noted that: both paths (P1, P2) are simultaneously in an active state and are in an active state during the duration of the third step of the phase shifter conversion. The phase shifts of such paths are usually different, or at worst, differ by 180°. This may lead to problems of partial or total cancellation of the signal at the output terminal (OUT). According to the teachings of the present disclosure, in order to overcome such problems, the conversion between one phase shift and another can be achieved in a step-by-step manner instead of directly. To clarify this, reference is made to the phase shifter (400) including switches (SW3, SW4) shown in Figure 4 . The terminals of such a switch are connected to each other through a plurality of paths, and the plurality of paths have unique phase shifts arranged in increasing order Each path from the input terminal (IN) to each terminal of the switches (SW3, SW4) includes a series switch and a shunt switch, and the series switch and the shunt switch are arranged in a manner similar to, for example, Figure 1C or Figures 2A to 2E The arrangement of the series switch (S11) and the shunt switch (S12) therein. The control voltages (V11, V12, V13) control the states of the internal series switch and the shunt switch of the switch (SW3), and the control voltages (V21, V22, V23) control the states of the internal series switch and the shunt switch of the switch (SW4). Further reference is made to Figure 3C , the phase shift The exemplary values of can be 0 degrees / 30 degrees / 60 degrees / 90 degrees / 120 degrees / 150 degrees / 180 degrees. For example, in order to switch from a path with a phase shift (F1), such as 0°, to a path with a phase shift (F7), such as 180°, the conversion can be performed in a sequence with increasing phase shifts according to . In other words, the conversion occurs recursively. In each iteration, the currently active path will be deactivated and the subsequent path with a higher phase shift will be activated. The advantage of such a method is that during any given intermediate conversion, due to the small phase shift increment, the signal cancellation problem is significantly reduced. In this method, due to the higher number of higher phase shift conversions, the overall conversion time may increase. In other embodiments, reference is made to Figures 3A to 3E , the signal cancellation problem at the output can be mitigated by carefully selecting the delays (ΔT1, ΔT2, ΔT3) to minimize the duration during which signal cancellation may occur. Figure 4 The phase shifter (400) implements a switch with eight terminals. Other embodiments implementing a switch with N terminals (where N is any integer greater than 3) and using the same method as described above can also be envisaged.

[0036] The disclosed method can also be applied to implement a multi-stage attenuator for a high isolation switch. Figure 5AShows a prior art multi - stage attenuator (500) that is implemented using an SPDT and includes a first path (P1) with an attenuator (A1) and a second path (P2) with an attenuator (A2). The operating principle of the multi - stage (500) is similar to that described for, for example Figure 1C the phase shifter (100C) in Figures 2A to 2J , except that instead of switching between different phase shifts, a switch occurs between different attenuations. In a similar manner to that described for Figure 5A the multi - stage attenuator (500) in Figures 3A to 3E , when switching from one attenuation to another, the same glitch problem may occur for the same reasons as previously described. Therefore, the switching steps disclosed for the embodiments of Figures 5B to 5E can also be applied to the multi - stage attenuator (500). This is shown successively in

[0037] In some applications, the phase shifters and multi - stage attenuators described may not require the shunt switch to be implemented as part of a high - isolation switch design. As an example, in a multi - stage attenuator that uses a larger attenuation in each path, further isolation provided by the shunt switch may not be required. Figure 6A Shows a prior art multi - stage attenuator (600) that has a similar architecture to the multi - stage (500) in Figure 5A , except that the shunt switch is not implemented as part of the multi - stage attenuator (600).

[0038] Referring to Figure 6A , when switching from path (P1) to path (P2), similar to that described with respect to Figure 2B , when both paths (P1, P2) are in an inactive state, in other words, when the switches (S11, S13, S21, S23) are simultaneously off during the switching period, the same glitch problem at the output terminals may occur during this switching period.

[0039] Figures 6A to 6C Shows exemplary steps for switching a multi - stage attenuator (600) from one attenuation (e.g., path (P1)) to another attenuation (e.g., path (P2)) according to an embodiment of the present disclosure. In a first step ( Figure 6A ), path (P1) is active and path (P2) is inactive. During a second step ( Figure 6B ), the series switches (S21, S23) are turned on. Next is a third step ( Figure 6C) During the third step, the series switches (S11, S13) are turned off. At this time, the conversion has occurred, and path (P2) couples the input terminal (IN) and the output terminal (OUT), while path (P1) is decoupled from these terminals.

[0040] To demonstrate an exemplary implementation of how to control the states of the series switches and the shunt switches when the phase shifter transitions from one phase shift to another, hereinafter, the phase shifter (100C) in Figure 1C is considered. Since Figure 1C the switch groups (110, 120) in

[0041] Figure 7 have similar functions, for clarity, only one of such switch groups and the corresponding implementation and control will be described. Figure 1C shows an exemplary circuit (700) according to an embodiment of the present disclosure. The circuit (700) includes a switch group (760) and a control circuit (750). The switch group (760) is Figure 7 an exemplary implementation of the first group of switches (110) in Figure 1C where the transistors (T11, T12, T21, T22) substantially represent the counterparts of the switches (S11, S12, S21, S22) respectively. Additionally, Figure 7 the paths (P11, P22) in Figure 1C are similar to the paths (P1, P2) in

[0042] Referring to Figure 7 , the delay block (740) is a fixed delay block, which means that regardless of the type of transition (low to high, or high to low) of the input signal applied to the input terminal of such a delay block, such an input signal will be passed to the output terminal of the block after a delay of duration (ΔT1). On the other hand, the delay blocks (741, 742, 743) are state-dependent delay blocks, which means that they only delay their input signals when a specific state transition (low to high, or high to low) occurs in the input signal. In an embodiment, the delay blocks (741, 743) delay their input signals by a delay of duration (ΔT1, ΔT3) respectively, and only delay when such an input signal undergoes a transition from logic low to high. A transition from logic high to low at the input terminal of the delay blocks (741, 743) will be passed to the output terminal of the delay block without any delay. The delay block (742) delays its input signal by a delay of duration (ΔT2), and only delays when a transition from logic high to low occurs in such an input signal.

[0043] In the following, the transition from path (P11) to path (P22) will be considered to demonstrate the functionality of the control circuit (750). Further referring to Figure 7 , a main control signal (730) is applied to node (N) of the control circuit (750). During a first step, wherein the control signal (730) is at a high logic level, the bias voltages at the gate terminals of the through transistor (T11) and the shunt transistor (T22) are positive, and thus the transistors (T11, T22) are turned on. Additionally, the bias voltages present at the gate terminals of the shunt transistor (T12) and the through transistor (T21) are zero or negative, sufficient to turn off the transistors (T12, T21). In other words, during the second step, path (P11) is active, coupling the input terminal (IN) to the output terminal ( Figure 7 (not shown in), and path (P22) is inactive. The transition from path (P11) to path (P22) is triggered by the falling edge of the control signal (730), in other words, the transition is triggered when the control signal (730) transitions from a high logic level to a low logic level. The transition from path (P11) to path (P22) proceeds through a series of four steps (the second step to the fifth step) as described below:

[0044] Second step

[0045] As Figure 7 shown, since the delay block (741) is a low-to-high transition delay block, the transition of the control signal (730) from a high logic level to a low logic level passes through the delay block (741) without any delay. Thus, the bias voltage at the gate terminal of the transistor (T22) becomes low, and thus, the shunt transistor (T22) is turned off. The transistors (T21, T11, T12) do not experience any immediate state change during the first step. The duration of the first step is ΔT1. Those skilled in the art will understand that high generally represents a positive voltage, and low is zero or a negative voltage to turn off the desired transistor.

[0046] Third step

[0047] At time ΔT′1, as indicated by the control signal (732), each output of the delay blocks (740, 742) will experience a transition from a low logic level to a high logic level, and thus, the bias voltage present at the gate terminal of the transistor (T21) becomes positive. Thus, the transistor (T21) will be turned on. The duration of the second step is ΔT′2. During the second step, the control signal (732) passes through the delay block (742) without any additional delay, since such a delay block is a high-to-low transition delay block.

[0048] Fourth step

[0049] At time ΔT′1 + ΔT′2, as indicated by the control signal (734), the bias voltage at the gate terminal of the transistor (T11) will transition from a positive voltage to a negative voltage, and thus the transistor (T11) will turn off. The states of the other transistors are not affected during this step. The duration of the third step is ΔT′3.

[0050] Fifth step

[0051] At time ΔT3, as indicated by the control signal (735), the bias voltage at the gate terminal of the shunt transistor (T12) will transition from a negative voltage to a positive voltage to turn on the transistor (T12). At this stage, the transition from path (P11) to path (P22) has occurred. In a preferred embodiment, ΔT′1 + ΔT′2 < ΔT′3.

[0052] As used in this disclosure, the term "MOSFET" includes any field - effect transistor (FET) having an insulated gate whose gate voltage determines the conductivity of the transistor, and includes insulated gates having metal or metal - like, insulator, and / or semiconductor structures. The term "metal" or "metal - like" includes at least one conductive material (such as aluminum, copper, or other metals, or highly doped polysilicon, graphene, or other electrical conductors), "insulator" includes at least one insulating material (such as silicon oxide or other dielectric materials), and "semiconductor" includes at least one semiconductor material.

[0053] As used in this disclosure, the term "radio frequency" (RF) refers to an oscillation frequency in the range of approximately 3 kHz to approximately 300 GHz. The term also includes the frequencies used in wireless communication systems. The RF frequency can be the frequency of an electromagnetic wave, or the frequency of an alternating voltage or current in a circuit.

[0054] Regarding the drawings cited in this disclosure, the dimensions of the various elements are not drawn to scale; for clarity or emphasis, some dimensions are significantly enlarged in the vertical and / or horizontal directions. Additionally, references to orientation and direction (e.g., "top", "bottom", "above", "below", "lateral", "vertical", "horizontal", etc.) are relative to the exemplary drawings and are not necessarily absolute orientation or direction.

[0055] The various embodiments of the present invention can be implemented to meet various specifications. Unless otherwise stated above, the selection of appropriate component values is a matter of design choice. The various embodiments of the present invention can be implemented in any suitable integrated circuit (IC) technology (including but not limited to MOSFET structures) or in the form of hybrid or discrete circuits. The integrated circuit embodiments can be fabricated using any suitable substrate and process, including but not limited to standard bulk silicon, high resistivity bulk CMOS, silicon-on-insulator (SOI), and silicon-on-sapphire (SOS). Unless otherwise stated above, the embodiments of the present invention can be implemented in other transistor technologies, such as bipolar, BiCMOS, LDMOS, BCD, GaAs HBT, GaN HEMT, GaAs pHEMT, and MESFET technologies. However, the embodiments of the present invention are particularly useful when fabricated using a SOI- or SOS-based process or when using a process with similar characteristics. Fabrication in CMOS using a SOI or SOS process enables the circuit to have low power consumption, the ability to withstand high power signals during operation due to FET stacking, good linearity, and high-frequency operation (i.e., radio frequencies up to and exceeding 300 GHz). Monolithic IC implementations are particularly useful because, through precise design, parasitic capacitances can typically be kept at low levels (or at least consistent across all cells for compensation).

[0056] Depending on the specific specifications and / or implementation technology (e.g., NMOS, PMOS, or CMOS, and enhancement-mode or depletion-mode transistor devices), the voltage levels can be adjusted and / or the polarities of voltage signals and / or logic signals can be inverted. The component voltage, current, and power handling capabilities can be adjusted as needed, for example, by adjusting the device size, "stacking" components (especially FETs) in series to withstand greater voltages, and / or using multiple components in parallel to handle greater currents. Additional circuit components can be added to enhance the performance of the disclosed circuit and / or provide additional functionality without significantly changing the function of the disclosed circuit.

[0057] The circuits and devices according to the present invention can be used alone or in combination with other components, circuits, and devices. Embodiments of the present invention can be fabricated as integrated circuits (ICs), which can be encapsulated in IC packages and / or modules to facilitate handling, fabrication, and / or improved performance. In particular, IC embodiments of the present invention are typically used in modules, where one or more of such ICs are combined with other circuit blocks (e.g., filters, amplifiers, passive components, and possibly additional ICs) into one package. The IC and / or module are then typically combined with other components, usually on a printed circuit board, to form part of a terminal product (e.g., a cellular phone, a laptop computer, or an electronic tablet), or to form a higher-level module that can be used in various products (e.g., vehicles, test equipment, medical equipment, etc.). Through various configurations of the modules and components, such ICs typically implement communication modes, usually wireless communication.

[0058] Multiple embodiments of the present invention have been described. It should be understood that various modifications can be made without departing from the spirit and scope of the present invention. For example, some of the steps described above can be order-independent and can thus be performed in a different order than the order described. In addition, some of the steps described above can be optional. The various activities described with respect to the methods identified above can be performed in a repetitive, serial, and / or parallel manner.

[0059] It should be understood that the foregoing description is intended to illustrate and not limit the scope of the present invention, which is defined by the scope of the claims, and other embodiments are within the scope of the claims. In particular, the scope of the present invention includes any and all feasible combinations of one or more of the processes, machines, manufactures, or compositions of matter set forth in the claims. (Note that the bracketed designations of claim elements are for ease of reference to such elements and do not themselves indicate a particular required order or enumeration of the elements; furthermore, such designations can be reused in dependent claims as a reference to additional elements without being regarded as starting a conflicting sequence of designations).

Claims

1. A phase shifter, comprising: A first terminal and a second terminal; A first phase shift element and a second phase shift element; A control circuit; Wherein, the control circuit is configured to: In a first step: Couple a first end of the first phase shift element to the first terminal and couple a second end of the first phase shift element to the second terminal; Decouple the first end and the second end of the first phase shift element from ground; Decouple a first end of the second phase shift element from the first terminal and decouple a second end of the second phase shift element from the second terminal; Couple the first end and the second end of the phase shift element to ground; In a second step: Decouple the first end and the second end of the second phase shift element from ground; In a third step delayed by a duration of a first delay: Couple a first end of the second phase shift element to the first terminal and couple a second end of the second phase shift element to the second terminal; In a fourth step delayed by a duration of a second delay: Decouple a first end of the first phase shift element from the first terminal and decouple a second end of the first phase shift element from the second terminal, and In a fifth step delayed by a duration of a third delay: Couple the first end and the second end of the first phase shift element to ground.

2. The phase shifter according to claim 1, wherein, The first delay is less than the second delay, and the second delay is less than the third delay.

3. The phase shifter according to claim 1, wherein, The first phase shift element and the second phase shift element include a transmission line or a reactance element, and the reactance element includes a capacitor and an inductor.

4. The phase shifter according to claim 1, wherein: A first end of the first phase shift element is coupled to the first terminal through a first series switch; A second end of the first shift element is coupled to the second terminal through a second series switch; A first end of the second phase shift element is coupled to the first terminal through a third series switch, and A second end of the second phase shift element is coupled to the second terminal through a fourth series switch.

5. The phase shifter according to claim 4, wherein: A first end of the first phase shift element is coupled to ground through a first shunt switch; A second end of the first phase shift element is coupled to ground through a second shunt switch; A first end of the second phase shift element is coupled to ground through a third shunt switch, and A second of the second phase shift element is coupled to ground through a fourth shunt switch.

6. The phase shifter according to claim 5, wherein: The first series switch and the first shunt switch are part of a first single-pole N-throw (SPNT); The second series switch and the second shunt switch are part of a second SPNT; The third series switch and the third shunt switch are part of a third SPNT; The fourth series switch and the fourth shunt switch are part of a fourth SPNT, and N is an integer greater than or equal to two.

7. An attenuator, comprising: A first terminal and a second terminal; A first attenuation element and a second attenuation element; A control circuit; Wherein, the control circuit is configured to: In a first step: Couple a first end of the first attenuation element to the first terminal and couple a second end of the first phase attenuation to the second terminal; Decouple a first end and a second end of the first attenuation element from ground; Decouple a first end of the second attenuation element from the first terminal and decouple a second end of the second attenuation element from the second terminal; Couple a first end and a second end of the attenuation element to ground; In a second step: Decouple a first end and a second end of the second attenuation element from ground; In a third step delayed by a duration of a first delay: Couple a first end of the second attenuation element to the first terminal and couple a second end of the second attenuation element to the second terminal; In a fourth step delayed by a duration of a second delay: Decouple a first end of the first attenuation element from the first terminal and decouple a second end of the first phase attenuation element from the second terminal, and In a fifth step delayed by a duration of a third delay: Couple a first end and a second end of the first attenuation element to ground.

8. The attenuator according to claim 7, wherein, The first delay is less than the second delay, and the second delay is less than the third delay.

9. The attenuator according to claim 7, wherein: The first end of the first attenuation element is coupled to the first terminal through a first series switch; The second end of the first attenuation element is coupled to the second terminal through a second series switch; The first end of the second attenuation element is coupled to the first terminal through a third series switch, and The second end of the second attenuation element is coupled to the second terminal through a fourth switch.

10. The attenuator according to claim 9, wherein: The first end of the first attenuation element is coupled to ground through a first shunt switch; The second end of the first attenuation element is coupled to ground through a second shunt switch; The first end of the second attenuation element is coupled to ground through a third shunt switch, and The second of the second attenuation element is coupled to ground through a fourth shunt switch.

11. The attenuator according to claim 10, wherein: The first series switch and the first shunt switch are part of a first single-pole N-throw (SPNT); and The second series switch and the second shunt switch are part of a second SPNT; The third series switch and the third shunt switch are part of a third SPNT; The fourth series switch and the fourth shunt switch are part of a fourth SPNT, and N is an integer greater than or equal to 2.

12. The phase shifter according to claim 5, wherein, The series switch and the shunt switch include field effect transistor (FET) switches.

13. The phase shifter according to claim 1, wherein, The first delay, the second delay, and the third delay are implemented using a combination of a fixed delay block and a state-dependent delay block.

14. The phase shifter according to claim 1, wherein, The first delay, the second delay, and the third delay are 200 ns, 300 ns, and 700 ns, respectively.

15. A method for reducing glitches at an output terminal of a phase shifter when transitioning from a first phase shift to a second phase shift, the phase shifter comprising: A first terminal and a second terminal; A first phase shift element and a second phase shift element; A control circuit; The method includes: In a first step: Couple a first end of the first phase-shifting element to the first terminal and couple a second end of the first phase-shifting element to the second terminal; Decouple the first end and the second end of the first phase-shifting element from ground; Decouple a first end of the second phase-shifting element from the first terminal and decouple a second end of the second phase-shifting element from the second terminal; Couple the first end and the second end of the phase-shifting element to ground; In a second step: Decouple the first end and the second end of the second phase-shifting element from ground; In a third step delayed by a duration of a first delay: Couple the first end of the second phase-shifting element to the first terminal and couple the second end of the second phase-shifting element to the second terminal; In a fourth step delayed by a duration of a second delay: Decouple the first end of the first phase-shifting element from the first terminal and decouple the second end of the first phase-shifting element from the second terminal, and In a fifth step delayed by a duration of a third delay: Couple the first end and the second end of the first phase-shifting element to ground.

16. The method according to claim 15, wherein, The first delay is less than the second delay, and the second delay is less than the third delay.

17. A method for switching from one phase shift to another in a phase shifter, the phase shifter comprising: A first terminal and a second terminal; A control circuit; N selectively switchable phase-shifting elements, each phase-shifting element: When switched in, couple an input terminal to an output terminal, and When switched out, decouple from the first terminal and the second terminal; The method includes: In a first step, starting from when the i-th phase-shifting element is switched in and the remaining phase-shifting elements among the phase-shifting elements are switched out, continuously switch out the i-th phase-shifting element and switch in the (i + 1)-th phase-shifting element in a recursive manner, where the (i + 1)-th phase-shifting element serves as the phase-shifting element to be switched in in the next iteration until the j-th phase-shifting element is switched in, and Where: i is an integer selected from 1, 2,..., N - 2, and j is an integer selected from i + 2,..., N; The combination of switching out the i-th phase-shifting element and switching in the (i + 1)-th phase-shifting element includes: In a second step: Decouple the first end and the second end of the (i + 1)-th phase-shifting element from ground; In a third step delayed by a duration of a first delay: Couple the first end of the (i + 1)-th phase-shifting element to the first terminal and couple the second end of the (i + 1)-th phase-shifting element to the second terminal; In a fourth step delayed by a duration of a second delay: Decouple the first end of the i-th phase-shifting element from the first terminal and decouple the second end of the i-th phase-shifting element from the second terminal, and In a fifth step delayed by a duration of a third delay: Couple the first end and the second end of the i-th phase-shifting element to ground.

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