Display panel, preparation method thereof and display device

Abstract

The invention provides a display panel, a preparation method thereof and a display device, and belongs to the technical field of display. The display panel includes a substrate, and a plurality of repeating units on the substrate. The repeating unit can be divided into a display area and a light-transmitting area and comprises a sub-pixel located in the display area, the sub-pixel comprises a pixel circuit and a light-emitting element which are coupled with each other, and the pixel circuit is used for driving the light-emitting element to emit light. The pixel circuit includes a storage capacitor. The storage capacitor comprises a first pole plate and a second pole plate which are overlapped with each other, and the first pole plate can be connected with the first electrode of the light-emitting element through the switching electrode. And the first polar plate and the first electrode are made of transparent conductive materials and are overlapped with the opening of the display area. Therefore, on the premise that all the parts are reliably coupled and the light-emitting elements are reliably driven to emit light, double-sided light emitting is achieved through the transparent capacitor design, and the display effect is good.

Description

Display panel and manufacturing method thereof, and display device Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular to a display panel and a manufacturing method thereof, and a display device. Background Art

[0002] Organic Light Emitting Diode (OLED) is an active light-emitting element. OLED display panels, including OLEDs, have advantages such as self-luminescence, low energy consumption, wide viewing angle, high contrast, and high brightness. Based on these advantages, OLED display panels are widely used in the field of display technology.

[0003] In related art, an OLED display panel generally includes a substrate and a plurality of pixels located on the substrate. The pixels include a pixel circuit and an OLED light-emitting element. The pixel circuit is connected to the OLED light-emitting element to drive the OLED light-emitting element to emit light.

[0004] However, current OLED display panels can only emit light from one side, resulting in poor display effects.

[0005] Summary of the Invention

[0006] The present disclosure provides a display panel, a method for manufacturing the same, and a display device. The technical solution is as follows:

[0007] In one aspect, a display panel is provided, comprising: a display substrate and a cover plate disposed opposite to each other; the display substrate comprising:

[0008] substrate;

[0009] a plurality of repeating units located on the substrate, the repeating units being divided into a display area and a light-transmitting area located on at least one side of the display area, and comprising a plurality of sub-pixels located in the display area, the sub-pixels comprising a coupled pixel circuit and a light-emitting element, the pixel circuit being configured to drive the light-emitting element to emit light;

[0010] The pixel circuit includes a storage capacitor, the storage capacitor includes a first plate and a second plate whose orthographic projections overlap on the substrate; the light-emitting element includes a first electrode; the first electrode is connected to the first plate via a switching electrode;

[0011] Furthermore, the first electrode, the switching electrode, the first electrode and the second electrode are located in different layers; the material of the first electrode and the material of the first electrode both include transparent conductive materials; the display area has at least one opening, and the orthographic projection of the first electrode on the substrate and the orthographic projection of the first electrode on the substrate both overlap with the orthographic projection of the opening on the substrate.

[0012] Optionally, the display area has a first opening and a second opening spaced apart from each other;

[0013] The first electrode includes: a first sub-electrode and a second sub-electrode located in the same layer and spaced apart from each other, the first sub-electrode being connected to the first electrode plate via the transition electrode;

[0014] In which, the orthographic projection of the first sub-electrode on the substrate overlaps with the orthographic projection of the first opening on the substrate, the orthographic projection of the first electrode on the substrate and the orthographic projection of the second sub-electrode on the substrate both overlap with the orthographic projection of the second opening on the substrate, and the orthographic projection of the switching electrode on the substrate is located within the orthographic projection of the interval between the first opening and the second opening on the substrate.

[0015] Optionally, the orthographic projection of the first sub-electrode on the substrate does not overlap with the orthographic projections of the first electrode plate and the second electrode plate on the substrate; the orthographic projection of the second sub-electrode on the substrate overlaps with the orthographic projections of the first electrode plate and the second electrode plate on the substrate.

[0016] Optionally, the display substrate further comprises: a pixel defining layer located on a side of the first electrode away from the substrate;

[0017] The pixel defining layer is used to define the first opening and the second opening.

[0018] Optionally, the display panel further comprises: a black matrix layer located on a side of the cover plate close to the display substrate;

[0019] The orthographic projection of the black matrix layer on the substrate is located within the orthographic projection of the pixel defining layer on the substrate.

[0020] Optionally, the opening includes: a top-emitting opening and a bottom-emitting opening that are arranged opposite to each other, the top-emitting opening is located on one side of the cover plate, and the bottom-emitting opening is located on one side of the display substrate;

[0021] The display substrate further comprises: a reflective electrode located on a side of the first electrode away from the substrate;

[0022] The orthographic projection of the reflective electrode on the substrate overlaps with the orthographic projection of the bottom-emitting opening on the substrate, and does not overlap with the orthographic projection of the top-emitting opening on the substrate.

[0023] Optionally, the reflective electrode is located between the first electrode and a pixel defining layer included in the display substrate.

[0024] Optionally, the display substrate further comprises: a first transparent conductive layer, an active layer, a gate metal layer, and a second transparent conductive layer stacked in sequence in a direction away from the substrate;

[0025] The first electrode and the first transparent conductive layer are located in the same layer; the switching electrode and the gate metal layer are located in the same layer; the first electrode and the second transparent conductive layer are located in the same layer; and the second electrode and the active layer are located in the same layer.

[0026] Optionally, the display substrate further comprises: a light-emitting layer and a second electrode located between the first electrode and the cover plate and stacked in sequence in a direction away from the substrate, wherein the material of the second electrode comprises a transparent conductive material;

[0027] The display substrate includes a pixel defining layer located between the light emitting layer and the first electrode.

[0028] Optionally, the material of the first transparent conductive layer and the material of the second transparent conductive layer both include: indium tin oxide; the material of the second electrode includes: indium zinc oxide; the material of the active layer includes: indium gallium zinc oxide;

[0029] Optionally, the display substrate further comprises: a buffer layer and a gate insulating layer located between the first transparent conductive layer and the gate metal layer and stacked in sequence in a direction away from the substrate;

[0030] and, a passivation layer and a planarization layer located between the gate metal layer and the second transparent conductive layer and stacked in sequence in a direction away from the substrate;

[0031] The first electrode is connected to the switching electrode through a first via hole penetrating the passivation layer and the planar layer; the switching electrode is connected to the first electrode plate through a second via hole penetrating the gate insulating layer and the buffer layer.

[0032] Optionally, an orthographic projection of the first via hole on the substrate does not overlap with an orthographic projection of the second via hole on the substrate;

[0033] An area of ​​an orthographic projection of the first via hole on the substrate is larger than an area of ​​an orthographic projection of the second via hole on the substrate.

[0034] Optionally, the orthographic projection of the first via hole on the substrate and the orthographic projection of the second via hole on the substrate are both located within the orthographic projection of the interval between the first opening and the second opening of the display area on the substrate.

[0035] Optionally, the display substrate further comprises: a metal light shielding layer located between the substrate and the buffer layer;

[0036] The pixel circuit is further connected to a plurality of signal lines, and is configured to drive the light-emitting element to emit light in response to signals provided by the plurality of signal lines;

[0037] Among them, the multiple signal lines include: a first power line, a second power line, a scan line, a data line and a sensing line; and the scan line extends along the first direction and is located in the same layer as the gate metal layer; the first power line, the second power line, the data line and the sensing line all extend along the second direction and are all located in the same layer as the metal shading layer; the first direction intersects with the second direction.

[0038] Optionally, the gate metal layer is further connected to the metal light-shielding layer, the first transparent conductive layer and the active layer respectively through via holes penetrating the gate insulating layer.

[0039] Optionally, the display panel further includes: a first color filter layer located on a side of the cover plate close to the display substrate;

[0040] The display substrate further includes: a second color filter layer located on a side of the first electrode close to the substrate;

[0041] The orthographic projection of the first color filter layer on the substrate and the orthographic projection of the second color filter layer on the substrate both overlap with the orthographic projection of the opening on the substrate.

[0042] Optionally, the second color filter layer is located between a passivation layer and a planarization layer included in the display substrate.

[0043] In another aspect, a method for manufacturing a display panel is provided, for manufacturing the display panel according to the above aspect; the method comprising:

[0044] providing a substrate;

[0045] forming a plurality of repeating units on one side of the substrate to obtain a display substrate;

[0046] providing a cover plate on an opposite side of the display substrate;

[0047] The formed repeating unit is divided into a display area and a light-transmitting area located on at least one side of the display area, and includes a plurality of sub-pixels located in the display area, wherein the sub-pixels include a coupled pixel circuit and a light-emitting element, and the pixel circuit is used to drive the light-emitting element to emit light;

[0048] Furthermore, the first electrode, the switching electrode, the first electrode and the second electrode are located in different layers; the material of the first electrode and the material of the first electrode both include transparent conductive materials; the display area has at least one opening, and the orthographic projection of the first electrode on the substrate and the orthographic projection of the first electrode on the substrate both overlap with the orthographic projection of the opening on the substrate.

[0049] Optionally, the opening includes: a top-emitting opening and a bottom-emitting opening that are oppositely arranged, the top-emitting opening is located on one side of the cover plate, and the bottom-emitting opening is located on one side of the display substrate; the method further includes:

[0050] forming a reflective electrode on a side of the first electrode away from the substrate;

[0051] The orthographic projection of the formed reflective electrode on the substrate overlaps with the orthographic projection of the bottom-emitting opening on the substrate, and does not overlap with the orthographic projection of the top-emitting opening on the substrate.

[0052] In another aspect, a display device is provided, comprising: a power supply component, and the display panel according to the above aspect;

[0053] The power supply component is connected to the display panel and is used to supply power to the display panel. BRIEF DESCRIPTION OF THE DRAWINGS

[0054] In order to more clearly illustrate the technical solutions in the embodiments of the present disclosure, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0055] FIG1 is a schematic cross-sectional view of a display panel provided by an embodiment of the present disclosure;

[0056] FIG2 is a schematic structural diagram of a display substrate provided by an embodiment of the present disclosure;

[0057] FIG3 is a schematic structural diagram of a repeating unit in a display substrate provided by an embodiment of the present disclosure;

[0058] FIG4 is a schematic diagram of a sub-pixel structure included in a repeating unit in a display substrate provided by an embodiment of the present disclosure;

[0059] FIG5 is a structural diagram of a display substrate provided by an embodiment of the present disclosure;

[0060] FIG6 is a partial structural diagram of a display substrate provided in an embodiment of the present disclosure;

[0061] FIG7 is a cross-sectional schematic diagram of a display substrate provided based on FIG6 ;

[0062] FIG8 is a structural diagram of an opening provided by an embodiment of the present disclosure;

[0063] FIG9 is a structural layout diagram of an opening and a reflective electrode provided in an embodiment of the present disclosure;

[0064] FIG10 is a schematic cross-sectional view of another display substrate provided by an embodiment of the present disclosure;

[0065] FIG11 is a structural diagram of a first transparent conductive layer in a display substrate provided by an embodiment of the present disclosure;

[0066] FIG12 is a structural diagram of a light shielding layer in a display substrate provided by an embodiment of the present disclosure;

[0067] FIG13 is a structural diagram of a first transparent conductive layer and a light shielding layer in a display substrate provided by an embodiment of the present disclosure;

[0068] FIG14 is a structural diagram of an active layer in a display substrate provided by an embodiment of the present disclosure;

[0069] FIG15 is a structural diagram of a first transparent conductive layer, a light shielding layer, and an active layer in a display substrate provided by an embodiment of the present disclosure;

[0070] FIG16 is a structural diagram of a gate insulating layer in a display substrate provided by an embodiment of the present disclosure;

[0071] FIG17 is a structural layout diagram of a first transparent conductive layer, a light shielding layer, an active layer, and a gate insulating layer in a display substrate provided by an embodiment of the present disclosure;

[0072] FIG18 is a structural layout diagram of a gate metal layer in a display substrate provided by an embodiment of the present disclosure;

[0073] FIG19 is a structural layout diagram of a first transparent conductive layer, a light shielding layer, an active layer, a gate insulating layer, and a gate metal layer in a display substrate provided by an embodiment of the present disclosure;

[0074] FIG20 is a structural diagram of a passivation layer in a display substrate provided by an embodiment of the present disclosure;

[0075] FIG21 is a structural diagram of a planar layer in a display substrate provided by an embodiment of the present disclosure;

[0076] FIG22 is a structural layout diagram of a first transparent conductive layer, a light shielding layer, an active layer, a gate insulating layer, a gate metal layer, a passivation layer, and a planarization layer in a display substrate provided by an embodiment of the present disclosure;

[0077] FIG23 is a structural diagram of a second transparent conductive layer in a display substrate provided by an embodiment of the present disclosure;

[0078] FIG24 is a structural layout diagram of a first transparent conductive layer, a light shielding layer, an active layer, a gate insulating layer, a gate metal layer passivation layer, a planarization layer, and a second transparent conductive layer in a display substrate provided by an embodiment of the present disclosure;

[0079] FIG25 is a structural diagram of a pixel definition layer in a display substrate provided by an embodiment of the present disclosure;

[0080] FIG26 is a structural layout diagram of a first transparent conductive layer, a light shielding layer, an active layer, a gate insulating layer, a gate metal layer passivation layer, a planarization layer, a second transparent conductive layer, and a pixel defining layer in a display substrate provided by an embodiment of the present disclosure;

[0081] FIG27 is a flow chart of a method for manufacturing a display panel according to an embodiment of the present disclosure;

[0082] FIG28 is an equivalent diagram showing a manufacturing process of a display substrate based on FIG7 ;

[0083] FIG29 is an equivalent diagram showing a manufacturing process of a display substrate based on FIG10;

[0084] FIG30 is a schematic structural diagram of a display device provided in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0085] In order to make the objectives, technical solutions and advantages of the present disclosure more clear, the embodiments of the present disclosure will be further described in detail below with reference to the accompanying drawings.

[0086] Fig. 1 is a schematic structural diagram of a display panel provided by an embodiment of the present disclosure. As shown in Fig. 1 , the display panel comprises: a display substrate 0 and a cover plate 1 arranged opposite to each other.

[0087] Based on Figure 1 , Figure 2 shows a schematic structural diagram of a display substrate. Referring to Figure 2 , it can be seen that the display substrate 0 includes: a substrate 01 , and a plurality of repeating units 02 located on the substrate 01 .

[0088] Among the multiple repeating units 02, at least one repeating unit 02 can be divided into a display area A1 and a light-transmitting area A2 located on at least one side of the display area A1. Furthermore, at least one repeating unit 02 includes multiple sub-pixels (not shown in FIG. 2 ) located in the display area A1. At least one sub-pixel can include a pixel circuit and a light-emitting element coupled to each other. The pixel circuit is configured to drive the light-emitting element to emit light, causing the pixel to illuminate and emit light.

[0089] As can be seen from this, the display area A1 in the repeating unit 02 can be used to display an image when multiple pixels therein are illuminated. The light-transmitting area A2 can be used to transmit light, allowing the repeating unit 02 to display images in a transparent state, i.e., transparent display. Optionally, the repeating unit 02 is the basic unit that constitutes the display substrate. By repeating and continuously arranging it in at least one direction, the display substrate 0 is formed. In other words, the display substrate 0 can be composed of multiple repeating units 02.

[0090] For example, FIG3 shows a schematic structural diagram of a repeating unit 02 based on FIG2 . As shown in FIG3 , the repeating unit 02 is divided into a display area A1 and a light-transmitting area A2 located to one side (e.g., the left side) of the display area A1. The display area A1 and the light-transmitting area A2 are adjacent to each other, i.e., they are adjacent to and in contact with each other. The repeating unit 02 includes four sub-pixels P1 located in the display area A1.

[0091] Optionally, continuing to refer to Figure 3, the four sub-pixels P1 can be: a white (white, W) sub-pixel P1_W for emitting white light, a blue (blue, B) sub-pixel P1_B for emitting blue light, a red (Red, R) sub-pixel P1_R for emitting red light, and a green (Green, G) sub-pixel P1_G for emitting green light.

[0092] Alternatively, with continued reference to FIG3 , the white sub-pixel P1_W and the green sub-pixel P1_G may be arranged adjacently along a first direction X, the red sub-pixel P1_R and the blue sub-pixel P1_B may be arranged adjacently along the first direction X, the white sub-pixel P1_W and the red sub-pixel P1_R may be arranged adjacently along a second direction Y, and the green sub-pixel P1_G and the blue sub-pixel P1_B may be arranged adjacently along the second direction Y. That is, the four sub-pixels may be arranged in a square, thereby effectively increasing the aperture ratio and the area of ​​the light-transmitting region, ensuring a better display effect.

[0093] The first direction X and the second direction Y may intersect, such as being perpendicular to each other. In the case of multiple rows and columns of pixels (i.e., multiple pixel rows and multiple pixel columns), the first direction X may refer to a row direction, and the second direction Y may refer to a column direction.

[0094] It should be noted that the above are merely illustrative examples of the region division method, the number of sub-pixels, the sub-pixel arrangement method, and the sub-pixel colors, and are not limited in the presently disclosed embodiments.

[0095] As described in the above embodiment, the sub-pixel may include a pixel circuit and a light-emitting element coupled to each other, and the pixel circuit may be used to drive the light-emitting element to emit light. On this basis, in combination with Figure 3, Figure 4 schematically shows a circuit structure diagram of a pixel. Referring to Figure 4, it can be seen that the pixel circuit 10 included in the sub-pixel can be a 3T1C structure, that is, a structure including a first transistor T1, a second transistor T2, and a third transistor T3, a total of 3 transistors, and a storage capacitor Cst. Of course, this structure is only a schematic example. For example, in some other embodiments, structures such as 7T1C or 6T2C can also be used.

[0096] Among them, the gate of the first transistor T1 can be coupled to the scan line G1, the first electrode of the first transistor T1 can be coupled to the data line Data, and the second electrode of the first transistor T1 can be coupled to the gate of the second transistor T2. When the turn-on signal (i.e., the scan signal with an effective potential) is applied to the scan line G1, the first transistor T1 can be turned on, so that the data signal provided by the data line Data is transmitted to the gate of the second transistor T2. When the turn-off signal (i.e., the scan signal with an invalid potential) is applied to the scan line G1, the first transistor T1 can be turned off. Accordingly, the first transistor T1 can also be called a data writing transistor.

[0097] The first electrode of the second transistor T2 can be coupled to the first power line VDD, and the second electrode of the second transistor T2 can be coupled to the first electrode of the light-emitting element 20. The second transistor T2 can transmit a light-emitting drive signal to the first electrode of the light-emitting element 20 based on the data signal received by its gate and the first power signal provided by the first power line VDD. For example, when the light-emitting element 20 is an OLED, the light-emitting drive signal here can be a drive current. The second electrode of the light-emitting element 20 can be coupled to the second power line VSS. The light-emitting element 20 can emit light under the action of the voltage difference between the light-emitting drive signal and the second power signal provided by the second power line VSS. Accordingly, the second transistor T2 can also be called a driving transistor.

[0098] The gate of the third transistor T3 can be coupled to the scan line G1, the first electrode of the third transistor T3 can be coupled to the second electrode of the second transistor T2 (i.e., the first electrode of the light-emitting element 20), and the second electrode of the third transistor T3 can be coupled to the sensing line Sense. When the turn-on signal (i.e., the scan signal of the effective potential) is applied to the scan line G1, the third transistor T3 can be turned on and the threshold voltage Vth and mobility of the second transistor T2 are extracted in response to the compensation timing to perform external compensation thereon. When the turn-off signal (i.e., the scan signal of the invalid potential) is applied to the scan line G1, the third transistor T3 can be turned off. Accordingly, the third transistor T3 can be referred to as a compensation transistor.

[0099] A first terminal of the storage capacitor Cst may be coupled to the second electrode of the second transistor T2, and a second terminal of the storage capacitor Cst may be coupled to the gate of the second transistor T2. The storage capacitor Cst may be used to store the potential of the gate of the second transistor T2.

[0100] It should be noted that, for the purpose of distinction, in FIG4 , the pixel circuit included in the white sub-pixel P1_W is identified as 10_W, and the light-emitting element 20 is identified as 20_W; the pixel circuit included in the green sub-pixel P1_G is identified as 10_G, and the light-emitting element 20 is identified as 20_G; the pixel circuit included in the red sub-pixel P1_R is identified as 10_R, and the light-emitting element 20 is identified as 20_R; and the pixel circuit included in the blue sub-pixel P1_B is identified as 10_B, and the light-emitting element 20 is identified as 20_B.

[0101] Optionally, the transistors in the pixel circuit 10 recorded in the embodiment of the present disclosure may all be N-type transistors, and accordingly, the effective potential recorded in the above embodiment may be a high potential relative to the invalid potential. Of course, in some other embodiments, the transistors in the pixel circuit 10 may all be P-type transistors, and accordingly, the effective potential may be a low potential relative to the invalid potential. Alternatively, the pixel circuit 10 may include both N-type transistors and P-type transistors. Of course, using the same type of transistors in the pixel circuit 10 can simplify the process flow, reduce the process difficulty, and improve the yield of the product. Of the first and second poles of the transistor, one pole may be a source and the other pole may be a drain. For example, in the embodiment of the present disclosure, the first pole is a source and the second pole is a drain for schematic illustration.

[0102] Optionally, in the embodiment of the present disclosure, the N-type transistor may be an oxide thin film transistor using an oxide material. The P-type transistor may be a low-temperature polysilicon thin film transistor using a low-temperature polysilicon (LTPS) material. The transistor materials here all refer to the materials of the active layer included in the transistor. Low-temperature polysilicon thin film transistors have the advantages of high mobility and fast charging, and oxide thin film transistors have the advantages of low leakage current. Therefore, on the basis of setting the pixel circuit 10 to include both P-type transistors and N-type transistors, low-temperature polysilicon thin film transistors and oxide thin film transistors can be integrated on a display substrate, that is, the display substrate belongs to a LTPS+Oxide (LTPO for short) display substrate. Furthermore, the advantages of both can be utilized to achieve low-frequency driving, reduce power consumption, and thus improve display quality.

[0103] Optionally, in the embodiment of the present disclosure, the potential of the first power signal provided by the first power line VDD may be a continuous high potential, and the potential of the second power signal provided by the second power line VSS may be a continuous low potential. Here, high potential and low potential are also relative.

[0104] Optionally, as described in the above embodiment, the light-emitting element 20 may be an OLED, and accordingly, its first pole may be an anode and the second pole may be a cathode. Alternatively, in some other embodiments, the first pole may be a cathode and the second pole may be an anode. A light-emitting layer may also be included between the first pole and the second pole. The light-emitting layer may emit light under the action of the voltage difference between the first pole and the second pole. Of course, in some other embodiments, the light-emitting element 20 may also be of other types, such as quantum dot light emitting diodes (QLEDs). The disclosed embodiments do not limit this.

[0105] Based on Figure 4, Figure 5 shows a structural layout of a display substrate. The structure shown in Figure 1 can be a cross-sectional view of the structural layout shown in Figure 5 along the AA' direction.

[0106] 1 , it can be seen that the pixel circuit 10 may include a storage capacitor Cst, and the storage capacitor Cst may include a first plate Cst1 and a second plate Cst2 , the orthographic projections of which overlap on the substrate 01 .

[0107] Among them, the first electrode Cst1 can refer to the first end coupled between the storage capacitor Cst and the second electrode of the second transistor T2 (that is, the first electrode of the light-emitting element 20, such as the anode), and the first electrode Cst1 and the anode of the light-emitting element 20 have the same signal; the second electrode Cst2 can refer to the second end coupled between the storage capacitor Cst and the gate of the second transistor T2, and the second electrode Cst2 and the gate of the second transistor T2 have the same signal.

[0108] The light-emitting element 20 may include a first electrode 201 (i.e., a first electrode, also called an anode). The first electrode 201 may be connected to the first electrode plate Cst1 via a connecting electrode 202. This ensures that the first end of the storage capacitor Cst is coupled to the anode of the light-emitting element 20 (i.e., the second electrode of the second transistor T2).

[0109] Furthermore, the first plate Cst1, the connecting electrode 202, the first electrode 201, and the second plate Cst2 may be located in different layers (i.e., different layers). The material of the first plate Cst1 and the material of the first electrode 201 may both include a transparent conductive material. In this way, the storage capacitor Cst can also be considered to be a transparent capacitor design.

[0110] The display area A1 can have at least one opening K1, and the orthographic projections of the first electrode Cst1 and the first electrode 201 on the substrate 01 can both overlap with the orthographic projection of the opening K1 on the substrate 01. Because the orthographic projection of the second electrode Cst2 on the substrate 01 overlaps with the orthographic projection of the first electrode Cst1 on the substrate 01, it can also be seen that the orthographic projection of the storage capacitor Cst on the substrate 01 overlaps with the orthographic projection of the opening K1 on the substrate 01. For example, the display area A1 shown in the figure has a first opening K11 and a second opening K12 spaced apart from each other. The space between the two openings can be a non-light-transmitting area, that is, it cannot transmit light.

[0111] As can be seen, the display panel described in the embodiments of the present disclosure utilizes a transparent capacitor design to form the storage capacitor Cst, which, by overlapping with the opening, can achieve a dual-sided illumination effect. Specifically, the region where the storage capacitor Cst resides can serve as the common portion of the top- and bottom-emitting openings, thereby achieving both top- and bottom-emitting dual-sided illumination, optimizing the opening and achieving the goal of superior product display.

[0112] 1 , top emission may refer to: emitting light from one side of the cover plate 1 in a direction away from the display substrate 0 (marked as L1); bottom emission may refer to: emitting light from one side of the substrate 0 in a direction away from the cover plate 1 (marked as L2).

[0113] In summary, an embodiment of the present disclosure provides a display panel. The display panel includes a substrate, and a plurality of repeating units located on the substrate. The repeating units can be divided into a display area and a light-transmitting area, and include sub-pixels located in the display area, the sub-pixels include mutually coupled pixel circuits and light-emitting elements, and the pixel circuits are used to drive the light-emitting elements to emit light. In addition, the pixel circuit includes a storage capacitor. On the display substrate, the storage capacitor includes a first electrode and a second electrode that overlap each other, and the first electrode can be connected to the first electrode of the light-emitting element through a switching electrode. In addition, the first electrode and the first electrode are both made of transparent conductive material and overlap with the opening of the display area. In this way, under the premise of reliable coupling of each part and ensuring reliable driving of the light-emitting element to emit light, a transparent capacitor design can be used to achieve double-sided light emission, and the display effect is better.

[0114] Figure 6 further illustrates a partial layout of the structure shown in Figure 5. Figure 7 illustrates a cross-sectional view of the structure shown in Figure 5 along the BB' direction. Referring to Figures 1 and 7 , it can be seen that the display area A1 may have a first opening K11 and a second opening K12 spaced apart from each other.

[0115] The first electrode 201 may include a first sub-electrode 2011 and a second sub-electrode 2012 located in the same layer and spaced apart from each other. Furthermore, the first sub-electrode 2011 may be connected to the first electrode plate Cst1 via the connecting electrode 202 .

[0116] The orthographic projection of the first sub-electrode 2011 on the substrate 01 may overlap with the orthographic projection of the first opening K11 on the substrate 01. The orthographic projections of the first electrode plate Cst1 and the second sub-electrode 2012 on the substrate 01 may both overlap with the orthographic projection of the second opening K12 on the substrate 01. The orthographic projection of the connecting electrode 202 on the substrate 01 may be located within the orthographic projection of the first opening K11 and the second opening K12 on the substrate 01, i.e., located in the non-light-transmitting area. In other words, the orthographic projection of the connecting electrode 202 on the substrate 01 does not overlap with the orthographic projections of the first opening K11 and the second opening K12 on the substrate 01.

[0117] Optionally, continuing to refer to Figures 1 and 7, it can be seen that the orthographic projection of the first sub-electrode 2011 on the substrate 01 may not overlap with the orthographic projections of the first plate Cst1 and the second plate Cst2 on the substrate 01, that is, the orthographic projection of the first sub-electrode 2011 on the substrate 01 may not overlap with the orthographic projection of the storage capacitor Cst on the substrate 01. The orthographic projection of the second sub-electrode 2012 on the substrate 01 may overlap with the orthographic projections of the first plate Cst1 and the second plate Cst2 on the substrate 01, that is, the orthographic projection of the second sub-electrode 2012 on the substrate 01 may overlap with the orthographic projection of the storage capacitor Cst on the substrate 01. The orthographic projection of the second sub-electrode 2012 on the substrate 01 shown in the figure is located within the orthographic projection of the storage capacitor Cst on the substrate 01.

[0118] 1 and 7 , the display substrate may further include a pixel definition layer (PDL) located on a side of the first electrode 201 away from the substrate 01. The pixel definition layer PDL may be used to define the first opening K11 and the second opening K12.

[0119] Optionally, the material of the pixel definition layer PDL may include polyimide, acrylic, or polyethylene terephthalate.

[0120] Optionally, referring to FIG. 1 , it can be seen that the display panel may further include a black matrix (BM) layer BM located on a side of the cover plate 1 close to the display substrate 0 .

[0121] The orthographic projection of the black matrix layer BM on the substrate 01 may be located within the orthographic projection of the pixel definition layer PDL on the substrate 01. Thus, it can be further determined that the interval between the first opening K11 and the second opening K12 is a non-light-transmitting area that cannot transmit light.

[0122] That is, referring to Figure 6 , in the disclosed embodiment, the connecting electrode 202 can be positioned at the center between the first opening K11 and the second opening K12, i.e., positioned in the non-light-transmitting region. The connecting electrode 202 is typically made of metal, meaning it is opaque. Positioning the connecting electrode 202 in the non-light-transmitting region avoids affecting the opening size, optimizing the opening and ensuring a better display effect.

[0123] Optionally, referring to FIG1 and FIG7 , it can be seen that the display substrate described in the embodiment of the present disclosure may further include: a first transparent conductive layer, an active layer, a gate (GT) metal layer GT, and a second transparent conductive layer stacked in sequence in a direction away from the substrate 01 .

[0124] Optionally, in the embodiment of the present disclosure, the material of the first transparent conductive layer and the material of the second transparent conductive layer may both include: indium tin oxide (ITO). Accordingly, the first transparent conductive layer is identified as 1ITO and the second transparent conductive layer is identified as 2ITO in the figure. The material of the active layer may include an oxide material or a low-temperature polycrystalline silicon LTPS material as described in the above embodiment. For example, when an oxide material is included, the material of the active layer may be an indium gallium zinc oxide (IGZO) material. Accordingly, the active layer is identified as IGZO in the figure. The material of the gate metal layer GT may include metal materials such as aluminum Al and silver Ag. It can also be seen that the gate metal layer GT is a non-transparent layer and is not light-transmitting.

[0125] Alternatively, referring to Figures 1 and 7 , it can be seen that the first electrode Cst1 described in the embodiments of the present disclosure can be located on the same layer as the first transparent conductive layer 1ITO. The connecting electrode 202 can be located on the same layer as the gate metal layer GT. Since the gate metal layer GT is opaque, it can be seen that the connecting electrode 202 is also opaque as described in the above embodiments. The first electrode 201 can be located on the same layer as the second transparent conductive layer 2ITO. The second electrode Cst2 can be located on the same layer as the active layer IGZO.

[0126] It should be noted that being located in the same layer may refer to a layer structure formed by patterning a film layer for forming a specific pattern using the same film forming process, and then patterning the film layer using the same mask through a single patterning process. Depending on the specific pattern, a single patterning process may include multiple exposure, development, or etching processes, and the specific pattern in the formed layer structure may be continuous or discontinuous. That is, multiple elements, components, structures, and / or parts located in the "same layer" are made of the same material and are formed by the same patterning process. In this way, the preparation process and preparation cost can be saved, and the preparation efficiency can be accelerated.

[0127] Optionally, continuing to refer to Figures 1 and 7, it can be seen that the display substrate recorded in the embodiment of the present disclosure may also include: a buffer layer Buffer and a gate insulation (GI) layer GI located between the first transparent conductive layer 1ITO and the gate metal layer GT, and stacked in sequence in a direction away from the substrate 01.

[0128] Also, a passivation (PVX) layer PVX and a planar layer are located between the gate metal layer GT and the second transparent conductive layer 2ITO and are sequentially stacked in a direction away from the substrate 01 .

[0129] Optionally, the material of the flat layer may include resin material. Accordingly, the flat layer is labeled as resin in the figure.

[0130] The first electrode 201 may be connected to the connection electrode 202 through a first via hole H1 penetrating the passivation layer PVX and the planar layer Resin, and the connection electrode 202 may be connected to the first electrode plate Cst1 through a second via hole H2 penetrating the gate insulating layer GI and the buffer layer Buffer.

[0131] That is, in the embodiment of the present disclosure, the storage capacitor Cst can be a transparent capacitor composed of the first transparent conductive layer 1ITO and the active layer IGZO. The anode of the light-emitting element 20 can be a transparent electrode composed of the second transparent conductive layer 2ITO. In combination with the circuit diagram shown in Figure 4, it can be seen that the first transparent conductive layer 1ITO can be used as one pole of the second transistor T2 (i.e., the driving transistor), and the gate metal layer GT is connected to it through the second via H2 penetrating the gate insulating layer GI and the buffer layer Buffer, and then connected to the second transparent conductive layer 2ITO through the first via H1 penetrating the passivation layer PVX and the flat layer Resin, forming two channels Ch1 and Ch2 to enter the anode region of the light-emitting element 20.

[0132] One of the two channels, Ch1, may be a channel connecting the connection electrode 202 to the first electrode (e.g., anode) of the light-emitting element 20, i.e., a channel connected via the first via H1. The other channel, Ch2, may be a channel connecting the first plate Cst1 of the storage capacitor Cst to the connection electrode 202, i.e., a channel connected via the second via H2. This facilitates sub-pixel maintenance design through different channels.

[0133] Alternatively, referring to FIG. 1 and FIG. 7 , it can be seen that the connection electrode 202 located on the same layer as the gate metal layer GT may include two integral parts. One part may be located within the second via hole H2 and respectively connect to the first transparent conductive layer 1ITO and the other part; the other part may be located on a side of the gate insulating layer GI away from the substrate 01 and further connect to the second transparent conductive layer 2ITO.

[0134] Alternatively, referring to Figures 1 and 7 , it can be seen that the first electrode 201, located on the same layer as the second transparent conductive layer 2ITO, can include two integral parts. One part is located within the first via H1, connecting to the connecting electrode 202 and the other part, respectively; the other part is located on the side of the planar layer Resin away from the substrate 01. Furthermore, as shown in Figures 1 and 7 , the via located within the first via H1 and penetrating the passivation layer PVX can have a "C" shape.

[0135] 1 and 7 , it can be seen that the orthographic projection of the first via H1 on the substrate 01 may not overlap with the orthographic projection of the second via H2 on the substrate 01. This prevents mutual interference between the signals transmitted by the two channels Ch1 and Ch2.

[0136] Optionally, the area of ​​the orthographic projection of the first via H1 on the substrate 01 may be larger than the area of ​​the orthographic projection of the second via H2 on the substrate 01. In this way, reliable connection between the connecting electrode 202 and the first electrode 201 and the first electrode 201 with a relatively larger area in the first electrode plate Cst1 can be ensured, thereby ensuring reliable signal transmission.

[0137] Alternatively, the orthographic projections of the first and second via holes H1 and H2 on substrate 01 can both be located within the orthographic projections of the spacing between the first and second openings K11 and K12 in display area A1 on substrate 01. In other words, similar to the connecting electrode 202, the first and second via holes H1 and H2 can also be located in the non-light-transmitting area. This prevents light leakage through the holes, avoids affecting the opening size, and optimizes the opening to ensure a better display effect.

[0138] Optionally, with continued reference to FIG. 1 and FIG. 7 , it can be seen that the display substrate described in the embodiment of the present disclosure may further include: a metal shielding light layer (SHL) located between the substrate 01 and the buffer layer Buffer.

[0139] Optionally, in the embodiment of the present disclosure, the pixel circuit 10 may be connected to a plurality of signal lines. The pixel circuit 10 may be configured to drive the light-emitting element 20 to emit light in response to signals provided by the plurality of signal lines. Furthermore, as shown in FIG4 , the plurality of signal lines may include a first power line VDD, a second power line VSS, a scan line G1, a data line Data, and a sense line Sense.

[0140] The scan line G1 may extend along the first direction X and may be located on the same layer as the gate metal layer GT. The first power line VDD, the second power line VSS, the data line Data, and the sensing line Sense may all extend along the second direction Y and may all be located on the same layer as the metal light shielding layer SHL.

[0141] Furthermore, the first direction X and the second direction Y may intersect. For example, referring to FIG4 , the first direction X and the second direction Y may be perpendicular to each other. In the case of a plurality of rows and columns of sub-pixels, the first direction X may refer to the row direction, and the second direction Y may refer to the column direction.

[0142] Optionally, in some embodiments, in the pixel circuit 10 included in at least one sub-pixel, the gate of the first transistor T1 and the gate of the third transistor T3 may be connected to the same scan line G1. In the pixel circuit 10 included in each sub-pixel in at least one row direction, the gates of multiple first transistors T1 and the gates of multiple third transistors T3 may be connected to the same scan line G1. In the pixel circuit 10 included in multiple sub-pixels of at least one repeating unit 02, the gates of multiple first transistors T1 and the gates of multiple third transistors T3 may be connected to the same scan line G1.

[0143] For example, referring to FIG4 , in the pixel circuit 10 shown therein, the gates of the four first transistors T1 and the gates of the four third transistors T3 of a repeating unit 02 are all connected to the same scan line G1. Furthermore, referring to FIG4 , it can be seen that the scan line G1 can be designed in a ring shape to facilitate layout and save space.

[0144] Optionally, in some embodiments, as can be seen from FIG. 4 , the first power line VDD and the second power line VSS can be located on either side of the first direction X, respectively. The sensing line Sense can be located between the first power line VDD and the second power line VSS, and can be located between two sub-pixels arranged along the first direction X. The two data lines coupled to the two sub-pixels located between the sensing line Sense and the first power line VDD and arranged along the second direction Y can be located between the sensing line Sense and the first power line VDD. Similarly, the two data lines coupled to the two sub-pixels located between the sensing line Sense and the second power line VSS and arranged along the second direction Y can be located between the sensing line Sense and the second power line VSS. Furthermore, the positions of the first power line VDD and the second power line VSS can be substantially mirror-symmetrical with respect to the sensing line Sense. The two data lines located between the sensing line Sense and the first power line VDD, and the two data lines located between the sensing line Sense and the second power line VSS, can be substantially mirror-symmetrical with respect to the sensing line Sense.

[0145] That is, in some embodiments, a scan line G1 may define two adjacent pixel rows, a sense line Sense may define two adjacent pixel columns, and the scan line G1 and the sense line Sense may define four sub-pixels, which is a repeating unit 02 .

[0146] Optionally, continuing to refer to Figures 1 and 7, it can be seen that the gate metal layer GT recorded in the embodiment of the present disclosure can also be connected to the metal shading layer SHL, the first transparent conductive layer 1ITO and the active layer IGZO respectively through vias (not identified one by one) penetrating the gate insulating layer GI, thereby reliably establishing the connection of the circuit shown in Figure 4.

[0147] 1 and 7 , the display substrate according to the embodiment of the present disclosure may further include: a light-emitting layer and a second electrode 203, which are located between the first electrode 201 and the cover plate 1 and are sequentially stacked in a direction away from the substrate 01. The pixel defining layer PDL included in the display substrate may be located between the light-emitting layer EL and the first electrode 201.

[0148] Optionally, the light-emitting layer may be an electroluminescent layer (EL), and accordingly, the light-emitting layer is labeled EL in the figure. Here, the second electrode 203 may refer to the cathode of the light-emitting element 20. The light-emitting layer EL may emit light in response to the voltage difference between the signals received by the first electrode 201 and the second electrode 203. The signal received by the first electrode 201 may be a light-emitting drive signal transmitted by the pixel circuit 10; the signal received by the second electrode 203 may be a second power supply signal provided by the second power supply line VSS.

[0149] Of course, in some other embodiments, the light-emitting layer may further include at least one of the following layers: a hole injection layer (HIL), a hole transport layer (HTL), an electron blocking layer (EBL), a hole blocking layer (HBL), an electron transport layer (ETL), and an electron injection layer (EIL). During the preparation process, the light-emitting layer EL may be formed by mask evaporation or by inkjet technology.

[0150] Optionally, the material of the second electrode 203 may also include a transparent conductive material to ensure double-sided light emission. For example, the material of the second electrode 203 may include indium zinc oxide (IZO).

[0151] Continuing with reference to FIG. 1 , it can be seen that the display panel described in the embodiment of the present disclosure may further include a first color filter (CF) layer CF1 located on the side of the cover plate 1 proximal to the display substrate 0. The orthographic projection of the first color filter layer CF1 on the substrate 01 overlaps with the orthographic projection of the opening K1 on the substrate 01. In other words, a CF on Cover Glass process can be employed to provide a color filter layer on one side of the cover plate for top-emitting light to achieve full-color display.

[0152] Furthermore, the display substrate may further include a second color filter layer CF2 located on the side of the first electrode 201 closest to the substrate 01. The orthographic projection of the second color filter layer CF2 on the substrate 01 may also overlap with the orthographic projection of the opening K1 on the substrate 01. In other words, a color filter layer may be provided on one side of the display substrate using a CF On Array process to provide bottom-emitting light and achieve full-color display.

[0153] For example, referring to FIG. 1 , the second color filter layer CF2 may be located between the passivation layer PVX and the planarization layer Resin included in the display substrate, thereby ensuring planarization of the color filter layer.

[0154] Alternatively, referring to FIG. 1 , it can be seen that both the first color filter layer CF1 and the second color filter layer CF2 may include filters for the three primary colors of red (R), green (G), and blue (B). Of course, this is merely a schematic illustration of one color division, and the presently disclosed embodiments are not limited thereto.

[0155] Optionally, in combination with Figure 1 and the schematic diagram of the partial structural layout shown in Figure 8, it can be seen that the opening K1 recorded in the embodiment of the present disclosure may include: a top-emitting opening K1_U and a bottom-emitting opening K1_B that are relatively arranged. The top-emitting opening K1_U can be located on one side of the cover plate 1 for providing top-emitting display. The bottom-emitting opening K1_B is located on one side of the display substrate 0 for providing bottom-emitting display. In combination with Figure 1 and Figure 8, it can be seen that, relative to the top-emitting opening K1_U for top-emitting display, the side of the bottom-emitting opening K1_B for bottom-emitting display will lose part of the luminous area due to the obstruction of the pixel circuit and non-transparent electrode wiring (including transistors and light-shielding layer SHL). However, this does not affect the compatibility with top and bottom double-sided display, and the purpose of achieving excellent display is achieved.

[0156] Optionally, based on FIG8 , further referring to the structural layout shown in FIG9 and the cross-sectional view shown in FIG10 , it can be seen that the display substrate described in the embodiment of the present disclosure may further include: a reflective electrode 204 located on the side of the first electrode 201 away from the substrate 01 .

[0157] For example, referring to FIG. 10 , the reflective electrode 204 shown therein is located between the first electrode 201 and the pixel defining layer PDL included in the display substrate 0 .

[0158] The orthographic projection of the reflective electrode 204 on the substrate 01 may overlap with the orthographic projection of the bottom-emitting opening K1_B on the substrate 01, but may not overlap with the orthographic projection of the top-emitting opening K1_U on the substrate 01. That is, the reflective electrode 204 may be the result of a logical NOT of the bottom-emitting opening K1_B and the top-emitting opening K1_U.

[0159] Optionally, the material of the reflective electrode 204 can be an opaque metal material. By arranging the reflective electrode 204 at the above position, the bottom light cannot be emitted due to the obstruction of the pixel circuit and the non-transparent electrode wiring. Therefore, the light emission rate of the top light can be increased without affecting the bottom light emission. Specifically, the reflective electrode 204 can perform microcavity enhancement on the top light emitting area, thereby increasing the light emission rate during top light emission. Thus, compared with the scheme of Figure 1, when the luminous brightness is fixed, the effect of reducing product power consumption can be achieved. The reflective electrode 204 can also be called a reflective anode.

[0160] Optionally, taking a repeating unit 02 shown in FIG4 as an example, in combination with FIG5 , FIG11 to FIG27 respectively show the structural layouts of different film layers. Referring to FIG11 to FIG27 , it can be further seen that a repeating unit 02 can be divided into a display area A1 and a light-transmitting area A2 located on one side of the display area A1, and a repeating unit 02 can include four sub-pixels located in the display area A1 and in a "Square" shape: a white sub-pixel P1_W, a green sub-pixel P1_G, a red sub-pixel P1_R, and a blue sub-pixel P1_B. It should be noted that the figures only schematically indicate the corresponding structure in one sub-pixel, and the same is true for other repeated parts, which are not marked again.

[0161] (1) Referring to FIG11 , a structural layout of a first transparent conductive layer 1ITO is shown. Referring to FIG11 , it can be seen that the first transparent conductive layer 1ITO can be used to form the first electrode Cst1 of the storage capacitor Cst (i.e., the first end of the storage capacitor Cst). In other words, the first electrode Cst1 and the first transparent conductive layer 1ITO described in the above embodiment can be located on the same layer.

[0162] 4 and 11 , it can be seen that the first plate Cst1 of the storage capacitor Cst in the white sub-pixel P1_W and the first plate Cst1 of the storage capacitor Cst in the green sub-pixel P1_G can be arranged along the first direction X; the first plate Cst1 of the storage capacitor Cst in the red sub-pixel P1_R and the first plate Cst1 of the storage capacitor Cst in the blue sub-pixel P1_B can be arranged along the first direction X; the first plate Cst1 of the storage capacitor Cst in the white sub-pixel P1_W and the first plate Cst1 of the storage capacitor Cst in the red sub-pixel P1_R can be arranged along the second direction Y; and the first plate Cst1 of the storage capacitor Cst in the green sub-pixel P1_G and the first plate Cst1 of the storage capacitor Cst in the blue sub-pixel P1_B can be arranged along the second direction Y.

[0163] Optionally, the shape of the first electrode plate Cst1 can be a rectangle with chamfered corners. Of course, this is only a schematic illustration of the shape. The size of the first electrode plate Cst1 in different sub-pixels can be the same or different. Here, the size can refer to the area of ​​the orthographic projection on the substrate 01.

[0164] (2) Referring to FIG12, which shows a structural layout of a light shielding layer SHL, FIG13 shows a structural layout including a first transparent conductive layer 1ITO and a light shielding layer SHL in combination with FIG11 and FIG12.

[0165] Referring to FIG. 12 , it can be seen that the light-shielding layer SHL can be used to form the sensing line Sense, the first power line VDD, the second power line VSS, and the data line Data described in the above embodiment. The data line Data includes the data line Data_W coupled to the white sub-pixel P1_W, the data line Data_G coupled to the green sub-pixel P1_G, the data line Data_R coupled to the red sub-pixel P1_R, and the data line Data_B coupled to the blue sub-pixel P1_B. In other words, the sensing line Sense, the first power line VDD, the second power line VSS, and the data line Data described in the above embodiment are all located on the same layer as the light-shielding layer SHL.

[0166] 4 and 12 , the sensing line Sense, the first power line VDD, the second power line VSS, and the data line Data may be arranged at intervals along the first direction X. The arrangement is described with reference to the above embodiment and will not be described in detail. Furthermore, each signal line may extend along the second direction Y.

[0167] Optionally, each signal line can be a straight line or a broken line of equal width, or a straight line or a broken line of unequal width. Using straight lines or broken lines of varying widths not only facilitates the layout of the pixel structure but also reduces parasitic capacitance on the signal line, thereby ensuring better reliability of the provided signal.

[0168] Continuing with FIG. 12 , it can be seen that the light shielding layer SHL can also be used to form a light shielding portion B1 for shielding the second transistor T2 (i.e., the drive transistor that generates the light-emitting drive signal) from light leakage. This can reduce the intensity of light incident on the drive transistor, lowering the leakage current of the drive transistor and thereby minimizing the impact on the drive transistor's characteristics, ensuring that the drive transistor can reliably generate the light-emitting drive signal to drive the light-emitting element 20 to emit light reliably.

[0169] (3) Referring to FIG14 , which shows a structural layout of an active layer IGZO, and FIG15 , in combination with FIG13 and FIG14 , shows a structural layout including a first transparent conductive layer 1ITO, a light shielding layer SHL, and an active layer IGZO.

[0170] 14 , it can be seen that the active layer IGZO can be used to form the active layer IGZO of the first transistor T1, the active layer IGZO of the second transistor T2, and the active layer IGZO of the third transistor T3, and can also be used to form the second electrode Cst2 of the storage capacitor Cst (i.e., the second end of the storage capacitor Cst). In this way, the storage capacitor Cst can be formed together with the first transparent conductive layer 1ITO shown in FIG.

[0171] For any sub-pixel, the active IGZO layer of the first transistor T1 and the active IGZO layer of the third transistor T3 can be located on the same side of the second electrode plate Cst2 in the second direction Y, and the active IGZO layer of the second transistor T2 can be located at an end of the second electrode plate Cst2 away from the same side. Furthermore, referring to FIG. 15 , it can be seen that the active IGZO layer of the second transistor T2 can overlap with the light shielding portion B1 formed by the light shielding layer SHL, so that the light shielding portion B1 can reliably shield the channel region of the second transistor T2, preventing light from affecting the channel, thereby protecting the electrical performance of the second transistor T2.

[0172] Optionally, the active layer IGZO of the first transistor T1 and the active layer IGZO of the third transistor T3 may be arranged alternately along the first direction X. Furthermore, the active layer IGZO of the first transistor T1 of two sub-pixels (e.g., P1_W and P1_G) arranged along the first direction X may be located on different sides of the active layer IGZO of the third transistor T3 thereof. Furthermore, the active layer IGZO of the first transistor T1 of two sub-pixels (e.g., P1_W and P1_R) arranged along the second direction Y may be located on different sides of the active layer IGZO of the third transistor T3 thereof.

[0173] Alternatively, referring to FIG. 14 , it can be seen that for any sub-pixel, the active IGZO layer of the first transistor T1 and the second electrode Cst2 can be interconnected as an integrated structure. Furthermore, for two sub-pixels arranged along the second direction Y, the active IGZO layers of their third transistors T3 can be interconnected as an integrated structure. This saves space, reduces the number of interconnections, and simplifies the process.

[0174] Optionally, the active IGZO layer of the first transistor T1 and the active IGZO layer of the third transistor T3 may be in an "I" shape, the active IGZO layer of the second transistor T2 may be rectangular with chamfered corners, and the second electrode plate Cst2 may be in an irregular shape as shown in the figure. Of course, these are merely schematic illustrations of the shapes.

[0175] Optionally, in conjunction with FIG. 14 and FIG. 15 , it can be seen that the orthographic projection of the active layer IGZO of the first transistor T1 on the substrate 01 does not overlap with the orthographic projection of the first plate Cst1 of the storage capacitor Cst on the substrate 01, and the orthographic projection of the active layer IGZO of the third transistor T3 on the substrate 01 does not overlap with the orthographic projection of the first plate Cst1 of the storage capacitor Cst on the substrate 01. This facilitates the design of the aspect ratios of the first transistor T1 and the third transistor T3.

[0176] Optionally, in two sub-pixels arranged along the first direction X, the positions and shapes of the active IGZO layer of the first transistor T1 and the active IGZO layer of the third transistor T3 may be substantially mirror-symmetrical with respect to a vertical reference line; the position of the active IGZO layer of the second transistor T2 may be substantially mirror-symmetrical with respect to the vertical reference line; and, in two sub-pixels arranged along the second direction Y, the position of the active IGZO layer of the second transistor T2 may also be substantially mirror-symmetrical with respect to the vertical reference line. The vertical reference line may be a straight line extending along the second direction Y and bisecting the display area in the first direction X.

[0177] Optionally, the active layer IGZO of each transistor may include a first region, a second region, and a channel region located between the first region and the second region.

[0178] Optionally, the active layer IGZO may be a single layer, a double layer, or a multi-layer.

[0179] (4) Referring to FIG16 , which shows a structural layout of a gate insulating layer GI, FIG17 shows a structural layout including a first transparent conductive layer 1ITO, a light shielding layer SHL, an active layer IGZO, and a gate insulating layer GI in combination with FIG15 and FIG16 .

[0180] 16 , it can be seen that the gate insulating layer GI can be used to form the second via hole H2 as described in the above embodiment, as well as the other multiple via holes H3 to H11 . Furthermore, it can be seen in conjunction with FIG17 :

[0181] The second via hole H2 can be used to connect the first transparent conductive layer 1ITO forming the first electrode Cst1 of the storage capacitor Cst with the subsequently formed gate metal layer GT to establish a channel Ch2 entering the anode region.

[0182] The orthographic projection of via H3 on substrate 01 can overlap with the orthographic projection of second power line VSS on substrate 01, allowing for connection between the subsequently formed gate metal layer GT and second power line VSS. As can be seen from the figure, multiple vias H3 can be included, and they can be arranged sequentially along the first direction X and the second direction Y to increase connection reliability.

[0183] The orthographic projection of via H4 on substrate 01 can overlap with the orthographic projection of first power line VDD on substrate 01, allowing for connection between the subsequently formed gate metal layer GT and first power line VDD. As can also be seen from the figure, multiple vias H2 can be included, and they can be arranged sequentially along the second direction Y to increase connection reliability.

[0184] The orthographic projection of the via H5 on the substrate 01 may overlap with the orthographic projection of the sensing line Sense on the substrate 01 , and may be used for connecting the subsequently formed gate metal layer GT with the sensing line Sense.

[0185] The orthographic projection of the via H6 on the substrate 01 may overlap with the orthographic projection of the data line Data on the substrate 01 , and may be used for connecting the subsequently formed gate metal layer GT with the data line Data.

[0186] The orthographic projection of the via hole H7 on the substrate 01 may overlap with the orthographic projection of the light shielding portion B1 on the substrate 01 , and may be used for connecting the subsequently formed gate metal layer GT with the light shielding portion B1 .

[0187] The orthographic projection of the via H8 on the substrate 01 can overlap with the orthographic projection of the active layer IGZO of the second transistor T2 on the substrate 01, and can be used to connect the subsequently formed gate metal layer GT to the active layer IGZO of the second transistor T2. The vias H8 can include two groups arranged along the first direction X, each group including one via, or two vias arranged along the second direction Y. One group can connect the gate metal layer GT to the first region of the active layer IGZO of the second transistor T2; the other group can connect the gate metal layer GT to the second region of the active layer IGZO of the second transistor T2.

[0188] The orthographic projection of the via H9 on the substrate 01 may overlap with the orthographic projection of the first plate Cst1 of the storage capacitor Cst on the substrate 01 , and may be used for connecting a subsequently formed gate metal layer GT with the first plate Cst1 .

[0189] The orthographic projection of the via H10 on the substrate 01 may overlap with the orthographic projection of the first plate Cst1 of the storage capacitor Cst on the substrate 01 , and may be used for connecting a subsequently formed gate metal layer GT with the storage capacitor Cst.

[0190] The orthographic projection of the via H11 on the substrate 01 may overlap with the orthographic projection of the active layer IGZO of the first transistor T1 on the substrate 01 , and may be used for connecting the subsequently formed gate metal layer GT with the active layer IGZO of the first transistor T1 .

[0191] The orthographic projection of the via H12 on the substrate 01 can overlap with the orthographic projection of the active layer IGZO of the third transistor T2 on the substrate 01, and can be used to connect the subsequently formed gate metal layer GT to the active layer IGZO of the third transistor T2. The vias H12 include two vias arranged in a staggered manner, one of which connects the gate metal layer GT to the first region of the active layer IGZO of the third transistor T2, and the other connects the gate metal layer GT to the second region of the active layer IGZO of the third transistor T2.

[0192] (5) Referring to FIG18 , which shows a structural layout of a gate metal layer GT, FIG19 shows a structural layout including a first transparent conductive layer 1ITO, a light shielding layer SHL, an active layer IGZO, a gate insulating layer GI, and a gate metal layer GT, in conjunction with FIG17 and FIG18 .

[0193] As can be seen from Figures 18 and 19 , the gate metal layer GT can be used to form a scan line G1. That is, the scan line G1 and the gate metal layer GT described in the above embodiment can be located on the same layer. Furthermore, the scan line G1 can be shared by the first transistor T1 and the third transistor T3 included in the four sub-pixels in a repeating unit O2.

[0194] Optionally, the scan line G1 may be located in the middle of the repeating unit 02, that is, between the sub-pixels arranged along the second direction Y. For any of the first transistor T1 and the third transistor T3, the region where the scan line G1 overlaps with its active layer IGZO may serve as the gate of the transistor, so that the scan line G1 may control the on / off state of the first transistor T1 and the second transistor T2.

[0195] Optionally, the scan line G1 extends along the first direction X and may have a ring-shaped portion and a strip-shaped portion; the ring-shaped portion may be located in the display area A1, and the strip-shaped portion may be located in the light-transmitting area A2.

[0196] Optionally, the annular portion may include two sub-lines extending along the first direction X, and the two sub-lines may be arranged along the second direction Y. Of the two sub-lines, one sub-line may be respectively connected to the pixel circuits 10 of two sub-pixels (e.g., white sub-pixel P1_W and green sub-pixel P1_G) arranged along the first direction X in one pixel row, and the other sub-line may be respectively connected to the pixel circuits 10 of two sub-pixels (e.g., red sub-pixel P1_R and blue sub-pixel P1_B) arranged along the first direction X in another pixel row. In this way, the connection between the double line segment and the pixel circuits included in the multiple sub-pixels in the repeating unit is achieved. Furthermore, the orthographic projection of one sub-line on substrate 01 can at least partially overlap with the orthographic projections of the active layers IGZO of the first transistor T1 and the active layers IGZO of the third transistor T3 in the two sub-pixels connected to it. The overlapping regions serve as the gates of the first transistor T1 and the third transistor T3, respectively. This sub-line is simultaneously connected to the gates of the first transistor T1 and the third transistor T3 in the two sub-pixels connected to it. The orthographic projections of another sub-line on substrate 01 can at least partially overlap with the orthographic projections of the active layers IGZO of the first transistor T1 and the third transistor T3 in the two sub-pixels connected to it. The overlapping regions serve as the gates of the first transistor T1 and the third transistor T3, respectively. That is, the other sub-line is simultaneously connected to the gates of the first transistor T1 and the third transistor T3 in the two sub-pixels connected to it. In this way, a sub-line transmitting the same scan signal can simultaneously control the on / off switching of all first transistors T1 and all third transistors T3 in the four sub-pixels of the repeating unit.

[0197] Optionally, the annular portion may include two sub-lines extending along the second direction Y, and the two sub-lines may be arranged along the first direction X and form an annular structure with the two sub-lines extending along the first direction X. The annular structure may be a rectangular ring or a polygonal ring. The two sub-lines may be connected in a one-to-one correspondence with the two strip-shaped sub-lines located in the light-transmitting area A2, thereby forming a continuous scan line G1 extending along the first direction X.

[0198] Optionally, the two sub-lines extending along the first direction X may be substantially mirror-symmetrical with respect to the vertical reference line; and the two sub-lines extending along the second direction Y may be substantially mirror-symmetrical with respect to the horizontal reference line. The horizontal reference line may be a straight line extending along the first direction X and bisecting the display area in the second direction Y, with the horizontal reference line and the vertical reference line being perpendicular to each other.

[0199] Optionally, for multiple repeating units 02 arranged sequentially in the first direction X, the strip-shaped portion and the ring-shaped portion of the scan line G1 coupled to each repeating unit 02 can be an interconnected integrated structure, and the strip-shaped portion and the ring-shaped portion of the scan line G1 coupled to multiple repeating units 02 can be an interconnected integrated structure.

[0200] Optionally, as described in the above embodiment, in at least one sub-pixel, one scan line G1 can simultaneously control the on / off switching of the first transistor T1 and the third transistor T3 in the sub-pixel. In at least one pixel row, one scan line G1 can simultaneously control the on / off switching of all first transistors T1 and all third transistors T3 in the pixel row. In at least one repeating unit O2, one scan line G1 can simultaneously control the on / off switching of all first transistors T1 and all third transistors T3 in the repeating unit.

[0201] Optionally, in combination with Figures 17 and 19, it can be seen that the orthographic projections of vias H6, H11, H12 and H5 on substrate 01 can be within the range of the orthographic projections of the area enclosed by the annular portion of the scan line G1 on substrate 01.

[0202] In addition, continuing to refer to Figure 18, it can be seen that the gate metal layer GT can also be used to form a connecting electrode 202, that is, the connecting electrode 202 and the gate metal layer GT recorded in the above embodiment can be located in the same layer. The connecting electrode 202 can be in the shape of a strip extending along the first direction X, one end of which can be connected to the first electrode Cst1 formed by the first transparent conductive layer 1ITO through the second via H2, and the other end can extend in a direction away from the sensing line Sense for connection with the subsequently formed second transparent conductive layer 2ITO (that is, the first electrode 201 of the light-emitting element 20). The connecting electrode 202 in the two sub-pixels arranged along the second direction Y can cross the first power line VDD, that is, the orthographic projection of the connecting electrode 202 on the substrate 01 and the orthographic projection of the first power line VDD on the substrate 01 can overlap.

[0203] Optionally, the connection electrode 202 may include two interconnected parts, one of which is in a strip shape and connected to the first electrode Cst1 through one end; and the other is in a rectangular shape and connected to the first electrode 201 of the light-emitting element 20 through the other end. The strip-shaped part crosses the first power line VDD.

[0204] Optionally, the two parts of the connecting electrode 202 may be located in the same layer and form an integrated structure that is interconnected.

[0205] Optionally, continuing to refer to Figure 18, it can be seen that the gate metal layer GT can also be used to form multiple transfer electrodes E1 to E5, as well as a gate electrode GE, a first power auxiliary line F1, a second power auxiliary line F2, a first power connection line L01, a second power connection line L02 and an auxiliary electrode F01.

[0206] The first auxiliary power line F1 can be in the shape of a strip extending along the second direction Y and can be disposed in two sub-pixels arranged along the second direction Y (e.g., the white sub-pixel P1_W and the red sub-pixel P1_R), located on one side of the storage capacitor Cst in the first direction X. The first auxiliary power line F1 can be connected to the first power line VDD through a via H4. The first auxiliary power line F1 and the first power line VDD form a double-layer routing structure, which not only ensures the reliability of power signal transmission but also effectively reduces the resistance of the first power line VDD, effectively reducing the voltage drop of the first power signal, and ensuring a better display effect.

[0207] Optionally, the second power auxiliary line F2 can be in the shape of a strip extending along the second direction Y and can be disposed in two other sub-pixels (e.g., the green sub-pixel P1_G and the blue sub-pixel P1_B) arranged along the second direction Y, located on one side of the storage capacitor Cst in the first direction X. The second power auxiliary line F2 can be connected to the second power line VSS through a via H3. The second power auxiliary line F2 and the second power line VSS form a double-layer routing structure, which not only ensures the reliability of power signal transmission but also effectively reduces the resistance of the second power line VSS, effectively reducing the voltage drop of the second power signal, and ensuring a better display effect.

[0208] Optionally, the first power connection line L01 can be in the shape of a strip extending along the first direction X, and the main portion of the first power connection line L01 can be respectively arranged in two sub-pixels (e.g., the white sub-pixel P1_W and the green sub-pixel P1_G) extending along the first direction X, and can be located on the side of the storage capacitor Cst of the sub-pixel away from the scan line G1.

[0209] In the white sub-pixel P1_W, a first end of the first power connection line L01 is connected to the first power auxiliary line F1 in the white sub-pixel P1_W, and a second end of the first power connection line L01 extends along the first direction X to the green sub-pixel P1_G. The first power auxiliary line F1 is used to connect to the switching electrodes in the white sub-pixel P1_W and the green sub-pixel P1_G, respectively.

[0210] In the red sub-pixel P1_R, the first end of the first power connection line L01 is connected to the first power auxiliary line F1 in the red sub-pixel P1_R, and the second end of the first power connection line L01 extends along the first direction X to the blue sub-pixel P1_B. The first power auxiliary line F1 is used to connect to the switching electrodes in the red sub-pixel P1_R and the blue sub-pixel P1_B, respectively.

[0211] Optionally, the first power connection line L01 can realize a one-to-four structure of the first power line VDD in a repeating unit 02, saving the number of signal lines, reducing the occupied space, having a simple structure and a reasonable layout, making full use of the layout space, improving space utilization, and facilitating improving resolution and transparency.

[0212] Optionally, in the overlapping area between the first power connection line L01 and the sensing line Sense, a strip-shaped opening (through hole) extending along the first direction X may be provided on the first power connection line L01, so that the area forms a ring structure to reduce the overlapping area between the first power connection line L01 and the data line Data and the sensing line Sense, reduce the parasitic capacitance between the signal lines, and improve the display effect.

[0213] Optionally, the first power connection line L01 and the at least one first power auxiliary line F1 in the white sub-pixel P1_W may be interconnected as an integral structure, and the first power connection line L01 and the at least one first power auxiliary line F1 in the red sub-pixel P1_R may be interconnected as an integral structure.

[0214] Optionally, the second power connection line L02 and the auxiliary electrode F01 can be disposed in the light-transmitting area A2 of the repeating unit 02. The second power connection line L02 can be in the shape of a strip extending along the first direction X. The first end of the second power connection line L02 is connected to the second power auxiliary line F2, and the second end of the second power connection line L02 extends toward the light-transmitting area A2 and is connected to the auxiliary electrode F01.

[0215] Optionally, the auxiliary electrode F01 may be rectangular and used to connect to another auxiliary electrode formed subsequently. The other auxiliary electrode is used to connect to the second electrode 203 (i.e., the cathode of the light-emitting element 20) formed subsequently, thereby enabling connection between the second power line VSS and the second electrode 203.

[0216] Alternatively, only one second power connection line L02 and one auxiliary electrode F01 may be provided. As shown, they may be provided in the light-transmitting area A2 adjacent to the blue sub-pixel P1_B. Alternatively, multiple second power connection lines L02 and multiple auxiliary electrodes F01 may be provided in a one-to-one correspondence at different locations. The extension lengths of the multiple second power connection lines L02 in the first direction X may be the same or different, and the areas of the multiple auxiliary electrodes F01 may be the same or different.

[0217] Optionally, the second power auxiliary line F2 and the auxiliary electrode F01 connected via the second power connection line L02 may be an integrated structure connected to each other.

[0218] Optionally, considering the voltage drop (IR Drop) problem existing in large-size transparent displays, the embodiment of the present disclosure specifically sets a second power line VSS for transmitting a low-potential second power signal in each repeating unit 02. The second power line VSS can be connected to the cathode of the subsequently formed light-emitting element 20 through an auxiliary electrode, which can effectively reduce the voltage drop of the second power signal, effectively solve the voltage drop problem existing in large-size transparent displays, and ensure display uniformity.

[0219] Optionally, the position and shape of the first power auxiliary line F1 and the first power connection line L01 in the white sub-pixel P1_W and the position and shape of the first power auxiliary line F1 and the first power connection line L01 in the red sub-pixel P1_R can be substantially mirror-symmetrical with respect to the horizontal reference line. The position and shape of the second power auxiliary line F2 in the green sub-pixel P1_G and the position and shape of the second power auxiliary line F2 in the blue sub-pixel P1_B can be substantially mirror-symmetrical with respect to the horizontal reference line. The position of the first power auxiliary line F1 in the white sub-pixel P1_W and the position of the second power auxiliary line F2 in the green sub-pixel P1_G can be substantially mirror-symmetrical with respect to the vertical reference line, and the position of the first power auxiliary line F1 in the red sub-pixel P1_R and the position of the second power auxiliary line F2 in the blue sub-pixel P1_B can be substantially mirror-symmetrical with respect to the vertical reference line.

[0220] Optionally, the gate electrode GE can be in the shape of a strip extending along the second direction Y, and can be located on the side close to the first power line VDD. One end of the gate electrode GE can be connected to the second plate Cst2 of the storage capacitor Cst, and the other end of the gate electrode GE can extend in a direction away from the scan line G1, and the positive projection of the gate electrode GE on the substrate 01 can at least partially overlap with the positive projection of the active layer IGZO of the second transistor T2 on the substrate 01. The gate electrode GE can serve as the gate of the second transistor T2 and can control the conduction or disconnection of the second transistor T2.

[0221] Optionally, the transfer electrode E1 can be rectangular, with one end of the transfer electrode E1 being connected to the active layer IGZO of the first transistor T1 through a via H11, and the other end of the transfer electrode E1 being connected to the data line Data through a via H6. The transfer electrode E1 can serve as the first electrode of the first transistor T1, enabling the data line Data to write a data signal to the first electrode of the first transistor T1. Optionally, the data line Data can include a data line Data_W coupled to the white sub-pixel P1_W, a data line Data_G coupled to the green sub-pixel P1_G, a data line Data_R coupled to the red sub-pixel P1_R, and a data line Data_B coupled to the blue sub-pixel P1_B.

[0222] Optionally, the transfer electrode E2 can be in the shape of a strip extending along the second direction Y. One end of the transfer electrode E2 can be connected to the first electrode plate Cst1 via a via H10, and the other end of the transfer electrode E2 can be connected to the active layer IGZO of the third transistor T3 via a via H12. The transfer electrode E2 can serve as the second electrode of the third transistor T3, ensuring that the second electrode of the third transistor T3 and the first electrode plate Cst1 have the same potential.

[0223] Optionally, the transfer electrode E3 may be in the shape of a strip extending along the second direction Y. One end of the transfer electrode E3 may be connected to the active layer IGZO of the second transistor T2 via a via H8, and the other end of the transfer electrode E3 may be connected to the first power connection line L01. The transfer electrode E3 may serve as the first electrode of the second transistor T2. Because the first power connection line L01 is connected to the first auxiliary power line F1, and the first auxiliary power line F1 is connected to the first power line VDD, the first power line VDD writes the first power signal provided to the first electrode of the second transistor T2.

[0224] Optionally, the switching electrode E3 of the white sub-pixel P1_W, the switching electrode E3 of the green sub-pixel P1_G, and the connected first power connection line L01 can be an integrated structure connected to each other. The switching electrode E3 of the red sub-pixel P1_R, the switching electrode E3 of the blue sub-pixel P1_B, and the connected first power connection line L01 can be an integrated structure connected to each other.

[0225] Optionally, the transfer electrode E4 may be in the shape of a strip extending along the second direction Y. One end of the transfer electrode E4 may be connected to the active layer IGZO of the second transistor T2 via a via H8, and the other end of the transfer electrode E4 may be connected to the first plate Cst1 of the storage capacitor Cst via a via H7. The transfer electrode E4 may serve as the second electrode of the second transistor T2, so that the second electrode of the second transistor T2 and the first plate Cst1 have the same potential.

[0226] Optionally, the transfer electrode E5 may be in the shape of a strip extending along the first direction X. One end of the transfer electrode E5 may be connected to the active layer IGZO of the third transistor T3 via a via H11, and the other end of the transfer electrode E5 may be connected to the sensing line Sense via a via H5. The transfer electrode E5 may serve as the first electrode of the third transistor T1, enabling the signal provided by the sensing line Sense to be written to the first electrode of the third transistor T1.

[0227] Optionally, since the active layers IGZO of the third transistor T3 of two adjacent sub-pixels in a pixel column in the second direction Y are an integrated structure connected to each other, the two sub-pixels share the active layer IGZO of the third transistor T3, and thus the two sub-pixels can share one switching electrode E5.

[0228] Optionally, the transfer electrodes E5 of the two pixel columns can be interconnected as an integrated structure. The transfer electrodes E5 of the two pixel columns form a connection line for the sensing line Sense. That is, the pixel circuits 10 of the four sub-pixels in a display area A1 can share a connection line for the sensing line Sense, thus realizing a one-to-four sensing line Sense structure in a repeating unit 02. This can reduce the number of signal lines, reduce occupied space, and achieve a simple structure and a reasonable layout, fully utilizing the layout space, improving space utilization, and facilitating improved resolution and transparency.

[0229] Optionally, since the sensing line Sense is arranged between two pixel columns, the sensing line Sense is connected to the third transistors T3 included in the sub-pixels in the two pixel columns through the switching electrode E5, respectively. The third transistors T3 of the two sub-pixels arranged along the first direction X can be symmetrically arranged relative to the sensing line Sense. Therefore, this symmetrical structure can ensure that the delay of writing the sensing signal into the third transistor T3 is basically the same, thereby ensuring display uniformity.

[0230] Optionally, the orthographic projections of the switching electrode E1 and the switching electrode E5 on the substrate 01 may be located within the range of the orthographic projection of the area enclosed by the portion of the scanning line G1 in the ring structure on the substrate 01 .

[0231] Optionally, for the other above-mentioned parts formed by the gate metal layer GT, the position of each pattern in the white sub-pixel P1_W and the position of each pattern in the red sub-pixel P1_R can be basically mirror-symmetrical with respect to the horizontal reference line, the position of each pattern in the green sub-pixel P1_G and the position of each pattern in the blue sub-pixel P1_B can be basically mirror-symmetrical with respect to the horizontal reference line, the position of each pattern in the white sub-pixel P1_W and the position of each pattern in the green sub-pixel P1_G can be basically mirror-symmetrical with respect to the vertical reference line, and the position of each pattern in the red sub-pixel P1_R and the position of each pattern in the blue sub-pixel P1_B can be basically mirror-symmetrical with respect to the vertical reference line.

[0232] (6) Referring to FIG20 , a structural layout of a passivation layer PVX is shown. Referring to FIG21 , a structural layout of a planarization layer Resin is shown. In conjunction with FIG19 , FIG20 , and FIG21 , FIG22 shows a structural layout including a first transparent conductive layer 1ITO, a light shielding layer SHL, an active layer IGZO, a gate insulating layer GI, a gate metal layer GT, a passivation layer PVX, and a planarization layer Resin.

[0233] It can be seen from FIG. 20 to FIG. 22 that the passivation layer PVX can be used to form the first via hole H1 described in the above embodiment, and also used to form the via hole H13 .

[0234] The orthographic projection of the first via H1 on the substrate 01 can overlap with the orthographic projection of the other end of the connecting electrode 202 on the substrate 01 , so as to connect the connecting electrode 202 with the anode portion of the subsequently formed second transparent conductive layer 2ITO serving as the light emitting element 20 .

[0235] The via hole H13 may be located in the light-transmitting area A2 , and the orthographic projection of the via hole H13 on the substrate 01 may overlap with the orthographic projection of the auxiliary electrode F01 on the substrate 01 , so as to connect the auxiliary electrode F01 with the subsequently formed second electrode 203 (ie, the cathode of the light-emitting element 20 ).

[0236] Optionally, the area of ​​the orthographic projection of the via hole H13 on the substrate 01 may be larger than the area of ​​the orthographic projection of the first via hole H1 on the substrate 01 .

[0237] Optionally, the planar layer Resin may have a plurality of planar openings TV, which may be rectangular with grooves or chamfers at the corners. The auxiliary electrode F01 and the portion of the connecting electrode 202 connected to the first electrode 201 of the light-emitting element 20 may be located within the planar openings TV.

[0238] (7) Referring to FIG. 23 , a structural layout of a second transparent conductive layer 2ITO is shown. In conjunction with FIG. 22 and FIG. 23 , FIG. 24 shows a structural layout including a first transparent conductive layer 1ITO, a light shielding layer SHL, an active layer IGZO, a gate insulating layer GI, a gate metal layer GT, a passivation layer PVX, a planarization layer Resin, and a second transparent conductive layer 2ITO.

[0239] 23 to 24 , it can be seen that the second transparent conductive layer 2ITO can be used to form the first electrode 201 of the light emitting element 20, and the first electrode 201 can be the anode of the light emitting element 20. That is, the first electrode 201 and the second transparent conductive layer 2ITO described in the above embodiment can be located in the same layer.

[0240] Optionally, the first electrode 201 may include a first sub-electrode 2011 and a second sub-electrode 2012 spaced apart from each other. The first sub-electrode 2011 and the second sub-electrode 2012 may be rectangular and arranged sequentially along the second direction Y.

[0241] Optionally, the first electrode 201 further includes a C-shaped portion (labeled as C1). This portion C1 can be connected to the first sub-electrode 2011 and the second sub-electrode 2012, respectively, and can be connected to the connecting electrode 202 formed on the gate metal layer GT through the first via H1, thereby achieving mutual connection between the first sub-electrode 2011 and the second sub-electrode 2012. Because this portion C1 is also connected to the connecting electrode 202, and the connecting electrode 202 is connected to the first plate Cst1 of the storage capacitor Cst, the first electrode 201 and the first plate Cst1 have the same potential.

[0242] Optionally, when a bright spot appears on the display substrate, the "C"-shaped portion C1 can be cut off by laser cutting, so that one of the first sub-electrode 2011 and the second sub-electrode 2012 is connected to the first electrode 11, and the other is floating, thereby quickly repairing the bright spot.

[0243] Optionally, the four first electrodes 201 in a repeating unit 02 can be arranged in a square, with the upper left first electrode 201 connected to the pixel circuit 10 in the white sub-pixel P1_W, the upper right first electrode 201 connected to the pixel circuit 10 in the green sub-pixel P1_G, the lower left first electrode 201 connected to the pixel circuit 10 in the red sub-pixel P1_R, and the lower right first electrode 201 connected to the pixel circuit 10 in the blue sub-pixel P1_B. Of course, in some possible implementations, the arrangement of the first electrodes 201 can be adjusted according to actual needs, and this disclosure does not specifically limit this.

[0244] Optionally, the first sub-electrode 2011 , the second sub-electrode 2012 and the “C”-shaped portion C1 may be an integrated structure connected to each other.

[0245] Optionally, the second transparent conductive layer 2ITO can also be used to form another auxiliary electrode F02. The auxiliary electrode F02 can be disposed in the light-transmitting area A2 on one side of the first direction X of the red sub-pixel P1_R and the blue sub-pixel P1_B.

[0246] Optionally, the auxiliary electrode F02 may be rectangular, and the orthographic projection of the auxiliary electrode F02 on the substrate 01 may at least partially overlap with the orthographic projection of the auxiliary electrode F01 on the substrate 01. The auxiliary electrode F02 may be connected to the auxiliary electrode F01 through the via H13, and the auxiliary electrode F02 is used to connect to the second electrode 203 formed subsequently.

[0247] (8) Referring to FIG. 25 , a structural layout diagram of a pixel definition layer (PDL) is shown. In conjunction with FIG. 24 and FIG. 25 , FIG. 26 shows a structural layout diagram including a first transparent conductive layer 1ITO, a light shielding layer SHL, an active layer IGZO, a gate insulating layer GI, a gate metal layer GT, a passivation layer PVX, a planarization layer Resin, a second transparent conductive layer 2ITO, and a pixel definition layer (PDL).

[0248] 25 and 26 , it can be seen that the pixel defining layer PDL may have a first opening K11 and a second opening K12 , and may further have a light-transmitting opening K0 .

[0249] The first opening K11 and the second opening K12 can be provided in the display area A1. The orthographic projection of the first opening K11 on the substrate 01 can overlap with the orthographic projection of the first sub-electrode 2011 in the first electrode 201 on the substrate 01. The orthographic projection of the second opening K12 on the substrate 01 can overlap with the orthographic projection of the second sub-electrode 2012 in the first electrode 201 on the substrate 01. The light-transmitting opening K0 can be provided in the light-transmitting area A2. A groove can be provided on the side of the light-transmitting opening K0 close to the display area A1. The connecting portion between the first electrode 201 and the connecting electrode 202 (i.e., the first via hole H1) can be provided in the groove, so that the pixel defining layer PDL can shield the first via hole H1 to prevent light leakage.

[0250] Optionally, the shapes of the first opening K11 and the second opening K12 may be similar to those of the sub-electrodes.

[0251] It should be noted that, as described in the above embodiment, the display substrate 0 may further include: a light-emitting layer EL and a second electrode 203 (i.e., the cathode of the light-emitting element 20) stacked in sequence along the side of the pixel definition layer PDL away from the substrate 01. Their structural layouts are not shown one by one. Furthermore, the display panel may also include a color filter layer and a black matrix layer.

[0252] Optionally, the substrate 01 may be a flexible substrate 01 or a rigid substrate 01. The rigid substrate may be, but is not limited to, one or more of glass and quartz, and the flexible substrate may be, but is not limited to, one or more of polyethylene terephthalate, polyethylene terephthalate, polyetheretherketone, polystyrene, polycarbonate, polyarylate, polyarylate, polyimide, polyvinyl chloride, polyethylene, and textile fiber.

[0253] Optionally, the flexible substrate 01 may include a first flexible material layer, a first inorganic material layer, an active layer, a second flexible material layer, and a second inorganic material layer stacked in sequence. The materials of the first flexible material layer and the second flexible material layer may be polyimide, polyethylene terephthalate, or a surface-treated polymer soft film, and the materials of the first inorganic material layer and the second inorganic material layer may be silicon nitride or silicon oxide to improve the water and oxygen resistance of the substrate 01.

[0254] Based on the above embodiment, it can be seen that the embodiment of the present disclosure is based on the pixel circuit 10 of the 3T1C architecture, and the anode of the light-emitting element 20 is connected to the first electrode Cst1 of the storage capacitor Cst through the gate metal layer GT. In addition, the first electrode Cst1 is formed by the first transparent conductive layer 1ITO to form a transparent capacitor, realizing top and bottom double-sided light emission, achieving excellent product display. In addition, the light shielding layer SHL is used for vertical wiring, and the gate metal layer GT is used for horizontal wiring, achieving full signal maintainability and high transparency.

[0255] It should be noted that the film materials, shapes, layouts and sizes described in the above embodiments of the present disclosure are only for illustrative purposes.

[0256] In summary, an embodiment of the present disclosure provides a display panel. The display panel includes a substrate, and a plurality of repeating units located on the substrate. The repeating units can be divided into a display area and a light-transmitting area, and include sub-pixels located in the display area, the sub-pixels include mutually coupled pixel circuits and light-emitting elements, and the pixel circuits are used to drive the light-emitting elements to emit light. In addition, the pixel circuit includes a storage capacitor. On the display substrate, the storage capacitor includes a first electrode and a second electrode that overlap each other, and the first electrode can be connected to the first electrode of the light-emitting element through a switching electrode. In addition, the first electrode and the first electrode are both made of transparent conductive material and overlap with the opening of the display area. In this way, under the premise of reliable coupling of each part and ensuring reliable driving of the light-emitting element to emit light, a transparent capacitor design can be used to achieve double-sided light emission, and the display effect is better.

[0257] FIG27 is a method for manufacturing a display panel provided by an embodiment of the present disclosure, which is used to manufacture the display panel described in the above embodiment. The method includes:

[0258] Step 2701: Provide a substrate.

[0259] Step 2702: Form a plurality of repeating units on one side of the substrate to obtain a display substrate.

[0260] Step 2703: Set a cover plate on the opposite side of the display substrate.

[0261] The formed repeating unit is divided into a display area and a light-transmitting area located on at least one side of the display area, and includes multiple sub-pixels located in the display area. The sub-pixels include coupled pixel circuits and light-emitting elements, and the pixel circuit is used to drive the light-emitting elements to emit light.

[0262] Furthermore, the first electrode, the switching electrode, the first electrode, and the second electrode are located in different layers. The material of the first electrode and the material of the first electrode both comprise a transparent conductive material. The display area has at least one opening, and the orthographic projections of the first electrode and the first electrode on the substrate overlap with the orthographic projection of the opening on the substrate.

[0263] That is, as an optional implementation:

[0264] As can be seen from the process flow chart shown in Figures 1 and 28, the formed display substrate 0 may include the following layers: a substrate 01, and a first transparent conductive layer 1ITO, a light shielding layer SHL, an active layer IGZO, a gate insulating layer GI, a gate metal layer GT, a passivation layer PVX, a first color filter layer CF1, a flat layer Resin, a second transparent conductive layer 2ITO, a pixel defining layer PDL, a light emitting layer EL, and a second electrode 203, located between the substrate 01 and the cover plate 1 and stacked sequentially in a direction away from the substrate 01. Figure 28 only schematically illustrates the sequential stacking of the first transparent conductive layer 1ITO to the pixel defining layer PDL.

[0265] Connections can be established between conductive film layers (eg, metal layers) through vias.

[0266] For example, referring to the Connection relationship shown in Figure 28, the gate metal layer GT can establish a connection with the light-shielding layer SHL and the first transparent conductive layer 1ITO respectively through vias penetrating the gate insulating layer GI; the second transparent conductive layer 2ITO can establish a connection with the gate metal layer GT through vias penetrating the passivation layer PVX and the flat layer Resin; and the gate metal layer GT can also establish a connection with the active layer IGZO through vias penetrating the gate insulating layer GI.

[0267] Optionally, in some embodiments, the opening may include: a top-emitting opening and a bottom-emitting opening disposed opposite each other, the top-emitting opening being located on one side of the cover plate, and the bottom-emitting opening being located on one side of the display substrate. The method further includes: forming a reflective electrode on a side of the first electrode away from the substrate.

[0268] The orthographic projection of the formed reflective electrode on the substrate overlaps with the orthographic projection of the bottom emission opening on the substrate, and does not overlap with the orthographic projection of the top emission opening on the substrate.

[0269] That is, as another optional implementation:

[0270] As can be seen from the process flow charts shown in Figures 10 and 29, the display substrate 0 formed includes, in addition to the film layers shown in Figure 28, a reflective electrode 204, also known as a reflective anode, located between the second transparent conductive layer 2ITO and the pixel definition layer PDL. The provision of the reflective anode can enhance the light extraction efficiency of the top emission, ensuring a better display effect.

[0271] Comparing Figures 28 and 29, it can be seen that, with the exception of the first color filter layer CF1, the structure shown in Figure 28 can be fabricated using nine masks for the display substrate. Of course, the passivation layer PVX and the planarization layer Resin can be formed simultaneously using a halftone mask, reducing the number of masks to eight. The structure shown in Figure 29 requires an additional reflective anode fabrication process, allowing the display substrate to be fabricated using nine masks.

[0272] It should be noted that the preparation method of each film layer can adopt the patterning process described in the above embodiment, which will not be described in detail here.

[0273] In summary, the embodiments of the present disclosure provide a method for preparing a display panel. The prepared display panel includes a substrate, and a plurality of repeating units located on the substrate. The repeating units can be divided into a display area and a light-transmitting area, and include sub-pixels located in the display area, and the sub-pixels include mutually coupled pixel circuits and light-emitting elements, and the pixel circuits are used to drive the light-emitting elements to emit light. In addition, the pixel circuit includes a storage capacitor. On the display substrate, the storage capacitor includes a first electrode and a second electrode that overlap with each other, and the first electrode can be connected to the first electrode of the light-emitting element through a switching electrode. In addition, the first electrode and the first electrode are both made of transparent conductive material and overlap with the opening of the display area. In this way, under the premise of reliable coupling of the various parts and ensuring reliable driving of the light-emitting element to emit light, a transparent capacitor design can be used to achieve double-sided light emission, and the display effect is better.

[0274] Figure 30 is a schematic diagram of the structure of a display device provided by an embodiment of the present disclosure. As shown in Figure 30, the display device includes: a power supply component and a display panel as described in the above embodiment.

[0275] The power supply component is connected to the display panel and is used to supply power to the display panel.

[0276] Since the display device can have substantially the same technical effects as the display panel described in the previous embodiment, for the purpose of brevity, the display device and the technical effects will not be repeatedly described here.

[0277] Optionally, the display device may be an organic light emitting diode (OLED) display device, a QLED display device, or an active-matrix organic light emitting diode (AMOLED) display device.

[0278] Optionally, the display device may include any product or component with a display function, such as a mobile phone, a tablet computer, a television, a monitor, a laptop computer, a digital photo frame, a navigator, etc., but the embodiments of the present disclosure are not limited thereto.

[0279] With the continuous development of display technology, OLED technology is increasingly used in transparent displays. Transparent display is an important personalized display field of display technology. It refers to the display of images in a transparent state. The viewer can not only see the image in the display device, but also the scene behind the display device, which can realize virtual reality (VR) and augmented reality (AR) and 3D display functions. A transparent display device using OLED technology usually divides each sub-pixel into a display area and a light-transmitting area. The display area is provided with a pixel circuit 10 and a light-emitting device to realize image display, and the light-transmitting area realizes light transmission, which can be adapted to the display panel recorded in the embodiment of the present disclosure.

[0280] It should be noted that the terms used in the examples of this disclosure are only used to explain the examples and are not intended to limit the present disclosure. Unless otherwise defined, technical terms or scientific terms used in the embodiments of this disclosure should have the common meanings understood by people with ordinary skills in the field to which this disclosure belongs.

[0281] For example, the words "first", "second" or "third" and similar words used in the patent application specification and claims of this disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components.

[0282] Likewise, the words “a” or “an” and the like do not denote a limitation of quantity, but rather denote the presence of at least one.

[0283] Words such as “include” or “comprising” mean that the elements or objects preceding “include” or “comprising” include the elements or objects listed after “include” or “comprising” and their equivalents, and do not exclude other elements or objects.

[0284] For convenience, words and phrases indicating orientation or positional relationships, such as "middle," "upper," "lower," "front," "back," "vertical," "horizontal," "top," "bottom," "inside," and "outside," are used to illustrate the positional relationships of components with reference to the accompanying drawings. This is merely to facilitate the description of this specification and simplify the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed, or operate in a specific orientation. Therefore, they should not be construed as limitations on the present disclosure. The positional relationships of the components may be appropriately changed depending on the direction in which the components are described. Therefore, the terms and phrases described in the specification are not limited and may be appropriately replaced as appropriate.

[0285] The scales of the figures in this disclosure can be used as a reference for actual processes, but are not limited to such. For example, the width-to-length ratio of the channel, the thickness and spacing of the various film layers, and the width and spacing of the various signal lines can be adjusted according to actual needs. The number of pixels in the display substrate and the number of sub-pixels in each pixel are not limited to the numbers shown in the figures. The figures described in this disclosure are merely schematic structural diagrams, and one embodiment of this disclosure is not limited to the shapes or values ​​shown in the figures.

[0286] In the embodiments of this disclosure, unless otherwise expressly specified or limited, the terms "mounted," "connected," and "connected" should be interpreted broadly. For example, they can refer to fixed connections, removable connections, or integral connections; mechanical connections, or electrical connections; direct connections, indirect connections through intermediaries, or internal communication between two components. Those skilled in the art will understand the specific meanings of these terms in this disclosure based on the specific circumstances.

[0287] In the embodiments of the present disclosure, a transistor refers to an element comprising at least three terminals: a gate electrode, a drain electrode, and a source electrode. The transistor has a channel region between a drain electrode (drain electrode terminal, drain region, or drain electrode) and a source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. Note that in this specification, the channel region refers to the region through which current primarily flows.

[0288] In the embodiments of the present disclosure, the first electrode can be a drain electrode and the second electrode can be a source electrode, or the first electrode can be a source electrode and the second electrode can be a drain electrode. In cases where transistors with opposite polarities are used or where the direction of current changes during circuit operation, the functions of the "source electrode" and "drain electrode" are sometimes interchangeable. Therefore, in this specification, "source electrode" and "drain electrode" can be interchanged, and "source terminal" and "drain terminal" can be interchanged.

[0289] In the embodiments of the present disclosure, "electrical connection" includes the connection of components via an element having some electrical function. There are no particular limitations on the "element having some electrical function" as long as it enables the transfer of electrical signals between the connected components. Examples of "element having some electrical function" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other elements having various functions.

[0290] In the embodiments of the present disclosure, "parallel" refers to a state where the angle formed by two straight lines is greater than -10° and less than 10°, and thus also includes a state where the angle is greater than -5° and less than 5°. Furthermore, "perpendicular" refers to a state where the angle formed by two straight lines is greater than 80° and less than 100°, and thus also includes a state where the angle is greater than 85° and less than 95°.

[0291] In the embodiments of the present disclosure, the terms "film" and "layer" may be interchanged. For example, "conductive layer" may be replaced with "conductive film." Similarly, "insulating film" may be replaced with "insulating layer."

[0292] In the embodiments of the present disclosure, triangles, rectangles, trapezoids, pentagons or hexagons are not in the strict sense, but may be approximate triangles, rectangles, trapezoids, pentagons or hexagons, etc. There may be some small deformations caused by tolerances, and there may be chamfers, arc edges and deformations.

[0293] In the embodiments of the present disclosure, “about” means that the limit is not strictly defined and a numerical value within the range of process and measurement errors is allowed.

[0294] The above description is merely an optional embodiment of the present disclosure and is not intended to limit the present disclosure. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of the present disclosure shall be included in the scope of protection of the present disclosure.

Claims

1. A display panel, comprising: A display substrate and a cover plate arranged opposite to each other; The display substrate comprises: substrate; A plurality of repeating units located on the substrate, the repeating units are divided into a display area and a light-transmitting area located on at least one side of the display area, and include a plurality of sub-pixels located in the display area, the sub-pixels include coupled pixel circuits and light-emitting elements, and the pixel circuit is used to drive the light-emitting elements to emit light; Wherein, the pixel circuit includes a storage capacitor, and the storage capacitor includes a first plate and a second plate whose orthographic projections overlap on the substrate; the light-emitting element includes a first electrode; and the first electrode is connected to the first plate via a switching electrode; Furthermore, the first electrode, the switching electrode, the first electrode and the second electrode are located in different layers; the material of the first electrode and the material of the first electrode both include transparent conductive materials; the display area has at least one opening, and the orthographic projection of the first electrode on the substrate and the orthographic projection of the first electrode on the substrate both overlap with the orthographic projection of the opening on the substrate.

2. The display panel according to claim 1, wherein: The display area has a first opening and a second opening spaced apart from each other; The first electrode comprises: a first sub-electrode and a second sub-electrode located in the same layer and spaced apart from each other, the first sub-electrode being connected to the first electrode plate via the switching electrode; Among them, the orthographic projection of the first sub-electrode on the substrate overlaps with the orthographic projection of the first opening on the substrate, the orthographic projection of the first electrode on the substrate and the orthographic projection of the second sub-electrode on the substrate both overlap with the orthographic projection of the second opening on the substrate, and the orthographic projection of the switching electrode on the substrate is located within the orthographic projection of the interval position between the first opening and the second opening on the substrate.

3. The display panel according to claim 2, wherein: The orthographic projection of the first sub-electrode on the substrate does not overlap with the orthographic projections of the first electrode plate and the second electrode plate on the substrate; the orthographic projection of the second sub-electrode on the substrate overlaps with the orthographic projections of the first electrode plate and the second electrode plate on the substrate.

4. The display panel according to claim 2, wherein: The display substrate further comprises: a pixel defining layer located on a side of the first electrode away from the substrate; The pixel defining layer is used to define the first opening and the second opening.

5. The display panel according to claim 4, wherein: The display panel further comprises: a black matrix layer located on a side of the cover plate close to the display substrate; The orthographic projection of the black matrix layer on the substrate is located within the orthographic projection of the pixel defining layer on the substrate.

6. The display panel according to any one of claims 1 to 5, wherein: The opening comprises: a top emission opening and a bottom emission opening which are arranged opposite to each other, wherein the top emission opening is located at one side of the cover plate, and the bottom emission opening is located at one side of the display substrate; The display substrate further comprises: a reflective electrode located on a side of the first electrode away from the substrate; The orthographic projection of the reflective electrode on the substrate overlaps with the orthographic projection of the bottom-emitting opening on the substrate, and does not overlap with the orthographic projection of the top-emitting opening on the substrate.

7. The display panel according to claim 6, wherein: The reflective electrode is located between the first electrode and a pixel defining layer included in the display substrate.

8. The display panel according to any one of claims 1 to 7, wherein: The display substrate further comprises: a first transparent conductive layer, an active layer, a gate metal layer, and a second transparent conductive layer stacked in sequence in a direction away from the substrate; Among them, the first electrode plate and the first transparent conductive layer are located in the same layer; the switching electrode and the gate metal layer are located in the same layer; the first electrode and the second transparent conductive layer are located in the same layer; the second electrode plate and the active layer are located in the same layer.

9. The display panel according to claim 8, wherein: The display substrate further comprises: a light-emitting layer and a second electrode which are located between the first electrode and the cover plate and are sequentially stacked in a direction away from the substrate, wherein the material of the second electrode comprises a transparent conductive material; The display substrate includes a pixel defining layer located between the light emitting layer and the first electrode.

10. The display panel according to claim 9, wherein: The material of the first transparent conductive layer and the material of the second transparent conductive layer both include: indium tin oxide; the material of the second electrode includes: indium zinc oxide; and the material of the active layer includes: indium gallium zinc oxide.

11. The display panel according to claim 8, wherein: The display substrate further includes: a buffer layer and a gate insulating layer located between the first transparent conductive layer and the gate metal layer and sequentially stacked in a direction away from the substrate; and, a passivation layer and a planarization layer located between the gate metal layer and the second transparent conductive layer and sequentially stacked in a direction away from the substrate; The first electrode is connected to the switching electrode through a first via hole penetrating the passivation layer and the planar layer; the switching electrode is connected to the first electrode plate through a second via hole penetrating the gate insulating layer and the buffer layer.

12. The display panel according to claim 11, wherein: The orthographic projection of the first via hole on the substrate does not overlap with the orthographic projection of the second via hole on the substrate; An area of ​​an orthographic projection of the first via hole on the substrate is greater than an area of ​​an orthographic projection of the second via hole on the substrate.

13. The display panel according to claim 11, wherein: The orthographic projection of the first via hole on the substrate and the orthographic projection of the second via hole on the substrate are both located within the orthographic projection of the interval between the first opening and the second opening of the display area on the substrate.

14. The display panel according to claim 11, wherein: The display substrate further comprises: a metal light shielding layer located between the substrate and the buffer layer; The pixel circuit is also connected to a plurality of signal lines, and the pixel circuit is used to drive the light-emitting element to emit light in response to signals provided by the plurality of signal lines; The plurality of signal lines include: a first power line, a second power line, a scan line, a data line and a sensing line; and the scan line extends along a first direction and is located at the same layer as the gate metal layer; The first power line, the second power line, the data line and the sensing line all extend along a second direction and are located in the same layer as the metal light shielding layer; the first direction intersects with the second direction.

15. The display panel according to claim 14, wherein: The gate metal layer is also connected to the metal light shielding layer, the first transparent conductive layer and the active layer respectively through via holes penetrating the gate insulating layer.

16. The display panel according to any one of claims 1 to 15, wherein: The display panel further comprises: a first color filter layer located on a side of the cover plate close to the display substrate; The display substrate further comprises: a second color filter layer located on a side of the first electrode close to the substrate; The orthographic projection of the first color filter layer on the substrate and the orthographic projection of the second color filter layer on the substrate both overlap with the orthographic projection of the opening on the substrate.

17. The display panel according to claim 16, wherein: The second color filter layer is located between the passivation layer and the planarization layer included in the display substrate.

18. A method for preparing a display panel, for preparing the display panel according to any one of claims 1 to 17; the method comprising: providing a substrate; forming a plurality of repeating units on one side of the substrate to obtain a display substrate; Disposing a cover plate on the opposite side of the display substrate; The formed repeating unit is divided into a display area and a light-transmitting area located on at least one side of the display area, and includes a plurality of sub-pixels located in the display area, the sub-pixels include a coupled pixel circuit and a light-emitting element, and the pixel circuit is used to drive the light-emitting element to emit light; Furthermore, the first electrode, the switching electrode, the first electrode and the second electrode are located in different layers; the material of the first electrode and the material of the first electrode both include transparent conductive materials; the display area has at least one opening, and the orthographic projection of the first electrode on the substrate and the orthographic projection of the first electrode on the substrate both overlap with the orthographic projection of the opening on the substrate.

19. The method according to claim 18, wherein: The opening comprises: a top emission opening and a bottom emission opening which are arranged opposite to each other, the top emission opening is located at one side of the cover plate, and the bottom emission opening is located at one side of the display substrate; the method further comprises: forming a reflective electrode on a side of the first electrode away from the substrate; The orthographic projection of the formed reflective electrode on the substrate overlaps with the orthographic projection of the bottom emission opening on the substrate, and does not overlap with the orthographic projection of the top emission opening on the substrate.

20. A display device, comprising: A power supply component, and a display panel as claimed in any one of claims 1 to 17; Wherein, the power supply component is connected to the display panel and is used to supply power to the display panel.

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