Dynamic characteristic test circuit suitable for quick response capacitive sensor

Abstract

The invention discloses a dynamic characteristic test circuit suitable for a quick response capacitive sensor, which comprises a reference capacitor, a capacitive sensor, a sampling capacitor, a voltage-controlled switch, an operational amplifier, a first square wave input signal and a second square wave input signal, the common end of the comparator is connected with the positive input end of the operational amplifier, the negative input end of the operational amplifier is connected with the output end of the operational amplifier and is connected with the Vo2 end of the voltage-controlled switch, and the Vout end of the voltage-controlled switch is connected with the sampling capacitor; the first square wave input signal is input into the reference capacitor, the second square wave input signal is used for controlling the connection or disconnection of the voltage-controlled switch, the two square wave input signals are two-phase non-overlapping clock signals, and the dynamic characteristic test of the capacitive sensor is realized by controlling the level jump time of the two square wave input signals. According to the invention, the dynamic characteristic test circuit requirement of the rapid response capacitive sensor can be met.

Description

Technical Field

[0001] The present invention belongs to the field of microelectromechanical systems (MEMS), and relates to a dynamic characteristic test circuit applicable to a fast-response capacitive sensor. Background Art

[0002] A capacitive sensor is a device that detects physical quantities based on the principle of capacitance change, and is widely used in fields such as displacement, pressure, humidity, proximity sensing, etc. With the development of industrial automation, intelligent terminals, and Internet of Things technologies, higher requirements are put forward for the response speed of capacitive sensors.

[0003] For capacitive sensors, the performance of capacitive sensors is mainly measured from aspects such as the response speed, sensitivity, and stability of the sensors. For fast-response capacitive sensors, special attention needs to be paid to the dynamic characteristics of the sensors. Since fast-response capacitive sensors generally have a response speed in the millisecond order or even the microsecond order, traditional dynamic test systems cannot correctly measure the dynamic characteristics of capacitive sensors. Therefore, it is necessary to additionally build a dynamic characteristic test system applicable to fast-response capacitive sensors, and the dynamic characteristic test circuit applicable to fast-response capacitive sensors is a key component.

[0004] In existing dynamic characteristic test systems for fast-response capacitive sensors, people use an LCR meter to read out rapidly changing capacitance values. However, the fastest speed of the LCR meter to read capacitance values is generally once every ten-odd milliseconds. If the LCR meter is used to test the dynamic characteristics of a capacitive sensor with a response time in the millisecond order or even the microsecond order, the measured response time will have errors. Therefore, it is necessary to design a dynamic characteristic test circuit that can meet the dynamic characteristic test requirements of fast-response capacitive sensors. Summary of the Invention

[0005] Object of the Invention: The object of the present invention is to propose a dynamic characteristic test circuit applicable to a fast-response capacitive sensor, which meets the dynamic characteristic test requirements of a fast-response capacitive sensor with a response speed in the millisecond order or even the microsecond order.

[0006] Technical solution: The present invention provides a dynamic characteristic test circuit applicable to a fast-response capacitive sensor, including: a reference capacitor Cr, a capacitive sensor S, a sampling capacitor Cs, a voltage-controlled switch S1, an operational amplifier OP1, a first square-wave input signal V1, and a second square-wave input signal V2. The reference capacitor Cr and the capacitive sensor S are connected in series, and their common terminal Vo1 is connected to the positive input terminal of the operational amplifier OP1. The negative input terminal of the operational amplifier OP1 is connected to its output terminal and is connected to the Vo2 terminal of the voltage-controlled switch S1. The voltage-controlled switch S1 is connected to the sampling capacitor Cs, and their common terminal is Vout. The C terminal of the sampling capacitor Cs is connected to the ground potential GND. The first square-wave input signal V1 is input to the reference capacitor Cr, and the second square-wave input signal V2 is used to control the on or off state of the voltage-controlled switch S1. The first square-wave input signal V1 and the second square-wave input signal V2 are two-phase non-overlapping clock signals. By controlling the level transition times of the first square-wave input signal V1 and the second square-wave input signal V2, the dynamic characteristics test of the capacitive sensor S is realized.

[0007] Optionally, the second square-wave input signal V2 is used to control the on or off state of the voltage-controlled switch S1, including: when the second square-wave input signal V2 is at the high level VDD, the voltage-controlled switch S1 is turned on; when the second square-wave input signal V2 is at the low level GND, the voltage-controlled switch S1 is turned off.

[0008] Optionally, the first square-wave input signal V1 and the second square-wave input signal V2 are two-phase non-overlapping clock signals. The specific phase information is: the time when the first square-wave input signal V1 rises from the low level GND to the high level VDD is earlier than that of the second square-wave input signal V2, and the time when the first square-wave input signal V1 falls from the high level VDD to the low level GND is later than that of the second square-wave input signal V2. Through the level transition times of these two square-wave input signals, the circuit includes four working states within one working cycle, corresponding to four time periods respectively.

[0009] Optionally, the four working states of the circuit within one working cycle include:

[0010] Working state 1: When the first square-wave input signal V1 is at the high level VDD and the second square-wave input signal V2 is at the low level GND, the voltage value Uout at the Vout terminal remains constant at the signal Uout collected in the previous working cycle.

[0011] Operating state 2: When the first square-wave input signal V1 is at the high level VDD and the second square-wave input signal V2 is at the high level VDD, the signal U1 output at the common terminal Vo1 changes correspondingly with the change of the capacitance value C of the capacitive sensor S. After this signal U1 passes through the operational amplifier OP1, a signal U2 that changes following U1 is generated, and the output voltage value Uout at the Vout terminal changes following the voltage value of U2.

[0012] Operating state 3: When the first square-wave input signal V1 is at the high level VDD and the second square-wave input signal V2 is at the low level GND, the output voltage Uout at the Vout terminal is constant and remains at the voltage value Uout at the Vout terminal collected at the moment when the second square-wave input signal V2 switches to the low level GND.

[0013] Operating state 4: When the first square-wave input signal V1 is at the low level GND and the second square-wave input signal V2 is at the low level GND, the output voltage Uout at the Vout terminal is constant and remains at the voltage value Uout at the Vout terminal collected at the moment when the second square-wave input signal V2 switches to the low level GND.

[0014] Optionally, in operating state 2, the expression of the signal U1 output at the common terminal Vo1 is:

[0015]

[0016] where U1 is the voltage output at the common terminal Vo1 during the time period T2, C1 is the capacitance value of the reference capacitor Cr, and C2 is the capacitance value of the capacitive sensor S.

[0017] The expression of Uout is:

[0018] Uout = U1.

[0019] The present invention also provides a test method based on the dynamic characteristic test circuit applicable to a fast-response capacitive sensor, including the following steps:

[0020] S1. Circuit initialization, setting the clock periods of the first square-wave input signal V1 and the second square-wave input signal V2, and the time when the first square-wave input signal V1 rises from the low level GND to the high level VDD is earlier than that of the second square-wave input signal V2, and the time when the first square-wave input signal V1 drops from the high level VDD to the low level GND is later than that of the second square-wave input signal V2.

[0021] S2. Divide one working cycle of the circuit into four time periods according to the clock cycles of the first square-wave input signal V1 and the second square-wave input signal V2, which are respectively: T1 time period: the first square-wave input signal V1 is at high level VDD and the second square-wave input signal V2 is at low level GND; T2 time period: both the first square-wave input signal V1 and the second square-wave input signal V2 are at high level VDD; T3 time period: the first square-wave input signal V1 is at high level VDD and the second square-wave input signal V2 is at low level GND; T4 time period: the first square-wave input signal V1 is at low level GND and the second square-wave input signal V2 is at low level GND;

[0022] S3. Generate the output voltage Uout at the Vout terminal within the T2 time period through these four time periods T1, T2, T3, and T4, so as to realize the dynamic characteristic test of the fast-response capacitive sensor within one working cycle of the circuit;

[0023] S4. Repeat steps S2 to S3. When the next working cycle arrives, the output voltage value Uout sampled at the Vout terminal will be updated again, thereby realizing the dynamic characteristic test of the fast-response capacitive sensor.

[0024] Further, within the T1 time period described in step S2, a useful signal U1 is output at the common terminal Vo1, and the voltage value Uout at the Vout terminal remains constant as the useful signal collected in the previous working cycle. This is the first working state;

[0025] Within the T2 time period, the signal U1 output at the common terminal Vo1 changes correspondingly with the change of the capacitance value C of the capacitive sensor S. After this signal U1 passes through the operational amplifier OP1, a signal U2 that changes following U1 is generated, and the output voltage Uout at the Vout terminal changes following the voltage value of U2. This is the second working state;

[0026] Within the T3 time period, useful signals are still output at the common terminal Vo1 and the Vo2 terminal, but the output voltage Uout at the Vout terminal no longer changes following the voltage value U1 at the Vo1 terminal. The output voltage Uout at the Vout terminal is constant and remains the voltage value Uout at the Vout terminal collected at the moment when the second square-wave input signal V2 switches to low level GND. This is the third working state;

[0027] Within the T4 time period, the voltage values at the common terminals Vo1 and Vo2 are both at ground potential GND, and the output voltage Uout at the Vout terminal is still constant and remains the voltage value Uout at the Vout terminal collected at the moment when the second square-wave input signal V2 switches to low level GND. This is the fourth working state.

[0028] Further, the expression of the signal U1 within the T2 time period is:

[0029]

[0030] Among them, U1 is the voltage output at the common terminal Vo1 during the time period T2, C1 is the capacitance value of the reference capacitor Cr, and C2 is the capacitance value of the capacitive sensor S;

[0031] The expression of Uout is:

[0032] Uout = U1.

[0033] The present invention also provides an electronic device, including a memory and a processor, wherein:

[0034] The memory is used to store a computer program that can run on the processor;

[0035] The processor is used to execute the steps of the test method when running the computer program.

[0036] The present invention also provides a storage medium, on which a computer program is stored, and when the computer program is executed by at least one processor, the steps of the test method are implemented.

[0037] Beneficial effects: Compared with the prior art, the significant technical effect of the present invention is that: four working states constitute a working cycle of the dynamic characteristic test circuit of the fast-response capacitive sensor. By the next working cycle, the sampled output voltage value will be updated again; therefore, as long as the signal frequency of the square-wave input signal of the dynamic characteristic test circuit is greater than 10 times the reciprocal of the response time of the fast-response capacitive sensor and above, by observing the waveform change of the output voltage value Uout at the Vout terminal using an oscilloscope, the response time of the fast-response capacitive sensor can be obtained according to the time required for the waveform to change from the valley value to the peak value. Therefore, the dynamic characteristic test circuit of the present invention can meet the requirements of the dynamic characteristic test circuit of the fast-response capacitive sensor. Description of the Drawings

[0038] Figure 1 It is a schematic diagram of the overall circuit structure of the present invention;

[0039] Figure 2 It is a waveform schematic diagram of a two-phase non-overlapping clock signal, wherein (a) is a waveform schematic diagram of the first square-wave input signal V1, and (b) is a waveform schematic diagram of the second square-wave input signal V1;

[0040] Figure 3Schematic diagram of waveforms at key nodes of the circuit according to the present invention. Among them, (a) is a schematic diagram of the waveform of the first square-wave input signal V1, (b) is a schematic diagram of the waveform of the second square-wave input signal V2, (c) is a schematic diagram of the change in the capacitance value of the capacitive sensor S, (d) is a schematic diagram of the waveforms of the voltages at nodes Vo1 and Vo2, and (e) is a schematic diagram of the waveform of the voltage at Vout;

[0041] In the figure: the first square-wave input signal V1, the second square-wave input signal V2, the voltage-controlled switch S1, the reference capacitor Cr, the capacitive sensor S, the sampling capacitor Cs, the operational amplifier OP1, the node Vo1, the node Vo2, the node Vout, the node A, the node B, the node C, the node D, the node E. Detailed implementation manners

[0042] The present invention will be described in detail below with reference to the accompanying drawings and specific embodiments. It should be noted that the accompanying drawings are in a very simplified form and not to precise scale, and are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present invention.

[0043] As Figure 1 shown, the dynamic characteristic test circuit applicable to a fast-response capacitive sensor according to the present invention includes a reference capacitor Cr, a capacitive sensor S, a sampling capacitor Cs, a voltage-controlled switch S1, an operational amplifier OP1, a first square-wave input signal V1, and a second square-wave input signal V2; the B terminal of the reference capacitor Cr is connected to the first square-wave input signal V1, the A terminal of the capacitive sensor S is connected to the ground potential GND, the reference capacitor Cr and the capacitive sensor S are connected in series and their common terminal Vo1 is connected to the positive input terminal of the operational amplifier OP1, the negative input terminal of the operational amplifier OP1 is connected to its output terminal and is connected to the Vo2 terminal of the voltage-controlled switch S1, and the voltage-controlled switch S1 is controlled by the second square-wave input signal V2 for its on / off state. When the second square-wave input signal V2 is at the high level VDD, the voltage-controlled switch S1 is turned on, and when the second square-wave input signal V2 is at the low level GND, the voltage-controlled switch S1 is turned off. The voltage-controlled switch S1 is connected to the sampling capacitor Cs and their common terminal is Vout, the C terminal of the sampling capacitor Cs is connected to the ground potential GND, the A terminal of the capacitive sensor S is connected to the ground potential GND, the D terminal of the first square-wave input signal V1 is connected to the ground potential GND, and the E terminal of the second square-wave input signal V2 is connected to the ground potential GND.

[0044] As Figure 2As shown in (a) and (b), the first square-wave input signal V1 and the second square-wave input signal V2 are two-phase non-overlapping clock signals. The specific phase information is as follows: The first square-wave input signal V1 rises from the low level GND to the high level VDD earlier than the second square-wave input signal V2, and the first square-wave input signal V1 drops from the high level VDD to the low level GND later than the second square-wave input signal V2. Through these two square-wave signals, the circuit can generate four working states. In Figure 2 the four working states of the circuit are represented by time periods T1, T2, T3, and T4 respectively.

[0045] Please continue to refer to Figure 1 and Figure 3 In (a) to (e), when the first square-wave input signal V1 is at the high level VDD and the second square-wave input signal V2 is at the low level GND, the signal U1 is output at the common terminal Vo1. However, since the voltage-controlled switch S1 is open at this time, the voltage value Uout at the Vout terminal remains constant at the signal Uout collected in the previous working cycle. This is the first working state, which is represented by the time period T1 in Figure 2 .

[0046] When the first square-wave input signal V1 is at the high level VDD and the second square-wave input signal V2 is at the high level VDD, the signal U1 is output at the common terminal Vo1. The expression of U1 is:

[0047]

[0048] where U1 is the voltage value output at the common terminal Vo1 during the time period T2, C1 is the capacitance value of the reference capacitor Cr, and C2 is the capacitance value of the capacitive sensor S.

[0049] When the capacitance value C2 of the capacitive sensor S changes during this time period, the output signal U1 at the common terminal Vo1 also changes accordingly. At this time, the signal U1 passes through the operational amplifier OP1 in the unity-gain form and generates the same signal U2 that follows the change of U1. At this time, since the second square-wave input signal V2 is at the high level VDD, the voltage-controlled switch S1 is turned on, and the output voltage Uout at the Vout terminal follows the voltage value of U2. The expression of Uout is:

[0050] Uout = U1 (2)

[0051] This is the second working state, which is represented by the time period T2 in Figure 2 .

[0052] When the first square-wave input signal V1 is at the high level VDD and the second square-wave input signal V2 is at the low level GND, although the voltage values output at the common terminal Vo1 and the Vo2 terminal are still U1, since the second square-wave input signal V2 is at the low level GND, the voltage-controlled switch S1 is turned off, and the output voltage Uout at the Vout terminal no longer changes following the voltage value at the Vo2 terminal. The output voltage Uout at the Vout terminal is constant and remains the voltage value Uout at the Vout terminal collected at the moment when the second square-wave input signal V2 switches to the low level GND. This is the third working state, which is represented by Figure 2 the T3 time period in

[0053] When the first square-wave input signal V1 is at the low level GND and the second square-wave input signal V2 is at the low level GND, at this time, the voltage values at the common terminal Vo1 and the Vo2 terminal are both the ground potential GND. The output voltage Uout at the Vout terminal is still constant and remains the voltage value Uout at the Vout terminal collected at the moment when the second square-wave input signal V2 switches to the low level GND. This is the fourth working state, which is represented by Figure 2 the T4 time period in

[0054] These four working states constitute a working cycle of the dynamic characteristic test circuit of the fast-response capacitive sensor. By the next working cycle, the output voltage value Uout sampled at the Vout terminal will be updated again. Therefore, as long as the signal frequency of the square-wave input signal of the dynamic characteristic test circuit is greater than 10 times the reciprocal of the response time of the fast-response capacitive sensor and above, by observing the waveform change of the output voltage value Uout at the Vout terminal using an oscilloscope, the response time of the fast-response capacitive sensor can be obtained according to the time required for the waveform to change from the valley value to the peak value. Therefore, the dynamic characteristic test circuit of the present invention can meet the requirements of the dynamic characteristic test circuit of the fast-response capacitive sensor.

[0055] In the circuit of the present invention, when the reference capacitor and the capacitive sensor receive a high-level square-wave input signal V1, they perform certain mathematical operations to generate a voltage value U1. The voltage signal U2 that varies with U1 is obtained through an operational amplifier in unity-gain form. Finally, the conduction and disconnection states of the switch are controlled by the square-wave input signal V2 to determine whether to sample the voltage value U2 to the output terminal Vout, and it is ensured that the voltage value Uout at Vout is not affected by the voltage fluctuation of the previous-stage circuit when the switch is off until the next sampling working cycle arrives. Therefore, as long as the signal frequency of the square-wave input signal of this dynamic characteristic test circuit is greater than 10 times the reciprocal of the response time of the fast-response capacitive sensor or more, by observing the waveform change of the output voltage value Uout at the Vout terminal using an oscilloscope, the response time of the fast-response capacitive sensor can be obtained based on the time required for the waveform to change from the valley value to the peak value. Therefore, the dynamic characteristic test circuit of the present invention can meet the requirements of the dynamic characteristic test circuit for the fast-response capacitive sensor.

[0056] The present invention also provides a test method based on the above-described dynamic characteristic test circuit applicable to a fast-response capacitive sensor, including the following steps:

[0057] S1. Circuit initialization, setting the clock periods of the first square-wave input signal V1 and the second square-wave input signal V2, and the time when the first square-wave input signal V1 rises from the low level GND to the high level VDD is earlier than that of the second square-wave input signal V2, and the time when the first square-wave input signal V1 falls from the high level VDD to the low level GND is later than that of the second square-wave input signal V2;

[0058] S2. Divide one working cycle of the circuit into four time periods according to the clock periods of the first square-wave input signal V1 and the second square-wave input signal V2, which are: T1 time period: the first square-wave input signal V1 is at the high level VDD and the second square-wave input signal V2 is at the low level GND; T2 time period: both the first square-wave input signal V1 and the second square-wave input signal V2 are at the high level VDD; T3 time period: the first square-wave input signal V1 is at the high level VDD and the second square-wave input signal V2 is at the low level GND; T4 time period: the first square-wave input signal V1 is at the low level GND and the second square-wave input signal V2 is at the low level GND;

[0059] S3. Generate the output voltage Uout at the Vout terminal during the T2 time period through these four time periods T1, T2, T3, and T4 to achieve the dynamic characteristic test of the fast-response capacitive sensor within one working cycle of the circuit;

[0060] S4. Repeat steps S2 to S3. By the next working cycle, the output voltage value Uout sampled at the Vout terminal will be updated again, thereby realizing the dynamic characteristic test of the fast-response capacitive sensor.

[0061] The present invention also provides an electronic device, including a memory and a processor, wherein:

[0062] The memory is used to store a computer program that can run on the processor;

[0063] The processor is used to execute the steps of the test method when running the computer program.

[0064] The present invention also provides a storage medium, on which a computer program is stored. When the computer program is executed by at least one processor, the steps of the test method are realized.

[0065] The above are only the preferred embodiments of the present invention and do not limit the scope of the present invention in any way. It should be pointed out that for those of ordinary skill in the art in the technical field, without departing from the principle of the present invention, several improvements and refinements can be made according to the above disclosure, and these improvements and refinements are all within the protection scope of the claims.

Claims

1. A dynamic characteristic test circuit applicable to a fast-response capacitive sensor, characterized in that, Including: A reference capacitor Cr, a capacitive sensor S, a sampling capacitor Cs, a voltage-controlled switch S1, an operational amplifier OP1, a first square-wave input signal V1, and a second square-wave input signal V2. The reference capacitor Cr and the capacitive sensor S are connected in series, and their common terminal Vo1 is connected to the positive input terminal of the operational amplifier OP1. The negative input terminal of the operational amplifier OP1 is connected to its output terminal and is also connected to the Vo2 terminal of the voltage-controlled switch S1. The voltage-controlled switch S1 is connected to the sampling capacitor Cs, and their common terminal is Vout. The C terminal of the sampling capacitor Cs is connected to the ground potential GND. The first square-wave input signal V1 is input to the reference capacitor Cr, and the second square-wave input signal V2 is used to control the on or off state of the voltage-controlled switch S1. The first square-wave input signal V1 and the second square-wave input signal V2 are two-phase non-overlapping clock signals. By controlling the level transition times of the first square-wave input signal V1 and the second square-wave input signal V2, the dynamic characteristics test of the capacitive sensor S is realized.

2. The dynamic characteristic test circuit for a fast-response capacitive sensor according to claim 1, characterized in that The second square-wave input signal V2 is used to control the on or off state of the voltage-controlled switch S1, including: when the second square-wave input signal V2 is at the high level VDD, the voltage-controlled switch S1 is turned on; when the second square-wave input signal V2 is at the low level GND, the voltage-controlled switch S1 is turned off.

3. The dynamic characteristic test circuit for a fast-response capacitive sensor according to claim 1, characterized in that, The first square-wave input signal V1 and the second square-wave input signal V2 are two-phase non-overlapping clock signals. The specific phase information is: the time when the first square-wave input signal V1 rises from the low level GND to the high level VDD is earlier than that of the second square-wave input signal V2, and the time when the first square-wave input signal V1 falls from the high level VDD to the low level GND is later than that of the second square-wave input signal V2. Through the level transition times of these two square-wave input signals, the circuit includes four working states within one working cycle, corresponding to four time periods respectively.

4. The dynamic characteristic test circuit for a fast response capacitive sensor according to claim 3, wherein The four working states of the circuit within one working cycle include: Working state one: when the first square-wave input signal V1 is at the high level VDD and the second square-wave input signal V2 is at the low level GND, the voltage value Uout at the Vout terminal remains constant at the signal Uout collected in the previous working cycle. Working state two: when the first square-wave input signal V1 is at the high level VDD and the second square-wave input signal V2 is at the high level VDD, the signal U1 output at the common terminal Vo1 changes correspondingly with the change of the capacitance value C of the capacitive sensor S. After this signal U1 passes through the operational amplifier OP1, a signal U2 that follows the change of U1 is generated, and the output voltage value Uout at the Vout terminal changes following the voltage value of U2. Working state three: when the first square-wave input signal V1 is at the high level VDD and the second square-wave input signal V2 is at the low level GND, the output voltage Uout at the Vout terminal is constant and remains at the voltage value Uout at the Vout terminal collected at the moment when the second square-wave input signal V2 switches to the low level GND. Operating state four: When the first square-wave input signal V1 is at the low level GND and the second square-wave input signal V2 is at the low level GND, the output voltage Uout at the Vout terminal is constant and remains at the voltage value Uout at the Vout terminal collected at the moment when the second square-wave input signal V2 switches to the low level GND.

5. The dynamic characteristic test circuit for a fast response capacitive sensor according to claim 4, characterized in that, When in operating state two, the expression of the signal U1 output at the common terminal Vo1 is: where U1 is the voltage output at the common terminal Vo1 during the T2 time period, C1 is the capacitance value of the reference capacitor Cr, and C2 is the capacitance value of the capacitive sensor S; The expression of Uout is: Uout = U1.

6. A testing method for a dynamic characteristic testing circuit of a fast response capacitive sensor according to any one of claims 1 to 5, characterized in that, It includes the following steps: S1. Initialize the circuit, set the clock periods of the first square-wave input signal V1 and the second square-wave input signal V2, and the time for the first square-wave input signal V1 to rise from the low level GND to the high level VDD is earlier than that of the second square-wave input signal V2, and the time for the first square-wave input signal V1 to fall from the high level VDD to the low level GND is later than that of the second square-wave input signal V2; S2. Divide a working cycle of the circuit into four time periods according to the clock periods of the first square-wave input signal V1 and the second square-wave input signal V2, which are: T1 time period: the first square-wave input signal V1 is at the high level VDD and the second square-wave input signal V2 is at the low level GND; T2 time period: both the first square-wave input signal V1 and the second square-wave input signal V2 are at the high level VDD; T3 time period: the first square-wave input signal V1 is at the high level VDD and the second square-wave input signal V2 is at the low level GND; T4 time period: the first square-wave input signal V1 is at the low level GND and the second square-wave input signal V2 is at the low level GND; S3. Generate the output voltage Uout at the Vout terminal during the T2 time period through these four time periods T1, T2, T3, and T4 to realize the dynamic characteristic test of the fast-response capacitive sensor within one working cycle of the circuit; S4. Repeat steps S2 to S3. By the next working cycle, the output voltage value Uout sampled at the Vout terminal will be updated again, thereby realizing the dynamic characteristic test of the fast-response capacitive sensor.

7. The test method according to claim 6, wherein During the T1 time period described in step S2, a useful signal U1 is output at the common terminal Vo1, and the voltage value Uout at the Vout terminal remains constant at the useful signal collected in the previous working cycle. This is operating state one; During the T2 time period, the signal U1 output at the common terminal Vo1 changes correspondingly with the change of the capacitance value C of the capacitive sensor S. After this signal U1 passes through the operational amplifier OP1, a signal U2 that changes following U1 is generated, and the output voltage Uout at the Vout terminal changes following the voltage value of U2. This is operating state two; During the T3 time period, useful signals are still output at the common terminal Vo1 and the Vo2 terminal, but the output voltage Uout at the Vout terminal no longer follows the change of the voltage value U1 at the Vo1 terminal. The output voltage Uout at the Vout terminal is constant and remains the voltage value Uout at the Vout terminal collected at the moment when the second square-wave input signal V2 switches to the low level GND. This is the third working state; During the T4 time period, the voltage values at the common terminal Vo1 and the Vo2 terminal are both at the ground potential GND. The output voltage Uout at the Vout terminal is still constant and remains the voltage value Uout at the Vout terminal collected at the moment when the second square-wave input signal V2 switches to the low level GND. This is the fourth working state.

8. The test method according to claim 7, wherein The expression of the signal U1 during the T2 time period is: where U1 is the voltage output at the common terminal Vo1 during the T2 time period, C1 is the capacitance value of the reference capacitor Cr, and C2 is the capacitance value of the capacitive sensor S; The expression of Uout is: Uout = U1.

9. An electronic device, characterized in that, It includes a memory and a processor, where: The memory is used to store a computer program that can run on the processor; The processor is used to execute the steps of the test method according to any one of claims 6-8 when running the computer program.

10. A storage medium, characterized in that, A computer program is stored on the storage medium, and when the computer program is executed by at least one processor, the steps of the test method according to any one of claims 6-8 are implemented.

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