Method and device for chip system-level testing and electronic equipment

Abstract

The invention discloses a method and device for chip system-level testing and electronic equipment. The method comprises the following steps: a test mainboard electrifies at least one tested daughter board connected with the test mainboard; testing by the tested daughter board according to a set test process to generate test data; and the tested daughter board transmits the test data to the test mainboard, so that the test data on the test mainboard is analyzed by the upper computer to obtain a test result. According to the technical scheme, the test mainboard is only responsible for power-on and power-off control of the tested daughter board, the execution of the whole system-level test is operated by the tested daughter board, even if the number of tested chips is large, the single-chip test time can be saved, the situation that the main control chip of the test mainboard is overloaded, and the test efficiency is improved is avoided. And the upper computer directly obtains the test data of the tested daughter board on the test mainboard and analyzes the test data to obtain the test result, so that the system-level test efficiency is effectively improved.

Description

Technical Field

[0001] The present invention relates to the technical field of chip testing, and in particular, to a method and device for chip system-level testing, and an electronic device. Background Art

[0002] SLT (System level test) is a test for the functionality and reliability of packaged chips at the system level, and the chips are screened based on the test results.

[0003] The main problems existing in the prior art chip system-level test methods are as follows: all test item controls are initiated by the master control chip. When there are too many chips under test, the master control chip will be overloaded, affecting the overall test time. Moreover, the binning operation for each test result is also completed by the master control chip, and the binning results are saved locally, which will also affect the overall test time and lead to a decrease in test efficiency. Summary of the Invention

[0004] The present invention provides a method and device for chip system-level testing, and an electronic device, which can effectively improve the system-level test efficiency.

[0005] In one aspect of the present invention, a method for chip system-level testing is provided. The method includes: powering on at least one sub-board under test connected to the test main board by the test main board; the sub-board under test performing tests according to a set test process to generate test data; and the sub-board under test transmitting the test data to the test main board, so that the test data on the test main board is parsed by the host computer to obtain test results.

[0006] In another aspect of the present invention, a device for chip system-level testing is provided. The device includes: a test main board and at least one sub-board under test, the sub-board under test being electrically coupled to the test main board via a corresponding device port, wherein the test main board is configured to power on at least one sub-board under test connected to it, and the sub-board under test is configured to perform tests according to a set test process to generate test data, and transmit the test data to the test main board, so that the test data on the test main board is parsed by the host computer to obtain test results.

[0007] In still another aspect of the present invention, an electronic device is provided. The electronic device includes: a memory configured to store an executable program; and a processor configured to execute the program so that the electronic device executes the above-mentioned method for chip system-level testing.

[0008] According to the technical solution of the present invention, the test main board powers on at least one DUT (Device Under Test) sub-board connected thereto, and the DUT sub-board performs tests according to a set test process to generate test data. The DUT sub-board transmits the test data to the test main board, so that the test data on the test main board is parsed by the host computer to obtain test results. In this way, the test main board is only responsible for the power-on and power-off control of the DUT sub-board, and the execution of the entire system-level test is performed by the DUT sub-board itself. Even if there are a large number of DUT chips, it can save the single-chip test time, avoid overloading the main control chip of the test main board, and the host computer directly obtains the test data of the DUT sub-board on the test main board and parses the test results, thereby effectively improving the system-level test efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figure 1 FIG. is a flowchart of a method for chip system-level testing according to an embodiment of the present invention; Figure 2 FIG. is a test flowchart of a method for chip system-level testing according to an embodiment of the present invention; Figure 3 FIG. is a schematic structural diagram of a device for chip system-level testing according to an embodiment of the present invention; Figure 4 FIG. is a schematic structural diagram of an electronic device according to an embodiment of the present invention. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0010] To describe in detail the technical content, achieved objectives and effects of the present invention, the following is described in conjunction with the embodiments and with reference to the accompanying drawings.

[0011] In the prior art, all test item controls in chip system-level testing are initiated by the main control chip. When there are too many DUT chips, it will cause the main control chip to be overloaded. In addition, the binning operation for each test result is also completed by the main control chip and the binning results are saved locally, affecting the overall test time and resulting in a decrease in test efficiency.

[0012] To solve at least the above technical problems, the present disclosure provides a method for chip system-level testing. The test main board powers on at least one DUT sub-board connected thereto, and the DUT sub-board performs tests according to a set test process to generate test data. The DUT sub-board transmits the test data to the test main board, so that the test data on the test main board is parsed by the host computer to obtain test results. In this way, the test main board is only responsible for the power-on and power-off control of the DUT sub-board, and the execution of the entire system-level test is performed by the DUT sub-board itself. Even if there are a large number of DUT chips, it can save the single-chip test time, avoid overloading the main control chip of the test main board, and the host computer directly obtains the test data of the DUT sub-board on the test main board and parses the test results, thereby effectively improving the system-level test efficiency.

[0013] In the following, the technical solutions according to the present disclosure will be described with reference to specific embodiments and in conjunction with the accompanying drawings.

[0014] Figure 1 is a flowchart showing a method 100 for system - on - chip testing according to an embodiment of the present disclosure. Referring to Figure 1 this, the method 100 includes the following steps 102 to step 106.

[0015] In step 102, the test main board powers on at least one DUT (Device Under Test) sub - board connected thereto.

[0016] In some embodiments, each chip to be tested is disposed on a corresponding DUT sub - board.

[0017] In step 104, the DUT sub - board performs tests according to a set test process to generate test data.

[0018] In some embodiments, in response to the power - on of the DUT sub - board, the chips to be tested on the DUT sub - board are tested according to a set test process to generate initial test data. Additionally, the initial test data is converted into Universal Serial Bus (USB) data as the test data.

[0019] In step 106, the DUT sub - board transmits the test data to the test main board, such that the test data on the test main board is parsed by the host computer to obtain a test result.

[0020] In some embodiments, the DUT sub - board transmits the test data to the hub via the device port of the hub of the test main board, and the DUT sub - board corresponds to the device port of the hub one - to - one. In some embodiments, the test data corresponding to the device port of the hub is traversed and parsed by the host computer to obtain the test result.

[0021] In some embodiments, the host computer parses the test data from the hub via the Universal Serial Bus to obtain system - level test data, and obtains the test result according to the system - level test data.

[0022] In this way, the test main board does not need to analyze the test result, but the host computer directly obtains the test data of the DUT sub - board, parses it, and obtains the test result, reducing the load of the main control chip of the test main board and improving the test efficiency.

[0023] In some embodiments, the method 100 may further include: the host computer sends a binning command to the sorter based on the test result. In this way, there is no need for the main control chip of the test main board to perform binning operations, shortening the system - level test time.

[0024] In some embodiments, the host computer determines the bin file number corresponding to the test result based on a preset correspondence table between test results and bin file numbers, and determines the device port where the DUT daughter board corresponding to the test result is located. Additionally, the host computer generates a bin sorting command according to the bin file number of the DUT daughter board and the device port where the DUT daughter board is located, and sends the bin sorting command to the sorter.

[0025] In some embodiments, the host computer determines the device port where the DUT daughter board corresponding to the test result is located according to a preset connection rule for the DUT daughter board. The preset connection rule for the DUT daughter board includes the DUT daughter board identifier and the device port of the USB hub in the test main board corresponding thereto.

[0026] In this way, since there is a strong connection relationship between the DUT daughter board and the device port of the USB hub of the test main board, when determining the device port where the DUT daughter board corresponding to the test result is located, it can be determined only according to the preset connection rule for the DUT daughter board, without the need for communication interaction between the host computer and the DUT daughter board, shortening the system-level test time and saving the test cost.

[0027] In some embodiments, the method 100 may further include: the host computer traversing all the device ports of the USB hub of the test main board; and for the target device port traversed, determining whether the connection status of the target device port is connected, and determining whether the DUT daughter board identifier connected to the target device port is the same as the DUT daughter board identifier corresponding to the target device port in the preset connection rule for the DUT daughter board. If both are satisfied, it is determined that the DUT daughter board has been successfully connected.

[0028] In this way, since there is a strong connection relationship between the DUT daughter board and the device port of the USB hub of the test main board, the host computer traverses all the device ports of the USB hub of the test main board, determines whether the connection status of the target device port traversed is connected, and determines whether the DUT daughter board identifier connected to the target device port is the same as the DUT daughter board identifier corresponding to the target device port in the preset connection rule for the DUT daughter board. Without a communication interaction link, the host computer can quickly and accurately determine the connection status of the DUT daughter board.

[0029] In some embodiments, the method 100 may further include: the host computer comparing the firmware version information in the test data with the test firmware version in the work order; if the comparison result is consistent, the host computer determines whether the firmware version information in the test data is the same as the firmware version information in the previously received test data to determine whether the DUT daughter board has been abnormally restarted; and if it is determined that there has been an abnormal restart, the test main board powers off the DUT daughter board.

[0030] In this way, the host computer compares the firmware version information in the test data with the test firmware version in the work order, realizes the inspection of the test firmware version, and ensures the reliability of the system-level test. When the test firmware version is correct, the host computer judges whether the firmware version information in the test data is the same as the firmware version information in the previously received test data. If they are the same, it indicates a repeated test, and the DUT sub-board is powered off, avoiding repeated tests caused by abnormal restart of the DUT sub-board during a single test, thereby improving the reliability of the system-level test.

[0031] In some embodiments, the method 100 may further include: the host computer judges whether the chip ID in the test data exists in the chip IDs of the historical test data; if not, the host computer compares the number of test items in the test data with a preset number of test items; if the result of the comparison is inconsistent, all the test items in the test data are compared with all the test items in the historical test data to obtain missing test items.

[0032] In this way, the host computer judges whether the chip ID in the test data exists in the chip IDs of the historical test data. If it exists, it indicates a repeated test, which can avoid the problem of stacked wafers caused by abnormal sorter programs. If not, the host computer compares the number of test items in the test data with a preset number of test items. If the comparison is inconsistent, all the test items in the test data are compared with all the test items in the historical test data to obtain missing test items, realizing the inspection and recovery of missing test items, and ensuring the reliability and effectiveness of the system-level test.

[0033] In the following, application scenarios of the method and device for chip system-level testing and an electronic device according to embodiments of the present invention will be described by way of examples.

[0034] Figure 2 is a flowchart showing a method for chip system-level testing according to an embodiment of the present invention. Referring to Figure 2 , the method includes the following steps 201 to step 208.

[0035] In step 201, a test main board thread and multiple DUT sub-board threads are created.

[0036] In step 202, wait for the sorter to be ready.

[0037] In step 203, the test main board powers on at least one DUT sub-board connected thereto.

[0038] In this embodiment, the UART (Universal Asynchronous Receiver / Transmitter) channel of each DUT daughter board is directly connected to a serial-to-USB chip, and is connected to the specified device port of the USB hub on the test main board through the socket method according to the preset connection rules of the DUT daughter board.

[0039] In step 204, the host computer traverses all device ports of the USB hub on the test main board; for the target device port traversed, it is judged whether the connection status of the target device port is connected, and it is judged whether the DUT daughter board identifier connected to the target device port is consistent with the DUT daughter board identifier corresponding to the target device port in the preset connection rules of the DUT daughter board. If both are true, it is determined that the DUT daughter board has completed the connection.

[0040] For example, if the preset connection rules of the DUT daughter board specify that DUT daughter board 1 is connected to USB port 2, then when the host computer traverses USB port 2 and detects that there is a device connected to this port, and at the same time the vid (vendor id) and pid (product id) of the connected device are consistent with the ID of the serial-to-USB chip at this port in the preset connection rules of the DUT daughter board, it indicates that DUT daughter board 1 has completed the connection with the test main board.

[0041] In step 205, the DUT daughter board performs tests according to the set test process to generate test data.

[0042] In some embodiments, in response to the power-on of the DUT daughter board, the chips under test on the DUT daughter board are tested according to the set test process to generate initial test data; and the initial test data is converted into USB data as test data. Among them, the test data includes the debugging content printed by the test program and the system-level test data, and the debugging content is used to output for engineers to view.

[0043] In some embodiments, the test data is checked. Specifically, it includes the following (1) to (6).

[0044] In some embodiments, the structure of the test data is: <<command word: data>>, mainly including the following content: 1. <<ver: firmware version>> 2. <<chip: chip id>> 3. <<start: test item software number_test item name>> 4. <<result: test item software number_test item name, errcode: error code>> 5. <<debug: debugging information>> 6. <<end: Number of test items>> 7. <<req: Software number of test item_Test item name>>.

[0045] (1)The host computer compares the firmware version information (ver) in the test data with the test firmware version in the work order.

[0046] (2)If the comparison result is consistent, the host computer determines whether the firmware version information in the test data is the same as the firmware version information in the previously received test data to determine whether the DUT sub-board has been abnormally restarted.

[0047] (3)If an abnormal restart is determined, the test main board powers off the DUT sub-board.

[0048] (4)The host computer determines whether the chip ID (chip) in the test data exists in the chip IDs of the historical test data.

[0049] In some embodiments, the historical test data is the test data of the previous ten tests before the current test.

[0050] (5)If it does not exist, the host computer compares the number of test items (end) in the test data with the preset number of test items.

[0051] (6)If the comparison result is inconsistent, the test items in the test data are compared with all the test items in the historical test data to obtain the missing test items.

[0052] In step 206, the DUT sub-board transmits the test data to the test main board, so that the test data on the test main board is parsed by the host computer to obtain the test result.

[0053] In some embodiments, the DUT sub-board transmits the test data to the hub through the device port of the hub on the test main board. The DUT sub-boards correspond to the device ports of the hub one by one. The test data corresponding to the device port of the hub is traversed and parsed by the host computer to obtain the test result.

[0054] In some embodiments, the DUT sub-board reports the test data to the host computer through the UART log channel. The host computer obtains the test data from the UART log channel through the listening thread, parses the test data from the hub via the universal serial bus, obtains the system-level test data, and obtains the test result according to the system-level test data.

[0055] In step 207, it is determined whether all the DUT sub-boards have completed the test. If so, step 208 is executed. If not, step 207 is repeated.

[0056] In step 208, the host computer sends a binning command to the sorter based on the test results, which may specifically include the following (1) to (3).

[0057] (1) The host computer determines the bin number corresponding to the test result based on the preset correspondence table between test results and bin numbers.

[0058] In some embodiments, the preset correspondence table between test results and bin numbers includes each test code (including error test codes and correct test codes) and its corresponding bin number.

[0059] (2) The host computer determines the device port where the DUT (Device Under Test) sub-board corresponding to the test result is located.

[0060] In some embodiments, the host computer determines the device port where the DUT sub-board corresponding to the test result is located according to the preset connection rules for the DUT sub-board. The preset connection rules for the DUT sub-board include the DUT sub-board identifier and the device port of the USB hub in the corresponding test main board.

[0061] (3) The host computer generates a binning command according to the bin number of the DUT sub-board and the device port where the DUT sub-board is located, and sends the binning command to the sorter.

[0062] In some embodiments, the sorter grabs the chips from the device port where the DUT sub-board is located to the specified bin according to the binning command.

[0063] Figure 3 FIG. is a block diagram showing a device 300 for chip system-level testing according to an embodiment of the present invention. Referring to Figure 3 , the device 300 for chip system-level testing includes a test main board 302 and at least one DUT sub-board 304. The at least one DUT sub-board 304 is electrically coupled to the test main board 302 via corresponding device ports.

[0064] The test main board 302 is configured to power on at least one DUT sub-board connected thereto.

[0065] The DUT sub-board 304 is configured to perform tests according to a set test process to generate test data, and transmit the test data to the test main board 302, so that the test data on the test main board 302 is parsed by the host computer to obtain test results.

[0066] In some embodiments, a USB hub function is integrated on the test main board 302. The host port of the USB hub is connected to the host computer, and multiple device ports are connected to multiple sockets on the test main board 302. Each device port has a fixed address, and the test sub-board 304 is connected to the test main board 302 in a socket manner.

[0067] It should be understood that the test main board 302 and at least one sub-board under test 304 can be further configured to execute the corresponding steps or actions in the methods described in the above embodiments, which will not be elaborated here.

[0068] In some embodiments, the apparatus 300 may further include the host computer described in the above embodiments.

[0069] According to another aspect of the present invention, Figure 4 is a schematic diagram showing an electronic device 400 according to an embodiment of the present invention. Referring to Figure 4 , the electronic device 400 includes a memory 402 and a processor 404. The memory 402 is configured to store an executable program that can run on the processor 404. The processor 404 is configured to execute the program so that the electronic device implements the respective steps or actions of the method for chip system-level testing described above.

[0070] In summary, for the method, apparatus, and electronic device for chip system-level testing provided by the present invention, the test main board powers on at least one sub-board under test connected thereto, the sub-board under test performs testing according to a set test process to generate test data, and the sub-board under test transmits the test data to the test main board, so that the test data on the test main board is parsed by the host computer to obtain a test result. In this way, the test main board is only responsible for the power-on and power-off control of the sub-board under test, and the execution of the entire system-level testing is self-run by the sub-board under test. Even if there are a large number of chips under test, it can save the single-chip testing time, avoid overloading the main control chip of the test main board, and the host computer directly obtains the test data of the sub-board under test on the test main board and parses to obtain the test result, thereby effectively improving the system-level testing efficiency. In addition, since there is a strong connection relationship between the sub-board under test and the device port of the USB hub of the test main board, when determining the device port where the sub-board under test corresponding to the test result is located, it can be determined only according to the preset connection rule of the sub-board under test, without the need for communication interaction between the host computer and the sub-board under test, shortening the system-level testing time and saving the testing cost. In addition, the host computer realizes the inspection of the test firmware version, repeated test inspection, and inspection and recovery of missing test items, improving the reliability of the system-level testing.

[0071] The above are only the embodiments of the present invention, and do not limit the patent scope of the present invention accordingly. Any equivalent transformation made using the content of the specification and drawings of the present invention, or directly or indirectly applied in the related technical fields, shall be included in the patent protection scope of the present invention by the same token.

Claims

1. A method for chip system-level testing, characterized in that, Including: Powering on at least one DUT (Device Under Test) sub-board connected to the test main board by the test main board; The DUT sub-board performing tests according to a set test process to generate test data; And The DUT sub-board transmitting the test data to the test main board, so that the test data on the test main board is parsed by the host computer to obtain test results.

2. The method according to claim 1, characterized in that The DUT sub-board performing tests according to a set test process to generate test data includes: In response to powering on the DUT sub-board, testing the chips under test on the DUT sub-board according to a set test process to generate initial test data; and Converting the initial test data into Universal Serial Bus (USB) data as the test data.

3. The method according to claim 1, characterized in that, The DUT sub-board transmitting the test data to the test main board includes: The DUT sub-board transmitting the test data to the hub via the device port of the hub of the test main board, and the DUT sub-board corresponds to the device port of the hub one by one.

4. The method according to claim 3, wherein Making the test data on the test main board be parsed by the host computer to obtain test results includes: Making the test data corresponding to the device port of the hub be traversed and parsed by the host computer to obtain the test results.

5. The method according to claim 1, wherein Also including: The host computer sending a binning command to the sorter based on the test results.

6. The method according to claim 3, wherein Making the test data on the test main board be parsed by the host computer to obtain test results includes: The host computer parsing the test data from the hub via the Universal Serial Bus to obtain system-level test data, and obtaining the test results according to the system-level test data.

7. The method according to claim 5, characterized in that The host computer sending a binning command to the sorter based on the test results includes: The host computer determining the bin file number corresponding to the test results based on a preset correspondence table between test results and bin file numbers; The host computer determining the device port where the DUT sub-board corresponding to the test results is located; and The host computer generating a binning command according to the bin file number of the DUT sub-board and the device port where the DUT sub-board is located, and sending the binning command to the sorter.

8. The method according to claim 7, wherein The host computer determining the device port where the DUT sub-board corresponding to the test results is located includes: The host computer determining the device port where the DUT sub-board corresponding to the test results is located according to a preset connection rule of the DUT sub-board, and the preset connection rule of the DUT sub-board includes the DUT sub-board identifier and the device port of the USB hub in the corresponding test main board.

9. The method according to claim 8, wherein Also including: The host computer traversing all device ports of the USB hub of the test main board; And For the target device port traversed, determining whether the connection status of the target device port is connected, and determining whether the DUT sub-board identifier connected to the target device port is consistent with the DUT sub-board identifier corresponding to the target device port in the preset connection rule of the DUT sub-board. If both are yes, it is determined that the DUT sub-board has been connected.

10. The method according to claim 1, characterized in that Also including: The host computer comparing the firmware version information in the test data with the test firmware version in the work order; If the result of the comparison is consistent, the host computer determines whether the firmware version information in the test data is the same as the firmware version information in the previously received test data to determine whether the DUT daughter board has been abnormally restarted; and If an abnormal restart is determined, the test main board powers off the DUT daughter board.

11. The method according to claim 10, wherein It further includes: The host computer determines whether the chip ID in the test data exists in the chip IDs of the historical test data; If not, the host computer compares the number of test items in the test data with a preset number of test items; If the result of the comparison is inconsistent, all the test items in the test data are compared with all the test items in the historical test data to obtain missing test items.

12. An apparatus for chip system-level testing, characterized in that, It includes a test main board and at least one DUT daughter board, and the DUT daughter board is electrically coupled to the test main board via a corresponding device port, wherein the test main board is configured to power on at least one DUT daughter board connected thereto, wherein the DUT daughter board is configured to perform tests according to a set test process to generate test data, and transmit the test data to the test main board, so that the test data on the test main board is parsed by the host computer to obtain test results.

13. An electronic device, characterized in that, It includes: A memory configured to store an executable program; and A processor configured to execute the program so that the electronic device executes the method according to any one of claims 1 to 11.

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