Photonic integrated circuit chip and method for manufacturing photonic integrated circuit chip

Abstract

The embodiment of the invention discloses a photonic integrated circuit chip and a manufacturing method of the photonic integrated circuit chip. The photonic integrated circuit chip comprises a grating coupler. The method comprises the following steps: forming the grating coupler; forming a first dielectric layer on the grating coupler, wherein the first dielectric layer covers the grating coupler; forming an etching stop layer on the first dielectric layer; a part of the etching stop layer is removed to form a first opening, the first opening is located above the grating coupler, and the grating coupler is exposed through the first opening; and forming a plurality of second openings in the etching stop layer to relieve uneven stress distribution. According to the embodiment of the invention, the second opening is formed in the etching stop layer, so that the stress of the etching stop layer is relieved, and the optical coupling performance of the grating coupler in the photonic integrated circuit chip is prevented from being affected.

Description

Technical Field

[0001] This application relates to the field of semiconductors, and particularly to a photonic integrated circuit chip and a manufacturing method thereof. Background Art

[0002] A photonic integrated circuit chip (PIC) integrates multiple optical devices (such as optical modulators, photodetectors, etc.) on a single chip and has important applications in the fields of optical communication, sensing, etc. A grating coupler is a commonly used key device in PICs and is used to achieve efficient optical signal coupling between the chip and external optical fibers, that is, the input and output of light. In a typical manufacturing process of a photonic integrated circuit chip, after photon devices such as grating couplers are formed, a multi-layer thin film structure including a dielectric layer and an etch-stop layer (ESL) is usually deposited above them. Summary of the Invention

[0003] This application provides a photonic integrated circuit chip and a manufacturing method thereof.

[0004] According to a first aspect of this application, a manufacturing method of a photonic integrated circuit chip is provided. The photonic integrated circuit chip includes a grating coupler. The method includes: forming a grating coupler; forming a first dielectric layer on the grating coupler, the first dielectric layer covering the grating coupler; forming an etch-stop layer on the first dielectric layer; removing a part of the etch-stop layer to form a first opening, the first opening being located above the grating coupler and exposing the grating coupler through the first opening; and forming a plurality of second openings in the etch-stop layer to relieve uneven stress distribution.

[0005] In some embodiments, after forming the etch-stop layer, the method further includes forming an interlayer dielectric layer.

[0006] In some embodiments, a part of the interlayer dielectric layer extends into the plurality of second openings.

[0007] In some embodiments, the manufacturing method further includes: providing a substrate, the substrate including an insulating layer and a first silicon layer, and forming a grating coupler using the first silicon layer.

[0008] In some embodiments, the manufacturing method further includes: etching the interlayer dielectric layer and the etch-stop layer to obtain a trench that penetrates the interlayer dielectric layer and the etch-stop layer in the thickness direction.

[0009] In some embodiments, the photonic integrated circuit chip further includes a photonic device, the photonic device is spaced apart from the grating coupler, and the photonic device is electrically connected to the metal layer in the trench.

[0010] In some embodiments, the photonic device is an optical modulator. Before forming the etch stop layer on the first dielectric layer, the method further includes: forming a conductive via using the first dielectric layer, one end of the conductive via is connected to the optical modulator, and the other end of the conductive via is connected to the trench.

[0011] In some embodiments, the thickness of the etch stop layer is 20 nm to 80 nm.

[0012] In some embodiments, the method further includes: alternately forming an etch stop layer and an interlayer dielectric layer, the interlayer dielectric layer is at least two layers, and the etch stop layer is at least two layers.

[0013] According to a second aspect of the present application, the present application provides a photonic integrated circuit chip manufactured by using the method according to any one of the above first aspects. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] The following combines the drawings and describes the specific embodiments of the present application in detail, and the technical solutions and other beneficial effects of the present application will be obvious.

[0015] Figure 1-2 Shows the relevant steps of the problems found by the inventor in the manufacture of the photonic integrated chip;

[0016] Figure 3 Shows a flowchart of the steps of the manufacturing method of the photonic integrated circuit chip according to an embodiment of the present application;

[0017] Figure 4 Shows a schematic diagram of a substrate according to an embodiment of the present application;

[0018] Figure 5 Shows a schematic diagram of the structure after forming the first part of the grating coupler and the optical modulator according to an embodiment of the present application;

[0019] Figure 6 Shows a schematic diagram of the structure after forming the grating coupler according to an embodiment of the present application;

[0020] Figure 7 Shows the structure after forming the first dielectric layer according to an embodiment of the present application Figure 6 in the schematic diagram;

[0021] Figure 8 Shows a schematic diagram of the structure after forming a conductive via using the first dielectric layer according to an embodiment of the present application;

[0022] Figure 9 Shows a schematic diagram after forming an etch stop layer according to an embodiment of the present application;

[0023] Figure 10 Shows the schematic diagram of the structure in Figure 9 after forming a first opening and a second opening by using the etch stop layer according to an embodiment of the present application;

[0024] Figure 11 Shows a plan view schematic diagram after forming a second opening on the etch stop layer 16 according to an embodiment of the present application;

[0025] Figure 12 Shows the schematic diagram of the structure in Figure 10 after forming an interlayer dielectric layer on the etch stop layer according to an embodiment of the present application;

[0026] Figure 13 Shows the schematic diagram of the structure in Figure 12 after forming a trench according to an embodiment of the present application;

[0027] The meanings of the reference numerals are as follows: grating coupler 100; first part 110 of the grating coupler; first grating tooth 111; second part 120 of the grating coupler; second grating tooth 121; optical modulator 200; conductive via 300; trench 400; substrate 10; bottom silicon 11; insulating layer 12; first silicon layer 13; third dielectric layer 14; oxide layer 15; etch stop layer 16; first opening 161; second opening 162; interlayer dielectric layer 17. Detailed implementation manners

[0028] Next, the technical solutions in the embodiments of the present application will be clearly and completely described with reference to the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without making creative efforts belong to the scope of protection of the present application.

[0029] In the description of the present application, it should be understood that the orientation or positional relationship indicated by terms such as "center", "longitudinal", "transverse", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", etc. is based on the orientation or positional relationship shown in the drawings. It is only for the convenience of describing the present application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation. Therefore, it should not be construed as a limitation to the present application. In addition, the terms "first" and "second" are only used for descriptive purposes and cannot be construed as indicating or implying relative importance or implicitly specifying the quantity of the indicated technical features. Thus, the features defined with "first" and "second" may explicitly or implicitly include one or more of the said features. In the description of the present application, "a plurality of" means two or more unless otherwise specifically defined.

[0030] In the description of the present application, it should be noted that unless otherwise clearly specified and defined, the terms "mounted", "connected" and "coupled" shall be construed broadly. For example, it may be a fixed connection, a detachable connection or an integral connection; it may be a mechanical connection, an electrical connection or a connection capable of mutual communication; it may be directly connected or indirectly connected through an intermediate medium, and it may be the communication inside two elements or the interaction relationship between two elements. For those of ordinary skill in the art, the specific meanings of the above terms in the present application can be understood according to specific circumstances.

[0031] In the present application, unless otherwise clearly specified and defined, the first feature being "on" or "under" the second feature may include the direct contact between the first and second features, or may include the situation where the first and second features are not in direct contact but in contact through additional features therebetween. Moreover, the first feature being "above", "over" and "on" the second feature includes that the first feature is directly above and obliquely above the second feature, or merely means that the horizontal height of the first feature is higher than that of the second feature. The first feature being "under", "beneath" and "under" the second feature includes that the first feature is directly below and obliquely below the second feature, or merely means that the horizontal height of the first feature is lower than that of the second feature.

[0032] The disclosure below provides many different embodiments or examples to realize the different structures of the present application. In order to simplify the disclosure of the present application, the parts and settings of specific examples are described below. Of course, they are only examples, and the purpose is not to limit the present application. In addition, the present application can repeat reference numbers and / or reference letters in different examples, and this repetition is for the purpose of simplification and clarity, which itself does not indicate the relationship between the various embodiments and / or settings discussed. In addition, the various specific processes and material examples provided by the present application, but those of ordinary skill in the art can appreciate the application of other processes and / or the use of other materials.

[0033] A photonic integrated circuit chip can integrate one or more optical devices, and a grating coupler is one of the important devices, which can be used to couple light from the outside world, thereby coupling the light with the photonic integrated circuit chip, so that the light is input into the photonic integrated circuit chip or output from the photonic integrated circuit chip. The applicant has found that in the manufacturing process of the photonic integrated circuit chip, the uneven stress distribution in the dielectric layer and the etch stop layer deposited on the grating coupler will cause the performance of the photonic integrated circuit chip to deteriorate. For example, when it is necessary to open a first opening for the grating coupler on the etch stop layer, the presence of the first opening will destroy the uniform distribution of stress in the etch stop layer, resulting in stress concentration or uneven distribution. Specifically, if Figures 1 to 2 As shown, it shows the problems found by the inventors when carrying out relevant manufacturing. The substrate of the photonic integrated circuit chip includes a stacked bottom silicon 11', an insulating layer 12' and a first silicon layer, and the first silicon layer is used to form at least a part of the grating coupler 100' and at least a part of the optical modulator 200'. A first dielectric layer 19' covering the grating coupler 100' and the optical modulator 200' is formed on the grating coupler 100' and the optical modulator 200', wherein the grating coupler 100' includes a first grating tooth and a second grating tooth separated by an oxide layer 15'. Figure 1 For along Figure 2 Schematic diagram of the cross-sectional structure along line AA'. Figure 2 The top view of the surface of the etching stop layer 16' is shown. In some process steps, the etching stop layer 16' is formed on the first dielectric layer 19'. It is necessary to form a first opening 161' on the etching stop layer 16' above the grating coupler 100'. The first opening 161' corresponds to the optical path area of ​​the subsequent grating coupler input or output light. Figure 2 The figure also shows a groove 400' for electrical connection. However, the presence of the first opening 161' will lead to uneven stress distribution on the etch stop layer 16', and the resulting deformation will affect the transmission path of light in the chip, causing the phase, frequency and other characteristics of the optical signal to change, resulting in degradation of the performance of the photonic integrated circuit chip.

[0034] The present application provides a method for manufacturing a photonic integrated circuit chip. Figure 3 The flowchart of steps of the method for manufacturing a photonic integrated circuit chip according to an embodiment of the present application is shown. The photonic integrated circuit chip includes a grating coupler. The above manufacturing method includes steps 101 to 106.

[0035] Step 101: Form a grating coupler.

[0036] Step 102: Form a first dielectric layer on the grating coupler, and the first dielectric layer covers the grating coupler.

[0037] Step 103: Form an etch stop layer on the first dielectric layer;

[0038] Step 104: Remove a part of the etch stop layer to form a first opening, the first opening is located above the grating coupler, and the grating coupler is exposed through the first opening;

[0039] Step 105: Form an interlayer dielectric layer on the etch stop layer, the interlayer dielectric layer covers the first opening, and the interlayer dielectric layer has a corresponding depression above the first opening;

[0040] Step 106: Form a plurality of second openings in the etch stop layer to relieve uneven stress distribution.

[0041] Figures 4 to 13 The structural schematic diagrams of the steps in the method for forming the semiconductor structure according to the embodiments of the present application are shown. The method for forming the semiconductor structure according to the embodiments of the present application will be described in detail below with reference to the accompanying drawings.

[0042] Figure 4 The schematic diagram of a substrate according to an embodiment of the present application is shown. The method may include providing a substrate for forming a grating coupler. The photonic devices in the photonic integrated circuit chip can be manufactured based on a semiconductor layer on an insulator, such as silicon-on-insulator (SOI), silicon-germanium-on-insulator (S-SiGeOI), etc. In addition, other substrates can also be provided for manufacturing photonic integrated structures. The substrate material can be: silicon, germanium, silicon carbide, gallium arsenide, gallium phosphide, which can be a compound semiconductor or an alloy semiconductor, etc., or a combination of the above materials.

[0043] In some embodiments, the substrate 10 is a silicon-on-insulator (SOI) substrate. The substrate 10 includes a bottom silicon layer 11, an insulating layer 12, and a first silicon layer 13. The insulating layer 12 and the first silicon layer 13 are sequentially disposed on the bottom silicon layer 11. The first silicon layer 13 can be utilized to form various types of photonic devices, such as optical waveguides, grating couplers, optical modulators, directional couplers, multi-mode interferometers (MMIs), photodetectors, optical splitters, etc. Specifically, photonic devices can be formed by performing steps such as photolithography, etching, patterning, etc. on the first silicon layer 13, as well as steps such as deposition and doping. When forming photonic devices, it may include depositing different types of semiconductor materials and metal materials. Exemplarily, one or more of various types of photonic devices formed in the first silicon layer 13 can be spaced apart, and there can be an electrical connection or an optical coupling connection relationship between the multiple photonic devices.

[0044] Figure 5 FIG. shows a schematic diagram after forming a first part of a grating coupler and an optical modulator according to an embodiment of the present application. The first part 110 of the grating coupler includes a plurality of first grating teeth 111, and the optical modulator 200 is spaced apart from the first part 110 of the grating coupler. In Figure 5 the illustrated embodiment, the first part 110 of the grating coupler and the optical modulator 200 are formed using the first silicon layer 13 (the first silicon layer 13 can be referred to Figure 4 ), and the first part 110 of the grating coupler and the optical modulator 200 can be formed by performing steps such as photolithography, etching, patterning, etc. on the first silicon layer 13, as well as steps such as deposition and doping.

[0045] Figure 6 FIG. shows a schematic diagram after forming a grating coupler. After forming the first part 110 of the grating coupler, a third dielectric layer 14 is formed. First, the third dielectric layer 14 can be deposited to at least fill the regions between adjacent two first grating teeth 111 and the regions where the first part 110 of the grating coupler is not provided, and then it is planarized until its upper surface is flush with the upper surface of the first part 110 of the grating coupler.

[0046] In some embodiments, the material of the third dielectric layer 14 includes silicon dioxide, but other oxides or dielectrics can also be used. The material should have uniform light transmittance. Any known deposition technique for insulating materials, such as CVD, PECVD, flowable CVD, spin-on dielectrics, or ALD, can be used to deposit the first dielectric layer. In Figure 6In the illustrated embodiment, after forming the third dielectric layer 14, an oxide layer 15 is formed. The oxide layer 15 can be used as a gate oxide layer for optoelectronic devices on the first silicon layer 13. The material of the oxide layer 15 can include at least one of silicon dioxide, silicon nitride, and silicon oxynitride. After forming the oxide layer 15, a second part 120 of the grating coupler is formed on the oxide layer 15. The grating coupler 100 is composed of a first part 110 and a second part 120 of the grating coupler. The second part 120 of the grating coupler includes a plurality of second grating teeth 121 corresponding to the first grating teeth 111.

[0047] Figure 7 A schematic diagram of the structure after forming the first dielectric layer according to an embodiment of the present application is shown. Figure 6 A schematic diagram of the structure shown in the figure is shown. After forming the second part 120 of the grating coupler, a first dielectric layer 19 is formed. The first dielectric layer 19 covers at least a part of the grating coupler 100 and the optical modulator 200, and has an isolation and protection effect on the grating coupler 100 and the optical modulator 200.

[0048] Figure 8 A schematic diagram of the structure after forming a conductive hole using the first dielectric layer according to an embodiment of the present application is shown. A through hole penetrating the first dielectric layer 19 and the oxide layer 15 is formed above the optical modulator 200. The through hole extends from the surface of the first dielectric layer 19 to the surface of the optical modulator 200. After filling the through hole with a conductive material, a conductive hole 300 is formed. The conductive hole 300 includes a conductive material and has conductivity. The conductive material can be, for example, a metal material. The number of conductive holes 300 can be multiple. In some embodiments, the number of conductive holes 300 is two, which are respectively disposed on the positive and negative electrodes of the optical modulator 200. An ohmic contact between the metal and the semiconductor is formed at the end where the conductive hole 300 is connected to the optical modulator 200.

[0049] Figure 9 A schematic diagram of the structure after forming an etch stop layer according to an embodiment of the present application is shown. The etch stop layer 16 can facilitate controlling the etch rate during subsequent etching processes (such as etching to form a trench 400 or other structures), so as to better control the position where the etching stops. For example, it can prevent removing the material below the etch stop layer 16 due to excessive etching.

[0050] In some embodiments, the etch stop layer 16 can be, for example, 30 nm or 50 nm. The typical thickness range is 20 nm to 80 nm. The material of the etch stop layer 16 can be silicon oxynitride or silicon nitride. Without special limitation, the above element ratios include non-stoichiometric ratios.

[0051] Figure 10Shows the structure after forming the first opening and the second opening by using an etch stop layer according to an embodiment of the present application. Figure 9 Schematic diagram of the structure in Figure 11 Shows a plan view after forming the second opening on the etch stop layer 16 according to an embodiment of the present application. The first opening 161 is located above the grating coupler 100, and this area is subsequently used to form a coupling path between the optical signal and the grating coupler 100. In some embodiments, as Figure 11 shown, a plurality of second openings 162 are uniformly distributed around the first opening 161. The presence of the second openings 162 reduces the adverse effect on the mechanical properties of the etch stop layer 16 caused by the first opening 161.

[0052] After forming the etch stop layer 16, the above method further includes forming an interlayer dielectric layer 17 on the etch stop layer 16.

[0053] Figure 12 Shows the structure in Figure 10 after forming the interlayer dielectric layer on the etch stop layer according to an embodiment of the present application. Due to the height difference between the part where the first opening 161 is located and the part where the second openings 162 are located and other parts of the etch stop layer 16, a part of the interlayer dielectric layer 17 extends into the first opening 161 and the plurality of second openings 162.

[0054] After forming the interlayer dielectric layer 17, the above manufacturing method further includes etching the interlayer dielectric layer and the etch stop layer to obtain a trench that penetrates the interlayer dielectric layer and the etch stop layer in the thickness direction.

[0055] Figure 13 Shows the structure in Figure 12 after forming the trench according to an embodiment of the present application. The trench 400 is disposed above the optical modulator 200 and corresponds to the conductive via 300 one by one. Above each conductive via 300, there is a trench 400 that penetrates the etch stop layer 16 and the interlayer dielectric layer 17.

[0056] In Figures 4 to 13 the embodiment shown, the case of forming a single etch stop layer 16 and interlayer dielectric layer 17 is shown. In some embodiments, a plurality of etch stop layers 16 and interlayer dielectric layers 17 may be alternately formed. The interlayer dielectric layer 17 is at least 2 layers, and the etch stop layer 16 is at least 2 layers. And, each etch stop layer 16 needs to form the second opening 162 to relieve stress.

[0057] In subsequent steps, it further includes filling the trench 400 with a conductive material, such as copper.

[0058] The present application also provides a photonic integrated circuit chip manufactured by using the manufacturing method of the above photonic integrated circuit chip.

[0059] In the above steps, the specific steps for depositing each layer can be designed according to actual needs, and the embodiments of the present application do not make specific limitations thereon. The specific steps for etching each layer can be designed according to actual needs, and the embodiments of the present application do not make specific limitations thereon. The specific steps for doping each layer can also be designed according to actual needs. Among them, the number of doping regions, the doping concentration of each doping region, and the doping ions can be determined according to actual needs.

[0060] In the above embodiments, the descriptions of the respective embodiments have their own emphases. For the parts not detailed or recorded in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0061] Specific examples are used in this article to elaborate on the principles and implementation manners of the present application. The descriptions of the above embodiments are only used to help understand the technical solutions and their core ideas of the present application; those of ordinary skill in the art should understand that they can still modify the technical solutions recorded in the foregoing embodiments, or perform equivalent replacements on some of the technical features; and these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A manufacturing method of a photonic integrated circuit chip, characterized in that, The photon integrated circuit chip includes a grating coupler, and the method includes: Forming a grating coupler; Forming a first dielectric layer on the grating coupler, the first dielectric layer covering the grating coupler; Forming an etch stop layer on the first dielectric layer; Removing a part of the etch stop layer to form a first opening, the first opening being located above the grating coupler, and exposing the grating coupler through the first opening; And forming a plurality of second openings in the etch stop layer to relieve uneven stress distribution.

2. The manufacturing method according to claim 1, characterized in that, After forming the etch stop layer, the method further includes forming an interlayer dielectric layer.

3. The manufacturing method according to claim 2, wherein, A part of the interlayer dielectric layer extends into the plurality of second openings.

4. The manufacturing method according to claim 1, characterized in that, The method further includes: Providing a substrate, the substrate including an insulating layer and a first silicon layer, and forming a grating coupler using the first silicon layer.

5. The manufacturing method according to claim 2, characterized in that, The method further includes: Etching the interlayer dielectric layer and the etch stop layer to obtain a trench that penetrates the interlayer dielectric layer and the etch stop layer in the thickness direction.

6. The manufacturing method according to claim 5, characterized in that, The photon integrated circuit chip further includes a photon device, the photon device being spaced apart from the grating coupler, and the photon device being electrically connected to a metal layer in the trench.

7. The manufacturing method according to claim 6, characterized in that, The photon device is an optical modulator. Before forming the etch stop layer on the first dielectric layer, the method further includes: Forming a conductive via using the first dielectric layer, one end of the conductive via being connected to the optical modulator, and the other end of the conductive via being connected to the trench.

8. The manufacturing method according to claim 1, wherein, The thickness of the etch stop layer is 20 nm to 80 nm.

9. The manufacturing method according to claim 2, wherein, The method further includes: alternately forming an etch stop layer and an interlayer dielectric layer, the interlayer dielectric layer being at least two layers, and the etch stop layer being at least two layers.

10. A photon integrated circuit chip manufactured by using the method according to any one of claims 1 to 9.

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