Display substrate and display panel

Abstract

The embodiment of the invention provides a display substrate and a display panel, and the display substrate is provided with first imitation areas at two sides of a first electrostatic discharge area and a second fan-out area along a first direction, and is provided with second imitation areas at two sides of the second electrostatic discharge area and a third fan-out area along the first direction. The imitation units are arranged in the first imitation area and / or the second imitation area, and the first imitation area and / or the second imitation area can be prevented from forming segment differences with the first electrostatic discharge area and / or the second electrostatic discharge area and the display area as much as possible through the imitation units. The problem that a screen is poor due to the fact that the damage degree of fur on the surface of Rubbing cloth is inconsistent can be solved.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular, to a display substrate and a display panel. Background Art

[0002] During the manufacturing process of a liquid crystal substrate, in order to make liquid crystal molecules form a certain angle, it is usually necessary to perform rubbing alignment on the alignment film on the substrate. If rubbing unevenness occurs during this process, it will cause poor panel quality. The generation mechanism of the rubbing unevenness (Rubbing Mura) phenomenon is that due to the unevenness of the surface being rubbed (Rubbing), during the Rubbing process, the distribution of the villi on the Rubbing cloth is uneven, resulting in Rubbing Mura. Summary of the Invention

[0003] The purpose of the embodiments of the present application is to provide a display substrate and a display panel. The specific technical solutions are as follows:

[0004] In a first aspect, the present application provides a display substrate, including:

[0005] A display area, a first non-display area, and a second non-display area;

[0006] The first non-display area includes a first fan-out area, a second fan-out area, a first common line area, a first electrostatic discharge area, and a first imitation area; the second fan-out area is adjacent to the display area, and the first fan-out area is located on the side of the second fan-out area away from the display area; the first common line area is arranged between the first fan-out areas; the first electrostatic discharge area is arranged between the first fan-out area and the second fan-out area;

[0007] The first imitation area is arranged along a first direction on both sides of the first electrostatic discharge area and the second fan-out area; the first direction is the gate line routing direction of the display area;

[0008] The second non-display area includes a third fan-out area, a second common line area, a second electrostatic discharge area, and a second imitation area; the third fan-out area is adjacent to the display area, and the second common line area is located on the side of the third fan-out area away from the display area; the second electrostatic discharge area is arranged between the third fan-out area and the second common line area;

[0009] The second imitation area is arranged along the first direction on both sides of the second electrostatic discharge area and the third fan-out area;

[0010] Imitation units are arranged in the first imitation area and / or the second imitation area.

[0011] In a possible implementation, the first imitation area includes a first virtual electrostatic discharge area; the first virtual electrostatic discharge area is arranged on both sides of the first electrostatic discharge area along a first direction;

[0012] The imitation unit includes an imitation electrostatic discharge unit or an imitation metal unit.

[0013] In a possible implementation, the second imitation area includes a second virtual electrostatic discharge area; the second virtual electrostatic discharge area is arranged on both sides of the second electrostatic discharge area along the first direction; the imitation unit includes an imitation electrostatic discharge unit or an imitation metal unit.

[0014] In a possible implementation, the first imitation area includes a first virtual metal line area; the first virtual metal line area is arranged on both sides of the second fan-out area along the first direction; the imitation unit includes a virtual metal line.

[0015] In a possible implementation, the second imitation area includes a second virtual metal line area; the second virtual metal line area is arranged on both sides of the third fan-out area along the first direction; the imitation unit includes a virtual metal line.

[0016] In a possible implementation, the imitation unit includes a gate line layer and a data signal layer.

[0017] In a possible implementation, the imitation unit further includes a first conductive layer.

[0018] In a possible implementation, the imitation unit further includes an active layer.

[0019] In a possible implementation, one end of the imitation electrostatic discharge unit is connected to a shorting ring, and the other end of the imitation electrostatic discharge unit is suspended.

[0020] In a possible implementation, both ends of the imitation electrostatic discharge unit are suspended.

[0021] In a possible implementation, one end of the imitation electrostatic discharge unit is connected to a shorting ring, and the other end of the imitation unit is connected to a common line.

[0022] In a possible implementation, the spacing between the imitation units is the same as the spacing between the electrostatic discharge units; or, the spacing between the imitation units is less than the width of the electrostatic discharge units and greater than 10 μm.

[0023] In a possible implementation, the virtual metal lines in the first virtual metal line area are parallel to the fan-out lines in the second fan-out area.

[0024] In a possible implementation manner, the dummy metal lines in the second dummy metal line region are parallel to the fan-out lines in the third fan-out region.

[0025] In a possible implementation manner, the width of the dummy metal lines in the first dummy metal line region is the same as the width of the fan-out lines in the second fan-out region, and the pitch between the dummy metal lines in the first dummy metal line region is the same as the pitch between the fan-out lines in the second fan-out region.

[0026] In a possible implementation manner, the width of the dummy metal lines in the second dummy metal line region is the same as the width of the fan-out lines in the third fan-out region, and the pitch between the dummy metal lines in the second dummy metal line region is the same as the pitch between the fan-out lines in the third fan-out region.

[0027] In a second aspect of the present application, a display panel is provided, including the display substrate according to any one of the above first aspects.

[0028] In a possible implementation manner, an alignment film is provided on the display substrate, and the alignment film is an optical alignment film or a rubbed alignment film.

[0029] In a third aspect of the present application, a display device is provided, including the display panel according to any one of the above second aspects.

[0030] Advantageous effects of the embodiments of the present application:

[0031] A display substrate and a display panel provided by the embodiments of the present application are provided with a first imitation region on both sides of the first electrostatic discharge region and the second fan-out region along a first direction on the display substrate, and a second imitation region on both sides of the second electrostatic discharge region and the third fan-out region along the first direction. Imitation units are arranged in the first imitation region and / or the second imitation region. Through the imitation units, it is possible to avoid as much as possible the formation of step differences between the first imitation region and / or the second imitation region and the first electrostatic discharge region and / or the second electrostatic discharge region and the display region. In this way, during the manufacturing process of the display panel, it is possible to avoid the problem of screen defects caused by inconsistent damage degrees of the hairs on the surface of the Rubbing cloth.

[0032] Of course, it is not necessary for any product or method implementing the present application to achieve all the above advantages simultaneously. Description of the Drawings

[0033] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the following will briefly introduce the drawings required for use in the description of the embodiments or the prior art. Obviously, the following drawings are only some embodiments of the present application, and those of ordinary skill in the art can also obtain other embodiments based on these drawings.

[0034] Figure 1-1 It is a schematic structural diagram of a display substrate in the related art;

[0035] Figure 1-2 It is Figure 1-1 a schematic structural diagram of the corner side of the DPO side of the shown display substrate;

[0036] Figure 1-3 It is Figure 1-1 a schematic structural diagram between the COFs on the DPO side of the shown display substrate;

[0037] Figure 1-4 It is Figure 1-1 a schematic plan view of the A-A' area of the display substrate shown in

[0038] Figure 1-5 It is Figure 1-4 an enlarged schematic diagram of area C in

[0039] Figure 2 It is Figure 1-1 a cross-sectional view of A-A' of the shown display substrate;

[0040] Figure 3 It is Figure 1-1 a cross-sectional view of B-B' of the shown display substrate;

[0041] Figure 4 a schematic diagram of Rubbing of the display substrate in the related art;

[0042] Figure 5 It is the first schematic structural diagram of the display substrate provided by the embodiment of the present application;

[0043] Figure 6-1 It is the second schematic structural diagram of the display substrate provided by the embodiment of the present application;

[0044] Figure 6-2 It is the first schematic structural diagram of the display substrate provided by the embodiment of the present application with an imitation electrostatic discharge unit provided;

[0045] Figure 6-3 It is provided by the embodiment of the present application Figure 6-2 an enlarged schematic diagram of

[0046] Figure 6-4 It is the second schematic structural diagram of the display substrate provided by the embodiment of the present application with an imitation electrostatic discharge unit provided;

[0047] Figure 6-5 It is the third schematic structural diagram of the display substrate provided by the embodiment of the present application with an imitation electrostatic discharge unit provided;

[0048] Figure 7 It is the third schematic structural diagram of the display substrate provided by the embodiment of the present application;

[0049] Figure 8 The first circuit diagram for imitating ESD provided for the display substrate in the embodiment of the present application;

[0050] Figure 9 The second circuit diagram for imitating ESD provided for the display substrate in the embodiment of the present application;

[0051] Figure 10 The third circuit diagram for imitating ESD provided for the display substrate in the embodiment of the present application;

[0052] Figure 11 The fourth circuit diagram for imitating ESD provided for the display substrate in the embodiment of the present application;

[0053] Figure 12 The fifth circuit diagram for imitating ESD provided for the display substrate in the embodiment of the present application;

[0054] Figure 13 The fourth structural schematic diagram of the display substrate provided for the embodiment of the present application;

[0055] Figure 14 A structural schematic diagram of the fan-out line in the related art;

[0056] Figure 15 A structural schematic diagram of setting a virtual metal line provided for the embodiment of the present application;

[0057] Figure 16 A structural schematic diagram of the display panel provided for the embodiment of the present application;

[0058] Figure 17 A structural schematic diagram of the display device provided for the embodiment of the present application. Detailed implementation manners

[0059] Next, the technical solutions in the embodiments of the present application will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art based on the present application belong to the scope of protection of the present application.

[0060] During the manufacturing process of the display panel, it is necessary to perform rubbing alignment on the PI (alignment) film. Rubbing alignment is to use a rubbing brush to rub on the alignment film to form grooves arranged in a certain direction. The liquid crystal material on the alignment film will achieve an alignment effect due to intermolecular forces, so that the liquid crystal molecules are arranged in a certain direction.

[0061] In the design of the TFT (Thin Film Transistor) side glass of the existing LCD display, in the AA area (active display area), generally, the same number of ESD (Electro-Static discharge) units as the number of data lines are set outside. The size of the ESD unit is smaller than the dot pitch (the width of the sub-pixel). Therefore, there are positions without patterns (patterns) between the COF (Chip On Film) or at the corners of the AA area, such as Figures 1-1 to 1-5 As shown, the display substrate includes an AA area, a first non-display area, and a second non-display area. The first non-display area is the non-display area on the data binding (DP) side, and the second non-display area is the non-display area on the opposite side of the data binding side (DPO). The first non-display area includes a first fanout area, a second fanout area (Sub Fanout1), a first common line area (Vcom1), a first electrostatic discharge area, such as Figure 1-1 As shown in, the second fanout area is adjacent to the display area, and the first fanout area is located on the side of the second fanout area away from the display area; the first common line area is set between the first fanout areas; the first electrostatic discharge area is set between the first fanout area and the second fanout area; the first electrostatic discharge area is provided with a plurality of electrostatic discharge units (ESD unit) arranged in an array along the first direction; the AA area is provided with pixel units, and the pixel units include red pixels (R), green pixels (G), and blue pixels (B). Among them, the red pixels emit red light, the green pixels emit green light, and the blue pixels emit blue light. The pixel units are arranged in a matrix form on the display substrate. The first direction is the gate line routing direction of the display area. A shorting ring is set in the display substrate to solve the electrostatic discharge problem in the display substrate. The display substrate also includes a common line, such as Vcom1 on the DP side shown in the figure.

[0062] The second non-display area includes a third fanout area (Sub Fanout2), a second common line area (Vcom2), and a second electrostatic discharge area; Sub Fanout2 is adjacent to the AA area, and the second common line area is located on the side of the third fanout area away from the display area; the second electrostatic discharge area is set between the third fanout area and the second common line area, and the second electrostatic discharge area is provided with a plurality of ESD unit arranged in an array along the first direction., the display substrate also includes a common line, such as Vcom2 on the DPO side shown in the figure. Figure 1-2 For Figure 1-1 A schematic structural diagram of the corner side of the DPO side of the shown display substrate; Figure 1-3 For Figure 1-1 A schematic structural diagram between the COFs on the DPO side of the shown display substrate; GND is the ground wire, ADD is the array substrate test signal enhancement line, and GOA is the display panel row driving circuit (Gate Driver on array).

[0063] The display panel includes an effective display area, i.e., the AA area, where the AA area includes multiple TX (Transport, transmission) blocks arranged in an array. For each TX block, the TX block includes multiple scan lines (gate lines). GOA is a technology that fabricates the driving circuit of the panel's horizontal scan lines on the panel around the display area using the original process of the flat display panel. The GOA circuit has a positive-phase clock signal input terminal CLK, an inverted-phase clock signal input terminal CLKB, and a low-voltage signal input terminal VSS. The GOA circuit outputs gate signals to scan the scan lines (gate lines) in the TX blocks. Figure 1-2 The GOA signal line in it refers to the signal line connecting the GOA circuit.

[0064] Such as Figure 2 、 Figure 3 shown, Figure 2 is the cross-sectional view of A - A', Figure 3 is the cross-sectional view of B - B'. The display substrate includes a Glass (cover glass) layer, a Gate (gate line) layer, a GI (gate insulating layer) layer, an SD (signal data) layer, a PVX (insulating protective layer) layer, a first conductive layer, and an Active (active layer) layer. Compared with the position without a pattern and the position of the ESD unit, there are more Gate layer, SD layer, Active layer, or Gate, SD, and the first conductive layer, thus forming a step difference. The step height of the Gate line layer and the SD layer is The step height of the Active layer is The step height of the first conductive layer is Then the step difference between the position without a pattern and the position with an ESD unit is

[0065] Figure 4 is a rubbing schematic diagram. When the Rubbing Roller passes through the ESD unit in the display substrate (panel), the step difference causes inconsistent damage to the Rubbing cloth. The Roller will pass through the AA area with this damage. When the rubbing direction is from the DP side → DPO side or the DPO side → DP side, as Figure 1-1 shown, the Roller (rubbing roller) will first pass through the periphery of the AA area and then reach the AA area. Due to the uneven design of the circuits or devices in the periphery of the AA area, a step difference occurs, and the damage degree of the hairs on the surface of the Rubbing cloth is inconsistent. When this influence accumulates to a certain extent, the alignment force of the PI after rubbing will be different, resulting in screen defects. That is, it affects the alignment force of the PI in the AA area, causing a difference in the pretilt angle of the liquid crystal, and Mura appears on the display screen, resulting in display defects on the screen.

[0066] The present application provides a display substrate, as Figure 5 shown, the display substrate includes:

[0067] a display area, a first non-display area, and a second non-display area;

[0068] The first non-display area includes a first fan-out area, a second fan-out area, a first common line area, a first electrostatic discharge area, and a first dummy area; the second fan-out area is adjacent to the display area, and the first fan-out area is located on a side of the second fan-out area away from the display area; the first common line area is disposed between the first fan-out areas; the first electrostatic discharge area is disposed between the first fan-out area and the second fan-out area.

[0069] The first dummy area is disposed along a first direction on both sides of the first electrostatic discharge area and the second fan-out area; the first direction is the gate line routing direction of the display area;

[0070] The second non-display area includes a third fan-out area, a second common line area, a second electrostatic discharge area, and a second dummy area; the third fan-out area is adjacent to the display area, and the second common line area is located on a side of the third fan-out area away from the display area; the second electrostatic discharge area is disposed between the third fan-out area and the second common line area;

[0071] The second dummy area is disposed along the first direction on both sides of the second electrostatic discharge area and the third fan-out area;

[0072] Dummy units are provided in the first dummy area and / or the second dummy area.

[0073] Pixel units are provided in the display area. The pixel units include red light pixels (R), green light pixels (G), and blue light pixels (B). Among them, the red light pixels emit red light, the green light pixels emit green light, and the blue light pixels emit blue light. The pixel units are arranged in a matrix form in the display substrate. The first direction is the gate line routing direction of the display area. The fan-out area is used for arranging data lines and signal lines. A plurality of electrostatic discharge units (ESD units) arranged in an array along the first direction are provided in the first electrostatic discharge area and the second electrostatic discharge area,

[0074] As Figure 5 shown, the first dummy area is a suspended area of the first non-display area, and the second dummy area is a suspended area of the second non-display area. The suspended area refers to an area where no devices or wire harnesses are provided. The suspended area forms a step difference with the electrostatic discharge area and the AA area.

[0075] In the first imitation area and / or the second imitation area, imitation units can be provided. The imitation units can be imitation electrostatic discharge units, imitation metals, or imitation metal wires. By means of the imitation units, the formation of height differences between the suspended area and the electrostatic discharge area and the AA area can be avoided as much as possible. In this way, during the production of the display panel, problems such as uneven damage to the surface hairs of the Rubbing cloth, which may lead to screen defects, can be avoided.

[0076] In a possible implementation manner, as Figure 6-1 shown, the first imitation area includes a first virtual electrostatic discharge area; the first virtual electrostatic discharge area is arranged on both sides of the first electrostatic discharge area along a first direction;

[0077] The imitation units include imitation electrostatic discharge units or imitation metal units.

[0078] As Figure 6-1 shown, there are suspended areas on both sides of the first electrostatic discharge area along the first direction. The suspended areas are the first virtual electrostatic discharge areas. In this area, imitation electrostatic discharge units or imitation metal units can be arranged in an array. For the arranged imitation units, see Figure 7 . Among them, the sizes of the imitation electrostatic discharge units or imitation metal units are preferably the same as those of the electrostatic discharge units. For example, the difference between the sizes of the imitation electrostatic discharge units or imitation metal units and the sizes of the electrostatic discharge units is not less than a preset difference value, which can be specifically set based on actual situations. In this way, the corresponding positions in the AA area are filled with imitation electrostatic discharge units or imitation metal units, thereby compensating for the height difference. The imitation electrostatic discharge units are electrical components that form electrical connections and can generate static electricity, while the imitation metal units are electrical components that do not form electrical connections and do not generate static electricity.

[0079] In a possible implementation manner, as Figure 6-1 shown, the second imitation area includes a second virtual electrostatic discharge area; the second virtual electrostatic discharge area is arranged on both sides of the second electrostatic discharge area along the first direction;

[0080] The imitation units include imitation electrostatic discharge units or imitation metal units.

[0081] As Figure 6-1As shown, there are suspended areas on both sides of the second electrostatic discharge area along the first direction. The suspended areas are the second virtual electrostatic discharge areas, and imitated electrostatic discharge units or imitated metal units can be arranged in these areas. Among them, the sizes of the imitated electrostatic discharge units or imitated metal units are preferably the same as those of the electrostatic discharge units. For example, the difference between the sizes of the imitated electrostatic discharge units or imitated metal units and those of the electrostatic discharge units is not less than a preset difference value, which can be specifically set based on the actual situation. The imitated electrostatic discharge units are electrical components forming electrical connections, and the imitated electrostatic discharge units can generate static electricity, while the imitated metal units are electrical components that do not form electrical connections, and the imitated metal units do not generate static electricity.

[0082] In a possible case, the imitated units filled in the first virtual electrostatic discharge area and / or the second virtual electrostatic discharge area are imitated electrostatic discharge units, and the imitated electrostatic discharge units include an active layer (Active layer).

[0083] That is to say, the imitated electrostatic discharge units include a gate line layer, a data signal layer, and an active layer, or the imitated electrostatic discharge units include a gate line layer, a data signal layer, a first conductive layer, and an active layer. Among them, the first conductive layer can be made of ITO (indium tin oxide, copper, or aluminum).

[0084] Imitated electrostatic discharge units are filled in the virtual electrostatic discharge area so that there are imitated electrostatic discharge units filled in the positions corresponding to the AA area, thereby compensating for the step difference.

[0085] In one example, as Figure 6-2 and Figure 6-3 shown, the imitated electrostatic discharge units including an active layer are also electrical components forming electrical connections. One end of the imitated electrostatic discharge unit is connected to a short circuit ring, and the other end of the imitated electrostatic discharge unit is suspended.

[0086] A short circuit ring is arranged in the display substrate to solve the electrostatic discharge problem in the display substrate, as Figure 8As shown, one end of the electrostatic discharge unit is connected to the short - circuit ring, and the other end of some of the electrostatic discharge units is connected to the common line (com), where com refers to Vcom1 in the first non - display area and Vcom2 in the second non - display area. The other end of some of the electrostatic discharge units is connected to different data lines, such as data1 and data2 shown in the figure. One end of the dummy electrostatic discharge unit (Dummy ESD) is connected to the short - circuit ring, and the other end of the dummy electrostatic discharge unit is floating. In the display substrate, a normally - used circuit structure is formed, that is, the number of TFTs between the short - circuit ring and the common line (the first common line / the second common line) changes from 4 levels to 4×(n + 1) parallel levels, where n is the number of added Dummy ESDs. When static electricity accumulates on the short - circuit ring or the data line, the dummy electrostatic discharge unit can act as a normally - used ESD unit, increasing the static - electricity release path. In this way, while avoiding the Rubbing Mura defect, electrostatic breakdown can also be avoided.

[0087] In one example, when there is an ADD line on the DPO side, the short - circuit ring on the DPO side is connected to the ADD line. Based on the actual wiring situation, to reduce the wiring difficulty and the length of the wiring, one end of the Dummy ESD on the DPO side can also be connected to the ADD line. By connecting to the ADD line, the static - electricity release path is increased. In this way, while avoiding the Rubbing Mura defect, electrostatic breakdown can also be avoided.

[0088] In one example, when one end of the dummy electrostatic discharge unit is connected to the short - circuit ring and the other end of the dummy electrostatic discharge unit is floating, the distance between the dummy electrostatic discharge units is greater than 10μm.

[0089] In one example, when one end of the dummy electrostatic discharge unit is connected to the short - circuit ring and the other end of the dummy electrostatic discharge unit is floating, the distance between the dummy units is the same as the distance between the electrostatic discharge units.

[0090] In one example, when one end of the dummy electrostatic discharge unit is connected to the short - circuit ring and the other end of the dummy electrostatic discharge unit is floating, the distance between the dummy electrostatic discharge units is less than the width of the electrostatic discharge unit and greater than 10μm.

[0091] In a possible implementation, as Figure 6-4 , the dummy electrostatic discharge unit including the active layer is an electrical component forming an electrical connection, and both ends of the dummy electrostatic discharge unit are floating.

[0092] As Figure 9As shown, the imitation electrostatic discharge unit is only filled for Rubbing Mura prevention and has no connection with the normal circuit in the substrate, and will not affect the electrical performance of the substrate. Since the imitation electrostatic discharge unit is provided with an Active layer, even if electrostatic accumulation occurs inside the imitation electrostatic discharge unit, when both ends of the imitation electrostatic discharge unit are suspended, it can be consumed within the imitation electrostatic discharge unit to avoid electrostatic breakdown.

[0093] In one example, when both ends of the imitation electrostatic discharge unit are suspended, the distance between the imitation electrostatic discharge units is greater than 10 μm to avoid electrostatic breakdown.

[0094] In a possible implementation manner, the imitation units filled in the first imitation electrostatic discharge area and / or the second imitation electrostatic discharge area are imitation electrostatic discharge units, and the imitation electrostatic discharge units do not include an active layer (Active layer).

[0095] That is to say, the imitation electrostatic discharge unit includes a gate line layer and a data signal layer, or the imitation electrostatic discharge unit includes a gate line layer, a data signal layer and a first conductive layer.

[0096] In a possible implementation manner, the imitation electrostatic discharge unit without an active layer is also an electrical component forming an electrical connection. One end of the imitation electrostatic discharge unit is connected to a short - circuit ring, and the other end of the imitation electrostatic discharge unit is suspended.

[0097] The thickness of the active layer is small and has little impact on the step difference, so there can be no active layer. As Figure 10 shown, the imitation electrostatic discharge unit can be connected to the short - circuit ring as a capacitor device. When there is electrostatic accumulation in the imitation electrostatic discharge unit, due to the capacitance coupling effect, the voltage will be conducted to the short - circuit ring. At this time, there is no voltage difference between the short - circuit ring and the Dummy ESD, and electrostatic breakdown will not occur, thus avoiding electrostatic breakdown.

[0098] In one example, when one end of the imitation electrostatic discharge unit is connected to a short - circuit ring and the other end of the imitation electrostatic discharge unit is suspended, the distance between the imitation electrostatic discharge units is greater than 10 μm.

[0099] In one example, when one end of the imitation electrostatic discharge unit is connected to a short - circuit ring and the other end of the imitation electrostatic discharge unit is suspended, the distance between the imitation units is the same as the distance between the electrostatic discharge units.

[0100] In one example, when one end of the imitation electrostatic discharge unit is connected to a short - circuit ring and the other end of the imitation electrostatic discharge unit is suspended, the distance between the imitation electrostatic discharge units is less than the width of the electrostatic discharge unit, and the distance between the imitation electrostatic discharge units is greater than 10 μm.

[0101] In a possible implementation, a dummy electrostatic discharge unit that does not include an active layer is also an electrical component that forms an electrical connection, and both ends of the dummy electrostatic discharge unit are suspended.

[0102] Such as Figure 11 , the dummy electrostatic discharge unit only serves as a filling for preventing Rubbing Mura and has no connection with the normal circuit in the substrate, and will not affect the electrical performance of the substrate. Since it does not include an active layer, when there is electrostatic accumulation, it cannot be consumed within the unit. It is necessary to increase the distance between the dummy electrostatic discharge unit and the short - circuit ring and the first common line. In one example, the distance between the dummy electrostatic discharge unit and the short - circuit ring, the first common line, and the second common line should be not less than 10 μm. For example, the distance between the dummy electrostatic discharge unit and the short - circuit ring, the first common line, and the second common line can be 10 μm to 55 μm to avoid electrostatic breakdown.

[0103] In one example, the distances between the dummy electrostatic discharge unit and the short - circuit ring, the first common line, and the second common line are 10 μm, 14 μm, 20 μm, 30 μm, 40 μm, 51 μm, and 55 μm.

[0104] In a possible implementation, such as Figure 6-5 shown, a dummy electrostatic discharge unit that does not include an active layer is also an electrical component that forms an electrical connection. One end of the dummy electrostatic discharge unit is connected to the short - circuit ring, and the other end of the dummy electrostatic discharge unit is connected to the common line.

[0105] That is to say, one end of the dummy electrostatic discharge unit arranged in the first dummy electrostatic discharge area is connected to the short - circuit ring, and the other end of the dummy electrostatic discharge unit is connected to the first common line.

[0106] One end of the dummy electrostatic discharge unit arranged in the second dummy electrostatic discharge area is connected to the short - circuit ring, and the other end of the dummy electrostatic discharge unit is connected to the second common line.

[0107] That is, the short - circuit ring and the common line are connected by a 4×n - stage capacitor structure. Such as Figure 12 , when there is electrostatic accumulation in the short - circuit ring, through the capacitance coupling effect, the voltage is conducted to the common line, so that there is no voltage difference between the two signal lines, avoiding electrostatic breakdown.

[0108] In a possible implementation, the dummy unit filled in the first virtual electrostatic discharge area and / or the second virtual electrostatic discharge area is a dummy metal unit. The dummy metal unit is an electrical component that does not form an electrical connection and does not generate static electricity. The corresponding positions in the AA area are all filled with dummy metal units to make up for the step difference.

[0109] In one example, the imitation metal unit may include a gate line layer and a data signal layer. The imitation metal unit may also include a gate line layer, a data signal layer, and a first conductive layer. The imitation metal unit may further include a gate line layer, a data signal layer, a first conductive layer, and an active layer.

[0110] The thicknesses of the first conductive layer and the active layer are small, and the influence on the Rubbing step difference is small. Therefore, the first conductive layer and the active layer may or may not be present. The imitation metal unit is a circuit device without electrical connection, and both ends of the imitation metal unit are suspended. The imitation metal unit can be disposed in the first virtual electrostatic discharge region and / or the second virtual electrostatic discharge region, without affecting the circuit connection within the substrate.

[0111] Using the imitation metal unit can compensate for the step difference and avoid the Rubbing Mura defect. Moreover, using the imitation metal unit instead of the imitation electrostatic discharge unit can reduce the cost of avoiding the Rubbing Mura defect.

[0112] In a possible implementation, as Figure 13 shown, the first imitation region includes a first virtual metal line region; the first virtual metal line region is disposed on both sides of the second fan-out region along a first direction; the imitation unit includes a virtual metal line.

[0113] In a possible implementation, as Figure 13 shown, the second imitation region includes a second virtual metal line region; the second virtual metal line region is disposed on both sides of the third fan-out region along a first direction; the imitation unit includes a virtual metal line.

[0114] There is a fan-out region (the second fan-out region for the first non-display region and the third fan-out region for the second non-display region) between the electrostatic discharge unit and the AA region. The fan-out regions (the second fan-out region and the third fan-out region) include fan-out lines, and the fan-out lines are data lines, signal lines, etc. of the fan-out region. As Figure 14 shown, Figure 14 is a schematic structural diagram of the fan-out lines in the fan-out region in the related art; this design exists on both the DP and DPO sides. Since the fan-out region is fan-out distributed, blank regions are left at both ends of the fan-out, resulting in a step difference. As Figure 13 shown by the first virtual metal line region and the second virtual metal line region, virtual metal lines can be added in the first virtual metal line region and / or the second virtual metal line region to compensate for the step difference, improve Rubbing Mura, and at the same time make the etching environment around the fan-out region more uniform, ensuring that the edge CD (Critical Dimension, line width) is consistent with the middle CD.

[0115] The virtual metal lines can be formed of metal and metal alloy materials commonly used in the art, which will not be elaborated here. The routing direction of the virtual metal lines can be parallel to the routing direction of the fan-out region. The width of the virtual metal lines is determined based on the width of the routing lines in the fan-out region. The difference between the width of the virtual metal lines and the width of the routing lines in the fan-out region is not less than a preset difference threshold, and the width of the virtual metal lines is preferably the same as the width of the routing lines in the fan-out region.

[0116] The pitch between the virtual metal lines can preferably be kept the same as the pitch between the routing lines in the fan-out region. That is to say, the virtual metal lines in the first virtual metal line region are parallel to the fan-out lines in the second fan-out region, the width of the virtual metal lines in the first virtual metal line region is the same as the width of the fan-out lines in the second fan-out region, the pitch between the virtual metal lines in the first virtual metal line region is the same as the pitch between the fan-out lines in the second fan-out region, the virtual metal lines in the second virtual metal line region are parallel to the fan-out lines in the third fan-out region, the width of the virtual metal lines in the second virtual metal line region is the same as the width of the fan-out lines in the third fan-out region, and the pitch between the virtual metal lines in the second virtual metal line region is the same as the pitch between the fan-out lines in the third fan-out region.

[0117] As Figure 15 shown, Figure 15 FIG. 2 is a second schematic structural diagram of the display substrate provided by the embodiment of the present application.

[0118] In a possible implementation, the pitch between the virtual metal lines and other metal lines is greater than 5 μm.

[0119] There may be short-circuit rings and common lines (first common line, second common line) around the virtual metal lines. The pitch between the virtual metal lines and other metal lines needs to be greater than 5 μm. In one example, the pitch between the virtual metal lines and other metal lines can be 5-20 μm, so as to avoid electrical problems caused by the too-close pitch between the virtual metal lines and other metal lines and ensure the safety of the display substrate.

[0120] As Figure 16 shown, the embodiment of the present application further provides a display panel 800, including the display substrate 801 described in any one of the above.

[0121] In a possible implementation, an alignment film is provided on the display substrate, and the alignment film is an optical alignment film or a rubbed alignment film.

[0122] The display panel includes a display substrate and an alignment film, and the alignment film is provided on the display substrate.

[0123] As Figure 17 shown, the embodiment of the present application further provides a display device 900, including the display panel 800 described in any one of the above.

[0124] It should be noted that, in this document, relational terms such as first and second are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the term "comprising", "including" or any other variant thereof is intended to cover non-exclusive inclusion, such that a process, method, article or device comprising a series of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such process, method, article or device. Without further limitation, an element defined by the statement "comprising an..." does not exclude the presence of additional identical elements in the process, method, article or device comprising said element.

[0125] Each embodiment in this specification is described in a related manner. For the same or similar parts among the embodiments, reference can be made to each other, and the differences between each embodiment and other embodiments are emphasized.

[0126] The above description is only a preferred embodiment of the present application and is not intended to limit the protection scope of the present application. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application are included within the protection scope of the present application.

Claims

1. A display substrate, characterized in that, Comprising: A display area, a first non-display area, and a second non-display area; The first non-display area includes a first fan-out area, a second fan-out area, a first common line area, a first electrostatic discharge area, and a first dummy area; the second fan-out area is adjacent to the display area, and the first fan-out area is located on the side of the second fan-out area away from the display area; the first common line area is disposed between the first fan-out areas; the first electrostatic discharge area is disposed between the first fan-out area and the second fan-out area; The first dummy area is disposed on both sides of the first electrostatic discharge area and the second fan-out area along a first direction; the first direction is the gate line routing direction of the display area; The second non-display area includes a third fan-out area, a second common line area, a second electrostatic discharge area, and a second dummy area; the third fan-out area is adjacent to the display area, and the second common line area is located on the side of the third fan-out area away from the display area; the second electrostatic discharge area is disposed between the third fan-out area and the second common line area; The second dummy area is disposed on both sides of the second electrostatic discharge area and the third fan-out area along the first direction; Dummy cells are provided in the first dummy area and / or the second dummy area.

2. The display substrate according to claim 1, wherein The first dummy area includes a first virtual electrostatic discharge area; the first virtual electrostatic discharge area is disposed on both sides of the first electrostatic discharge area along the first direction; The dummy cell includes a dummy electrostatic discharge cell or a dummy metal cell.

3. The display substrate according to claim 1, wherein The second dummy area includes a second virtual electrostatic discharge area; the second virtual electrostatic discharge area is disposed on both sides of the second electrostatic discharge area along the first direction; the dummy cell includes a dummy electrostatic discharge cell or a dummy metal cell.

4. The display substrate according to claim 1, wherein The first dummy area includes a first virtual metal line area; the first virtual metal line area is disposed on both sides of the second fan-out area along the first direction; the dummy cell includes a virtual metal line.

5. The display substrate according to claim 1, characterized in that, The second dummy area includes a second virtual metal line area; the second virtual metal line area is disposed on both sides of the third fan-out area along the first direction; the dummy cell includes a virtual metal line.

6. The display substrate according to claim 2 or 3, characterized in that, The dummy cell includes a gate line layer and a data signal layer.

7. The display substrate according to claim 6, wherein The dummy cell further includes a first conductive layer.

8. The display substrate according to claim 6, wherein, The dummy cell further includes an active layer.

9. The display substrate according to claim 7 or 8, characterized in that, One end of the dummy electrostatic discharge cell is connected to a shorting ring, and the other end of the dummy electrostatic discharge cell is floating.

10. The display substrate according to claim 7 or 8, characterized in that, Both ends of the dummy electrostatic discharge cell are floating.

11. The display substrate according to claim 6, characterized in that, One end of the dummy electrostatic discharge cell is connected to a shorting ring, and the other end of the dummy cell is connected to a common line.

12. The display substrate according to claim 2 or 3, characterized in that, The pitch between the dummy cells is the same as the pitch between the electrostatic discharge cells; or, the pitch between the dummy cells is less than the width of the electrostatic discharge cell, and the pitch between the dummy cells is greater than 10 μm.

13. The display substrate according to claim 4, wherein The virtual metal lines in the first virtual metal line area are parallel to the fan-out lines in the second fan-out area.

14. The display substrate according to claim 5, wherein The virtual metal lines in the second virtual metal line area are parallel to the fan-out lines in the third fan-out area.

15. The display substrate according to claim 13, wherein The width of the dummy metal lines in the first dummy metal line region is the same as the width of the fan-out lines in the second fan-out region, and the pitch between the dummy metal lines in the first dummy metal line region is the same as the pitch between the fan-out lines in the second fan-out region.

16. The display substrate according to claim 14, wherein The width of the dummy metal lines in the second dummy metal line region is the same as the width of the fan-out lines in the third fan-out region, and the pitch between the dummy metal lines in the second dummy metal line region is the same as the pitch between the fan-out lines in the third fan-out region.

17. A display panel, characterized in that, A display substrate according to any one of claims 1-16.

18. The display panel according to claim 17, wherein An alignment film is provided on the display substrate, and the alignment film is a photo-alignment film or a rubbed alignment film.

19. A display device, characterized in that, A display panel according to claim 17 or 18.

Images