Pixel level TDC with bidirectional counting fine conversion
Through bidirectional counting and fine conversion pixel-level TDC, the charge-to-digital conversion error problem caused by random incident photons is solved, and efficient pixel-level charge quantization is achieved, reducing data volume and power consumption, and improving readout rate.
Patent Information
- Application Number
- CN202510402797.6
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-04-01
- Publication Date
- 2025-07-04
AI Technical Summary
In the prior art, in the TOT-based energy measurement scheme, the rising and falling edges of the square wave output square wave caused by random events of incident photons cannot be aligned with the global clock clock edge, resulting in errors in charge-digital conversion, and high-resolution ADCs cannot be integrated in pixels, increasing data bandwidth, area and power consumption.
Using a pixel-level TDC with bidirectional counting fine conversion, through the combination of a local timing controller, a two-stage counter and a pixel-level voltage-controlled oscillator VCO, a coarse quantization and fine quantization counter are used to perform incremental and decrement counting respectively, to achieve the quantization of the time difference, reduce the number of counter bits and complete the fine measurement data calculation in the pixels.
Without losing measurement accuracy, the amount of data is reduced, the pixel area and power consumption is reduced, the digital signal processing steps are simplified, and the readout rate is improved.
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Figure CN120255303A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the technical field of time - to - digital converters (TDCs), and particularly to a pixel - level TDC adopting two - way counting fine conversion. Background Art
[0002] In the related art, grazing - incidence focusing X - ray imaging technology is an important means for solar X - ray astronomical observations. Among them, X - ray imaging payloads with an energy range of 3 - 80 keV generally use large - area array semiconductor pixel detectors. Such X - ray imaging detectors need to be equipped with pixel - type read - out ASICs (Application Specific Integrated Circuits) to complete the energy measurement of incident X - photons, and then study the laws of solar activities. When an incident X - photon bombards the detector, charges proportional to the photon energy are generated. The pixel - level analog front - end circuit reads out and amplifies the signal and quantifies the charges within an extremely short time, and finally converts them into digital signals for output. Generally, there are two ways of pixel - level charge - to - digital conversion: one is to convert the charge quantity into a voltage quantity and use an analog - to - digital converter (ADC) to convert it into a digital signal; the other is an energy measurement method based on the time - over - threshold (TOT), that is, quantifying the width of the square - wave signal output by the discriminator using a time - to - digital converter (abbreviation: TDC). Since the high - resolution ADC has a large area in the first way and cannot be integrated in the pixel, the latter way is the main solution for pixel - level charge quantization at present.
[0003] In the energy measurement scheme based on TOT, the traditional method is to use a high - frequency clock to drive a digital counter for measurement. Since the incident photons are a random event, there is a phenomenon that the rising edge and falling edge of the square - wave output by the discriminator in the analog front - end circuit cannot be aligned with the clock edge of the global clock. When quantifying using a TDC, it will cause errors in charge - to - digital conversion.
[0004] It should be noted that the information disclosed in the above background art section is only used to enhance the understanding of the background of the present invention, and thus may include information that does not constitute the prior art known to those of ordinary skill in the art. Summary of the Invention
[0005] The present invention provides a pixel - level TDC adopting two - way counting fine conversion, which can overcome the defects existing in the prior art to a certain extent.
[0006] Other features and advantages of the present invention will become apparent through the following detailed description, or will be partially learned through the practice of the present invention.
[0007] According to a first aspect of the present invention, there is provided a pixel-level TDC employing two-way counting fine conversion, comprising:
[0008] a local timing controller, a two-stage counter, and a pixel-level voltage-controlled oscillator VCO; wherein, the two-stage counter includes: a coarse quantization counter and a fine quantization counter;
[0009] The local timing controller is respectively connected to the two-stage counter and the pixel-level voltage-controlled oscillator VCO; the pixel-level voltage-controlled oscillator VCO is connected to the two-stage counter;
[0010] wherein, the local timing controller is configured to send a VCO enable control signal to the pixel-level voltage-controlled oscillator VCO; and, the local timing controller is configured to send a counting mode control signal to the two-stage counter;
[0011] The pixel-level voltage-controlled oscillator VCO is configured to generate a fine quantization counter drive clock signal and send it to the fine quantization counter.
[0012] In some exemplary embodiments, when the front-end output exceeds a set threshold, the discriminator outputs a square wave to the local timing controller; the local timing controller responds to the global clock signal and drives the coarse quantization counter to count to obtain coarse measurement data.
[0013] In some exemplary embodiments, when the VCO enable control signal is at a high level and the counting mode control signal is at a high level, the fine quantization counter increments;
[0014] when the VCO enable control signal is at a high level and the counting mode control signal is at a low level, the fine quantization counter decrements;
[0015] when the VCO enable control signal is at a low level, the output data of the fine quantization counter remains unchanged.
[0016] In some exemplary embodiments, the coarse quantization counter includes an 11-bit coarse quantization counter;
[0017] The fine quantization counter includes a 5-bit fine quantization counter.
[0018] In some exemplary embodiments, the coarse quantization counter is of an asynchronous structure and includes a plurality of flip-flops; wherein,
[0019] The clock signal is connected to the clock terminal of the first flip-flop, and the clock inputs of the subsequent flip-flops are driven by the output of the previous flip-flop.
[0020] In some exemplary embodiments, the fine quantization counter includes: an adder, a subtractor, a selector, and a D flip-flop; the input ends of the selector are respectively connected to the adder and the subtractor; the output end of the selector is connected to the D flip-flop;
[0021] Wherein, when the selector responds to a high-level direction control signal, it operates in an increment counting mode; when the selector responds to a low-level direction control signal, it operates in a decrement counting mode.
[0022] In some exemplary embodiments, the pixel-level voltage-controlled oscillator VCO includes a plurality of current-starved delay units and forms a ring oscillator structure.
[0023] In some exemplary embodiments, the local timing controller responds to a low-level reset signal to control each counter to be reset, the VCO enable control signal is at a low level, and the counting mode control signal is at a high level;
[0024] The local timing controller responds to a high-level reset signal to control the circuit to maintain an initial waiting state.
[0025] The pixel-level TDC adopting bidirectional counting fine conversion provided by the embodiments of the present invention connects the local timing controller to two-stage counters and the pixel-level voltage-controlled oscillator VCO respectively, and the pixel-level voltage-controlled oscillator VCO is connected to the two-stage counters; by using a two-stage counter to complete the quantization of the time difference t between the rising edge / falling edge of the square wave output by the discriminator and the rising edge of the clock rise and t fall , and can adopt an increment counting mode for the quantization of t rise , and a decrement counting mode for the quantization of t fall ; adopting a control principle and timing different from the prior art for the fine quantization counter can further compress the counter bits and reduce the data volume without sacrificing the measurement accuracy, and the fine quantization counter completes the calculation of the fine measurement data within the pixel, and the output is the final fine count data, reducing the digital signal processing steps from the original data.
[0026] It should be understood that the above general description and the following detailed description are only exemplary and explanatory, and cannot limit the present invention. BRIEF DESCRIPTION OF THE DRAWINGS
[0027] The drawings herein are incorporated into the specification and form a part of the specification, showing embodiments consistent with the present invention, and are used together with the specification to explain the principles of the present invention. Obviously, the drawings in the following description are only some embodiments of the present invention, and those of ordinary skill in the art can obtain other drawings based on these drawings without creative efforts.
[0028] Figure 1Schematic diagram showing a charge quantization method based on over-domain time;
[0029] Figure 2a Schematic diagram showing a pixel structure of a coarse-fine two-stage over-threshold time measurement scheme;
[0030] Figure 2b Schematic diagram showing a timing diagram of a coarse-fine two-stage over-threshold time measurement scheme;
[0031] Figure 3a Schematic diagram showing a circuit structure of a pixel-level TDC using bidirectional counting fine conversion according to an exemplary embodiment of the present invention;
[0032] Figure 3b Schematic diagram showing a timing control of a pixel-level TDC using bidirectional counting fine conversion according to an exemplary embodiment of the present invention;
[0033] Figure 4 Schematic diagram showing a data rate comparison under the same conditions according to an exemplary embodiment of the present invention;
[0034] Figure 5 Schematic diagram showing a power consumption comparison under the same conditions according to an exemplary embodiment of the present invention;
[0035] Figure 6 Schematic diagram showing an area comparison under the same conditions according to an exemplary embodiment of the present invention;
[0036] Figure 7 Schematic diagram showing the principle of a coarse counter according to an exemplary embodiment of the present invention;
[0037] Figure 8 Schematic diagram showing the principle of a bidirectional counter according to an exemplary embodiment of the present invention;
[0038] Figure 9 Schematic diagram showing the principle of a voltage-controlled oscillator according to an exemplary embodiment of the present invention;
[0039] Figure 10 Schematic diagram showing the state transition of a control logic according to an exemplary embodiment of the present invention. Detailed implementation manners
[0040] Example embodiments will now be described more fully with reference to the accompanying drawings. However, the example embodiments can be implemented in various forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided so that this invention will be more complete and comprehensive, and will fully convey the concept of the example embodiments to those skilled in the art. The features, structures, or characteristics described can be combined in any suitable manner in one or more embodiments.
[0041] In addition, the accompanying drawings are only schematic illustrations of the present invention and are not necessarily drawn to scale. The same reference numerals in the drawings denote the same or similar parts, and thus repeated descriptions thereof will be omitted. Some of the block diagrams shown in the drawings are functional entities and do not necessarily correspond to physically or logically independent entities. These functional entities may be implemented in software form, or implemented in one or more hardware modules or integrated circuits, or implemented in different networks and / or processor devices and / or microcontroller devices.
[0042] In the related art, in the energy measurement scheme based on TOT, the traditional method is to use a high-frequency clock to drive a digital counter for measurement. Since the incident photons are a random event, there is a phenomenon that the rising and falling edges of the square wave output by the discriminator in the analog front-end circuit cannot be aligned with the clock edges of the global clock. When using a TDC for quantization, it will cause errors in charge-digital conversion, as Figure 1 shown. Assume that the driving clock period is T clk_ref , and the time differences between the rising / falling edges of the square wave output by the discriminator and the rising edge of the clock are t rise and t fall Then the total measurement error is:
[0043] Δt error = t rise - t fall (1)
[0044] wherein, the maximum values of t rise and t fall are one clock period, i.e., T clk .
[0045] The total error Δt error ranges from:
[0046] - T clk_ref ≤ Δt error ≤ T clk_ref (2)
[0047] However, in this charge quantization method based on the over-domain time, in order to reduce the error, only the clock period can be reduced, that is, the clock frequency is increased, which will not only increase the dynamic power consumption, but also bring more interference to the analog circuit.
[0048] In addition, in some schemes, a two-stage coarse and fine counting type TDC scheme based on a voltage-controlled oscillator is proposed, and its pixel structure and timing diagram are as Figure 2a , Figure 2b shown. When the output of the analog front-end exceeds the set threshold, the discriminator outputs a square wave, and an 11-bit coarse quantization counter is used to count under the drive of the global clock (Clk_ref) to obtain coarse measurement data, denoted as Dc [10:0]. In order to accurately quantify t rise and t fall , a high-speed clock signal with a period of T clk_hf generated by the VCO is used. Two 4-bit fine quantization counters are used to count under the high-speed clock output by the VCO, so as to obtain the quantization data of t rise and t fall , which are respectively denoted as D f1 [3:0] and D f2 [3:0]. Then the total measurement time is:
[0049]
[0050] where t coarse is the counting time of the coarse quantization counter. The total measurement error range is:
[0051] -T clk_hf ≤Δt error ≤T clk_hf (4)
[0052] Since T clk_hf <<T clk_ref , the total measurement error is significantly reduced, thus improving the measurement accuracy. However, in this method, two counters with the same number of bits need to be added for fine measurement, which will introduce the following problems for a large array of pixel readout circuits: 1) additional data bandwidth overhead: Since fine measurement requires additional counting measurement, the data bit width of each pixel is 19 bits. When the array size is large, the data rate output by the serial interface also increases, thus increasing the bandwidth overhead of data transmission; 2) additional area and power consumption overhead: The use of two repeated counters for the fine quantization counter will bring additional area and dynamic power consumption overhead; 3) additional signal processing steps: As can be seen from formula (3), the fine measurement data in each data packet needs to be subtracted after being read out.
[0053] In view of the disadvantages and deficiencies of the prior art, an improved pixel-level analog front-end charge-digital conversion circuit is provided in this exemplary embodiment. By reducing the number of fine quantization counters, on the premise of achieving the same measurement accuracy, the data volume of pixel-level charge-digital conversion is reduced, thereby improving the readout rate of the entire pixel-type readout chip, reducing the pixel area and power consumption, and avoiding additional signal processing steps at the same time.
[0054] Next, the pixel-level TDC with two-way counting fine conversion in this exemplary embodiment will be described in more detail with reference to the accompanying drawings and embodiments.
[0055] In an exemplary embodiment, refer to Figure 3aAs shown in the figure, the pixel-level TDC adopting two-way counting fine conversion includes: a local timing controller (Local TCON), two-stage counters, and a pixel-level voltage-controlled oscillator VCO; among them, the local timing controller is used to implement local timing control logic; the two-stage counters include: a coarse quantization counter (Coarse_ToT) and a fine quantization counter (Fine_ToT); the local timing controller is respectively connected to the two-stage counters and the pixel-level voltage-controlled oscillator VCO; the pixel-level voltage-controlled oscillator VCO is connected to the two-stage counters. Among them, the local timing controller is used to send a VCO enable control signal to the pixel-level voltage-controlled oscillator VCO; and, the local timing controller is used to send a counting mode control signal to the two-stage counters; the pixel-level voltage-controlled oscillator VCO is used to generate a fine quantization counter drive clock signal and send it to the fine quantization counter.
[0056] Exemplarily, the coarse quantization counter includes an 11-bit coarse quantization counter; the fine quantization counter includes a 5-bit fine quantization counter.
[0057] Exemplarily, when the front-end output exceeds the set threshold, the discriminator outputs a square wave to the local timing controller; the local timing controller responds to the global clock signal and drives the coarse quantization counter to count to obtain coarse measurement data.
[0058] Exemplarily, when the VCO enable control signal is at a high level and the counting mode control signal is at a high level, the fine quantization counter increments its count;
[0059] When the VCO enable control signal is at a high level and the counting mode control signal is at a low level, the fine quantization counter decrements its count;
[0060] When the VCO enable control signal is at a low level, the output data of the fine quantization counter remains unchanged.
[0061] Specifically, the drive clock of the Fine_ToT counter is generated by the VCO, and the VCO enable control signal (EN_VCO) and the counting mode control signal (Up / Down) are generated through the Local TCON. When EN_VCO is at a high level and Up / Down is at a high level, the Fine_ToT counter increments its count; when EN_VCO is at a high level and Up / Down is at a low level, the Fine_ToT counter decrements its count; when EN_VCO is at a low level, the output data of the Fine_ToT counter remains unchanged.
[0062] When the front-end output exceeds the set threshold, the discriminator outputs a square wave, and an 11-bit coarse quantization counter counts under the drive of the global clock (Clk_ref) to obtain coarse measurement data, denoted as Dc[10:0].
[0063] Exemplarily, the coarse quantization counter is of an asynchronous structure and includes a plurality of flip - flops; wherein, a clock signal is connected to the clock terminal of the first flip - flop, and the clock inputs of subsequent flip - flops are driven by the output of the previous flip - flop.
[0064] Specifically, the schematic diagram of the 11 - bit coarse counter is as Figure 7 shown. This counter adopts an asynchronous structure. The clock CLK is connected to the clock terminal of the first flip - flop, while the clock inputs of subsequent flip - flops are driven by the output of the previous flip - flop. In an asynchronous counter, the clock beats of each flip - flop are different. When a counting pulse signal is input, the outputs of each flip - flop will be gradually updated asynchronously. And the operation of an asynchronous counter does not require continuous clock triggering, avoiding the interference of digital clocks on analog signals, and is suitable for mixed - signal integrated circuits with low - noise requirements.
[0065] Exemplarily, the fine quantization counter includes: an adder, a subtractor, a selector, and a D flip - flop; the input terminals of the selector are respectively connected to the adder and the subtractor; the output terminal of the selector is connected to the D flip - flop;
[0066] wherein, when the response direction control signal of the selector is at a high level, it operates in the increment counting mode; when the response direction control signal of the selector is at a low level, it operates in the decrement counting mode.
[0067] Specifically, the schematic diagram of the 5 - bit bidirectional counter is as Figure 8 shown, which is composed of an adder, a subtractor, a selector, and a D flip - flop. Different from an increment counter, this can simultaneously implement the increment and decrement counting functions. When the direction control signal (DIR) in the bidirectional counter is at a high level, it operates in the increment counting mode; conversely, it operates in the decrement counting mode.
[0068] Exemplarily, the pixel - level voltage - controlled oscillator VCO includes a plurality of current - starved delay cells and forms a ring oscillator structure.
[0069] Specifically, the voltage - controlled oscillator adopts a ring oscillator structure composed of current - starved delay cells, and the complete circuit is as Figure 9 shown. The first three inverter delay cells composed of transistors M1 - M3 are in a current - starved connection form, and the remaining inverter cell composed of M4 is biased at the power supply voltage. Transistors M5 / M6 are placed in the path from the power supply to the ground of the delay inverter cell to limit the pull - up / pull - down current. The external enable signal controls whether the voltage - controlled oscillator circuit oscillates through transistor M7.
[0070] Exemplarily, the local timing controller responds to a low-level reset signal, controls each counter to be reset, the VCO enable control signal is at a low level, and the counting mode control signal is at a high level; the local timing controller responds to a high-level reset signal, and the control circuit maintains the initial waiting state.
[0071] Specifically, the timing control logic is generated by Local TCON and has the following several states. The state transition diagram is as Figure 10 shown.
[0072] IDLE: When the circuit detects that the reset signal is low, all counters are reset, the EN_VCO enable signal is pulled low, and the Up / Down signal is pulled high; when the circuit detects that the reset signal is high, the circuit is in the initial waiting state, and the circuit remains in this state until the rising edge of the Trigger signal arrives, and the circuit transfers from IDLE to STATE1 to prepare for subsequent counting operations.
[0073] STATE1: When the rising edge of the Trigger signal arrives, EN_VCO is pulled high, the VCO starts, and the fine counter Fine_TOT performs incremental counting under the clock output by the VCO. The circuit will remain in this state until the rising edge of the external clock Clk_ref arrives, EN_VCO is pulled low, the VCO stops working, and at this time the fine counter Fine_TOT stops counting.
[0074] STATE2: After the rising edge of Trigger arrives, when the first rising edge of the external clock Clk_ref arrives, the coarse counter starts to perform incremental counting. The circuit remains in this state until the falling edge of Trigger arrives, and the coarse counter stops counting.
[0075] STATE3: When the falling edge of Trigger arrives, EN_VCO is pulled high, the VCO restarts, and the fine counter starts to perform decremental counting from the previous incremental counting result. The circuit maintains this state until it detects the next rising edge of the external clock Clk_ref, EN_VCO is pulled low, the VCO stops working, and the fine counter stops counting.
[0076] STATE4: When Trigger and EN_VCO are both low, the counter stops counting, the circuit enters the waiting state, and waits for the counting data to be read. After the data is read, the circuit will be reset to the IDLE state.
[0077] For example, the output data rates under different array scales are as Figure 4 shown. When the pixel size is 75×75μm 2 , and the incident photon flux is 1 Mcps / cm 2, under the same condition that the VCO oscillation frequency is 16 times the global reference clock, compared with the data rate generated by the fine quantization counter when the same accuracy is achieved in Document [1] (i.e., the above-mentioned existing two-stage coarse-fine counting type TDC scheme based on a voltage-controlled oscillator), the data rate of the present invention decreases significantly under different array scales. Under the 512×512 array, the data rate of the output interface is reduced to 62.2% of the scheme in Document [1]. The area and power consumption comparison results are shown respectively in Figure 5 and Figure 6 as shown. Implemented using a 130-nanometer CMOS process, the area and power consumption of the TDC circuit proposed by the present invention are reduced to 82.9% and 70.9% of those in Document [1] respectively.
[0078] The present invention realizes the improvement of the existing two-stage coarse-fine counting type time-to-digital conversion scheme. Compared with the existing technology, the present invention can further compress the counter bits to reduce the data volume without sacrificing the measurement accuracy, and the fine quantization counter completes the calculation of the fine measurement data within the pixel and outputs the final fine count data, reducing the digital signal processing steps from the original data.
[0079] The pixel-level TDC with bidirectional counting fine conversion provided by the embodiment of the present invention only uses one bidirectional counter to complete the quantization of t rise and t fall , where the quantization of t rise adopts an increment counting mode, and the quantization of t fall adopts a decrement counting mode. Different counting modes are selected by detecting the rising edge and falling edge of the output signal of the discriminator, so as to complete the fine measurement time difference operation within the pixel and finally output t rise -t fall time difference data. When t rise <t fall , the time difference is negative, so an additional sign bit needs to be added, that is, the highest bit of the fine quantization counter is used as the sign bit. Thus, the working principle and timing of the fine quantization counter completely different from the existing technology are realized.
[0080] Specifically, in response to the requirements of pixel-level charge measurement and quantization in large-array pixel-type readout integrated circuits, the present invention proposes a new two-stage pixel-level time-to-digital conversion scheme based on the over-domain time measurement method. By using only one counter, the fine time quantization in over-domain time measurement is realized, effectively solving the problem of high data rate caused by the large pixel quantization bit width in large-area array pixel-type readout integrated circuits. In the scheme proposed by the present invention, a bidirectional counter is used to replace the two increment counters in the prior art. On the premise of ensuring the same measurement accuracy as the existing scheme, the single-pixel data volume is further compressed, thereby compressing the pixel array data volume to optimize the area and power consumption, and simplifying the subsequent data processing. The scheme proposed by the present invention can also be used for time-to-digital conversion in other applications.
[0081] It should be noted that the above-mentioned drawings are only schematic illustrations of the processes included in the method according to the exemplary embodiments of the present invention, rather than for limiting purposes. It is easy to understand that the processes shown in the above-mentioned drawings do not indicate or limit the time sequence of these processes. Additionally, it is also easy to understand that these processes can be executed synchronously or asynchronously in, for example, multiple modules.
[0082] It should be noted that although several modules or units of devices for action execution are mentioned in the above detailed description, such a division is not mandatory. In fact, according to the embodiments of the present invention, the features and functions of the two or more modules or units described above can be embodied in one module or unit. Conversely, the features and functions of one module or unit described above can be further divided and embodied by multiple modules or units.
[0083] Those skilled in the art will readily think of other embodiments of the present invention after considering the specification and practicing the invention herein. This application is intended to cover any variations, uses, or adaptations of the present invention, which follow the general principles of the present invention and include well-known common knowledge or conventional technical means in the technical field not disclosed by the present invention. The specification and embodiments are only regarded as exemplary, and the true scope and spirit of the present invention are pointed out by the claims.
[0084] It should be understood that the present invention is not limited to the exact structures described above and shown in the drawings, and various modifications and changes can be made without departing from its scope. The scope of the present invention is only limited by the appended claims.
Claims
1. A pixel-level TDC using bidirectional counting fine conversion, characterized in that, Comprising: A local timing controller, a two-stage counter, and a pixel-level voltage-controlled oscillator VCO; wherein, the two-stage counter includes: a coarse quantization counter and a fine quantization counter; The local timing controller is respectively connected to the two-stage counter and the pixel-level voltage-controlled oscillator VCO; the pixel-level voltage-controlled oscillator VCO is connected to the two-stage counter; Wherein, the local timing controller is used to send a VCO enable control signal to the pixel-level voltage-controlled oscillator VCO; and, the local timing controller is used to send a counting mode control signal to the two-stage counter; The pixel-level voltage-controlled oscillator VCO is used to generate a fine quantization counter driving clock signal and send it to the fine quantization counter.
2. The pixel-level TDC using two-way counting fine conversion according to claim 1, characterized in that When the front-end output exceeds the set threshold, the discriminator outputs a square wave to the local timing controller; the local timing controller responds to the global clock signal and drives the coarse quantization counter to count to obtain coarse measurement data.
3. The pixel-level TDC using two-way counting fine conversion according to claim 1, characterized in that When the VCO enable control signal is at a high level and the counting mode control signal is at a high level, the fine quantization counter increments; When the VCO enable control signal is at a high level and the counting mode control signal is at a low level, the fine quantization counter decrements; When the VCO enable control signal is at a low level, the output data of the fine quantization counter remains unchanged.
4. The pixel-level TDC using two-way counting fine conversion according to claim 1, wherein, The coarse quantization counter includes an 11-bit coarse quantization counter; The fine quantization counter includes a 5-bit fine quantization counter.
5. The pixel-level TDC using two-way counting fine conversion according to claim 1 or 4, characterized in that The coarse quantization counter is of an asynchronous structure and includes a plurality of flip-flops; Wherein, the clock signal is connected to the clock terminal of the first flip-flop, and the clock input of the subsequent flip-flops is driven by the output of the previous flip-flop.
6. The pixel-level TDC using two-way counting fine conversion according to claim 1 or 4, characterized in that The fine quantization counter includes: an adder, a subtractor, a selector, and a D flip-flop; the input terminals of the selector are respectively connected to the adder and the subtractor; the output terminal of the selector is connected to the D flip-flop; Wherein, when the selector responds to the direction control signal being at a high level, it works in the increment counting mode; when the selector responds to the direction control signal being at a low level, it works in the decrement counting mode.
7. The pixel-level TDC using two-way counting fine conversion according to claim 1, characterized in that The pixel-level voltage-controlled oscillator VCO includes a plurality of current-starved delay cells and forms a ring oscillator structure.
8. The pixel-level TDC using two-way counting fine conversion according to claim 1, characterized in that The local timing controller responds to a low-level reset signal to control each counter to be reset, the VCO enable control signal is at a low level, and the counting mode control signal is at a high level; The local timing controller responds to a high-level reset signal to control the circuit to maintain the initial waiting state.