Redundancy processing device

Abstract

The invention relates to a redundancy processing device. The redundancy processing device comprises a sampling circuit, a processing circuit and a centering circuit which are connected in sequence, the sampling circuit is used for carrying out signal sampling on the sampling points to obtain a plurality of to-be-processed signals; the processing circuit is used for outputting a plurality of candidate sampling signals of the plurality of to-be-processed signals; the middle taking circuit is used for outputting a target sampling signal according to the plurality of candidate sampling signals; the target sampling signal is not a maximum signal and a minimum signal in the plurality of candidate sampling signals. According to the redundancy processing device, redundancy processing of key signals is carried out on the signals output by the sampling circuit in an analog circuit mode, and the reliability of the sampling circuit is improved to a certain extent.

Description

Technical Field

[0001] This application relates to the technical field of DC power supplies for energy storage systems, and particularly to a redundancy processing device. Background Art

[0002] Energy storage systems have high requirements for reliability and usually design many protection logics and protection circuits. Common protection logics and protection circuits need to collect signals through a sampling circuit. If the sampling circuit has problems, it will cause the upper protection logic and protection circuit to malfunction or even fail to operate. Therefore, improving the reliability of the sampling circuit has high engineering value for enhancing the reliability of the energy storage system.

[0003] Therefore, how to improve the reliability of the sampling circuit has become an urgent problem to be solved in the current application of energy storage systems. Summary of the Invention

[0004] Based on this, in view of the above technical problems, it is necessary to provide a redundancy processing device that can improve the reliability of the sampling circuit.

[0005] In a first aspect, this application provides a redundancy processing device. The redundancy processing device includes: a sampling circuit, a processing circuit, and a median circuit connected in sequence;

[0006] The sampling circuit is configured to sample signals at sampling points to obtain a plurality of signals to be processed; the plurality of signals to be processed includes at least three signals to be processed;

[0007] The processing circuit is configured to output a plurality of candidate sampling signals of the plurality of signals to be processed;

[0008] The median circuit is configured to output a target sampling signal according to the plurality of candidate sampling signals; the target sampling signal is not the maximum signal and the minimum signal among the plurality of candidate sampling signals.

[0009] The redundancy processing device described in the embodiments of this application realizes the redundant processing of key signals for the signals output by the sampling circuit in an analog circuit manner, that is, it realizes the screening of normal sampling signals in the case of any one or any two faulty signals, and improves the reliability of the sampling circuit to a certain extent. In addition, the above redundancy processing device uses an analog circuit manner for redundant processing. Compared with a digital circuit, its operation speed is faster than the delay of the digital conversion circuit, and the signal noise can effectively avoid the phenomenon of the digital chip program running wild due to the digital signal processing scheme, which improves the reliability of the sampling circuit from another aspect.

[0010] In one embodiment, the multiple candidate sampling signals include a sum signal, a signal with the maximum intensity, and a signal with the minimum intensity. The processing circuit includes: a summing circuit and a gating circuit; the sampling circuit is respectively connected to the summing circuit and the gating circuit, and both the summing circuit and the gating circuit are also connected to the median circuit;

[0011] The summing circuit is configured to perform a summation operation on the multiple signals to be processed and output the sum signal of the multiple signals to be processed;

[0012] The gating circuit is configured to gate the multiple signals to be processed and output the signal with the maximum intensity and the signal with the minimum intensity among the multiple signals to be processed.

[0013] The processing circuit described in the embodiments of the present application realizes redundant processing of key signals for the signals output by the sampling circuit in an analog circuit manner by setting an analog circuit of a summing circuit and a gating circuit, that is, it realizes screening out normal sampling signals in the case of any one - path failure or any two - path failure signals, and improves the reliability of the sampling circuit to a certain extent.

[0014] In one embodiment, the gating circuit includes: a maximum gating circuit and a minimum gating circuit; the sampling circuit is respectively connected to the maximum gating circuit and the minimum gating circuit;

[0015] The maximum gating circuit is configured to output the signal with the maximum intensity among the multiple candidate sampling signals according to the signal intensities of the multiple candidate sampling signals;

[0016] The minimum gating circuit is configured to output the signal with the minimum intensity among the multiple candidate sampling signals according to the signal intensities of the multiple candidate sampling signals.

[0017] The processing circuit described in the embodiments of the present application realizes redundant processing of key signals for the signals output by the sampling circuit in an analog circuit manner by setting an analog circuit of a summing circuit, a maximum gating circuit, and a minimum gating circuit, that is, it realizes screening out normal sampling signals in the case of any one - path failure or any two - path failure signals, and improves the reliability of the sampling circuit to a certain extent.

[0018] In one embodiment, the redundancy processing device further includes: a scaling circuit and a restoration circuit; the scaling circuit is respectively connected to the sampling circuit and the processing circuit; the median circuit is connected to the restoration circuit;

[0019] The scaling circuit is configured to perform a reduction processing on each of the signals to be processed by a preset multiple;

[0020] The reduction circuit is used to perform reduction processing on the target sampling signal output by the middle-taking circuit to obtain the reduced target sampling signal.

[0021] In the redundant processing device described in the embodiments of the present application, by setting a scaling circuit and a reduction circuit, the voltage of the input signal input to the processing circuit can match the power supply range of the processing circuit, so that the processing circuit can accurately process the signal to be processed, thereby improving the signal processing accuracy of the redundant processing device.

[0022] In one embodiment, the sampling circuit includes a plurality of sub-sampling circuits; the plurality of sub-sampling circuits are all connected to the processing circuit;

[0023] The plurality of sub-sampling circuits are used to perform signal sampling at different times for the same sampling point to obtain the signals to be processed corresponding to the respective sub-sampling circuits;

[0024] Alternatively, different sub-sampling circuits are used to perform signal sampling for different sampling points to obtain the signals to be processed corresponding to the respective sub-sampling circuits.

[0025] The sampling circuit described in the embodiments of the present application includes a plurality of sub-sampling circuits, which can realize sampling of multiple sampling points or multiple samplings of the same sampling point, and use the provided processing circuit to process the signals of multiple sampling points or the multiple sampling signals of the same sampling point, realizing redundant processing of key signals for the signals output by the plurality of sub-sampling circuits in an analog circuit manner, that is, screening out normal sampling signals in the case of any one path failure or any two path failure signals, and improving the reliability of the sampling circuit to a certain extent.

[0026] In one embodiment, the sampling circuit includes a first sub-sampling circuit, a second sub-sampling circuit, and a third sub-sampling circuit; the first sub-sampling circuit, the second sub-sampling circuit, and the third sub-sampling circuit are all connected to the processing circuit;

[0027] The first sub-sampling circuit is used to perform the first signal sampling for the same sampling point to obtain the signal to be processed corresponding to the first sub-sampling circuit; the second sub-sampling circuit is used to perform the second signal sampling for the same sampling point to obtain the signal to be processed corresponding to the second sub-sampling circuit; the third sub-sampling circuit is used to perform the third signal sampling for the same sampling point to obtain the signal to be processed corresponding to the third sub-sampling circuit;

[0028] Alternatively, the first sampling sub - circuit is used to sample a signal at a first sampling point to obtain a signal to be processed corresponding to the first sampling sub - circuit; the second sampling sub - circuit is used to sample a signal at a second sampling point to obtain a signal to be processed corresponding to the second sampling sub - circuit; the third sampling sub - circuit is used to sample a signal at a third sampling point to obtain a signal to be processed corresponding to the third sampling sub - circuit.

[0029] The redundancy processing device described in the embodiments of the present application is composed of three input signals, a scaling circuit, a summing circuit, a maximum gating circuit, a minimum gating circuit, and a restoration circuit. It realizes taking the intermediate value among the three input signals by extracting the sum signal, the signal with the maximum intensity, and the signal with the minimum intensity, realizes redundant processing of the input signals, and removes the signals that are prone to anomalies, thereby improving the sampling accuracy.

[0030] In one embodiment, the maximum gating circuit includes: a plurality of maximum gating operational amplifiers, a plurality of maximum conducting devices, and a first follower;

[0031] The plurality of maximum gating operational amplifiers are connected in parallel, and the input terminals of each of the maximum gating operational amplifiers are connected to the sampling circuit. The output terminals of each of the maximum gating operational amplifiers are connected to each of the maximum conducting devices, and each of the maximum conducting devices is connected to the first follower.

[0032] In one embodiment, the plurality of maximum gating operational amplifiers include: a first maximum gating operational amplifier, a second maximum gating operational amplifier, and a third maximum gating operational amplifier; the plurality of maximum conducting devices include a first maximum conducting device, a second maximum conducting device, and a third maximum conducting device;

[0033] The first maximum gating operational amplifier, the second maximum gating operational amplifier, and the third maximum gating operational amplifier are connected in parallel; the positive input terminals of the first maximum gating operational amplifier, the second maximum gating operational amplifier, and the third maximum gating operational amplifier are respectively connected to the sampling circuit;

[0034] The output terminal of the first maximum gating operational amplifier is connected to the first maximum conducting device, the output terminal of the second maximum gating operational amplifier is connected to the second maximum conducting device, and the output terminal of the third maximum gating operational amplifier is connected to the third maximum conducting device;

[0035] The first maximum conducting device, the second maximum conducting device, and the third maximum conducting device are all connected to the first follower.

[0036] The maximum gating circuit described in the embodiments of the present application realizes the gating of the maximum-intensity signal through an analog circuit by setting up an operational amplifier, a conductor, and a follower. Compared with the digital circuit implementation method, the maximum gating circuit has a faster response and less signal noise, which improves the reliability of the redundancy processing device to a certain extent.

[0037] In one embodiment, the minimum gating circuit includes: a plurality of minimum gating operational amplifiers, a plurality of minimum conducting devices, and a second follower;

[0038] The plurality of minimum gating operational amplifiers are connected in parallel, and the input terminals of each of the minimum gating operational amplifiers are connected to the sampling circuit. The output terminals of each of the minimum gating operational amplifiers are connected to each of the minimum conducting devices, and each of the minimum conducting devices is connected to the second follower.

[0039] In one embodiment, the plurality of minimum gating operational amplifiers include: a first minimum gating operational amplifier, a second minimum gating operational amplifier, and a third minimum gating operational amplifier; the plurality of minimum conducting devices include a first minimum conductor, a second minimum conductor, and a third minimum conductor;

[0040] The first minimum gating operational amplifier, the second minimum gating operational amplifier, and the third minimum gating operational amplifier are connected in parallel; the positive input terminals of the first minimum gating operational amplifier, the second minimum gating operational amplifier, and the third minimum gating operational amplifier are respectively connected to the sampling circuit;

[0041] The output terminal of the first minimum gating operational amplifier is connected to the first minimum conductor, the output terminal of the second minimum gating operational amplifier is connected to the second minimum conductor, and the output terminal of the third minimum gating operational amplifier is connected to the third minimum conductor. The first minimum conductor, the second minimum conductor, and the third minimum conductor are all connected to the second follower.

[0042] The minimum gating circuit described in the embodiments of the present application realizes the gating of the minimum-intensity signal through an analog circuit by setting up an operational amplifier, a conductor, and a follower. Compared with the digital circuit implementation method, the minimum gating circuit has a faster response and less signal noise, which improves the reliability of the redundancy processing device to a certain extent.

[0043] In one embodiment, the minimum gating circuit further includes a resistor; the resistor is respectively connected to the first minimum conductor, the positive input terminal of the second follower, and the power supply.

[0044] The above description is only an overview of the technical solution of the present application. In order to understand the technical means of the present application more clearly, it can be implemented according to the content of the specification. And in order to make the above and other purposes, features and advantages of the present application more obvious and understandable, the specific embodiments of the present application are hereinafter specifically exemplified. Description of the Drawings

[0045] By reading the following detailed description of the preferred embodiments, various other advantages and benefits will become clear to those of ordinary skill in the art. The drawings are only for the purpose of showing the preferred embodiments and are not considered to be a limitation of the present application. And in all the drawings, the same reference numerals are used to represent the same components. In the drawings:

[0046] Figure 1 It is a schematic structural diagram of a redundancy processing device in one embodiment;

[0047] Figure 2 It is a schematic structural diagram of a redundancy processing device in another embodiment;

[0048] Figure 3 It is a schematic structural diagram of a redundancy processing device in another embodiment;

[0049] Figure 4 It is a schematic structural diagram of a redundancy processing device in another embodiment;

[0050] Figure 5 It is a schematic structural diagram of a redundancy processing device in another embodiment;

[0051] Figure 6 It is a schematic structural diagram of a redundancy processing device in another embodiment;

[0052] Figure 7 It is a schematic structural diagram of a maximum gating circuit in one embodiment;

[0053] Figure 8 It is a schematic structural diagram of a minimum gating circuit in one embodiment. Detailed Embodiments

[0054] In order to make the purpose, technical solution and advantages of the present application clearer, the present application will be further described in detail below with reference to the drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.

[0055] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the technical field to which this application belongs; the terms used herein are for the purpose of describing specific embodiments only and are not intended to limit this application; the terms "including" and "having" and any variations thereof in the specification and claims of this application and the above drawings are intended to cover non-exclusive inclusion.

[0056] In the description of the embodiments of this application, technical terms such as "first" and "second" are only used to distinguish different objects and cannot be understood as indicating or implying relative importance or implicitly indicating the quantity, specific order or primary-secondary relationship of the indicated technical features. In the description of the embodiments of this application, the meaning of "a plurality" is two or more unless otherwise specifically defined.

[0057] Referring to "embodiments" herein means that the specific features, structures or characteristics described in connection with the embodiments can be included in at least one embodiment of this application. The phrase appears in various places in the specification and does not necessarily refer to the same embodiment, nor is it an independent or alternative embodiment mutually exclusive with other embodiments. Those skilled in the art will explicitly and implicitly understand that the embodiments described herein can be combined with other embodiments.

[0058] Existing energy storage systems have high requirements for reliability and usually design a lot of protection logics and protection circuits. Common protection logics and protection circuits need to collect signals through a sampling circuit. If there is a problem with the sampling circuit, it will cause the upper-layer protection logic and protection circuit to malfunction or even fail to operate. Therefore, improving the reliability of the sampling circuit has high engineering value for improving the reliability of the energy storage system. In the field of digital circuits, in order to achieve reliable operation of protection signals, a two-out-of-three circuit is often used to improve the reliability of protection signals when any two or more signals are fault-free. However, in the field of analog circuits, if a similar two-out-of-three logic is to be implemented, the three analog signals need to be digitally processed, but using digital processing has risks such as long AD conversion time, AD conversion signal noise, and restart of the digital processing chip, and the signal noise, real-time performance, and reliability of the corresponding solution are not ideal. To address this problem, the embodiments of this application provide a redundancy processing device that can improve the reliability of the sampling circuit, and the following embodiments will illustrate this redundancy processing device.

[0059] In one embodiment, Figure 1An embodiment is a redundancy processing device 1, which includes: a sampling circuit 10, a processing circuit 20, and a median circuit 30 connected in sequence; the sampling circuit 10 is used to sample signals at sampling points to obtain a plurality of signals to be processed; the processing circuit 20 is used to output a plurality of candidate sampling signals of the plurality of signals to be processed; the median circuit 30 is used to output a target sampling signal according to the plurality of candidate sampling signals; the target sampling signal is not the maximum signal and the minimum signal among the plurality of candidate sampling signals.

[0060] The above-mentioned sampling circuit 10 is specifically used to perform signal sampling on the same sampling point multiple times to obtain a plurality of signals to be processed after multiple samplings; optionally, the above-mentioned sampling circuit 10 can also be used to perform signal sampling on different sampling points to obtain signals to be processed corresponding to different sampling points.

[0061] The above-mentioned processing circuit 20 is specifically used to screen and process a plurality of signals to be processed according to the signal intensities of the plurality of signals to be processed, and obtain a plurality of candidate sampling signals after screening and processing. The plurality of signals to be processed includes at least three signals to be processed.

[0062] The above-mentioned median circuit 30 is specifically used to perform a median process on the plurality of candidate sampling signals, that is, select a signal with a signal intensity value in the middle among the plurality of candidate sampling signals, that is, obtain the target sampling signal. Among them, the target sampling signal is not the maximum signal and the minimum signal among the plurality of candidate sampling signals, the maximum signal is the signal with the largest signal intensity value among the plurality of candidate sampling signals, and the minimum signal is the signal with the smallest signal intensity value among the plurality of candidate sampling signals. Optionally, the above-mentioned median circuit 30 is specifically used to perform a median process on the plurality of candidate sampling signals, initially select a signal with a signal intensity value in the middle among the plurality of candidate sampling signals. If the signals in the middle are multiple signals, the median circuit 30 can further screen the multiple signals in the middle by comparing the signal intensities of the multiple signals in the middle, and screen out the signal with the middle value among the multiple signals in the middle, and finally screen out the target sampling signal.

[0063] In the embodiments of the present application, the sampling circuit 10 performs multiple signal samplings on the same sampling point, or performs different signal samplings on different sampling points, to obtain multiple signals to be processed, and sends the multiple signals to be processed to the processing circuit 20. The processing circuit 20 screens and processes the multiple signals to be processed, screens out the maximum signal and the minimum signal among the multiple signals to be processed, and outputs the multiple signals to be processed at the same time. Then, the median circuit 30 screens out the signal with the intermediate signal strength value from the multiple signals to be processed according to the maximum signal and the minimum signal; optionally, the processing circuit 20 can also screen and process the multiple signals to be processed, screen out the maximum signal and the minimum signal among the multiple signals to be processed, and perform a sum operation on the multiple signals to be processed to obtain a sum signal. Then, the median circuit 30 performs further processing on the maximum signal, the minimum signal, and the sum signal to obtain the target sampling signal. It should be noted that at least one comparator can be set in the processing circuit 20, so that the processing circuit 20 can screen and process the multiple signals to be processed by comparing the signal strengths of the multiple signals to be processed, so as to output multiple candidate sampling signals; at least one operational amplifier, at least one proportional amplifier, at least one follower, at least one various types of arithmetic units, etc. can be set in the processing circuit 20, so that the processing circuit 20 can screen and process the multiple signals to be processed by performing operations on the multiple signals to be processed, so as to output multiple candidate sampling signals.

[0064] The redundancy processing device described in the embodiments of the present application realizes the redundancy processing of key signals for the signals output by the sampling circuit in an analog circuit manner, that is, it realizes the screening of normal sampling signals in the case of any one-way failure or any two-way failure signals, and improves the reliability of the sampling circuit to a certain extent. In addition, the above redundancy processing device uses an analog circuit method for redundancy processing. Compared with a digital circuit, its operation speed is faster than the delay of the digital conversion circuit, and the signal noise can effectively avoid the phenomenon of the digital chip program running wild due to the digital signal processing scheme, which improves the reliability of the sampling circuit from another aspect.

[0065] In one embodiment, when the above multiple candidate sampling signals include a sum signal, a signal with the maximum strength, and a signal with the minimum strength, a corresponding processing circuit 20 is provided, such as Figure 2 shown. The processing circuit 20 includes a summing circuit 201 and a gating circuit 202; the sampling circuit 10 is respectively connected to the summing circuit 201 and the gating circuit 202, and the summing circuit 201 and the gating circuit 202 are also both connected to the median circuit 30.

[0066] Among them, the summing circuit 201 is used to perform a sum operation on the multiple signals to be processed and output the sum signal of the multiple signals to be processed. For example, the multiple signals to be processed are 、 、......、 After the summing circuit 201 performs a summation operation on multiple signals to be processed, the sum signal obtained can be , that is .

[0067] The above gating circuit 202 is used to gate multiple signals to be processed and output the signal with the maximum intensity and the signal with the minimum intensity among the multiple signals to be processed. Specifically, it is used to perform maximum gating on multiple signals to be processed to output the signal with the maximum intensity, and is also used to perform minimum gating on multiple signals to be processed to output the signal with the minimum intensity. For example, the multiple signals to be processed are , ,......, . After performing maximum gating and minimum gating on multiple signals to be processed by the above gating circuit 202, the signal with the maximum intensity and the signal with the minimum intensity can be obtained, that is and .

[0068] In the embodiment of the present application, the sampling circuit 10 performs multiple signal samplings on the same sampling point or different signal samplings on different sampling points to obtain multiple signals to be processed; the summing circuit 201 in the processing circuit 20 can perform a summation operation on the multiple signals to be processed to obtain the sum signal of the multiple signals to be processed; the gating circuit 202 in the processing circuit 20 can perform maximum screening and minimum screening of the signal intensity values on the multiple signals to be processed to obtain the signal with the maximum intensity and the signal with the minimum intensity among the multiple signals to be processed, and then the median circuit 30 performs a difference operation on the sum signal, the signal with the maximum intensity, and the signal with the minimum intensity, and uses the signal after the difference operation as the target sampling signal. It should be noted that at least one comparator can be set in the gating circuit 202, so that the gating circuit 202 can perform maximum screening and minimum screening on multiple signals to be processed by comparing the signal intensities of the multiple signals to be processed, so as to output the signal with the maximum intensity and the signal with the minimum intensity; optionally, at least one operational amplifier, at least one proportional amplifier, at least one follower, at least one various types of arithmetic units, etc. can be set in the gating circuit 202, so that the gating circuit 202 can perform maximum screening and minimum screening on multiple signals to be processed by performing operations on the multiple signals to be processed, so as to output the signal with the maximum intensity and the signal with the minimum intensity.

[0069] The processing circuit described in the embodiment of the present application realizes redundant processing of key signals of the signals output by the sampling circuit in an analog circuit manner by setting a sum circuit and an analog circuit of a gating circuit, that is, realizes screening out normal sampling signals in the case of any one path failure or any two path failure signals (for example, the maximum signal and the minimum signal), and improves the reliability of the sampling circuit to a certain extent.

[0070] In one embodiment, a gating circuit 202 is provided, as Figure 3 shown. The gating circuit 202 includes: a maximum gating circuit 2021 and a minimum gating circuit 2022. The sampling circuit 10 is respectively connected to the maximum gating circuit 2021 and the minimum gating circuit 2022. The maximum gating circuit 2021 is configured to output the signal with the maximum intensity among the plurality of signals to be processed according to the signal intensities of the plurality of signals to be processed. The minimum gating circuit 2022 is configured to output the signal with the minimum intensity among the plurality of signals to be processed according to the signal intensities of the plurality of signals to be processed.

[0071] The above-mentioned maximum gating circuit 2021 is configured to perform maximum gating on a plurality of signals to be processed and output the signal with the maximum intensity among the plurality of signals to be processed. For example, the plurality of signals to be processed are , ,......, . After performing maximum gating on the plurality of signals to be processed by the above-mentioned maximum gating circuit 2021, the signal with the maximum intensity can be obtained, that is, .

[0072] The above-mentioned minimum gating circuit 2022 is configured to perform minimum gating on a plurality of signals to be processed and output the signal with the minimum intensity among the plurality of signals to be processed. For example, the plurality of signals to be processed are , ,......, . After performing minimum gating on the plurality of signals to be processed by the above-mentioned minimum gating circuit 2022, the signal with the minimum intensity can be obtained, that is, .

[0073] In the embodiment of the present application, the sampling circuit 10 performs signal sampling on the same sampling point multiple times or performs different signal samplings on different sampling points to obtain a plurality of signals to be processed. The summing circuit 201 in the processing circuit 20 can perform a summation operation on the plurality of signals to be processed to obtain the sum signal of the plurality of signals to be processed. The maximum gating circuit 2021 in the processing circuit 20 can perform maximum screening on the plurality of signals to be processed to obtain the signal with the maximum intensity. The minimum gating circuit 2022 in the processing circuit 20 can perform minimum screening on the plurality of signals to be processed to obtain the signal with the minimum intensity. Then, the median circuit 30 performs a difference operation on the sum signal, the signal with the maximum intensity, and the signal with the minimum intensity, and uses the signal after the difference operation as the target sampling signal.

[0074] It should be noted that at least one comparator can be set in the maximum gating circuit 2021, so that the maximum gating circuit 2021 can perform maximum screening on multiple signals to be processed by comparing the signal strengths of the multiple signals to be processed to output the signal with the maximum strength; optionally, at least one operational amplifier, at least one proportional amplifier, at least one follower, at least one operator of various types, etc. can be set in the maximum gating circuit 2021, so that the maximum gating circuit 2021 can perform maximum screening on multiple signals to be processed by performing operations on multiple signals to be processed to output the signal with the maximum strength.

[0075] The minimum selection circuit 2022 can be provided with at least one comparator, so that the minimum selection circuit 2022 can perform minimum screening on multiple signals to be processed by comparing the signal strengths of the multiple signals to be processed to output a signal with minimum strength; optionally, at least one operational amplifier, at least one proportional amplifier, at least one follower, at least one operator of various types, etc. can be provided in the minimum selection circuit 2022, so that the minimum selection circuit 2022 can perform minimum screening on multiple signals to be processed by performing operations on the multiple signals to be processed to output a signal with minimum strength.

[0076] The processing circuit described in the embodiment of the present application realizes redundant processing of key signals output by the sampling circuit using analog circuits by setting analog circuits of the sum circuit, the maximum gating circuit, and the minimum gating circuit, that is, it realizes screening out normal sampling signals in the event of any one fault or any two fault signals, thereby improving the reliability of the sampling circuit to a certain extent.

[0077] In one embodiment, a redundant processing device is also provided. Figure 3 The redundant processing device is based on Figure 4 As shown, the redundant processing device 1 further includes: a scaling circuit 40 and a restoration circuit 50 ; the scaling circuit 40 is connected to the sampling circuit 10 and the processing circuit 20 respectively; and the centering circuit 30 is connected to the restoration circuit 50 .

[0078] The above-mentioned scaling circuit 40 is used to scale down each signal to be processed by a preset multiple; wherein the preset multiple can be determined in advance according to the requirements of the input signal of the processing circuit 20, for example, the voltage signal input by the processing circuit 20 is not higher than the power supply voltage of the processing circuit 20. Optionally, the scaling circuit 40 may include multiple scaling sub-circuits, and the scaling multiples of each scaling sub-circuit are the same, which can be the preset multiples, and each scaling sub-circuit is used to scale down one channel of the signal to be processed by a preset multiple. For example, multiple signals to be processed are , ,......, , the preset multiple is , after using each scaling sub - circuit in the above - mentioned scaling circuit 40 to perform a reduction process on each signal to be processed by a preset multiple, signals reduced by various multiples can be obtained. The signals after being reduced by various multiples are: , ,......, .

[0079] The above - mentioned restoration circuit 50 is used to perform a restoration process on the target sampling signal output by the middle - taking circuit 30 to obtain the restored target sampling signal. For example, the restoration circuit 50 can specifically perform an amplification and restoration on the processed signal after the reduction process, and amplify it by a preset multiple. For example, if the scaling circuit reduces the signal by times, then the corresponding restoration circuit amplifies the reduced signal by times.

[0080] In the embodiment of the present application, the sampling circuit 10 performs multiple signal samplings on the same sampling point, or performs different signal samplings on different sampling points to obtain multiple signals to be processed; the scaling circuit 40 can perform a reduction process on each signal to be processed respectively, or each reduction sub - circuit in the scaling circuit 40 can perform a reduction process on each signal to be processed to obtain multiple reduced signals; the summation circuit 201 in the processing circuit 20 can perform a summation operation on the multiple reduced signals to obtain the sum signal of the multiple reduced signals; the maximum selection circuit 2021 in the processing circuit 20 can perform a maximum screening on the multiple reduced signals to obtain the signal with the maximum intensity among them; the minimum selection circuit 2022 in the processing circuit 20 can perform a minimum screening on the multiple reduced signals to obtain the signal with the minimum intensity among them; then the middle - taking circuit 30 performs a difference operation on the sum signal, the signal with the maximum intensity, and the signal with the minimum intensity, and uses the signal after the difference operation as the target sampling signal. The restoration circuit 50 performs a restoration and amplification on the target sampling signal to restore it to the processed signal after being selected.

[0081] The redundancy processing device described in the embodiment of the present application can match the voltage of the input signal input to the processing circuit with the power supply range of the processing circuit by setting a scaling circuit and a restoration circuit, so that the processing circuit can accurately process the signal to be processed, thereby improving the signal processing accuracy of the redundancy processing device.

[0082] In one embodiment, a sampling circuit 10 is provided, as Figure 5 shown. The sampling circuit 10 includes multiple sampling sub - circuits 101; the multiple sampling sub - circuits 101 are all connected to the processing circuit 20; the multiple sampling sub - circuits 101 are used to perform different - time signal samplings on the same sampling point to obtain the signals to be processed corresponding to each sampling sub - circuit; or different sampling sub - circuits 101 are used to perform signal samplings on different sampling points to obtain the signals to be processed corresponding to each sampling sub - circuit.

[0083] In the embodiments of the present application, each sampling sub-circuit 101 performs multiple signal samplings on the same sampling point to obtain multiple signals to be processed; alternatively, different sampling sub-circuits 101 perform signal samplings on different sampling points to obtain multiple signals to be processed; the summing circuit 201 in the processing circuit 20 can perform a summation operation on the multiple signals to be processed to obtain a sum signal of the multiple signals to be processed; the maximum gating circuit 2021 in the processing circuit 20 can perform maximum screening on the multiple signals to be processed to obtain the signal with the maximum intensity; the minimum gating circuit 2022 in the processing circuit 20 can perform minimum screening on the multiple signals to be processed to obtain the signal with the minimum intensity; then, the median circuit 30 performs a difference operation on the sum signal, the signal with the maximum intensity, and the signal with the minimum intensity again, and uses the signal after the difference operation as the target sampling signal.

[0084] The sampling circuit described in the embodiments of the present application includes multiple sampling sub-circuits, which can achieve sampling of multiple sampling points or multiple samplings of the same sampling point, and uses the provided processing circuit to process the signals of multiple sampling points or the multiple sampling signals of the same sampling point, realizing redundant processing of key signals for the signals output by multiple sampling sub-circuits in an analog circuit manner, that is, screening out normal sampling signals in the case of any one or any two faulty signals, and improving the reliability of the sampling circuit to a certain extent.

[0085] In one embodiment, another redundant processing device is provided, as Figure 6 shown. The sampling circuit 10 in the redundant processing device includes a first sampling sub-circuit 102, a second sampling sub-circuit 103, and a third sampling sub-circuit 104; the scaling circuit 40 includes a first scaling-down sub-circuit 402, a second scaling-down sub-circuit 403, and a third scaling-down sub-circuit 404; the first sampling sub-circuit 102 is connected to the first scaling-down sub-circuit 402, the second sampling sub-circuit 103 is connected to the second scaling-down sub-circuit 403, and the third sampling sub-circuit 104 is connected to the third scaling-down sub-circuit 404.

[0086] Among them, the first sampling sub-circuit 102 is configured to perform a first signal sampling on the same sampling point to obtain a signal to be processed corresponding to the first sampling sub-circuit; the second sampling sub-circuit 103 is configured to perform a second signal sampling on the same sampling point to obtain a signal to be processed corresponding to the second sampling sub-circuit; the third sampling sub-circuit 104 is configured to perform a third signal sampling on the same sampling point to obtain a signal to be processed corresponding to the third sampling sub-circuit; or, the first sampling sub-circuit 102 is configured to perform a signal sampling on the first sampling point to obtain a signal to be processed corresponding to the first sampling sub-circuit; the second sampling sub-circuit 103 is configured to perform a signal sampling on the second sampling point to obtain a signal to be processed corresponding to the second sampling sub-circuit; the third sampling sub-circuit 104 is configured to perform a signal sampling on the third sampling point to obtain a signal to be processed corresponding to the third sampling sub-circuit. Among them, the first sampling point, the second sampling point, and the third sampling point are different sampling points.

[0087] In the embodiment of the present application, the first sampling sub-circuit 102, the second sampling sub-circuit 103, and the third sampling sub-circuit 104 perform three signal samplings on the same sampling point to obtain three signals to be processed; or, the first sampling sub-circuit 102 performs one sampling on the first sampling point, the second sampling sub-circuit 103 performs one sampling on the second sampling point, and the third sampling sub-circuit 104 performs one sampling on the third sampling point to obtain three signals to be processed; correspondingly, the first reduction sub-circuit 402 performs a reduction process on the signal to be processed output by the first sampling sub-circuit 102, the second reduction sub-circuit 403 performs a reduction process on the signal to be processed output by the second sampling sub-circuit 103, and the third reduction sub-circuit 404 performs a reduction process on the signal to be processed output by the third sampling sub-circuit 104; the summation circuit 201 in the processing circuit 20 can perform a summation operation on the signals output by the first reduction sub-circuit 402, the signals output by the second reduction sub-circuit 40, and the signals output by the third reduction sub-circuit 404 to obtain the sum signal of the three reduced signals; the maximum gating circuit 2021 in the processing circuit 20 can perform a maximum screening on the signals output by the first reduction sub-circuit 402, the signals output by the second reduction sub-circuit 40, and the signals output by the third reduction sub-circuit 404 to obtain the signal with the maximum intensity among them; the minimum gating circuit 2022 in the processing circuit 20 can perform a minimum screening on the signals output by the first reduction sub-circuit 402, the signals output by the second reduction sub-circuit 40, and the signals output by the third reduction sub-circuit 404 to obtain the signal with the minimum intensity among them; then the median circuit 30 performs a difference operation on the sum signal, the signal with the maximum intensity, and the signal with the minimum intensity, and uses the signal after the difference operation as the target sampling signal, and then the restoration circuit 50 restores the target sampling signal to obtain the restored target sampling signal.

[0088] Exemplary description Figure 6The redundancy processing method of the redundancy processing device described in the embodiment. For example, the signals to be processed output by the first sampling sub-circuit 102, the second sampling sub-circuit 103, and the third sampling sub-circuit 104 are: , , . After being reduced by the first reduction sub-circuit 402, the second reduction sub-circuit 403, and the third reduction sub-circuit 404, the reduced signals are obtained: , , . The reduced signals are input to the summing circuit 201 to output a sum signal: . The reduced signals are input to the maximum selection circuit 2021 to output a signal with the maximum intensity: . The reduced signals are input to the minimum selection circuit 2022 to output a signal with the minimum intensity: . The outputs of the summing circuit 201, the maximum selection circuit 2021, and the minimum selection circuit 2022 are used as the inputs of the median circuit 30. After passing through the median circuit 30, the median value in the reduced signals can be obtained, and its output is:

[0089] ;

[0090] After passing through the median circuit 30, a median sampling signal reduced by times can be obtained. By passing this signal through the restoration circuit 50, a median sampling signal of the original size can be obtained.

[0091] The redundancy processing device described in the embodiment of the present application is composed of three input signals, a scaling circuit, a summing circuit, a maximum selection circuit, a minimum selection circuit, and a restoration circuit. By extracting the sum signal, the signal with the maximum intensity, and the signal with the minimum intensity, the median value is obtained among the three input signals, and the input signals are redundantly processed to remove the signals that are prone to anomalies, thereby improving the sampling accuracy.

[0092] In one embodiment, a maximum selection circuit 2021 is provided. The maximum selection circuit 2021 includes: a plurality of maximum selection operational amplifiers, a plurality of maximum conduction devices, and a first follower; the plurality of maximum selection operational amplifiers are connected in parallel, and the input terminals of each maximum selection operational amplifier are connected to the scaling circuit. The output terminals of each maximum selection operational amplifier are connected to each maximum conduction device, and each maximum conduction device is connected to the first follower.

[0093] Exemplarily, a specific implementation manner of the maximum selection circuit 2021 described in the above embodiment is provided, that is, as Figure 7As shown, the multiple maximum gating operational amplifiers in the maximum gating circuit 2021 include: a first maximum gating operational amplifier 2021_1, a second maximum gating operational amplifier 2021_2, and a third maximum gating operational amplifier 2021_3; the multiple maximum conduction devices include a first maximum conductor 2023_1, a second maximum conductor 2023_2, and a third maximum conductor 2023_3;

[0094] The first maximum gating operational amplifier 2021_1, the second maximum gating operational amplifier 2021_2, and the third maximum gating operational amplifier 2021_3 are connected in parallel; the positive input terminal of the first maximum gating operational amplifier 2021_1 is connected to the first scaling sub-circuit 402, the positive input terminal of the second maximum gating operational amplifier 2021_2 is connected to the second scaling sub-circuit 403, and the positive input terminal of the third maximum gating operational amplifier 2021_3 is connected to the third scaling sub-circuit 404;

[0095] The output terminal of the first maximum gating operational amplifier 2021_1 is connected to the first maximum conductor 2023_1, the output terminal of the second maximum gating operational amplifier 2021_2 is connected to the second maximum conductor 2023_2, and the output terminal of the third maximum gating operational amplifier 2021_3 is connected to the third maximum conductor 2023_3;

[0096] The first maximum conductor 2023_1, the second maximum conductor 2023_2, and the third maximum conductor 2023_3 are all connected to the first follower 2021_4.

[0097] Among them, represents the positive power supply input, represents the negative power supply input, Represents the output of the maximum gating circuit 2021, which is the signal with the maximum intensity. It should be noted that in order to ensure that the input of the first maximum gating operational amplifier 2021_1 does not exceed the supply voltage of the operational amplifier, the input terminal of the first maximum gating operational amplifier 2021_1 can be connected to the first scaling sub-circuit 402 for input voltage scaling, so that the input of the first maximum gating operational amplifier 2021_1 can match the first maximum gating operational amplifier 2021_1, that is, its input does not exceed the power supply of the first maximum gating operational amplifier 2021_1; in order to ensure that the input of the second maximum gating operational amplifier 2021_2 does not exceed the supply voltage of the operational amplifier, the input terminal of the second maximum gating operational amplifier 2021_2 can be connected to the second scaling sub-circuit 403 for input voltage scaling, so that the input of the second maximum gating operational amplifier 2021_2 can match the second maximum gating operational amplifier 2021_2, that is, its input does not exceed the power supply of the second maximum gating operational amplifier 2021_2; in order to ensure that the input of the third maximum gating operational amplifier 2021_3 does not exceed the supply voltage of the operational amplifier, the input terminal of the third maximum gating operational amplifier 2021_3 can be connected to the third scaling sub-circuit 404 for input voltage scaling, so that the input of the third maximum gating operational amplifier 2021_3 can match the third maximum gating operational amplifier 2021_3, that is, its input does not exceed the power supply of the third maximum gating operational amplifier 2021_3.

[0098] In the maximum gating circuit 2021 described in the embodiments of the present application, As the input signal of the positive input terminal of the first maximum gating operational amplifier 2021_1, As the input signal of the positive input terminal of the second maximum gating operational amplifier 2021_2, As the input signal of the positive input terminal of the third maximum gating operational amplifier 2021_3;

[0099] If is greater than , and is greater than ; or if is greater than , and is greater than, then the first maximum switch 2023_1 conducts, the second maximum switch 2023_2 cuts off, the third maximum switch 2023_3 cuts off, and the first maximum switch 2023_1 inputs the signal to the positive input terminal of the first follower 2021_4, and the first follower 2021_4 outputs this signal as the maximum signal Output , achieving maximum gating;

[0100] If is greater than , and is greater than ; or Greater than and greater than , then the first maximum conductor 2023_1 is turned off, the second maximum conductor 2023_2 is turned on, the third maximum conductor 2023_3 is turned off, and the second maximum conductor 2023_2 inputs the signal to the positive input terminal of the first follower 2021_4, and the first follower 2021_4 outputs this signal as the maximum signal to achieve maximum gating;

[0101] If is greater than , and is greater than , or if is greater than , and is greater than , then the first maximum conductor 2023_1 is turned off, the second maximum conductor 2023_2 is turned off, the third maximum conductor 2023_3 is turned on, and the third maximum conductor 2023_3 inputs the signal to the positive input terminal of the first follower 2021_4, and the first follower 2021_4 outputs this signal as the maximum signal to achieve maximum gating.

[0102] The maximum gating circuit described in the embodiments of the present application realizes the selection of the maximum intensity signal through an analog circuit by setting operational amplifiers, conductors, and followers. Compared with the digital circuit implementation method, the maximum gating circuit has a faster response and less signal noise, and improves the reliability of the redundancy processing device to a certain extent.

[0103] In one embodiment, a minimum gating circuit 2022 is provided, as shown in Figure 8 , the minimum gating circuit includes: a plurality of minimum gating operational amplifiers, a plurality of minimum conducting devices, and a second follower;

[0104] The plurality of minimum gating operational amplifiers are connected in parallel, and the input terminals of each minimum gating operational amplifier are connected to the scaling circuit. The output terminals of each minimum gating operational amplifier are connected to each minimum conducting device, and each minimum conducting device is connected to the second follower.

[0105] An exemplary specific implementation manner of the minimum gating circuit 2022 described in the above embodiment is provided, that is, as shown in Figure 8As shown, the minimum gating circuit 2022 includes: a first minimum gating operational amplifier 2022_1, a second minimum gating operational amplifier 2022_2, and a third minimum gating operational amplifier 2022_3; a plurality of minimum conduction devices 2023 include a first minimum conductor 2024_1, a second minimum conductor 2024_2, and a third minimum conductor 2024_3;

[0106] The first minimum gating operational amplifier 2022_1, the second minimum gating operational amplifier 2022_2, and the third minimum gating operational amplifier 2022_3 are connected in parallel; the positive input terminal of the first minimum gating operational amplifier 2022_1 is connected to the first scaling sub-circuit 402, the positive input terminal of the second minimum gating operational amplifier 2022_2 is connected to the second scaling sub-circuit 403, and the positive input terminal of the third minimum gating operational amplifier 2022_3 is connected to the third scaling sub-circuit 404;

[0107] The output terminal of the first minimum gating operational amplifier 2022_1 is connected to the first minimum conductor 2024_1, the output terminal of the second minimum gating operational amplifier 2022_2 is connected to the second minimum conductor 2024_2, and the output terminal of the third minimum gating operational amplifier 2022_3 is connected to the third minimum conductor 2024_3;

[0108] The first minimum conductor 2024_1, the second minimum conductor 2024_2, and the third minimum conductor 2024_3 are all connected to the second follower 2022_4.

[0109] Wherein, represents the positive power supply input, represents the negative power supply input, represents the output of the minimum gating circuit 2022, that is, the minimum intensity signal. The conduction direction of the first minimum conductor 2024_1 is opposite to that of the first maximum conductor 2023_1; the conduction direction of the second minimum conductor 2024_2 is opposite to that of the second maximum conductor 2023_2; the conduction direction of the third minimum conductor 2024_3 is opposite to that of the third maximum conductor 2023_3.

[0110] In the minimum gating circuit 2022 described in the embodiment of the present application, as the input signal of the positive input terminal of the first minimum gating operational amplifier 2022_1, as the input signal of the positive input terminal of the second minimum gating operational amplifier 2022_2, as the input signal of the positive input terminal of the third minimum gating operational amplifier 2022_3;

[0111] If is less than , and is less than ; or if Less than , and Less than , then the first minimum conductor 2024_1 conducts, the second minimum conductor 2024_2 cuts off, the third minimum conductor 2024_3 cuts off, and the first minimum conductor 2024_1 inputs the signal to the positive input terminal of the second follower 2022_4, and the second follower 2022_4 outputs this signal as the minimum signal to achieve minimum gating;

[0112] If Less than , and Less than ; or Less than , and Less than , then the first minimum conductor 2024_1 cuts off, the second minimum conductor 2024_2 conducts, the third minimum conductor 2024_3 cuts off, and the second minimum conductor 2024_2 inputs the signal to the positive input terminal of the second follower 2022_4, and the second follower 2022_4 outputs this signal as the minimum signal to achieve minimum gating;

[0113] If Less than , and Less than , or if Less than, and Less than , then the first minimum conductor 2024_1 cuts off, the second minimum conductor 2024_2 cuts off, the third minimum conductor 2024_3 conducts, and the third minimum conductor 2024_3 inputs the signal to the positive input terminal of the second follower 2022_4, and the second follower 2022_4 outputs this signal as the minimum signal to achieve minimum gating.

[0114] In one embodiment, the above minimum gating circuit 2022 further includes: a resistor 2025; the resistor 2025 is respectively connected to the first minimum conductor 2022_1, the positive input terminal of the second follower 2022_4, and the power supply.

[0115] The minimum gating circuit described in the embodiments of the present application realizes the selection of the minimum intensity signal through an analog circuit by setting an operational amplifier, a conductor, and a follower. Compared with the digital circuit implementation method, the minimum gating circuit has a faster response and less signal noise, and improves the reliability of the redundancy processing device to a certain extent.

[0116] The scope of protection claimed in the above embodiments is not limited to the above specific embodiments. Moreover, for those skilled in the art, the present invention can have various deformations and modifications. Any modification, improvement, and equivalent replacement made within the concept and principle of the present invention should be included within the scope of protection of the present invention.

[0117] The technical features of the above embodiments can be combined arbitrarily. For the sake of brevity of description, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, it should be considered as the scope described in this specification.

[0118] The above-described embodiments merely represent several implementation manners of the present application. The description is relatively specific and detailed, but it should not be construed as a limitation on the scope of the patent of the present application. It should be noted that for those of ordinary skill in the art, without departing from the concept of the present application, several deformations and improvements can still be made, and these all belong to the scope of protection of the present application. Therefore, the scope of protection of the present application shall be subject to the appended claims.

Claims

1. A redundancy processing device, characterized in that, The redundancy processing device includes: a sampling circuit, a processing circuit, and a median circuit that are connected in sequence; The sampling circuit is configured to perform signal sampling on sampling points to obtain a plurality of signals to be processed; the plurality of signals to be processed includes at least three signals to be processed; The processing circuit is configured to output a plurality of candidate sampling signals of the plurality of signals to be processed; The median circuit is configured to output a target sampling signal according to the plurality of candidate sampling signals; the target sampling signal is not the maximum signal and the minimum signal among the plurality of candidate sampling signals.

2. The device according to claim 1, characterized in that, The plurality of candidate sampling signals includes a sum signal, a maximum intensity signal, and a minimum intensity signal. The processing circuit includes: a summing circuit and a gating circuit; the sampling circuit is respectively connected to the summing circuit and the gating circuit, and the summing circuit and the gating circuit are also both connected to the median circuit; The summing circuit is configured to perform a sum operation on the plurality of signals to be processed and output the sum signal of the plurality of signals to be processed; The gating circuit is configured to perform gating on the plurality of signals to be processed and output the maximum intensity signal and the minimum intensity signal among the plurality of signals to be processed.

3. The device according to claim 2, wherein The gating circuit includes: a maximum gating circuit and a minimum gating circuit; the sampling circuit is respectively connected to the maximum gating circuit and the minimum gating circuit; The maximum gating circuit is configured to output the maximum intensity signal among the plurality of signals to be processed according to the signal intensities of the plurality of signals to be processed; The minimum gating circuit is configured to output the minimum intensity signal among the plurality of signals to be processed according to the signal intensities of the plurality of signals to be processed.

4. The device according to any one of claims 1-3, characterized in that The redundancy processing device further includes: a scaling circuit and a restoration circuit; the scaling circuit is respectively connected to the sampling circuit and the processing circuit; the median circuit is connected to the restoration circuit; The scaling circuit is configured to perform a reduction process on each of the signals to be processed by a preset multiple; The restoration circuit is configured to perform a restoration process on the target sampling signal output by the median circuit to obtain a restored target sampling signal.

5. The device according to claim 3, characterized in that, The sampling circuit includes a plurality of sampling sub-circuits; the plurality of sampling sub-circuits are all connected to the processing circuit; The plurality of sampling sub-circuits are configured to perform signal sampling at different times for the same sampling point to obtain the signals to be processed corresponding to the respective sampling sub-circuits; Alternatively, different sampling sub-circuits are configured to perform signal sampling for different sampling points to obtain the signals to be processed corresponding to the respective sampling sub-circuits.

6. The device according to claim 4, characterized in that, The sampling circuit includes a first sampling sub-circuit, a second sampling sub-circuit, and a third sampling sub-circuit; the scaling circuit includes a first reduction sub-circuit, a second reduction sub-circuit, and a third reduction sub-circuit; the first sampling sub-circuit is connected to the first reduction sub-circuit, the second sampling sub-circuit is connected to the second reduction sub-circuit, and the third sampling sub-circuit is connected to the third reduction sub-circuit; The first sampling sub-circuit is configured to perform a first signal sampling on the same sampling point to obtain a signal to be processed corresponding to the first sampling sub-circuit; the second sampling sub-circuit is configured to perform a second signal sampling on the same sampling point to obtain a signal to be processed corresponding to the second sampling sub-circuit; the third sampling sub-circuit is configured to perform a third signal sampling on the same sampling point to obtain a signal to be processed corresponding to the third sampling sub-circuit; Alternatively, the first sampling sub-circuit is configured to perform a signal sampling on a first sampling point to obtain a signal to be processed corresponding to the first sampling sub-circuit; the second sampling sub-circuit is configured to perform a signal sampling on a second sampling point to obtain a signal to be processed corresponding to the second sampling sub-circuit; the third sampling sub-circuit is configured to perform a signal sampling on a third sampling point to obtain a signal to be processed corresponding to the third sampling sub-circuit.

7. The device according to claim 6, characterized in that The maximum gating circuit includes: a plurality of maximum gating operational amplifiers, a plurality of maximum conducting devices, and a first follower; The plurality of maximum gating operational amplifiers are connected in parallel, and the input terminals of each of the maximum gating operational amplifiers are connected to the scaling circuit. The output terminals of each of the maximum gating operational amplifiers are connected to each of the maximum conducting devices, and each of the maximum conducting devices is connected to the first follower.

8. The device according to claim 7, characterized in that, The plurality of maximum gating operational amplifiers include: a first maximum gating operational amplifier, a second maximum gating operational amplifier, and a third maximum gating operational amplifier; the plurality of maximum conducting devices include a first maximum conductor, a second maximum conductor, and a third maximum conductor; The first maximum gating operational amplifier, the second maximum gating operational amplifier, and the third maximum gating operational amplifier are connected in parallel; the positive input terminal of the first maximum gating operational amplifier is connected to the first scaling sub-circuit, the positive input terminal of the second maximum gating operational amplifier is connected to the second scaling sub-circuit, and the positive input terminal of the third maximum gating operational amplifier is connected to the third scaling sub-circuit; The output terminal of the first maximum gating operational amplifier is connected to the first maximum conductor, the output terminal of the second maximum gating operational amplifier is connected to the second maximum conductor, and the output terminal of the third maximum gating operational amplifier is connected to the third maximum conductor; The first maximum conductor, the second maximum conductor, and the third maximum conductor are all connected to the first follower.

9. The device according to claim 6, characterized in that The minimum gating circuit includes: a plurality of minimum gating operational amplifiers, a plurality of minimum conducting devices, and a second follower; The plurality of minimum gating operational amplifiers are connected in parallel, and the input terminals of each of the minimum gating operational amplifiers are connected to the scaling circuit. The output terminals of each of the minimum gating operational amplifiers are connected to each of the minimum conducting devices, and each of the minimum conducting devices is connected to the second follower.

10. The device according to claim 9, characterized in that, The plurality of minimum gating operational amplifiers include: a first minimum gating operational amplifier, a second minimum gating operational amplifier, and a third minimum gating operational amplifier; the plurality of minimum conducting devices include a first minimum conductor, a second minimum conductor, and a third minimum conductor; The first minimum gating operational amplifier, the second minimum gating operational amplifier, and the third minimum gating operational amplifier are connected in parallel; the positive input terminal of the first minimum gating operational amplifier is connected to the first scaling sub-circuit, the positive input terminal of the second minimum gating operational amplifier is connected to the second scaling sub-circuit, and the positive input terminal of the third minimum gating operational amplifier is connected to the third scaling sub-circuit; The output terminal of the first minimum gating operational amplifier is connected to the first minimum conduction device, the output terminal of the second minimum gating operational amplifier is connected to the second minimum conduction device, and the output terminal of the third minimum gating operational amplifier is connected to the third minimum conduction device; The first minimum conduction device, the second minimum conduction device, and the third minimum conduction device are all connected to the second follower.

11. The device according to claim 10, characterized in that, The minimum gating circuit further includes a resistor; the resistor is respectively connected to the first minimum conduction device, the positive input terminal of the second follower, and the power supply.

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