Data writing control method and memory storage device

Abstract

The invention provides a data writing control method and a memory storage device. Performance and initialization efficiency of the memory storage device can be improved. The memory storage device comprises a memory controller and a memory module. The data write-in control method comprises the following steps: receiving configuration information and interrupt information, and generating a plurality of write-in instruction sequences according to the configuration information; sequentially executing multiple write operations corresponding to the multiple write instruction sequences, and monitoring execution results of the write operations; and determining an execution strategy according to the execution result and / or the interrupt information until the multiple writing operations are executed.

Description

Technical Field

[0001] The present invention relates to a memory management technology, and more particularly to a data writing control method and a memory storage device. Background Art

[0002] In recent years, the growth of smart phones, tablet computers, and personal computers has been very rapid, resulting in a sharp increase in consumers' demand for storage media. Since rewritable non-volatile memory modules (e.g., flash memory) have characteristics such as data non-volatility, power saving, small size, and no mechanical structure, they are very suitable for being built into various portable multimedia devices exemplified above.

[0003] Due to the data retention characteristics of rewritable non-volatile memory modules, when physical units are not used for a long time and / or no data is written to physical units, problems such as data loss and / or damage may occur. To avoid the foregoing problems, a common practice is to write dummy data to the rewritable non-volatile memory module during the initialization of the memory storage device. However, this practice requires a large amount of time cost and resource usage, thereby affecting the performance of the memory storage device. Summary of the Invention

[0004] Exemplary embodiments of the present invention provide a data writing control method and a memory storage device, which can improve the performance and initialization efficiency of the memory storage device.

[0005] Exemplary embodiments of the present invention provide a data writing control method for a memory storage device. The memory storage device includes a memory module and a memory controller. The data writing control method includes: receiving configuration information and interrupt information, and generating a plurality of write instruction sequences according to the configuration information, where the configuration information includes write data and start and end addresses; sequentially executing a plurality of write operations corresponding to the plurality of write instruction sequences, and monitoring the execution results of the write operations; and determining an execution strategy according to the execution results and / or the interrupt information until the plurality of write operations are completed.

[0006] In an exemplary embodiment of the present invention, the execution policy includes a first execution policy and a second execution policy. The step of determining the execution policy according to the execution result and / or the interruption information includes: if a first execution result corresponding to a first write operation indicates that the first write operation does not fail, determining the execution policy as the first execution policy, where the first write operation is one of the multiple write operations; and if the first execution result indicates that the first write operation fails, determining the execution policy according to the interruption information.

[0007] In an exemplary embodiment of the present invention, the step of determining the execution policy according to the interruption information includes: judging whether to perform an error handling operation according to the interruption information; if so, determining the execution policy as the second execution policy; and if not, determining the execution policy as the first execution policy.

[0008] In an exemplary embodiment of the present invention, the first execution policy includes sequentially executing the multiple write operations until the multiple write operations are completed. The second execution policy includes interrupting the write operation to be executed, performing the error handling operation according to the interruption information, and continuing to execute the write operation to be executed until the multiple write operations are completed.

[0009] In an exemplary embodiment of the present invention, the interruption information includes: bad block table information and key area information. The step of judging whether to perform the error handling operation according to the interruption information includes: judging whether a first physical unit corresponding to the first write operation is recorded in the key area information; and if the first physical unit is recorded in the key area information, interrupting the write operation to be executed and performing the error handling operation according to the bad block table information.

[0010] In an exemplary embodiment of the present invention, the step of performing the error handling operation according to the bad block table information includes: judging whether the first physical unit is recorded in the bad block table according to the bad block table information; if the first physical unit is not recorded in the bad block table, updating the bad block table and continuing to execute the write operation to be executed; and if the first physical unit is recorded in the bad block table, continuing to execute the write operation to be executed.

[0011] In an exemplary embodiment of the present invention, it further includes: if the first physical unit is not recorded in the key area information, not performing the error handling operation and continuing to execute the write operation to be executed.

[0012] In an exemplary embodiment of the present invention, the written data is virtual data.

[0013] Exemplary embodiments of the present invention further provide a memory storage device, which includes a connection interface unit, a memory module, and a memory controller. The memory controller is coupled to the connection interface unit and the memory module. The connection interface unit is coupled to a host system. The memory controller is configured to receive configuration information and interruption information, and generate multiple write instruction sequences according to the configuration information, wherein the configuration information includes write data and start and end addresses. The memory controller is further configured to sequentially execute multiple write operations corresponding to the multiple write instruction sequences, and monitor the execution results of each of the write operations. The memory controller is further configured to determine an execution strategy according to the execution results and / or the interruption information until the multiple write operations are completed.

[0014] In the exemplary embodiments of the present invention, the execution strategy includes a first execution strategy and a second execution strategy. If a first execution result corresponding to a first write operation indicates that the first write operation does not fail, the memory controller determines that the execution strategy is the first execution strategy, wherein the first write operation is one of the multiple write operations. If the first execution result indicates that the first write operation fails, the memory controller determines the execution strategy according to the interruption information.

[0015] In the exemplary embodiments of the present invention, the memory controller is further configured to determine whether to perform an error handling operation according to the interruption information. If so, the memory controller determines that the execution strategy is the second execution strategy. If not, the memory controller determines that the execution strategy is the first execution strategy.

[0016] In the exemplary embodiments of the present invention, the interruption information includes: bad block table information and key area information. The memory controller determines whether a first physical unit corresponding to the first write operation is recorded in the key area information. If the first physical unit is recorded in the key area information, the memory controller interrupts the write operation to be executed and performs the error handling operation according to the bad block table information.

[0017] In the exemplary embodiments of the present invention, the memory controller is further configured to determine whether the first physical unit is recorded in the bad block table according to the bad block table information. If the first physical unit is not recorded in the bad block table, the memory controller updates the bad block table and continues to execute the write operation to be executed. If the first physical unit is recorded in the bad block table, the memory controller continues to execute the write operation to be executed.

[0018] In an exemplary embodiment of the present invention, if the first entity unit is not recorded in the key area information, the memory controller does not perform the error handling operation and continues to perform the to-be-executed write operation.

[0019] Based on the above, the present invention provides a data write control method and a memory storage device, which can generate multiple write instruction sequences according to received configuration information and execute multiple write operations accordingly to write virtual data into the memory module, thereby improving the performance and initialization efficiency of the memory storage device. In addition, the data correctness and integrity can be improved by monitoring whether the foregoing multiple write operations fail and adopting corresponding execution strategies.

[0020] To make the above features and advantages of the present invention more obvious and understandable, specific embodiments are hereinafter given and detailed descriptions are made in conjunction with the accompanying drawings as follows. Description of the Drawings

[0021] Figure 1 is a schematic diagram of a host system, a memory storage device, and an input / output (I / O) device shown according to an exemplary embodiment of the present invention;

[0022] Figure 2 is a schematic diagram of a host system, a memory storage device, and an I / O device shown according to an exemplary embodiment of the present invention;

[0023] Figure 3 is a schematic diagram of a host system and a memory storage device shown according to an exemplary embodiment of the present invention;

[0024] Figure 4 is a schematic diagram of a memory storage device shown according to an exemplary embodiment of the present invention;

[0025] Figure 5 is a schematic diagram of a memory controller shown according to an exemplary embodiment of the present invention;

[0026] Figure 6 is a schematic diagram of managing a memory module shown according to an exemplary embodiment of the present invention;

[0027] Figure 7 is a flowchart of a data write control method shown according to an exemplary embodiment of the present invention;

[0028] Figure 8 is a flowchart of a data write control method shown according to an exemplary embodiment of the present invention. Detailed Embodiments

[0029] Reference will now be made in detail to exemplary embodiments of the present invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numerals will be used in the drawings and the description to refer to the same or like parts.

[0030] Generally, a memory storage device (also referred to as a memory storage system) includes a rewritable non-volatile memory module and a controller (also referred to as a control circuit). The memory storage device can be used with a host system so that the host system can write data to the memory storage device or read data from the memory storage device.

[0031] Figure 1 FIG. is a schematic diagram of a host system, a memory storage device, and an input / output (I / O) device according to an exemplary embodiment of the present invention. Figure 2 FIG. is a schematic diagram of a host system, a memory storage device, and an I / O device according to an exemplary embodiment of the present invention.

[0032] Please refer to Figure 1 and Figure 2 , the host system 11 may include a processor 111, a random access memory (RAM) 112, a read only memory (ROM) 113, and a data transmission interface 114. The processor 111, the random access memory 112, the read only memory 113, and the data transmission interface 114 may be coupled to a system bus 110.

[0033] In an exemplary embodiment, the host system 11 may be coupled to the memory storage device 10 through the data transmission interface 114. For example, the host system 11 may store data to the memory storage device 10 or read data from the memory storage device 10 via the data transmission interface 114. In addition, the host system 11 may be coupled to the I / O device 12 through the system bus 110. For example, the host system 11 may transmit an output signal to the I / O device 12 or receive an input signal from the I / O device 12 via the system bus 110.

[0034] In an exemplary embodiment, the processor 111, the random access memory 112, the read only memory 113, and the data transmission interface 114 may be disposed on a motherboard 20 of the host system 11. The number of the data transmission interfaces 114 may be one or more. Through the data transmission interface 114, the motherboard 20 may be coupled to the memory storage device 10 in a wired or wireless manner.

[0035] In an exemplary embodiment, the memory storage device 10 may be, for example, a USB flash drive 201, a memory card 202, a solid state drive (SSD) 203, or a wireless memory storage device 204. The wireless memory storage device 204 may be, for example, a near field communication (NFC) memory storage device, a wireless fidelity (WiFi) memory storage device, a Bluetooth memory storage device, or a low energy Bluetooth memory storage device (e.g., iBeacon), etc., which are memory storage devices based on various wireless communication technologies. In addition, the motherboard 20 may also be coupled to various I / O devices such as a global positioning system (GPS) module 205, a network interface card 206, a wireless transmission device 207, a keyboard 208, a screen 209, a speaker 210, etc. via a system bus 110. For example, in an exemplary embodiment, the motherboard 20 may access the wireless memory storage device 204 via the wireless transmission device 207.

[0036] In an exemplary embodiment, the host system 11 is a computer system. In an exemplary embodiment, the host system 11 may be any system that can substantially cooperate with the memory storage device to store data. In an exemplary embodiment, the host system 11 is a vehicle-mounted system. In an exemplary embodiment, the memory storage device 10 and the host system 11 may respectively include Figure 3 the memory storage device 30 and the host system 31.

[0037] Figure 3 is a schematic diagram of the host system and the memory storage device shown in the exemplary embodiment of the present invention.

[0038] Please refer to Figure 3 , the memory storage device 30 may be used in conjunction with the host system 31 to store data. For example, the host system 31 may be a system such as a digital camera, a video camera, a communication device, an audio player, a video player, or a tablet computer. For example, the memory storage device 30 may be various non-volatile memory storage devices such as a secure digital (SD) card 32, a compact flash (CF) card 33, or an embedded storage device 34 used by the host system 31. The embedded storage device 34 includes various types of embedded storage devices such as an embedded multi media card (eMMC) 341 and / or an embedded multi chip package (eMCP) storage device 342, etc., which directly couple the memory module to the substrate of the host system.

[0039] Figure 4 It is a schematic diagram of a memory storage device shown in an exemplary embodiment of the present invention.

[0040] Please refer to Figure 4 , the memory storage device 10 includes a connection interface unit 41, a memory controller 42, and a memory module 43.

[0041] The connection interface unit 41 is used to couple the memory storage device 10 to the host system 11. The memory storage device 10 can communicate with the host system 11 via the connection interface unit 41. In an exemplary embodiment, the connection interface unit 41 is compatible with the Peripheral Component Interconnect Express (PCI Express) standard. In an exemplary embodiment, the connection interface unit 41 can also be compliant with the Serial Advanced Technology Attachment (SATA) standard, the Parallel Advanced Technology Attachment (PATA) standard, the Institute of Electrical and Electronic Engineers (IEEE) 1394 standard, the Universal Serial Bus (USB) standard, the SD interface standard, the Ultra High Speed-I (UHS-I) interface standard, the Ultra High Speed-II (UHS-II) interface standard, the Memory Stick (MS) interface standard, the MCP interface standard, the MMC interface standard, the eMMC interface standard, the Universal Flash Storage (UFS) interface standard, the eMCP interface standard, the CF interface standard, the Integrated Device Electronics (IDE) standard, or other suitable standards. The connection interface unit 41 can be packaged in a single chip with the memory controller 42, or the connection interface unit 41 is disposed outside a chip containing the memory controller 42.

[0042] The memory controller 42 is coupled to the connection interface unit 41 and the memory module 43. The memory controller 42 is used to execute a plurality of logic gates or control instructions implemented in hardware or firmware form and perform operations such as data writing, reading, and erasing in the memory module 43 according to the instructions of the host system 11.

[0043] The memory module 43 is used to store data written by the host system 11. The memory module 43 may include a single-level cell (SLC) NAND flash memory module (i.e., a flash memory module in which 1 bit can be stored in one memory cell), a multi-level cell (MLC) NAND flash memory module (i.e., a flash memory module in which 2 bits can be stored in one memory cell), a triple-level cell (TLC) NAND flash memory module (i.e., a flash memory module in which 3 bits can be stored in one memory cell), a quad-level cell (QLC) NAND flash memory module (i.e., a flash memory module in which 4 bits can be stored in one memory cell), other flash memory modules, or other memory modules with the same characteristics.

[0044] Each memory cell in the memory module 43 stores one or more bits by a change in voltage (hereinafter also referred to as the threshold voltage). Specifically, there is a charge trapping layer between the control gate and the channel of each memory cell. By applying a write voltage to the control gate, the amount of electrons in the charge trapping layer can be changed, thereby changing the threshold voltage of the memory cell. This operation of changing the threshold voltage of the memory cell is also referred to as "writing data into the memory cell" or "programming the memory cell". As the threshold voltage changes, each memory cell in the memory module 43 has multiple storage states. By applying a read voltage, it can be determined which storage state a memory cell belongs to, and thereby obtain one or more bits stored in this memory cell.

[0045] In an exemplary embodiment, the memory cells of the memory module 43 may form multiple physical programming units, and these physical programming units may form multiple physical units. Specifically, the memory cells on the same word line may form one or more physical programming units. If each memory cell can store more than 2 bits, the physical programming units on the same word line can be at least classified into a lower physical programming unit and an upper physical programming unit. For example, the least significant bit (LSB) of a memory cell belongs to the lower physical programming unit, and the most significant bit (MSB) of a memory cell belongs to the upper physical programming unit. Generally speaking, in an MLC NAND flash memory, the write speed of the lower physical programming unit is greater than that of the upper physical programming unit, and / or the reliability of the lower physical programming unit is higher than that of the upper physical programming unit.

[0046] In an exemplary embodiment, the physical programming unit is the smallest unit for programming. That is, the physical programming unit is the smallest unit for writing data. For example, the physical programming unit can be a physical page or a physical sector. If the physical programming unit is a physical page, these physical programming units can include a data bit area and a redundancy bit area. The data bit area contains a plurality of physical sectors for storing user data, and the redundancy bit area is used for storing system data (e.g., management data such as error correction codes). In this exemplary embodiment, the data bit area contains 32 physical sectors, and the size of one physical sector is 512 bytes (byte, B). However, in other exemplary embodiments, the data bit area may also contain 8, 16, or a greater or smaller number of physical sectors, and the size of each physical sector can also be larger or smaller. On the other hand, the physical unit is the smallest unit for erasing. That is, each physical unit contains the smallest number of storage units that are erased together. For example, the physical unit is a physical block.

[0047] Figure 5 is a schematic diagram of a memory controller according to an exemplary embodiment of the present invention.

[0048] Please refer to Figure 5 , the memory controller 42 includes a memory management circuit 51, a host interface 52, and a memory interface 53.

[0049] The memory management circuit 51 is used to control the overall operation of the memory controller 42. Specifically, the memory management circuit 51 has a plurality of control instructions, and when the memory storage device 10 operates, these control instructions will be executed to perform operations such as data writing, reading, and erasing. When explaining the operation of the memory management circuit 51 below, it is equivalent to explaining the operation of the memory controller 42.

[0050] In an exemplary embodiment, the control instructions of the memory management circuit 51 are implemented in the form of firmware. For example, the memory management circuit 51 has a microprocessor unit (not shown) and a read-only memory (not shown), and these control instructions are burned into this read-only memory. When the memory storage device 10 operates, these control instructions will be executed by the microprocessor unit to perform operations such as data writing, reading, and erasing.

[0051] In an exemplary embodiment, the control instructions of the memory management circuit 51 may also be stored in a specific area of the memory module 43 in the form of code (e.g., the system area of the memory module dedicated to storing system data). In addition, the memory management circuit 51 has a microprocessor unit (not shown), a read-only memory (not shown), and a random access memory (not shown). In particular, this read-only memory has a boot code, and when the memory controller 42 is enabled, the microprocessor unit first executes this boot code to load the control instructions stored in the memory module 43 into the random access memory of the memory management circuit 51. After that, the microprocessor unit runs these control instructions to perform operations such as writing, reading, and erasing data.

[0052] In an exemplary embodiment, the control instructions of the memory management circuit 51 may also be implemented in a hardware form. For example, the memory management circuit 51 includes a microcontroller, a storage unit management circuit, a memory write circuit, a memory read circuit, a memory erase circuit, and a data processing circuit. The storage unit management circuit, the memory write circuit, the memory read circuit, the memory erase circuit, and the data processing circuit are coupled to the microcontroller. The storage unit management circuit is used to manage the storage units or groups of storage units of the memory module 43. The memory write circuit is used to issue a write instruction sequence to the memory module 43 to write data into the memory module 43. The memory read circuit is used to issue a read instruction sequence to the memory module 43 to read data from the memory module 43. The memory erase circuit is used to issue an erase instruction sequence to the memory module 43 to erase data from the memory module 43. The data processing circuit is used to process the data to be written into the memory module 43 and the data read from the memory module 43. The write instruction sequence, the read instruction sequence, and the erase instruction sequence may each include one or more codes or instruction codes and are used to instruct the memory module 43 to perform corresponding write, read, and erase operations. In an exemplary embodiment, the memory management circuit 51 may also issue other types of instruction sequences to the memory module 43 to instruct the execution of corresponding operations.

[0053] The host interface 52 is coupled to the memory management circuit 51. The memory management circuit 51 can communicate with the host system 11 through the host interface 52. The host interface 52 is used to receive and identify the instructions and data transmitted by the host system 11. For example, the instructions and data transmitted by the host system 11 can be transmitted to the memory management circuit 51 through the host interface 52. In addition, the memory management circuit 51 can transmit data to the host system 11 through the host interface 52. In this exemplary embodiment, the host interface 52 is compatible with the PCI Express standard. However, it must be understood that the present invention is not limited thereto, and the host interface 52 can also be compatible with the SATA standard, PATA standard, IEEE 1394 standard, USB standard, SD standard, UHS-I standard, UHS-II standard, MS standard, MMC standard, eMMC standard, UFS standard, CF standard, IDE standard, or other suitable data transmission standards.

[0054] The memory interface 53 is coupled to the memory management circuit 51 and is used to access the memory module 43. For example, the memory management circuit 51 can access the memory module 43 through the memory interface 53. That is, the data to be written to the memory module 43 will be converted into a format acceptable to the memory module 43 through the memory interface 53. Specifically, if the memory management circuit 51 wants to access the memory module 43, the memory interface 53 will transmit a corresponding instruction sequence. For example, these instruction sequences can include a write instruction sequence for indicating writing data, a read instruction sequence for indicating reading data, an erase instruction sequence for indicating erasing data, and corresponding instruction sequences for indicating various memory operations (such as changing the read voltage level or performing a garbage collection operation, etc.). These instruction sequences are, for example, generated by the memory management circuit 51 and transmitted to the memory module 43 through the memory interface 53. These instruction sequences can include one or more signals, or data on the bus. These signals or data can include instruction codes or codes. For example, in the read instruction sequence, information such as the read identification code and memory address will be included.

[0055] In an exemplary embodiment, the memory controller 42 further includes an error checking and correction circuit 54, a buffer memory 55, and a power management circuit 56.

[0056] The error checking and correcting circuit 54 is coupled to the memory management circuit 51 and is configured to perform error checking and correcting operations to ensure the correctness of data. Specifically, when the memory management circuit 51 receives a write command from the host system 11, the error checking and correcting circuit 54 generates corresponding error correcting code (ECC) and / or error detecting code (EDC) for the data corresponding to this write command, and the memory management circuit 51 writes the data corresponding to this write command and the corresponding error correcting code and / or error detecting code into the memory module 43. After that, when the memory management circuit 51 reads data from the memory module 43, it simultaneously reads the corresponding error correcting code and / or error detecting code of this data, and the error checking and correcting circuit 54 performs error checking and correcting operations on the read data based on this error correcting code and / or error detecting code.

[0057] The buffer memory 55 is coupled to the memory management circuit 51 and is configured to temporarily store data. The power management circuit 56 is coupled to the memory management circuit 51 and is configured to control the power supply of the memory storage device 10.

[0058] In an exemplary embodiment, Figure 4 the memory module 43 may include a flash memory module. In an exemplary embodiment, Figure 4 the memory controller 42 may include a flash memory controller. In an exemplary embodiment, Figure 5 the memory management circuit 51 may include a flash memory management circuit.

[0059] Figure 6 is a schematic diagram of managing a memory module according to an exemplary embodiment of the present invention.

[0060] Please refer to Figure 6 , the memory management circuit 51 may logically group the physical units 610(0) - 610(B) in the memory module 43 into a storage area 601 and a spare area 602. One physical unit refers to a virtual block (VB). A virtual block may include multiple physical programming units. For example, a virtual block may contain one or more physical units.

[0061] The physical units 610(0) - 610(A) in the storage area 601 are used to store user data (such as from Figure 1user data of the host system 11). For example, the physical units 610(0) to 610(A) in the storage area 601 can store valid data and invalid data. The physical units 610(A + 1) to 610(B) in the idle area 602 do not store data (such as valid data). For example, if a physical unit does not store valid data, this physical unit can be associated (or added) to the idle area 602. In addition, the physical units in the idle area 602 (or physical units that do not store valid data) can be erased. When writing new data, one or more physical units can be extracted from the idle area 602 to store this new data. In an exemplary embodiment, the idle area 602 is also referred to as a free pool.

[0062] The memory management circuit 51 can configure the logic units 612(0) to 612(C) to map the physical units 610(0) to 610(A) in the storage area 601. In an exemplary embodiment, each logic unit corresponds to a logical address. For example, a logical address can include one or more logical block addresses (LBAs) or other logical management units.

[0063] It should be noted that a logic unit can be mapped to one or more physical units. If a physical unit is currently mapped by a logic unit, it means that the data stored in this physical unit currently contains valid data. Conversely, if a physical unit is not currently mapped by any logic unit, it means that the data stored in this physical unit does not contain any valid data.

[0064] The memory management circuit 51 can record the management data (also referred to as logical-to-physical mapping information) describing the mapping relationship between the logic units and the physical units in at least one logical-to-physical mapping table. When the host system 11 wants to read data from the memory storage device 10 or write data to the memory storage device 10, the memory management circuit 51 can perform data access operations on the memory storage device 10 according to the information in this logical-to-physical mapping table.

[0065] The memory storage device 10 has the characteristic of data retention. When the physical units in the memory module 43 are not used for a long time and / or the physical units are not written with data, problems such as data loss and / or damage may occur due to charge leakage. Accordingly, when the memory storage device 10 is initialized (i.e., card opening), the memory management circuit 51 can pre-write dummy data into all the physical units in the memory module 43 that are not full, to ensure the transmission efficiency between the memory management circuit 51 and the memory module 43 and the integrity and correctness of the data.

[0066] In the conventional approach, a memory management circuit 51 generates a sequence of write instructions for indicating the writing of virtual data, and transmits the sequence of write instructions to a memory interface 53. Then, the memory interface 53 transmits the sequence of write instructions to a memory module 43 to write the virtual data into the memory module 43. It should be noted that the physical programming unit (for example, a physical page) is the smallest unit for writing. Therefore, the memory management circuit 51 usually transmits the sequence of write instructions to the memory interface 53 multiple times in units of physical pages to pre-write the virtual data into all the physical units in the memory module 43 that are not fully written.

[0067] However, the operation of the memory management circuit 51 transmitting the sequence of write instructions to the memory interface 53 multiple times will cause the process of pre-writing the virtual data into the memory module 43 to consume a large amount of time cost and resource usage.

[0068] In view of this, the present invention provides a data writing control method. The memory interface 53 can generate a sequence of write instructions for indicating the writing of virtual data, and transmit the sequence of write instructions to the memory module 43 to write the virtual data into the memory module 43, so as to save time cost and improve the performance of the memory storage device 10. In addition, the memory interface 53 can also monitor whether multiple write operations for writing virtual data fail, so as to improve data correctness and integrity.

[0069] Figure 7 It is a flowchart of the data writing control method shown in an exemplary embodiment of the present invention. Please refer to Figure 7 。

[0070] In step S701, the memory interface 53 can receive configuration information and interrupt information, and generate multiple sequences of write instructions according to the configuration information.

[0071] In an exemplary embodiment, the configuration information may include but is not limited to a start and end address and write data. The start and end address is used to indicate the physical addresses of multiple physical units (for example, multiple physical blocks) that need to be written with the write data, where the write data is virtual data.

[0072] In an exemplary embodiment, the memory interface 53 supports an auto program operation with a physical unit (that is, a physical block) as the smallest unit. The memory interface 53 can generate multiple sequences of write instructions according to the start and end addresses in the configuration information. Specifically, the configuration information mentioned in the solution of the present application is transmitted to the memory interface 53 in the form of instructions through the memory management circuit 51.

[0073] Specifically, the memory interface 53 can parse the to-be-executed instructions transmitted by the memory management circuit 51, and obtain the configuration information in the to-be-executed instructions. The configuration information includes, but is not limited to: multiple pieces of data to be written and the start and end address information of data writing. Further, according to the configuration information, a sequence of write instructions in units of physical programming units is generated in batches.

[0074] Accordingly, the memory management circuit 51 only needs to transmit the to-be-executed instructions containing the configuration information to the memory interface 53, instead of generating and transmitting the write instruction sequence to the memory interface 53 multiple times as in the above conventional method. In this way, the usage cost of the memory management circuit 51 can be effectively reduced, and the data writing efficiency can be improved by reducing the instruction interaction process.

[0075] In step S702, the memory interface 53 can sequentially execute multiple write operations corresponding to the multiple write instruction sequences, and monitor the execution results of each write operation.

[0076] In an exemplary embodiment, the memory interface 53 can sequentially issue multiple write instruction sequences to the memory module 43 to sequentially execute multiple write operations, so as to write virtual data into multiple to-be-written physical units in the memory module 43. At the same time, the memory interface 53 can monitor the execution results of each write operation, and determine the corresponding execution strategy according to the execution results and / or interruption information of each write operation until multiple write operations are completed.

[0077] In step S703, the memory interface 53 can determine whether the current write operation (also referred to as the first write operation) fails according to the execution result.

[0078] In an exemplary embodiment, the foregoing execution strategy includes a first execution strategy and a second execution strategy. If the execution result corresponding to the first write operation (also referred to as the first execution result) indicates that the first write operation does not fail, the memory interface 53 can determine the execution strategy as the first execution strategy and enter step S704. In contrast, if the first execution result indicates that the first write operation fails, the memory interface 53 can further determine the execution strategy according to the interruption information and enter step S705.

[0079] In step S704, the memory interface 53 can determine whether the current write operation (that is, the first write operation) is the last one among the foregoing multiple write operations. If the current write operation is the last one, that is, the foregoing multiple write operations are all completed, the memory interface 53 can end Figure 7The method for controlling data writing. In contrast, if the current writing operation is not the last one, that is, there are unfinished writing operations among the foregoing multiple writing operations (that is, writing operations to be executed), the memory interface 53 can return to step S702 to complete the writing operations to be executed. That is to say, the first execution strategy includes sequentially executing multiple writing operations until all the multiple writing operations are completed.

[0080] On the other hand, in step S705, the memory interface 53 can determine whether to perform an error handling operation according to the interrupt information.

[0081] In an exemplary embodiment, the interrupt information includes bad block table information and key area information. Specifically, the key area information can be used to indicate relevant information (such as a physical address) of physical units that need to be key-checked. The memory interface 53 can determine whether the first physical unit corresponding to the first writing operation (one of the multiple physical units to be written) is recorded in the key area information to decide whether to perform an error handling operation on the first physical unit.

[0082] If the first physical unit is not recorded in the key area information, the memory interface 53 can determine that no error handling operation needs to be performed, and determine the execution strategy as the first execution strategy to return to step S704. The implementation details of step S704 have been described in detail in the foregoing exemplary embodiment, so they will not be repeated here. It should be noted that the virtual data is only used to fill the unfilled physical units to avoid problems such as data loss and / or damage caused by charge leakage. Therefore, the actual content of the virtual data is not important. Thus, if the first writing operation fails and the first physical unit is not a physical unit that needs to be key-checked, the memory interface 53 does not need to report this error to the memory management circuit 51 (that is, does not perform an error handling operation), and continues to execute the writing operations to be executed.

[0083] In contrast, if the first physical unit is recorded in the key area information (that is, the first physical unit is a physical unit that needs to be key-checked), the memory interface 53 can determine that an error handling operation needs to be performed, and determine the execution strategy as the second execution strategy to enter step S706.

[0084] In step S706, the memory interface 53 can interrupt the writing operations to be executed.

[0085] Specifically, the memory interface 53 can temporarily interrupt the writing operations to be executed to facilitate subsequent execution of the error handling operation.

[0086] After that, in step S707, the memory interface 53 can determine whether the first physical unit is recorded in the bad block table according to the bad block table information included in the interrupt information.

[0087] In an exemplary embodiment, the bad block table information is used to indicate all bad blocks in the memory module 43 (e.g., all factory bad blocks). If the first physical unit is recorded in the block table, the process returns to step S704. Specifically, if the first physical unit has been recorded in the block table, which means the first physical unit is a factory bad block (also known as an initial bad block), the memory interface 53 can return to step S704 to continue performing the pending write operation or end Figure 7 the data write control method.

[0088] In contrast, if the first physical unit is not recorded in the block table, the process proceeds to step S708.

[0089] In step S708, the memory interface 53 can update the bad block table.

[0090] In an exemplary embodiment, the memory interface 53 can record the relevant information of the first physical unit in the bad block table to update the bad block table, and then return to step S704 to continue performing the pending write operation or end Figure 7 the data write control method.

[0091] That is to say, the second execution strategy includes interrupting the pending write operation, performing an error handling operation according to the interrupt information, and continuing to perform the pending write operation until multiple write operations are completed.

[0092] According to the above, for the data write control method provided by the present invention, the memory management circuit 51 can transmit configuration information and interrupt information to the memory interface 53, and then the memory interface 53 that supports the auto program operation can generate a sequence of multiple write instructions according to the configuration information, and accordingly write virtual data into all the physical units in the memory module 43 that are not fully written (i.e., the physical blocks to be written), so as to avoid the problem of data loss and / or damage caused by the data retention characteristics of the memory storage device 10.

[0093] It should be noted that compared with the conventional method of the memory management circuit 51 generating and transmitting a sequence of multiple write instructions for writing virtual data to the memory interface 53, for the data write control method provided by the present invention, the memory interface 53 generates a sequence of multiple write instructions according to the configuration information received from the memory management circuit 51, which can effectively save the usage cost of the memory management circuit 51 and greatly reduce the time cost required to fill the memory module 43 with virtual data. In addition, during the process of writing virtual data, the data write control method of the present invention can also monitor whether each write operation corresponding to the sequence of multiple write instructions fails by the memory interface 53 and adopt corresponding execution strategies to improve data correctness and integrity.

[0094] It is worth mentioning that since Figure 7 the data writing control method is executed when the memory storage device 10 is initialized (i.e., card opening), therefore, when the memory controller 42 completes Figure 7 the data writing control method, the bad block table of the memory storage device 10 at the time of factory will also be updated by the memory controller 42 accordingly. In this way, the error rate of subsequent erase, write, and / or read operations can be effectively reduced.

[0095] Figure 8 is a flowchart of the data writing control method shown in an exemplary embodiment of the present invention. Please refer to Figure 8 . In step S801, configuration information and interrupt information are received, and multiple write instruction sequences are generated according to the configuration information, where the configuration information includes write data and start and end addresses. In step S802, multiple write operations corresponding to the multiple write instruction sequences are sequentially executed, and the execution result of each write operation is monitored. In step S803, an execution strategy is determined according to the execution result and / or interrupt information until the multiple write operations are completed.

[0096] However, Figure 8 each step in Figure 8 has been described in detail above and will not be elaborated here. It should be noted that Figure 8 each step in

[0097] can be implemented as multiple pieces of program code or circuits, and the present invention does not limit this. In addition, Figure 8 the method of

[0097] can be used in conjunction with the above embodiments or used alone, and the present invention does not limit this.

[0097] In summary, the data writing control method and the memory storage device proposed in the exemplary embodiments of the present invention can generate multiple write instruction sequences by the memory interface according to the configuration information received from the memory management circuit, and execute multiple write operations accordingly to write virtual data into the memory module, which can improve the performance and initialization efficiency of the memory storage device and avoid the problems of data loss and / or damage caused by charge leakage. In addition, the data writing control method and the memory storage device proposed in the exemplary embodiments of the present invention can also monitor whether the above-mentioned multiple write operations fail by the memory interface, and adopt corresponding execution strategies to perform error handling operations during the execution of the multiple write operations, so as to greatly improve data correctness and effectively reduce the error rate of subsequent erase, write, and / or read operations.

[0098] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it; although the present invention has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that they can still modify the technical solutions described in the foregoing embodiments, or perform equivalent replacements on some or all of the technical features; and these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A data writing control method, characterized in that, For a memory storage device, the memory storage device includes a memory controller and a memory module, and the data writing control method includes: Receiving configuration information and interruption information, and generating a plurality of writing instruction sequences according to the configuration information, where the configuration information includes writing data and start and end addresses; Sequentially performing a plurality of writing operations corresponding to the plurality of writing instruction sequences, and monitoring the execution results of each of the writing operations; and Determining an execution strategy according to the execution results and / or the interruption information until the plurality of writing operations are completed.

2. The data writing control method according to claim 1, where the execution strategy includes a first execution strategy and a second execution strategy, and the step of determining the execution strategy according to the execution results and / or the interruption information includes: If a first execution result corresponding to a first writing operation indicates that the first writing operation has not failed, determining that the execution strategy is the first execution strategy, where the first writing operation is one of the plurality of writing operations; and If the first execution result indicates that the first writing operation has failed, determining the execution strategy according to the interruption information.

3. The data writing control method according to claim 2, where the step of determining the execution strategy according to the interruption information includes: Judging whether to perform an error handling operation according to the interruption information; If so, determining that the execution strategy is the second execution strategy; And If not, determining that the execution strategy is the first execution strategy.

4. The data writing control method according to claim 3, where the first execution strategy includes sequentially performing the plurality of writing operations until the plurality of writing operations are completed, The second execution strategy includes interrupting the to-be-executed writing operation and performing the error handling operation according to the interruption information; and, Continuing to perform the to-be-executed writing operation until the plurality of writing operations are completed.

5. The data writing control method according to claim 3, wherein the interruption information includes: Bad block table information and key area information, where the step of judging whether to perform the error handling operation according to the interruption information includes: Judging whether a first physical unit corresponding to the first writing operation is recorded in the key area information; and If the first physical unit is recorded in the key area information, interrupting the to-be-executed writing operation and performing the error handling operation according to the bad block table information.

6. The data writing control method according to claim 5, where the step of performing the error handling operation according to the bad block table information includes: Judging whether the first physical unit is recorded in the bad block table according to the bad block table information; If the first physical unit is not recorded in the bad block table, updating the bad block table and continuing to perform the to-be-executed writing operation; And If the first physical unit is recorded in the bad block table, continuing to perform the to-be-executed writing operation.

7. The data writing control method according to claim 5, further includes: If the first physical unit is not recorded in the key area information, not performing the error handling operation and continuing to perform the to-be-executed writing operation.

8. The data writing control method according to claim 1, wherein the written data is virtual data.

9. A memory storage device, characterized in that, Comprising: A connection interface unit for coupling to a host system; A memory module; And A memory controller coupled to the connection interface unit and the memory module, wherein the memory controller is configured to: Receive configuration information and interruption information, and generate a plurality of write instruction sequences according to the configuration information, wherein the configuration information includes written data and start and end addresses; Sequentially execute a plurality of write operations corresponding to the plurality of write instruction sequences, and monitor the execution results of each of the write operations; Determine an execution strategy according to the execution results and / or the interruption information until the plurality of write operations are completed.

10. The memory storage device according to claim 9, wherein the execution strategy includes a first execution strategy and a second execution strategy, wherein, If a first execution result corresponding to a first write operation indicates that the first write operation has not failed, the memory controller determines that the execution strategy is the first execution strategy, wherein the first write operation is one of the plurality of write operations, and If the first execution result indicates that the first write operation has failed, the memory controller determines the execution strategy according to the interruption information.

11. The memory storage device according to claim 10, wherein the memory controller is further configured to determine whether to perform an error handling operation according to the interruption information, If so, the memory controller determines that the execution strategy is the second execution strategy, and If not, the memory controller determines that the execution strategy is the first execution strategy.

12. The memory storage device according to claim 11, wherein the first execution strategy includes sequentially executing the plurality of write operations until the plurality of write operations are completed, The second execution strategy includes interrupting a write operation to be executed, and performing the error handling operation according to the interruption information; and, Continuing to execute the write operation to be executed until the plurality of write operations are completed.

13. The memory storage device according to claim 11, wherein the interruption information includes: Bad block table information and key area information, wherein, The memory controller determines whether a first physical unit corresponding to the first write operation is recorded in the key area information, and If the first physical unit is recorded in the key area information, the memory controller interrupts the write operation to be executed, and performs the error handling operation according to the bad block table information.

14. The memory storage device according to claim 13, wherein the memory controller is further configured to determine whether the first physical unit is recorded in the bad block table according to the bad block table information, If the first physical unit is not recorded in the bad block table, the memory controller updates the bad block table and continues to execute the write operation to be executed, and If the first physical unit is recorded in the bad block table, the memory controller continues to execute the write operation to be executed.

15. The memory storage device according to claim 13, wherein if the first physical unit is not recorded in the key area information, the memory controller does not perform the error handling operation and continues to perform the write operation to be executed.

16. The memory storage device according to claim 9, wherein the written data is virtual data.

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