Data processing method, storage medium, electronic device and program product

Abstract

The present application discloses a data processing method, storage medium, electronic device, and program product, relating to the field of data storage technology. The method first obtains temperature information of a flash memory storage unit, the number of erase / write times corresponding to each block in the flash memory storage unit, and historical access information of each page corresponding to each block; then, based on the temperature information and the number of erase / write times, analyzes charge leakage risk information corresponding to each block; then, based on the historical access information, analyzes access heat information corresponding to each page; based on the charge leakage risk information and access heat information, generates a refresh list, wherein the refresh list stores a target block and a target page corresponding to the target block; finally, executes a refresh function according to the refresh list to read the data of the target page into the page register of the flash memory storage unit. Compared with the current existing technology, the present application improves the pertinence and execution efficiency of the refresh operation, and avoids the resource waste problem caused by fixed-cycle and fixed-position refresh.

Description

Technical Field

[0001] The present disclosure relates to the technical field of data storage, and in particular to a data processing method, a storage medium, an electronic device, and a program product. Background Art

[0002] NAND flash memory is a commonly used storage technology that uses a special type of transistor—a floating-gate transistor—to store data. These transistors have an insulating layer that locks the charge representing the data. Over time, this insulating layer can allow some charge to "leak," especially in high-temperature environments. Data that has not been read for a long time can drift in threshold voltage, leading to an increase in the first-read bit error rate (BER).

[0003] In order to solve the above problem, the current related technology uses a refresh function to periodically traverse all blocks, read the corresponding page data into the page register according to a fixed read position, and refresh the charge state.

[0004] However, the page data read into the page register according to the fixed read position may be data that the host does not need to read, which wastes resources and increases the time and bandwidth occupied when the refresh function is executed. Summary of the Invention

[0005] The present disclosure provides a data processing method, storage medium, electronic device, and program product. The main purpose is to solve the problem that related technologies read page data from a page register according to a fixed read position, which may lead to resource waste and increase the time and bandwidth occupied by the refresh function.

[0006] In a first aspect, the present application provides a data processing method, comprising:

[0007] Acquire temperature information of a flash memory storage unit, the number of erase / write times corresponding to each block in the flash memory storage unit, and historical access information of each page corresponding to each block;

[0008] Analyzing charge leakage risk information corresponding to each block according to the temperature information and the number of erase and write times;

[0009] Analyzing the access popularity information corresponding to each page according to the historical access information;

[0010] generating a refresh list based on the charge leakage risk information and the access heat information, wherein the refresh list stores a target block and a target page corresponding to the target block;

[0011] A refresh function is executed according to the refresh list to read the data of the target page into the page register of the flash memory storage unit.

[0012] In a second aspect, the present application provides a data processing device, comprising:

[0013] an acquisition module configured to acquire temperature information of a flash memory storage unit, a number of erase / write times corresponding to each block in the flash memory storage unit, and historical access information of each page corresponding to each block;

[0014] A first analysis module is configured to analyze charge leakage risk information corresponding to each block according to the temperature information and the number of erase and write times;

[0015] A second analysis module is configured to analyze access popularity information corresponding to each page based on the historical access information;

[0016] a generating module configured to generate a refresh list based on the charge leakage risk information and the access heat information, wherein the refresh list stores a target block and a target page corresponding to the target block;

[0017] The execution module is configured to execute a refresh function according to the refresh list to read the data of the target page into the page register of the flash memory storage unit.

[0018] In a third aspect, the present application provides a computer-readable storage medium having a computer program stored thereon, which implements the method of the first aspect when the computer program is executed by a processor.

[0019] In a fourth aspect, the present application provides an electronic device comprising a storage medium, a processor, and a computer program stored on the storage medium and executable on the processor, wherein the processor implements the method of the first aspect when executing the computer program.

[0020] In a fifth aspect, the present application provides a computer program product having a computer program stored thereon, which implements the method of the first aspect when the computer program is executed by a processor.

[0021] The present disclosure provides a data processing method, storage medium, electronic device and program product, wherein the method includes: first obtaining temperature information of a flash memory storage unit, the number of erase and write times corresponding to each block in the flash memory storage unit, and historical access information of each page corresponding to each block; then analyzing charge leakage risk information corresponding to each block based on the temperature information and the number of erase and write times; then analyzing access heat information corresponding to each page based on the historical access information; generating a refresh list based on the charge leakage risk information and the access heat information, wherein the refresh list stores a target block and a target page corresponding to the target block; finally, executing a refresh function according to the refresh list to read the data of the target page into the page register of the flash memory storage unit. Compared with the current existing technology, this application dynamically generates a refresh list and performs on-demand refresh by comprehensively considering multi-dimensional information such as temperature, number of erase and write times, and page access popularity, thereby improving the targetedness and execution efficiency of the refresh operation, avoiding the resource waste caused by fixed-cycle and fixed-position refresh, and at the same time, after the refresh, the high-priority page data is moved to the page register of the flash storage unit in combination with the bus status, further realizing pre-read optimization, reducing the delay and bandwidth occupancy during actual host reading, thereby significantly improving the overall performance and energy efficiency of the storage system while ensuring data reliability.

[0022] It should be understood that the content described in this section is not intended to identify the key or important features of the embodiments of the present application, nor is it intended to limit the scope of the present application. Other features of the present application will become easily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] In order to more clearly illustrate the embodiments of the present application, the following is a brief introduction to the drawings required for use in the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0024] Figure 1 A flow chart of a data processing method provided in an embodiment of the present application is shown;

[0025] Figure 2 A flow chart of another data processing method provided in an embodiment of the present application is shown;

[0026] Figure 3 A schematic diagram showing an example provided by an embodiment of the present application is shown;

[0027] Figure 4 A structural diagram of a data processing device provided in an embodiment of the present application is shown. DETAILED DESCRIPTION

[0028] The following will be combined with the accompanying drawings in the embodiments of this application to clearly and completely describe the technical solutions in the embodiments of this application. Obviously, the embodiments described are only part of the embodiments of this application, not all of them. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of this application.

[0029] It should be noted that, in the description of this application, the terms "comprises," "includes," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or device comprising a series of elements includes not only those elements, but also other elements not explicitly listed, or elements inherent to such process, method, article, or device. The terms "first," "second," etc., in this application are used to distinguish similar objects, and are not used to describe a particular order or sequence.

[0030] The insulating layer of the floating-gate transistor in NAND flash memory cells leaks charge over time. This causes threshold voltage drift in data that has not been read for a long time, leading to increased first-time read error rates. In high-temperature environments (>55°C), this charge leakage accelerates, potentially reducing data retention to less than 30% of its original value.

[0031] Related technologies typically use a refresh function to periodically traverse all blocks, refreshing the charge state by reading data from a specified page into a page register. However, this method has limitations: after a refresh, the data is only stored in the page register and not cached in external memory. Subsequent host access requires data movement, wasting time and bandwidth. Furthermore, the fixed read position makes the probability of the host hitting the specified page extremely low, further reducing the efficiency of the refresh operation. The refresh strategy remains static regardless of the number of program / erase cycles (PE) and temperature conditions, lacking flexibility.

[0032] In order to improve the technical problem that the current related technology reads page data into the page register according to a fixed read position, which may cause resource waste and increase the time and bandwidth occupied when the refresh function is executed.

[0033] This embodiment provides a data processing method, such as Figure 1 As shown, the method comprises the following steps:

[0034] Step 101: Acquire temperature information of a flash memory storage unit, the number of erase / write times corresponding to each block in the flash memory storage unit, and historical access information of each page corresponding to each block.

[0035] In some examples, temperature information can be directly read through temperature sensors integrated on the NAND Flash chip or its controller. These sensors monitor the operating temperature of the storage device in real time and feed the data back to the system's monitoring module.

[0036] In some examples, the number of erase / write cycles is automatically tracked by the firmware and recorded in the metadata as an important indicator of the wear level of each block. Each time a program (write) or erase operation is performed, the corresponding counter is incremented, ensuring that the aging status of each block can be accurately assessed.

[0037] In some examples, historical access information is collected through an access log in the file system or Flash Translation Layer (FTL), which records details such as the access frequency and the most recent access time of each page.

[0038] Step 102: Analyze the charge leakage risk information corresponding to each block based on the temperature information and the number of erase and write cycles.

[0039] For example, a risk assessment model can be set to quantitatively score each block, identify high-risk blocks, and optimize the refresh strategy accordingly to ensure timely data maintenance and improve data integrity and storage system reliability.

[0040] Step 103: Analyze the access popularity information corresponding to each page based on the historical access information.

[0041] In some examples, historical access information can be analyzed to calculate the access frequency, access interval, and access pattern of each page, thereby obtaining corresponding access popularity information. Access popularity is an important indicator of how frequently a page of data is accessed by the host. It is usually weighted by a time decay factor to reflect the importance of recent access behavior.

[0042] Step 104: Generate a refresh list based on the charge leakage risk information and the access popularity information.

[0043] For example, based on charge leakage risk information and access popularity information, target blocks with higher risks can be screened out, and target pages for refresh priority can be determined from each target block. For example, for blocks with higher charge leakage risk, the access popularity of their internal pages can be further analyzed, and pages with high access frequency or high priority can be selected as refresh targets. A refresh list is then generated, which stores the target blocks and their corresponding target pages.

[0044] Step 105 : Execute a refresh function according to the refresh list to read the data of the target page into the page register of the flash memory storage unit.

[0045] For example, the generated refresh list can be used to sequentially execute refresh operations on the target blocks and target pages specified in the list. By triggering the NAND Flash read process, the target page data is read from the storage unit into the page register, thereby restoring the unstable data state caused by charge leakage, effectively improving the integrity and reliability of the data, and preparing for subsequent possible pre-read or cache operations.

[0046] Compared with the current existing technology, this embodiment dynamically generates a refresh list and performs on-demand refresh by comprehensively considering multi-dimensional information such as temperature, number of erase and write times, and page access popularity, thereby improving the targetedness and execution efficiency of the refresh operation, avoiding the resource waste caused by fixed-cycle and fixed-position refresh, and at the same time, after the refresh, the high-priority page data is moved to the page register of the flash storage unit in combination with the bus status, further realizing pre-read optimization, reducing the delay and bandwidth occupancy during the actual reading of the host, thereby significantly improving the overall performance and energy efficiency of the storage system while ensuring data reliability.

[0047] In order to further illustrate the specific implementation process of the method of this embodiment, this embodiment provides the following Figure 2 The specific method shown includes:

[0048] Step 201: Acquire temperature information of a flash memory storage unit, the number of erase / write times corresponding to each block in the flash memory storage unit, and historical access information of each page corresponding to each block.

[0049] For example, Figure 3 As shown, the data processing system in this embodiment includes a refresh pre-read module, a data path optimization module, and a refresh frequency modulation module. The refresh pre-read module integrates refresh operations with pre-read prediction functions. By comprehensively analyzing NAND Flash temperature information, the number of erase / write cycles (e.g., PE cycles) corresponding to each block in the flash memory, and historical access information (e.g., historical input / output (IO) statistics), it uses a specific algorithm to dynamically generate target pages for refresh, effectively addressing data retention issues and optimizing First Read BER. This module also intelligently determines whether to prioritize refresh or pre-read operations based on the current system bus occupancy. In pre-read priority mode, data is directly moved to DDR memory after a refresh, improving data hit rate and read efficiency during subsequent host accesses. In refresh priority mode, only refresh operations are performed without data movement, saving bandwidth and reducing bus resource usage.

[0050] Step 202: Analyze the charge leakage risk information corresponding to each block based on the temperature information and the number of erase and write cycles.

[0051] For example, the higher the temperature, the faster the charge leakage rate of each block; the more times the erase and write are performed, the more serious the aging of the insulation layer of the storage unit, the decrease in data retention ability, and the greater the risk of charge leakage.

[0052] For example, a charge leakage risk scoring model can be introduced to weight factors such as temperature, erase / write cycles, and data retention time to quantify the risk level of each block. This can then identify high-risk blocks and dynamically adjust refresh strategies accordingly, prioritizing refresh operations on these high-risk blocks. This effectively reduces the first-time read error rate, improving data reliability and the overall stability of the storage system.

[0053] Optionally, step 202 may specifically include: obtaining a time list of first read bit error rates under different conditions; and calculating a charge leakage risk score corresponding to each block based on the time list and in combination with temperature information and erase / write times.

[0054] In some examples, the Retention Risk Score (RRS) is calculated as follows:

[0055] (Formula 1)

[0056] in, is the data retention time when the first read ber appears in the block, P / E(b) is the number of times the block is erased and written. is the current temperature (unit: °C), is the critical temperature of 85°C, λ is the weight coefficient, which can be adjusted through firmware configuration, for example, λ1=0.5, λ2=0.3, λ3=0.2.

[0057] Step 203: Analyze the access popularity information corresponding to each page based on the historical access information.

[0058] In some examples, historical access information can be analyzed to calculate the access frequency, access interval, and access pattern of each page, thereby obtaining corresponding access popularity information. By analyzing access popularity information, high-popularity pages (i.e., frequently accessed pages) and low-popularity pages can be identified, providing a basis for subsequent pre-reading, caching, and refresh decisions.

[0059] Optionally, step 203 may specifically include: obtaining the historical number of visits and the timestamp of the last visit of each page, as well as the historical visit correlation of each page based on historical visit information; obtaining the maximum number of visits among the historical number of visits of each page; and calculating the access heat value corresponding to each page based on the historical number of visits and the timestamp of the last visit of each page, as well as the maximum number of visits, and in combination with the historical visit correlation.

[0060] In some examples, the calculation formula for access hot value (HV) is as follows:

[0061] (Formula 2)

[0062] Where F(p) is the historical access count for page p, calculated by time window (e.g., the last 24 hours), Fmax is the maximum access count among all pages (normalization factor), tlast(p) is the timestamp of the last access to the page (temporal locality), and S(p) is the spatial relevance score. If the current I / O request is a sequential LBA access, S(p) for the adjacent pages (±10 pages) is 1, otherwise it is 0. For example, α = 0.6, β = 0.3, and γ = 0.1, weight coefficients, sum to 1.

[0063] : Smoothing factor to prevent division by zero.

[0064] Step 204 : Filter out target blocks from the blocks based on the charge leakage risk scores corresponding to the blocks.

[0065] For example, the target blocks and target pages that need to be refreshed can be screened from the NAND Flash based on the charge leakage risk score of each block to optimize data retention and reduce the first read error rate.

[0066] Step 205: Determine the target page corresponding to the target block based on the access heat value corresponding to each page and the target block.

[0067] For example, a dynamic target page algorithm can be used to comprehensively evaluate charge leakage risk information and access popularity, and accordingly select a target page. The calculation formula for the comprehensive priority is as follows:

[0068] (Formula 3)

[0069] Wherein, ω(p) is the page weight coefficient. The read time of different pages in the TLC particle is different. The specific value can be determined according to the read time of different pages in actual applications.

[0070] For example, in the dynamic target page algorithm, in order to balance the relationship between access heat and charge leakage risk, HV(p) may be processed in a logarithmic manner to prevent the risk of charge leakage from being masked when the HV value is too large.

[0071] For example, in actual applications, a priority threshold can be set (adjustable according to system requirements, usually ranging from 0.05 to 0.83). First, the priority value Prior(p) of each page is calculated. If the calculated Prior(p) exceeds this adjustable priority threshold, the page is considered to have a higher refresh or pre-read priority and is thus selected for subsequent refresh operations or data migration to DDR memory. This ensures that both attention is paid to data pages with high access popularity and the potential risk of data loss due to charge leakage is effectively managed, thereby optimizing the overall performance and reliability of the system.

[0072] Optionally, step 205 may specifically include: performing the following judgments on the page with the most historical read times of each block: if the access heat value corresponding to the page is greater than a preset heat threshold, and the block where the page is located belongs to the target block, then the page is used as the target page of the target block where it is located; if the access heat value corresponding to the page is greater than the preset heat threshold, and the block where the page is located does not belong to the target block, then the comprehensive priority of the page is calculated, and the comprehensive priority is calculated based on the charge leakage risk score of the block where the page is located and the access heat value of the page; when the comprehensive priority is greater than the preset priority threshold, the block where the page is located is used as the target block, and the page is used as the target page of the target block where it is located; if the access heat value corresponding to the page is less than the preset heat threshold, and the block where the page is located belongs to the target block, then a page that meets the preset access heat requirements is obtained from multiple pages of the block where the page is located as the target page of the target block where it is located.

[0073] For example, by working together with multiple modules, the first read bit error rate (First Read BER) can be effectively reduced and system performance can be improved. First, the refresh frequency modulation module dynamically calculates the optimal refresh cycle through a formula based on the current NAND Flash temperature, PE number, data retention time and other parameters, and updates the timer; when the timer returns to zero, the refresh operation is triggered to implement adaptive refresh control based on actual operating conditions. The refresh pre-read module runs periodically and uses the RRS algorithm to evaluate the data retention risk of each Block. If the RRS value of a Block exceeds the set threshold, it is marked as requiring refresh and added to the refresh list. Then, the most frequently accessed Page in each Block is obtained from the FTL, and its HV is calculated to determine its priority.

[0074] For example, if the HV of the Page with the most historical read times in a data block is higher than the preset heat threshold (HVThreshold), and the Block where it is located has been marked as requiring refresh, the Page number is added to the refresh list.

[0075] For example, if the HV of the page with the most historical read times in the data block is still higher than the threshold, but the block is not included in the refresh list, the Prior value is further calculated. If the Prior is greater than the Prior Threshold, the block is added to the refresh list and the page is recorded synchronously; otherwise, it is ignored.

[0076] For example, if the HV of the Page with the most historical read times in a data block is lower than the threshold and the block it belongs to is not in the refresh list, it is directly ignored.

[0077] For example, if the HV of the page with the most historical reads in a data block is lower than the threshold but the block needs to be refreshed, the search continues for the second most frequently read page in the block, and so on. At most, the top five high-frequency pages are checked. If no page that meets the conditions is found, the page with the largest HV is selected as the representative.

[0078] In some embodiments, the RRS theoretical value range is 0-1.2, the HV theoretical value range is 0-1, and the Prior theoretical threshold is 0-0.83. Taking the Yangtze Memory x3-9070 as an example, the read times of three pages (lower, middle, and upper pages) are 35, 43, and 35 μs, respectively. The measured first read ber times at different P / E and temperature are shown in Table 1:

[0079] Table 1

[0080]

[0081] For example, if page p1 is a middle page, P / E=3000, temperature 70°C, F(p1)=300, tlast(p1)=2 hours ago, S(p1)=1, then according to the data in the table above, formula 1 The selection can be based on the following formula:

[0082] (Formula 4)

[0083] In this embodiment, since P / E < 5000, =1, substitute this parameter into formula 1, and we can get ; Substituting into formula 2, we can get Furthermore, during the Prior calculation process, based on the read times of the three pages mentioned above, we know that the middle page's latency is 22.8% (43-35) / 35) higher than the other pages. Therefore, ω(p) for the lower, middle, and upper pages is set to 1, 1.2, and 1, respectively. Substituting these values ​​into Formula 3, we calculate the following: .

[0084] For example, if the RRS threshold is 0.4, the HV threshold is 0.3, and the Prior threshold is 0.5, the block where the page p1 is located needs to be refreshed, and the page needs to be pre-read and moved to the DDR.

[0085] Step 206: Generate a refresh list based on the target block and the target page corresponding to the target block.

[0086] For example, after completing charge leakage risk assessment and page-level access heat analysis for each block, target blocks with higher risks are screened out, and within each target block, target pages that require priority refresh are further determined. Based on these target blocks and their corresponding target pages, the system generates a refresh list containing the block numbers and corresponding page numbers that require refresh operations. This list serves as the basis for subsequent refresh operations, guiding the storage controller to trigger the NAND Flash read and charge recovery processes as needed, ensuring that high-risk data is processed promptly, thereby reducing the first read bit error rate (FirstRead BER) and improving data reliability.

[0087] Step 207 : Execute a refresh function according to the refresh list to read the data of the target page into the page register of the flash memory storage unit.

[0088] For example, the data path optimization module can, based on the refresh pre-read module's decision, move eligible data directly from the page register to the synchronous dynamic random access memory (Double Data Rate, DDR) after the refresh operation completes. A mapping relationship between this data and the logical block address (LBA) is established in the FTL. When the host initiates a read request, the system can quickly respond and return data directly from the DDR, significantly improving read performance and reducing access latency.

[0089] Optionally, the method of this embodiment may further include: determining whether the bus is idle; if the bus is idle, moving the data of the target page in the page register to the memory, and adding a pre-read mark, which is used to instruct the host to read from the memory when reading the data of the target page.

[0090] In some examples, when the host initiates a read request, the FTL first queries whether the LBA is marked as "read-ahead cache" and whether the data is still valid in the DDR. If so, the data is returned directly from the DDR; if the data is still in the page register and has not expired, it is read from the page register; if neither hits, the NAND Flash array is triggered to perform a normal read and update the relevant data status information.

[0091] Optionally, the method of this embodiment may further specifically include: obtaining the data retention time of the flash memory storage unit; calculating the retention time coefficient based on the data retention time, and calculating the temperature change coefficient based on the temperature information; based on the retention time coefficient and the temperature change coefficient, and in combination with the preset reference period corresponding to the refresh function, dynamically determining the execution period of the refresh function.

[0092] For example, the refresh frequency modulation module can dynamically adjust the refresh frequency according to the real-time working status of the NAND Flash. By collecting the current temperature of the NAND and combining it with the data retention time of the flash memory storage unit, a dynamic refresh algorithm is used to calculate a reasonable refresh cycle. The calculation formula of the dynamic refresh algorithm is as follows:

[0093] (Formula 5)

[0094] Tbase is the base period (e.g., 20 minutes). For a specific refresh rate, refer to the typical refresh rate of enterprise-class SSDs (15-30 minutes) to balance reliability and performance overhead. The temperature variation coefficient can be found in the JEDEC standard (JESD218B) for the typical operating temperature of NAND Flash (25 degrees Celsius). is the retention time coefficient. For details, refer to the definition of cold data in the JEDEC standard (JESD219) (retention time > 30 days is high-risk data). The probability of charge leakage increases significantly after exceeding this threshold. The weight coefficients k1 = 0.6 and k2 = 0.4. Since high temperature has a greater impact on charge leakage, the temperature weighting is higher than the time weighting.

[0095] In some embodiments, in a high temperature and long retention scenario, Tcurrent=70, Retentionavg=60, substituting into Formula 5, .

[0096] In some embodiments, in the operating temperature short retention scenario, Tcurrent=50, Retentionavg=5, substituting into Formula 5, .

[0097] In some examples, the temperature variation coefficient is calculated by comprehensively combining data retention time and temperature information. Combined with the preset baseline refresh cycle, the execution cycle of the next refresh operation is dynamically determined, thereby achieving adaptive management of the charge leakage risk of the storage unit, ensuring good data integrity under different temperatures and usage conditions, and improving system reliability and energy efficiency.

[0098] For example, when the dynamically calculated refresh operation cycle (T-refresh) arrives, the system performs the actual read operation of the NAND Flash according to the block and page information in the refresh list, completes the charge refresh, records the timestamp of this refresh, and resets the next refresh operation cycle. For pages in the refresh list with a Prior value higher than the PriorThreshold, after the refresh is completed, if the bus is in an idle state, its data is immediately moved from the page register to the DDR memory and marked as "pre-read cache" in the FTL. At the same time, the mapping relationship between the DDR cache address and the LBA is recorded.

[0099] In this embodiment, in terms of bit error rate optimization, the first read bit error rate is greatly reduced, which effectively improves the reliability of data reading; in terms of performance improvement, the pre-read hit rate is increased from the original 40% to 82% in the YCSB mixed load test, which significantly enhances the data access efficiency; at the same time, the read latency is significantly reduced, for example, the read time of the TLC type middle page is reduced from the original 43μs to about 2μs (read directly from DDR); in addition, compared with the fixed-cycle refresh mechanism, this embodiment significantly reduces the bus occupancy while ensuring data integrity, further optimizing the utilization efficiency of system resources.

[0100] Compared with the existing technology, this embodiment realizes charge refresh and data pre-reading simultaneously through a single read operation, which significantly improves the efficiency and data reliability of the system. This mechanism is based on the charge leakage risk-heat joint model, uses RRS and HV to calculate the priority of each page, and adopts a weight adaptive strategy to dynamically adjust the importance of various parameters. In addition, a dynamic refresh scheduling method is introduced. According to the actual temperature and data retention time of NAND Flash, a specific formula and feedback control logic are used to dynamically adjust the refresh cycle to ensure that data integrity can be optimally maintained under different working conditions. It not only reduces the first read bit error rate, but also improves the pre-read hit rate, reduces read latency and bus occupancy, thereby greatly improving the overall performance and energy efficiency of the storage system.

[0101] The embodiment of the present application also provides a data processing device, as Figure 1 and Figure 2The specific implementation of the method shown is shown in Figure 4. The device includes: an acquisition module 31, a first analysis module 32, a second analysis module 33, a generation module 34 and an execution module 35.

[0102] an acquisition module 31 configured to acquire temperature information of a flash memory storage unit, a number of erase / write times corresponding to each block in the flash memory storage unit, and historical access information of each page corresponding to each block;

[0103] A first analysis module 32 is configured to analyze the charge leakage risk information corresponding to each block according to the temperature information and the number of erase and write times;

[0104] The second analysis module 33 is configured to analyze the access popularity information corresponding to each page according to the historical access information;

[0105] A generating module 34 is configured to generate a refresh list based on the charge leakage risk information and the access heat information, wherein the refresh list stores a target block and a target page corresponding to the target block;

[0106] The execution module 35 is configured to execute a refresh function according to the refresh list to read the data of the target page into the page register of the flash memory storage unit.

[0107] In some examples of this embodiment, the first analysis module 32 is specifically configured to obtain a list of durations of first read bit error rates under different conditions; based on the duration list, and in combination with the temperature information and the number of erases and writes, calculate the charge leakage risk score corresponding to each block.

[0108] In some examples of this embodiment, the second analysis module 33 is specifically configured to obtain the historical number of visits and the timestamp of the last visit of each page, as well as the historical visit correlation of each page based on the historical visit information; obtain the maximum number of visits among the historical number of visits of each page; and calculate the access heat value corresponding to each page based on the historical number of visits and the timestamp of the last visit of each page, as well as the maximum number of visits, and in combination with the historical visit correlation.

[0109] In some examples of this embodiment, the generation module 34 is specifically configured to filter out the target block from the blocks based on the charge leakage risk scores corresponding to the blocks; determine the target page corresponding to the target block based on the access heat values ​​corresponding to the pages and the target block; and generate the refresh list based on the target block and the target page corresponding to the target block.

[0110] In some examples of this embodiment, the generation module 34 is further configured to perform the following judgments for the page with the most historical read times of each block: if the access heat value corresponding to the page is greater than the preset heat threshold, and the block where the page is located belongs to the target block, then the page is used as the target page of the target block where it is located; if the access heat value corresponding to the page is greater than the preset heat threshold, and the block where the page is located does not belong to the target block, then the comprehensive priority of the page is calculated, and the comprehensive priority is calculated based on the charge leakage risk score of the block where the page is located and the access heat value of the page; when the comprehensive priority is greater than the preset priority threshold, the block where the page is located is used as the target block, and the page is used as the target page of the target block where it is located; if the access heat value corresponding to the page is less than the preset heat threshold, and the block where the page is located belongs to the target block, then a page that meets the preset access heat requirements is obtained from multiple pages of the block where the page is located as the target page of the target block where it is located.

[0111] In some examples of this embodiment, the execution module 35 is specifically configured to determine whether the bus is idle; if the bus is idle, the data of the target page in the page register is moved to the memory, and a pre-read mark is added, and the pre-read mark is used to instruct the host to read from the memory when reading the data of the target page.

[0112] In some examples of this embodiment, the execution module 35 is further configured to obtain the data retention time of the flash memory storage unit; calculate the retention time coefficient based on the data retention time, and calculate the temperature change coefficient based on the temperature information; based on the retention time coefficient and the temperature change coefficient, and in combination with the preset reference period corresponding to the refresh function, dynamically determine the execution period of the refresh function.

[0113] It should be noted that for other corresponding descriptions of the functional units involved in the data processing device provided in this embodiment, please refer to Figure 1 and Figure 2 The corresponding description in will not be repeated here.

[0114] Based on the above Figure 1 and Figure 2 The method shown in FIG. 1 is a method for performing the above-mentioned steps. Accordingly, this embodiment further provides a computer-readable storage medium having a computer program stored thereon. When the computer program is executed by a processor, the computer program can realize the above-mentioned steps. Figure 1 and Figure 2 The method shown.

[0115] Based on the above Figure 1 and Figure 2 The method shown in FIG. 1 is a method for performing the above-mentioned operations. Accordingly, this embodiment further provides a computer program product having a computer program stored thereon. When the computer program is executed by a processor, the above-mentioned Figure 1 and Figure 2 The method shown.

[0116] Based on this understanding, the technical solution of the present application can be embodied in the form of a software product, which can be stored in a non-volatile storage medium (which can be a CD-ROM, USB flash drive, mobile hard disk, etc.), and includes a number of instructions for enabling a computer device (which can be a personal computer, server, or network device, etc.) to execute the methods of various implementation scenarios of the present application.

[0117] Based on the above Figure 1 and Figure 2 The method shown, and Figure 4 In order to achieve the above-mentioned purpose, the embodiment of the present application further provides an electronic device, such as a personal computer or a server, which includes a storage medium and a processor; the storage medium is used to store a computer program; the processor is used to execute the computer program to achieve the above-mentioned Figure 1 and Figure 2 The method shown.

[0118] In some embodiments, the physical device may further include a user interface, a network interface, a camera, a radio frequency (RF) circuit, a sensor, an audio circuit, a Wi-Fi module, etc. The user interface may include a display, an input unit such as a keyboard, etc. Optional user interfaces may also include a USB interface, a card reader interface, etc. In some embodiments, the network interface may include a standard wired interface, a wireless interface (such as a Wi-Fi interface), etc.

[0119] Those skilled in the art will understand that the above-mentioned physical device structure provided in this embodiment does not constitute a limitation on the physical device, and may include more or fewer components, or a combination of certain components, or different component arrangements.

[0120] The storage medium may also include an operating system and a network communication module. The operating system is a program that manages the hardware and software resources of the physical device, supporting the execution of information processing programs and other software and / or programs. The network communication module is used to enable communication between components within the storage medium, as well as with other hardware and software within the physical information processing device.

[0121] Through the description of the above implementation methods, those skilled in the art can clearly understand that the present application can be implemented by means of software plus the necessary general hardware platform, or by hardware. By applying the solution of this embodiment, compared with the current existing technology, this embodiment dynamically predicts the pages that the host may access, and gives priority to reading these pages with a high probability of being accessed when performing a refresh operation, combining charge refresh and data pre-reading into a data reading process. If a subsequent host IO request hits the pre-read data, the data can be directly transferred from the page register of the NAND Flash via the bus without having to read the page register from the Flash array again, thereby significantly reducing the delay. In addition, a dynamic prediction algorithm based on heat value and environmental parameters is used to select the refresh target page, giving priority to those pages located in high error risk blocks and with a higher access probability, and executing a strategy of moving metadata or high-frequency access pages to the DDR memory immediately after refresh, so that the host can directly access the data in the DDR when reading, further reducing the access delay. The adaptive refresh mechanism automatically adjusts the refresh cycle and range based on real-time temperature, data hot and cold distribution, and bus occupancy, balancing the bandwidth usage between refresh operations and normal I / O operations, and optimizing system performance and resource utilization efficiency.

[0122] It should be noted that, in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the terms "comprises," "comprising," or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, method, article, or device that includes a series of elements includes not only those elements, but also other elements not explicitly listed, or elements inherent to such process, method, article, or device. In the absence of further limitations, an element defined by the phrase "comprising a ..." does not exclude the presence of other identical elements in the process, method, article, or device that includes the element.

[0123] The above are merely specific embodiments of the present application, which are intended to enable those skilled in the art to understand or implement the present application. Various modifications to these embodiments will be apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present application. Therefore, the present application will not be limited to these embodiments herein, but rather is intended to conform to the widest scope consistent with the principles and novel features of the present application.

Claims

1. A data processing method, characterized in that: include: Obtaining temperature information of a flash memory storage unit, the number of erase / write times corresponding to each block in the flash memory storage unit, and historical access information of each page corresponding to each block; wherein the number of erase / write times is an important indicator for measuring the degree of wear of each block; Analyzing charge leakage risk information corresponding to each block according to the temperature information and the number of erase and write times; According to the historical access information, the number of historical accesses and the timestamp of the last access of each page, as well as the historical access relevance of each page, are obtained; Obtain the maximum number of visits among the historical number of visits to each page; Based on the historical access counts and the timestamp of the last access of each page, as well as the maximum access count, and in combination with the historical access correlation, the access popularity value corresponding to each page is calculated; wherein the access popularity is an important indicator for measuring the frequency of access of a certain page data by the host; Based on the charge leakage risk information and the access heat value, a refresh list is generated, wherein the refresh list stores target blocks and target pages corresponding to the target blocks; wherein the target pages are pages in the target blocks that need to be refreshed first, and the target pages corresponding to the target blocks are determined based on the access heat values ​​corresponding to the respective pages and the target blocks; executing a refresh function according to the refresh list to read the data of the target page into the page register of the flash memory storage unit; Determine whether the bus is idle; If the bus is idle, the data of the target page in the page register is moved to the memory, and a pre-read mark is added, where the pre-read mark is used to instruct the host to read from the memory when reading the data of the target page.

2. The method according to claim 1, characterized in that Analyzing the charge leakage risk information corresponding to each block according to the temperature information and the number of erase / write times includes: Get a list of durations of first read bit error rates under different conditions; Based on the time length list and in combination with the temperature information and the number of erase and write times, a charge leakage risk score corresponding to each block is calculated.

3. The method according to claim 1, characterized in that The generating a refresh list based on the charge leakage risk information and the access heat value includes: Screening out the target block from the blocks according to the charge leakage risk scores corresponding to the blocks; Determining the target page corresponding to the target block according to the access heat values ​​corresponding to the respective pages and the target block; The refresh list is generated based on the target block and the target page corresponding to the target block.

4. The method according to claim 3, characterized in that The determining the target page corresponding to the target block according to the access heat values ​​corresponding to the respective pages and the target block includes: The following judgment is performed on the page with the most historical read times in each block: If the access heat value corresponding to the page is greater than a preset heat threshold, and the block where the page is located belongs to the target block, the page is used as the target page of the target block where it is located; If the access heat value corresponding to the page is greater than a preset heat threshold, and the block where the page is located does not belong to the target block, then calculating a comprehensive priority of the page, the comprehensive priority being calculated based on the charge leakage risk score of the block where the page is located and the access heat value of the page; if the comprehensive priority is greater than the preset priority threshold, the block where the page is located is designated as the target block, and the page is designated as the target page of the target block where it is located; If the access heat value corresponding to the page is less than the preset heat threshold and the block where the page is located belongs to the target block, a page that meets the preset access heat requirement is obtained from multiple pages in the block where the page is located as the target page of the target block where the page is located.

5. The method according to claim 1, wherein The method further comprises: Obtaining a data retention time of the flash memory storage unit; Calculating a retention time coefficient based on the data retention time, and calculating a temperature variation coefficient based on the temperature information; Based on the retention time coefficient and the temperature variation coefficient, and in combination with a preset reference period corresponding to the refresh function, the execution period of the refresh function is dynamically determined.

6. A data processing device, characterized in that: include: an acquisition module configured to acquire temperature information of a flash memory storage unit, a number of erase / write times corresponding to each block in the flash memory storage unit, and historical access information of each page corresponding to each block; wherein the number of erase / write times is an important indicator for measuring the degree of wear of each block; A first analysis module is configured to analyze charge leakage risk information corresponding to each block according to the temperature information and the number of erase and write times; The second analysis module is configured to obtain, based on the historical access information, the number of historical accesses and the timestamp of the last access of each page, as well as the historical access relevance of each page; obtain the maximum number of accesses among the historical accesses of each page; and calculate the access popularity value corresponding to each page based on the historical accesses and the timestamp of the last access of each page, as well as the maximum number of accesses, and in combination with the historical access relevance; wherein the access popularity is an important indicator for measuring the frequency with which a certain page of data is accessed by a host; a generation module configured to generate a refresh list based on the charge leakage risk information and the access heat value, wherein the refresh list stores target blocks and target pages corresponding to the target blocks; wherein the target pages are pages in the target blocks that need to be refreshed first, and the target pages corresponding to the target blocks are determined based on the access heat values ​​corresponding to the respective pages and the target blocks; an execution module configured to execute a refresh function according to the refresh list to read the data of the target page into a page register of the flash memory storage unit; The execution module is specifically configured to determine whether the bus is idle; if the bus is idle, the data of the target page in the page register is moved to the memory, and a pre-read mark is added, wherein the pre-read mark is used to instruct the host to read from the memory when reading the data of the target page.

7. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the method according to any one of claims 1 to 5 is implemented.

8. An electronic device comprising a storage medium, a processor, and a computer program stored in the storage medium and executable on the processor, wherein: When the processor executes the computer program, the method according to any one of claims 1 to 5 is implemented.

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