Pre-decoding method of variable-length instruction set, electronic device and storage medium

Abstract

The present invention relates to the field of chip design technology, and in particular to a variable-length instruction set pre-decoding method, electronic device, and storage medium. The method comprises the following steps: taking N cache blocks from a memory, obtaining R cascaded atomic windows, configuring a window length wid for each of the atomic windows; inputting the same cache block into the R-level atomic windows for pre-decoding, and obtaining instruction data of the first instruction in the atomic window; wherein the i-th cache block cache_line i The pre-decoding step of obtaining the instruction data of the first instruction in the atomic window during the j-th slide includes: according to the starting position, the atomic window slides on the cache block to take out the instruction data of the fixed length and pre-decodes to obtain the instruction data and length of the first instruction, and outputs the starting position of the next slide; the instruction data of each variable-length instruction is extracted by this method, thereby improving the decoding efficiency of the variable-length instruction set, and being able to flexibly adapt to various variable-length instruction sets.

Description

Technical Field

[0001] The present invention relates to the technical field of chip design, and in particular to a pre-decoding method, electronic equipment and storage medium for a variable-length instruction set. Background Art

[0002] In modern processor architectures, variable-length instruction sets (VLIs) are widely used in mainstream instruction set architectures such as x86 and RISC-V due to their high code density and flexible instruction encoding. Unlike fixed-length instruction sets, the encoding length of VLIs changes dynamically based on the opcode type and operand combination, posing a significant challenge to the design of instruction prefetch and decode units.

[0003] When a chip executes instructions, it needs to retrieve a fixed-length piece of data from the memory before issuing the instruction. However, for variable-length instruction sets, it is extremely difficult to determine how many instructions are contained in this fixed-length data. Because instructions vary in length, this fixed-length data may contain instructions of various lengths, or even partial fragments of a single instruction. This makes it impossible to simply split instructions based on fixed-step shifts when parsing variable-length instruction sets, as is the case with fixed-length instruction sets, making the parsing process difficult. Therefore, how to efficiently and accurately parse variable-length instruction sets has become a key issue that needs to be addressed in chip design. Summary of the Invention

[0004] In order to solve the above technical problems, the present invention adopts a technical solution: a variable-length instruction set pre-decoding method, the method comprising the following steps:

[0005] S100, fetch N cache blocks from the memory, where N is greater than or equal to 1.

[0006] S200, obtaining R cascaded atomic windows, configuring a window length wid for each of the atomic windows; the starting position of the next sliding output of the atomic window of the current level is used as the input of the atomic window of the next level, where R is greater than or equal to 1.

[0007] S300, input the same cache block into the atomic window of level R for pre-decoding, and obtain the instruction data of the first instruction in the atomic window; wherein the i-th cache block cache_line i The pre-decoding steps for obtaining the instruction data of the first instruction in the atomic window after the j-th slide include:

[0008] S310, get cache_line i The starting position index of the j-th slide i,j .

[0009] S320, the cache_line i and its indexi,j Enter the Atom window.

[0010] S330, the atomic window obtains cache_line i Index i,j The command data data with the starting position and length wid i,j .

[0011] S340, the data i,j Perform pre-decoding to obtain the length of the first instruction.

[0012] S350, intercepting the data according to the length of the first instruction i,j , get the instruction data of the first instruction, and generate the starting position index of the j+1th slide i,j+1 .

[0013] In addition, the present invention also provides a non-transitory computer-readable storage medium, which stores at least one instruction or at least one program, and the at least one instruction or at least one program is loaded and executed by a processor to implement the above method.

[0014] In addition, the present invention also provides an electronic device including a processor and the above-mentioned non-transitory computer-readable storage medium.

[0015] The present invention has at least the following beneficial effects:

[0016] The present invention provides a pre-decoding method, electronic device and storage medium for a variable-length instruction set, which uses an atomic window to slide on a cache block to retrieve instruction data of a preset length and pre-decode to obtain the instruction data and length of the first instruction. The atomic window intercepts the instruction data according to the instruction length of the first instruction and calculates the starting position of the next slide. Through this method, each variable-length instruction is extracted, thereby improving the decoding efficiency of the variable-length instruction set. The length of the sliding window and the number of cascades can be flexibly configured, and can be flexibly adapted to various variable-length instruction sets. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0018] Figure 1 A flow chart of a method for pre-decoding a variable-length instruction set provided by an embodiment of the present invention;

[0019] Figure 2Cache_line provided by the embodiment of the present invention i The flowchart of the pre-decoding steps for obtaining the instruction data of the first instruction in the atomic window by sliding for the jth time;

[0020] Figure 3 A schematic diagram of the structure of a single atomic window provided by the present invention;

[0021] Figure 4 A schematic structural diagram of R cascaded atomic windows provided by the present invention. DETAILED DESCRIPTION

[0022] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without making any creative efforts shall fall within the scope of protection of the present invention.

[0023] Unless otherwise defined, all technical and scientific terms used in the embodiments of the present invention have the same meanings as commonly understood by those skilled in the art.

[0024] See also Figure 1 , which shows a flow chart of a method for pre-decoding a variable-length instruction set, the method comprising the following steps:

[0025] S100, fetch N cache blocks from the memory, where N is greater than or equal to 1.

[0026] A cache line is the basic unit of data storage and transmission within the cache, allowing data to be transferred and stored between the cache and memory in blocks. A cache line contains multiple instruction data of equal or varying lengths. Because cache lines are fixed in length, instruction data is evenly divided across multiple cache lines of fixed length. Therefore, a complete instruction may be mechanically divided between the end of the current cache line and the beginning of the next cache line.

[0027] S200, obtaining R cascaded atomic windows, configuring a window length wid for each of the atomic windows; the starting position of the next sliding output of the atomic window of the current level is used as the input of the atomic window of the next level, where R is greater than or equal to 1.

[0028] The atomic window is a window structure used to extract instruction data of length wid from the cache block and pre-decode the extracted instruction data. The wid configured in the atomic window determines the amount of instruction data extracted from the cache block each time. The atomic window's pre-decoding operation on the extracted data is an indivisible whole and will not be interrupted or interfered with by other operations. The input of each atomic window is the cache block and the starting position of the next slide, and the output is the pre-decoded instruction and the starting position of the next set of slides.

[0029] In one embodiment, wid is the maximum length of all instructions in the current instruction set. wid can be flexibly configured according to changes in the instruction set.

[0030] Each atom window is from cache_line i The instruction data of wid obtained in the atomic window may include a group of instructions. As an example, when the instructions in the instruction set include instruction A, instruction B and instruction C, the length of instruction A is 32 bits, the length of instruction B is 64 bits, and the length of instruction C is 96 bits. Instruction C has the largest length, so the length of the atomic window is 96 bits. The instruction data in the cashline obtained by the atomic window may be the instruction data of three instructions A, or the instruction data of instruction A and instruction B, or the instruction data of instruction C, or the instruction data of instruction B and part of instruction C. During the pre-decoding process, only the instruction data of the first instruction will be retained, and the instruction data of the remaining instructions will be discarded.

[0031] The starting position of the next slide refers to the starting position of the first instruction in the instruction data taken out by the next atomic window.

[0032] In one embodiment, see Figure 3 When R is 1, when the atomic window first slides, the starting position of the first slide is the initial position of the cache block; after the initial position of the first slide and the cache block are input into the atomic window, the starting position of the next slide output by the atomic window is used as the input of the atomic window. Among them, using a single atomic window for pre-decoding not only enables pre-decoding of variable-length instruction sets, but also significantly reduces chip area compared to using multiple atomic windows.

[0033] In one embodiment, see Figure 4In S200, when R is greater than 1, when the atomic window slides for the first time, the starting position of the first slide is the initial position of the cache block; the initial position of the first slide is input into the first-level atomic window, and the cache block is input into R atomic windows at the same time, and the R-level atomic windows are synchronously pre-decoded; wherein, the starting position of the next slide output by the r-th level atomic window is used as the input of the r+1-th level atomic window. Using R cascaded atomic windows cannot realize the pre-decoding of variable-length instruction sets, and compared with a single atomic window, R cascaded atomic windows can complete pre-decoding within the same clock cycle, which greatly improves the efficiency of instruction pre-decoding.

[0034] When the chip area is limited or the efficiency requirement is low, the value of R can be configured to a lower value. When the chip area is sufficient or the efficiency requirement is high, the value of R can be configured to a higher value. The number of cascades can be flexibly configured according to the needs of the chip.

[0035] S300: Input the same cache block into the atomic window of level R for pre-decoding to obtain instruction data of the first instruction in the atomic window.

[0036] For further information, see Figure 2 , which shows the i-th cache block cache_line i The pre-decoding steps for obtaining the instruction data of the first instruction in the atomic window after the j-th slide include:

[0037] S310, get cache_line i The starting position index of the j-th slide i,j .

[0038] S320, the cache_line i and its index i,j Enter the Atom window.

[0039] S330, the atomic window obtains cache_line i Index i,j The command data data with the starting position and length wid i,j .

[0040] Among them, when cache_line i When the remaining instruction data that has not been pre-decoded is incomplete, it needs to be spliced ​​first and then pre-decoded through the atomic window.

[0041] In one embodiment, S330 further includes:

[0042] S331, determine cache_line i Index i,jChecks whether the instruction data at the starting position is complete. If not, waits to retrieve cache_line. i+1 .

[0043] In one embodiment, when index i,j When the length of the instruction data at the starting position is less than the length configured in the length field segment carried by the current instruction, it is determined that the instruction data is incomplete.

[0044] S332, when cache_line i+1 When retrieving, cache_line i and cache_line i+1 Stitched together as a whole.

[0045] S333, the atomic window obtains the entire spliced ​​structure with index i,j The command data data with the starting position and length wid i,j .

[0046] The problem of instruction fragments can be correctly handled through S331-S333.

[0047] S340, the data i,j Perform pre-decoding to obtain the length of the first instruction.

[0048] In one embodiment, the length of the first instruction is the length configured in the length field of the first instruction.

[0049] In one embodiment, the length of the first instruction is a fixed length of instructions specified in an instruction set.

[0050] S350, intercepting the data according to the length of the first instruction i,j , get the instruction data of the first instruction, and generate the starting position index of the j+1th slide i,j+1 .

[0051] Among them, the corresponding instructions are intercepted and pre-decoded by using a sliding window method, so that the system can parse the corresponding instructions more accurately, breaking the limitation of only being able to parse fixed-length instructions.

[0052] It should be noted that wid is the maximum length of all instruction lengths in the instruction set. Therefore, no matter how many instructions are included in an atomic window, only the instruction data of the first instruction is retained according to the instruction length of the first instruction, and the instruction data of other instructions are directly discarded. In this way, the instruction data of each variable-length instruction is stripped out from the cache block, and pre-decoding is completed, making the subsequent decoding process more efficient. It should be noted that the instruction data discarded by the atomic window does not affect the original instruction data in the cache block. The starting position of the next slide actually starts to slide with the next address of the first instruction obtained by the current slide, that is, the starting position of the next instruction, and so on. All variable-length instructions are stripped out one by one to complete the task of pre-decoding, so that instructions will not be lost.

[0053] In one embodiment, in S350, index i,j+1 Satisfies: index i,j+1 =index i,j +size i,j , size i,j cache_line i The instruction length of the first instruction obtained by the j-th sliding pre-decoding.

[0054] In one embodiment, S350 further includes: determining whether the first instruction is a branch jump instruction according to the operation code of the first instruction, and if so, starting a branch prediction processing operation to improve the efficiency of the pipeline. Figure 2 and Figure 3 The result output by the atomic window also includes the judgment result of whether the current instruction obtained by pre-decoding is a branch jump instruction.

[0055] Among them, when the end position of the first instruction in the atomic window happens to be cache_line i The end address of the first instruction in the atomic window exceeds the cache_line i When the last address is reached, the next sliding index i,j+1 Points to the next cache block.

[0056] In one embodiment, S350 further includes: when the end position of the first instruction obtained by the j-th sliding pre-decoding is the end address of the current cache block or crosses the end address of the current cache block, the first instruction obtained by the j-th sliding pre-decoding is cache_line i The last instruction in the i,j+1 For the i+1 cache block cache_line i+1 See again for the starting position in Figure 2 and Figure 3,The result output by the atomic window also includes the ,judgment result of whether the pre-decoded instruction is the last instruction.

[0057] In summary, the present invention provides a pre-decoding method for a variable-length instruction set, which uses an atomic window to slide on a cache block to retrieve instruction data of a preset length and pre-decode to obtain the instruction data and length of the first instruction. The atomic window intercepts the instruction data according to the instruction length of the first instruction and calculates the starting position of the next slide. Through this method, each variable-length instruction is extracted to improve the decoding efficiency of the variable-length instruction set. The length of the sliding window and the number of cascades can be flexibly configured, and can be flexibly adapted to various variable-length instruction sets.

[0058] An embodiment of the present invention also provides a non-transitory computer-readable storage medium, which can be set in an electronic device to store at least one instruction or at least one program related to implementing a method in a method embodiment. The at least one instruction or the at least one program is loaded and executed by the processor to implement the method provided in the above embodiment.

[0059] An embodiment of the present invention further provides an electronic device including a processor and the aforementioned non-transitory computer-readable storage medium.

[0060] An embodiment of the present invention further provides a computer program product comprising program code. When the program product is run on an electronic device, the program code is used to enable the electronic device to execute the steps of the method according to various exemplary embodiments of the present invention described above in this specification.

[0061] Those skilled in the art will clearly understand that for the sake of convenience and brevity of description, only the division of the above-mentioned functional units and modules is used as an example. In actual applications, the above-mentioned functions can be distributed to different functional units and modules as needed, that is, the internal structure of the device can be divided into different functional units or modules to complete all or part of the functions described above.

[0062] Although some specific embodiments of the present invention have been described in detail by way of example, it should be understood by those skilled in the art that the above examples are for illustration only and are not intended to limit the scope of the present invention. It should also be understood by those skilled in the art that various modifications may be made to the embodiments without departing from the scope and spirit of the present invention. The scope of the present invention is defined by the appended claims.

Claims

1. A variable-length instruction set pre-decoding method, characterized in that: The method comprises the following steps: S100, fetch N cache blocks from the memory, where N is greater than or equal to 1; S200, obtaining R cascaded atomic windows, configuring a window length wid for each of the atomic windows; using the starting position of the next sliding output by the atomic window of the current level as the input of the atomic window of the next level, where R is greater than or equal to 1; When R is equal to 1, when the atomic window slides for the first time, the starting position of the first slide is the initial position of the cache block; After the initial position of the first slide and the cache block are input into the atomic window, the starting position of the next slide output by the atomic window is used as the input of the atomic window; When R is greater than 1, when the atomic window slides for the first time, the starting position of the first slide is the initial position of the cache block; Input the initial position of the first slide into the first-level atomic window, input the cache block into R atomic windows at the same time, and synchronize the R-level atomic windows for pre-decoding. The starting position of the next slide output by the r-th level atomic window is used as the input of the r+1-th level atomic window. S300, input the same cache block into the atomic window of level R for pre-decoding, and obtain the instruction data of the first instruction in the atomic window; wherein the i-th cache block cache_line i The pre-decoding steps for obtaining the instruction data of the first instruction in the atomic window after the j-th slide include: S310, get cache_line i The starting position index of the j-th slide i,j ; S320, the cache_line i and its index i,j Enter the atom window; S330, the atomic window obtains cache_line i Index i,j The command data data with the starting position and length wid i,j ; S340, the data i,j Perform pre-decoding to obtain the length of the first instruction; S350, intercepting the data according to the length of the first instruction i,j , get the instruction data of the first instruction, and generate the starting position index of the j+1th slide i,j+1 .

2. The method according to claim 1, characterized in that In S350, index i,j+1 satisfy: index i,j+1 =index i,j +size i,j , size i,j cache_line i The instruction length of the first instruction obtained by the j-th sliding pre-decoding.

3. The method according to claim 1, characterized in that S350 also includes: judging whether the first instruction is a branch jump instruction according to the operation code of the first instruction, and if so, starting a branch prediction processing operation.

4. The method according to claim 1, wherein The S330 also includes: S331, determine cache_line i Index i,j Checks whether the instruction data at the starting position is complete. If not, waits to retrieve cache_line. i+1 ; S332, when cache_line i+1 When retrieving, cache_line i and cache_line i+1 Spliced ​​into a whole; S333, the atomic window obtains the entire spliced ​​structure with index i,j The command data data with the starting position and length wid i,j .

5. The method according to claim 1, wherein S350 also includes: when the end position of the first instruction obtained by the j-th sliding pre-decoding is the end address of the current cache block or crosses the end address of the current cache block, the first instruction obtained by the j-th sliding pre-decoding is cache_line i The last instruction in the i,j+1 For the i+1 cache block cache_line i+1 The starting position in .

6. The method according to claim 1, characterized in that wid is the maximum length of all instructions in the current instruction set.

7. A non-transitory computer-readable storage medium, wherein at least one instruction or at least one program is stored in the storage medium, characterized in that: The at least one instruction or the at least one program is loaded and executed by a processor to implement the method according to any one of claims 1 to 6.

8. An electronic device, characterized in that: The device comprises a processor and the non-transitory computer-readable storage medium as claimed in claim 7.

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