Control method of image correction coefficient memory

Abstract

The invention relates to the field of image correction coefficient storage, in particular to a control method of an image correction coefficient storer, which comprises the following steps: if the number m of image correction coefficients of a spectrum is less than or equal to the number n of storage addresses of a sub-sector, a flash chip allocates one sub-sector for the spectrum; if m is larger than the number n of storage addresses of one sub-sector but smaller than the number p of storage addresses of one sector, the flash chip allocates x sub-sectors to the spectrum segment, and x meets the condition that m is larger than or equal to xn and smaller than (x + 1) n; if m is larger than the storage address number p of one sector and larger than the storage address number n of one sub-sector, the flash chip distributes y sectors and z sub-sectors for the spectrum band, and y and z meet the conditions that m is larger than or equal to yp + zn and smaller than yp + (z + 1) n, and m is larger than or equal to yp + zn and smaller than (y + 1) p + zn. According to the method, the image correction coefficients among the spectrum segments are mutually independent, so that mutual influence during partial updating is avoided.

Description

Technical Field

[0001] The present invention belongs to the technical field of image correction coefficient storage, and particularly relates to a control method for an image correction coefficient memory. Background Art

[0002] Since changing the gain of the detector will change the response curve of the detector, generally, the non-uniform image correction coefficients of TDI detectors change with the change of the gain parameter value; the change of the detector pixel size will also cause the response characteristics to change, and the image correction coefficients need to be changed accordingly; for the change of the integration level and the push-broom direction, the image correction coefficients do not change accordingly. For fine correction applications, the number of rows of photosensitive pixels applied by the TDI detector at different integration levels is different. The TDI detector has different numbers of rows of photosensitive pixels applied at the same integration level and different scanning directions, and there are also slight differences in the response. If the gain parameter value, integration level value, pixel size, and push-broom direction of the detector are mapped in four dimensions, the image correction coefficients are huge.

[0003] The patent with publication number CN116800950A and publication date September 22, 2023 discloses an image correction coefficient generation and update method, which mainly stores image correction coefficients based on MRAM. However, the storage capacity of MRAM is relatively small and it is difficult to store huge image correction coefficients. The flash chip has a large storage capacity and has good application potential. However, the same address of the flash chip needs to be erased before each write operation. The erase operation is performed in units of sectors, and there is a risk that the information to be retained will be erased. For example, during the process of radiation calibration to determine image correction coefficients, it will be evaluated whether the image correction coefficients need to be updated according to the correction effect. It may be necessary to update the image correction coefficients of some spectral bands. If the image correction coefficients of multiple spectral bands are stored in the same sector, the image correction coefficients of the spectral bands that do not need to be updated will be erased when the sector is erased. Summary of the Invention

[0004] In view of this, the present invention aims to provide a control method for an image correction coefficient memory to solve the technical problem that the flash chip cannot perform erasure on local addresses.

[0005] To achieve the above object, the technical solution of the present invention is realized as follows: A control method for an image correction coefficient memory allocates storage address spaces for the image correction coefficients of each spectral band of the detector; when the image correction coefficient memory uses a flash chip, the allocation of storage address spaces by the flash chip is divided into the following three cases: The first case: If the number m of image correction coefficients in a spectral band is less than or equal to the number n of storage addresses in a sub-sector, the flash chip allocates a sub-sector for this spectral band; The second case: If the number m of image correction coefficients in a spectral band is greater than the number n of storage addresses in a sub-sector but less than the number p of storage addresses in a sector, the flash chip allocates x sub-sectors for this spectral band, and the number x of sub-sectors is calculated according to the following rules: ; The third case: If the number m of image correction coefficients in a spectral band is greater than the number p of storage addresses in a sector and also greater than the number n of storage addresses in a sub-sector, the flash chip allocates y sectors and z sub-sectors for this spectral band, and the number y of sectors and the number z of sub-sectors are calculated according to the following rules: .

[0006] Furthermore, for the first case, first perform an erase operation on the allocated sub-sector, and then perform a programming operation; for the second case, first perform an erase operation on the allocated x sub-sectors, and then perform a programming operation; for the third case, first perform an erase operation on the allocated y sectors and z sub-sectors, and then perform a programming operation.

[0007] Furthermore, the programming operation is performed in units of packets of a preset size, and the number of data stored in the sector and sub-sector is an integer multiple of the number of data per packet.

[0008] Furthermore, the programming operation adopts a write cache mode. If the number of continuously written data in the write cache programming operation is r, and the interval time of the write cache programming operation is t, then the time interval t is greater than the total time required to complete the continuous write cache programming operation: ; where, is the time length of each instruction cycle, is the waiting time of the write cache programming operation, and s is the number of instruction cycles for the additional overhead of the write cache programming operation.

[0009] Furthermore, the transmission time of a packet of image correction coefficients is greater than the interval time t of the flash chip write cache programming operation, that is: ; where, a is the total number of bytes of a packet of image correction coefficients, b is the total number of serial bits included when transmitting a single-byte data, and f is the transmission baud rate of the image correction coefficients.

[0010] Compared with the prior art, the present invention can achieve the following beneficial effects: 1. According to the magnitudes of the image correction coefficients of each spectral band of the detector, storage address spaces are allocated for the image correction coefficients of each spectral band to ensure the independence of the image correction coefficients between spectral bands, thereby avoiding mutual influence during partial updates.

[0011] 2. If the continuous content to be updated in the flash chip is greater than one sector, sector operations are performed; if the continuous content to be updated in the flash chip is less than one sector, sub-sector operations are performed, so that only the content to be updated is erased and programmed, improving the efficiency of data update.

[0012] 3. The programming operation is updated in units of packets. The number of data stored in the sector and sub-sector is an integer multiple of the number of data of each packet of image correction coefficients, thereby reducing cross-sector operations. In addition, it is required that the transmission time of one packet of image correction coefficients is greater than the interval time t of the flash chip write cache programming operation, so as to ensure the continuous transmission of image correction coefficients and avoid the situation of missed programming of the transmitted image correction coefficients.

[0013] 4. The programming operation adopts the write cache programming mode to improve the programming efficiency by continuously writing multiple data. Description of the Drawings

[0014] The drawings constituting a part of the present invention are used to provide a further understanding of the present invention. The schematic embodiments and descriptions thereof of the present invention are used to explain the present invention and do not constitute an improper limitation to the present invention. In the drawings: Figure 1 is a schematic logical structure diagram of the imaging system of the detector according to the embodiment of the present invention. Detailed Embodiments

[0015] In order to make the purpose, technical solutions and advantages of the present invention clearer, the present invention will be further described in detail below with reference to the drawings and specific embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and do not constitute a limitation to the present invention.

[0016] It should be noted that, without conflict, the embodiments in the present invention and the features in the embodiments can be combined with each other.

[0017] In the description of the present invention, it should be understood that the orientation or positional relationship indicated by the terms "center", "longitudinal", "transverse", "up", "down", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc. is based on the orientation or positional relationship shown in the drawings. It is only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation. Therefore, it should not be construed as a limitation to the present invention. In addition, the terms "first", "second", etc. are only used for descriptive purposes and cannot be understood as indicating or implying relative importance or implicitly specifying the quantity of the indicated technical features. Thus, the features defined with "first", "second", etc. may explicitly or implicitly include one or more of such features. In the description of the present invention, unless otherwise specified, the meaning of "a plurality" is two or more.

[0018] In the description of the present invention, it should be noted that unless otherwise clearly specified and limited, the terms "mounted", "connected", "coupled" shall be understood in a broad sense. For example, it may be a fixed connection, a detachable connection, or an integral connection; it may be a mechanical connection or an electrical connection; it may be directly connected or indirectly connected through an intermediate medium, and it may be the communication inside two elements. For those of ordinary skill in the art, the specific meanings of the above terms in the present invention can be understood through specific situations.

[0019] The present invention will be described in detail below with reference to the drawings and in conjunction with embodiments.

[0020] As Figure 1 shown, the control method of the image correction coefficient memory provided by the embodiment of the present invention is implemented through the imaging system of the detector. The imaging system of the detector includes a camera controller, an imaging controller power supply chip, an imaging controller, a detector power supply chip, a multi-spectrum detector, an erasable main and standby flash chip, a PROM, a flash chip, a cameralink chip, a cameralink connector, a 2711 chip, and a 2711 connector.

[0021] The camera controller receives the primary power supply input externally, generates various required power supplies; meanwhile, it receives the second pulse input externally and communicates with the outside through the 1553 bus. The camera controller communicates with the imaging controller through the 422 communication signal, provides the second pulse for the imaging controller, and provides the power supply for the imaging controller through the imaging controller power supply chip. The imaging controller provides the drive control signal for the multi-spectral detector, provides the power supply for the multi-spectral detector through the detector power supply chip, and receives the serial image data output by the multi-spectral detector. The imaging controller is simultaneously connected to the loaded configuration data source PROM and the erasable main and standby flash chips, and is also connected to the flash chips to update the image correction coefficients and load the image correction coefficients before each imaging. The imaging controller can output the image data through the cameralink chip and the cameralink connector according to the selection, or can also output the image data through the 2711 chip and the 2711 connector.

[0022] The imaging controller power supply chip uses a 510 DCDC module; the detector uses an area array detector of Changguang Chenxin Co., Ltd.; the camera controller mainly uses a DSP chip; the imaging controller mainly uses the imaging controller and refresh chip of Shanghai Fudan Microelectronics Co., Ltd.; the detector power supply chip mainly uses the LDO of TI Company; the 2711 chip uses the TLK2711 chip; the 2711 connector uses the micro coaxial connector of Sichuan Huafeng; the cameralink chip uses the DS90CR287; the cameralink connector uses the MDR26 connector of 3M Company; the erasable main and standby flash chips use the products of Fudan Micro; the PROM uses the products of Xilinx Company; the flash chips use the products of Fudan Micro.

[0023] In the control method of the image correction coefficient memory provided by the embodiment of the present invention, the image correction coefficient memory refers to a flash chip with a large storage capacity. Storage address spaces are allocated for the image correction coefficients of each spectral band of the detector inside the flash chip, and the image correction coefficients are updated according to the allocated storage address spaces.

[0024] The allocation of storage address spaces for the flash chip is divided into the following three cases: The first case: If the number m of the image correction coefficients of a spectral band is less than or equal to the number n of storage addresses of a sub-sector, the flash chip allocates a sub-sector for this spectral band.

[0025] For the first case, when the image correction coefficients of a spectral band do not exceed the capacity of a sub-sector, the image correction coefficients of the spectral band only occupy one sub-sector, and only allocating the space of one sub-sector can meet the update of the image correction coefficients of this spectral band.

[0026] The second case: If the number m of image correction coefficients in a spectral band is greater than the number n of storage addresses in a sub-sector but less than the number p of storage addresses in a sector, the flash chip allocates x sub-sectors for this spectral band. The number x of sub-sectors is calculated according to the following rules: .

[0027] For the second case, when the image correction coefficients of a spectral band exceed the capacity of a sub-sector but do not exceed the capacity of the entire sector, the image correction coefficients of this spectral band occupy x sub-sectors, where x is the smallest integer that satisfies the above inequality.

[0028] : It means that at least x sub-sectors are required to store the number m of correction coefficients. Each sub-sector has n storage addresses, so the total storage capacity of x sub-sectors is xn. xn ≤ m ensures that the number m of correction coefficients is not less than the total storage capacity of x sub-sectors.

[0029] : It means that the number m of correction coefficients is less than the total storage capacity of x + 1 sub-sectors. This means that the number m of correction coefficients does not exceed the total storage capacity of x + 1 sub-sectors, thus ensuring that the number m of correction coefficients is within the storage range of x sub-sectors.

[0030] The above inequality ensures that the number m of correction coefficients is reasonably allocated to x sub-sectors, neither wasting storage space nor exceeding the storage capacity of a single sector.

[0031] The third case: If the number m of image correction coefficients in a spectral band is greater than the number p of storage addresses in a sector and also greater than the number n of storage addresses in a sub-sector, the flash chip allocates y sectors and z sub-sectors for this spectral band. The number y of sectors and the number z of sub-sectors are calculated according to the following rules: .

[0032] For the third case, when the image correction coefficients of a spectral band exceed the capacity of a sector and also exceed the capacity of a sub-sector of another sector, the image correction coefficients of this spectral band occupy y sectors and z sub-sectors.

[0033] : It means that at least y sectors and z sub-sectors are required to store the number m of image correction coefficients, but it has not reached the capacity that requires adding another sub-sector. That is: is the lower limit of the total capacity of y sectors and z sub-sectors.

[0034] is the upper limit of the capacity after adding a sub-sector.

[0035] Therefore, if the number m of image correction coefficients falls within this interval, it indicates that the current number z of sub-sectors is sufficient and no additional sub-sectors are required.

[0036] : It means that the number m of image correction coefficients also requires z sub-sectors in y sectors, but does not reach the capacity of needing to add another sector. That is: is the upper limit of the capacity after adding one sector.

[0037] Therefore, if the number m of image correction coefficients falls within this interval, it indicates that the current number y of sectors is sufficient and no additional sectors are required.

[0038] and These two inequalities together ensure that the number m of image correction coefficients can be exactly stored in y sectors and z sub-sectors, neither requiring an increase in sub-sectors due to exceeding the sub-sector capacity nor an increase in sectors due to exceeding the sector capacity, ensuring that the storage allocation neither wastes sub-sectors nor wastes sectors.

[0039] According to the magnitudes of the image correction coefficients of each spectral band of the detector, storage address spaces are allocated for the image correction coefficients of each spectral band to ensure that the image correction coefficients between spectral bands are independent of each other, thus avoiding mutual influence during partial updates.

[0040] If the continuous content to be updated in the flash chip is larger than one sector, sector operations are performed; if the continuous content to be updated in the flash chip is smaller than one sector, sub-sector operations are performed, so that only the content to be updated is erased and programmed, improving the efficiency of data update.

[0041] For the update of correction coefficients, an erase operation is first performed, and a programming operation can be performed only after receiving the telemetry return information indicating that the erase operation is completed; if the telemetry return information is not received within the specified time, the programming operation is abandoned.

[0042] For the first case, an erase operation is first performed on the allocated sub-sector, and then a programming operation is performed; for the second case, an erase operation is first performed on the allocated x sub-sectors, and then a programming operation is performed; for the third case, an erase operation is first performed on the allocated y sectors and z sub-sectors, and then a programming operation is performed.

[0043] The programming operation is performed for writing and updating in units of packets of a preset size, and the number of data stored in sectors and sub-sectors is an integer multiple of the number of data per packet, thereby reducing cross-sector operations.

[0044] The programming operation adopts the write cache mode to improve the programming efficiency by continuously writing r data. r is a positive integer and less than or equal to the maximum number allowed by the flash chip write cache mode. The interval time for the write cache programming operation is t, and the time interval t is greater than the total time required to complete the continuous write cache programming operation: ; Among them, is the time length of each instruction cycle, is the waiting time for the write cache programming operation, and s is the number of instruction cycles for the additional overhead of the write cache programming operation.

[0045] The above inequality is used to ensure the time security of continuous write cache operations. If the actual time tt does not satisfy this inequality, it may lead to operation failure or data corruption.

[0046] It is required that the transmission time of a packet of image correction coefficients is greater than the interval time t of the flash chip write cache programming operation, that is: ; Among them, a is the total number of bytes of a packet of image correction coefficients, including redundant data such as correction coefficients, synchronization headers, identification codes, and checksums; b is all the serial bits included in the transmission of a single-byte data, including start bits, parallel data bit widths, parity bits, stop bits, and idle bits; f is the transmission baud rate of the image correction coefficients.

[0047] The above inequality is used to ensure that after the link transmission finishes transmitting a packet of image correction coefficients, the flash chip has enough time to complete the programming operation, avoiding data loss or operation failure caused by timing conflicts.

[0048] It should be understood that various forms of the processes shown above can be used, reordering, adding, or deleting steps. For example, the steps recorded in the disclosure of the present invention can be executed in parallel, sequentially, or in different orders, as long as the desired results of the technical solutions disclosed in the present invention can be achieved, and no limitations are imposed herein.

[0049] The above specific embodiments do not constitute a limitation to the protection scope of the present invention. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the present invention shall be included within the protection scope of the present invention.

Claims

1. A control method for an image correction coefficient memory, characterized in that Allocate storage address space for the image correction coefficients of each spectral band of the detector; when the image correction coefficient memory uses a flash chip, the allocation of storage address space for the flash chip is divided into the following three cases: The first case: If the number m of image correction coefficients of a spectral band is less than or equal to the number n of storage addresses of a sub-sector, the flash chip allocates one sub-sector for this spectral band; The second case: If the number m of image correction coefficients of a spectral band is greater than the number n of storage addresses of a sub-sector but less than the number p of storage addresses of a sector, the flash chip allocates x sub-sectors for this spectral band, and the number x of sub-sectors is calculated according to the following rules: ； The third case: If the number m of image correction coefficients of a spectral band is greater than the number p of storage addresses of a sector and also greater than the number n of storage addresses of a sub-sector, the flash chip allocates y sectors and z sub-sectors for this spectral band, and the number y of sectors and the number z of sub-sectors are calculated according to the following rules: 。 2. The control method of the image correction coefficient memory according to claim 1, wherein For the first case, first perform an erase operation on the allocated sub-sector, and then perform a programming operation; for the second case, first perform an erase operation on the allocated x sub-sectors, and then perform a programming operation; for the third case, first perform an erase operation on the allocated y sectors and z sub-sectors, and then perform a programming operation.

3. The control method of the image correction coefficient memory according to claim 2, wherein The programming operation is written in units of packets of a preset size, and the number of data stored in the sector and sub-sector is an integer multiple of the number of data per packet.

4. The control method of the image correction coefficient memory according to claim 3, characterized in that, The programming operation adopts a write cache mode. If the number of continuously written data for the write cache programming operation is r and the interval time for the write cache programming operation is t, then the time interval t is greater than the total time required to complete the continuous write cache programming operation: ； Wherein, is the time length of each instruction cycle, is the waiting time for the write cache programming operation, and s is the number of instruction cycles for the additional overhead of the write cache programming operation.

5. The control method of the image correction coefficient memory according to claim 4, wherein The transmission time of a packet of image correction coefficients is greater than the interval time t of the flash chip write cache programming operation, that is: ； where a is the total number of bytes of a packet of image correction coefficients, b is all the serial bits included in the transmission of a single-byte data, and f is the transmission baud rate of the image correction coefficients.

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