Signal identification method and device, electronic equipment and storage medium

Abstract

The invention discloses a signal identification method and device, electronic equipment and a storage medium, and relates to the technical field of computers, the identification method is applied to a backboard in target equipment, and the backboard is connected with a mainboard through a first connector; the backboard is connected with the switch through the second connector. The first connector is connected with the voltage division circuit; the second connector is connected with a grounding resistor, and is used for receiving a signal which is output after voltage value conversion is carried out on a mainboard signal sent by the mainboard port by the voltage division circuit, or receiving a second voltage signal which is output after voltage value conversion is carried out on a switch signal of the switch by the grounding resistor, and switching the switch on the basis of the received voltage signal; and determining the voltage value of the voltage signal so as to identify the source of the voltage signal according to the voltage value. As the voltage value is wide in recognizable range relative to the address bit, the technical effects of increasing the expandability of the target equipment and improving the performance of the target equipment can be achieved, and the technical problem that the expandability of the current target equipment is limited is solved.

Description

Technical Field

[0001] This application relates to the field of computer technology, and particularly to a signal recognition method, apparatus, electronic device, and storage medium. Background Art

[0002] In modern data centers and cloud computing environments, the flexibility and scalability of computer devices have become key factors in supporting business growth and coping with changes in data processing requirements. However, when facing diverse application scenarios and ever-upgrading hardware requirements, traditional computer devices have exposed a series of technical problems in hardware resource management, which limit the overall performance of computer devices.

[0003] Currently, in terms of hardware resource management, computer devices rely on limited address bit resources to distinguish between the motherboard and the switch. Specifically, by setting different high and low voltage combinations of the address bits, different motherboard ports of the switch and the motherboard are mapped, and then the hard disk devices connected under the switch and the motherboard are controlled.

[0004] However, with the increase in the number of switch and motherboard ports, especially in high-density servers, this resource allocation method based on fixed address bits has become difficult to meet the requirements, limiting the scalability of computer devices and seriously affecting the performance of computer devices. Summary of the Invention

[0005] This application provides a signal recognition method, apparatus, electronic device, and storage medium to at least solve the problem that the scalability of the target device in related technologies is limited.

[0006] This application provides a signal recognition method applied to a backplane in a target device. The backplane is connected to a motherboard through a first connector; the backplane is connected to a switch through a second connector; the first connector is connected to a voltage dividing circuit; the second connector is connected to a grounding resistor, and includes: receiving a voltage signal, where the voltage signal includes: a first voltage signal or a second voltage signal; the first voltage signal is a signal output through a pin of the first connector after the voltage dividing circuit converts the voltage value of the motherboard signal sent by the motherboard port of the motherboard; the second voltage signal is a signal output through a pin of the second connector after the grounding resistor converts the voltage value of the switch signal sent by the switch; determining the voltage value of the voltage signal, and identifying the signal source of the voltage signal according to the voltage value.

[0007] The present application also provides a signal recognition device, including: a receiving module, configured to receive a voltage signal, where the voltage signal includes: a first voltage signal or a second voltage signal; the first voltage signal is a signal output through a pin of a first connector after a voltage value conversion is performed on a motherboard signal sent by a motherboard port of a motherboard by a voltage dividing circuit; the second voltage signal is a signal output through a pin of a second connector after a voltage value conversion is performed on a switch signal sent by a switch by a grounding resistor; an identification module, configured to determine a voltage value of the voltage signal and identify a signal source of the voltage signal according to the voltage value.

[0008] The present application also provides an electronic device, including: a memory, configured to store a computer program; a processor, configured to implement the steps of any one of the above signal recognition methods when executing the computer program.

[0009] The present application also provides a computer-readable storage medium, in which a computer program is stored, where the computer program implements the steps of any one of the above signal recognition methods when executed by a processor.

[0010] The present application also provides a computer program product, including a computer program, where the computer program implements the steps of any one of the above signal recognition methods when executed by a processor.

[0011] Through the present application, it is applied to a backplane in a target device, the backplane is connected to the motherboard through a first connector; the backplane is connected to a switch through a second connector; the first connector is connected to a voltage dividing circuit; the second connector is connected to a grounding resistor, and thus it is possible to receive a signal output through a pin of the first connector after a voltage value conversion is performed on a motherboard signal sent by a motherboard port of the motherboard by the voltage dividing circuit, or receive a second voltage signal output through a pin of the second connector after a voltage value conversion is performed on a switch signal sent by the switch by the grounding resistor. Since the voltage value of the received voltage signal, that is, the first voltage signal or the second voltage signal, can be determined, the source of the voltage signal can be identified according to the voltage value. Since the voltage value has a wider recognizable range relative to the address bits and has higher flexibility, more motherboard ports and switches can be distinguished, and the technical problem that the scalability of the current target device is limited can be solved, achieving the technical effects of increasing the flexibility and scalability of the target device and improving the performance of the target device. Description of the Drawings

[0012] To more clearly illustrate the embodiments of the present application, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0013] Figure 1(a) is one of the hardware structure block diagrams of the target device provided by the embodiment of the present application;

[0014] Figure 1(b) is the second hardware structure block diagram of the target device provided by the embodiment of the present application;

[0015] Figure 2 is the flowchart of a signal recognition method provided by the embodiment of the present application;

[0016] Figure 3 is one of the hardware structure topology diagrams of the target device provided by the embodiment of the present application;

[0017] Figure 4 is the topology structure diagram of the connection between the main board and the backplane in the related art;

[0018] Figure 5 is the second hardware structure topology diagram of the target device provided by the embodiment of the present application;

[0019] Figure 6 is the topology structure diagram of the connection between the switch and the backplane in the related art;

[0020] Figure 7 is the structure block diagram of a signal recognition device provided by the embodiment of the present application. Detailed implementation manners

[0021] Next, the technical solutions in the embodiments of the present application will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present application.

[0022] It should be noted that in the description of the present application, the terms "include", "comprise" or any other variation thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements not only includes those elements but also includes other elements not expressly listed, or further includes elements inherent to such process, method, article or device. The terms "first", "second", etc. in the present application are used to distinguish similar objects, rather than to describe a specific order or sequence.

[0023] In order to enable those skilled in the art of this technology to better understand the solution of the present application, the present application will be further described in detail below in conjunction with the accompanying drawings and specific implementation manners.

[0024] In the embodiments of the present application, the signal recognition method embodiments can be executed on the backplane of the target device, and the target device can specifically be a server device or a similar computing device. Specifically, taking the backplane running on the server device as an example, Figure 1(a) is a hardware structure block diagram of the connection between the motherboard and the backplane in the embodiments of the present application. The backplane is connected to the motherboard through a first connector; the first connector is connected to a voltage dividing circuit; furthermore, the backplane can receive the signal output through the pins of the first connector after the voltage value conversion of the motherboard signal sent by the motherboard port of the motherboard by the voltage dividing circuit. As shown in Figure 1(b), it is a hardware structure block diagram of the connection between the switch and the backplane. The backplane is connected to the switch through a second connector, and the second connector is connected to a grounding resistor. Furthermore, it can receive the signal output through the pins of the first connector after the voltage value conversion of the motherboard signal sent by the motherboard port of the motherboard by the voltage dividing circuit, or receive the second voltage signal output through the pins of the second connector after the voltage value conversion of the switch signal sent by the switch by the grounding resistor.

[0025] An embodiment of the present application provides a signal recognition method. This method is applied to the backplane in the target device. The target device can specifically refer to a server device. The backplane is connected to the motherboard through a first connector; the backplane is connected to the switch through a second connector; the first connector is connected to a voltage dividing circuit; the second connector is connected to a grounding resistor. As Figure 2 shown, this method includes the following steps S202-204:

[0026] S202, receive a voltage signal, where the voltage signal includes: a first voltage signal or a second voltage signal; the first voltage signal is the signal output through the pins of the first connector after the voltage value conversion of the motherboard signal sent by the motherboard port of the motherboard by the voltage dividing circuit; the second voltage signal is the signal output through the pins of the second connector after the voltage value conversion of the switch signal sent by the switch by the grounding resistor.

[0027] Among them, the backplane is an important component for realizing high-speed data transmission and control signal exchange of all functional components of a computer device (such as a central processing unit, GPU (Graphics Processing Unit), storage device, network interface, etc.). A CPLD (Complex Programmable Logic Device) can be integrated on the backplane to implement various signal processing and control logics.

[0028] The motherboard integrates multiple components such as a central processing unit (CPU), memory slots, PCIe (PCI Express, a high-speed serial computer expansion bus standard) slots, hot-swap interfaces, and a baseboard management controller (BMC). The motherboard can work with other hardware components (such as the CPLD on the backplane) through motherboard ports (such as the processor port) to achieve efficient and flexible control logic.

[0029] The switch refers to a PCIe SW switch. The PCIe SW can expand the number of PCIe ports on the motherboard, allowing more devices (such as GPUs, NVMe (Non-Volatile Memory Host Controller Interface Specification) hard drives) to be connected to the server device. Especially when the server device needs to handle a large number of parallel computing tasks or storage requirements, the PCIe SW provides the necessary interface expansion.

[0030] It can be understood that whether it is the switch or the motherboard port, it can send a voltage signal to the backplane so that the backplane can identify the source of the signal based on the voltage signal, and then can identify and execute the control instructions sent by the motherboard or the switch (such as the lighting instruction, that is, an instruction to display the status of computer components (such as hard drives, drives, etc.)). The backplane performs a lighting operation based on the lighting instruction to indicate whether the hard drive is in place, whether it is running normally, or whether there is a fault, etc. Exemplarily, when the hard drive is connected to the motherboard, the motherboard port sends a first voltage signal to the backplane through the first connector; when the hard drive is connected to the switch, the switch sends a second voltage signal to the backplane.

[0031] It should be noted that the voltage signal is used to indicate the source of the signal, that is, through the voltage signal, the backplane can clearly identify whether the signal comes from the motherboard port or the switch. The motherboard port can send a signal to the backplane through the first connector, and the voltage value of the motherboard signal sent by the motherboard port is converted by the voltage dividing circuit connected to the first connector, and then output to the backplane through the pins of the first connector. The scenarios where the motherboard port sends the motherboard signal include but are not limited to the following situations: device presence recognition and fault detection, etc. Among them, device presence recognition means that the motherboard can regularly send the motherboard signal to inform the backplane that the hard drive is present. For example, after a certain hard drive is detected to be ready, the motherboard sends the motherboard signal to the backplane through the motherboard port. After the backplane recognizes that the signal is sent by the motherboard port, the motherboard port can then send the first lighting instruction to the backplane to make the backplane light up the "online" or "ready" indicator of the slot or bracket where the hard drive is located. Fault detection means that when the motherboard detects that the hard drive has a fault, it will send a signal to inform the backplane. After the backplane recognizes that the signal is the motherboard signal sent by the motherboard, it will then send the second lighting instruction to the backplane to make the backplane light up the fault indicator.

[0032] It can be understood that the switch can send a switch signal to the backplane through the second connector. The grounding resistor connected to the second connector converts the voltage value of the switch signal sent by the switch, and then outputs it to the backplane through the pins of the second connector. Among them, the scenario of the switch sending the switch signal is the same as that of the main board, which will not be elaborated in this application.

[0033] In some embodiments, the voltage dividing circuit can be composed of two precision resistors (R1 and R2), where R1 is pulled up to the 3v3 power supply and R2 is connected to the ground (GND). According to the resistance value of the resistors and the voltage division principle, when the main board signal passes through the first connector, the voltage value of the main board signal is converted by the voltage dividing circuit connected to the first connector and then output. For example, R1 can be set to 30kΩ, and when R2 is set to 1000kΩ, that is, 1MΩ, the calculated theoretical value after voltage conversion is 3.21V.

[0034] In some other embodiments, the second connector is connected to a grounding resistor R4, and the resistance value of R4 can be fixedly set to 0Ω. When the switch signal passes through the second connector, the voltage value of the switch signal is converted by the grounding resistor R4 connected to the second connector and then output, and the level of the switch signal is pulled down to 0V.

[0035] In some embodiments, the voltage dividing circuit can be connected through any pin of the first connector and the second connector. The types of the pins of the first connector and the second connector can be the same, so as to ensure that for different connection situations (i.e., the main board and the backplane are connected, the switch and the backplane are connected), the signal can be accurately transmitted, maintaining the overall signal transmission consistency and compatibility.

[0036] S204, determine the voltage value of the voltage signal, and identify the signal source of the voltage signal according to the voltage value.

[0037] It can be understood that at the backplane end, an ADC (analog-to-digital conversion) pin can be configured. Through the ADC (analog-to-digital conversion) pin, the voltage signal sent by the pin of the first connector or the second connector can be received, and the analog voltage signal is converted into a digital signal for the voltage signal to obtain the voltage value.

[0038] In an exemplary embodiment, the identifying the signal source of the voltage signal according to the voltage value includes: obtaining a pre-constructed port mapping table, where the port mapping table at least includes: a plurality of voltage ranges and target voltage values; the voltage values included in the plurality of voltage ranges do not include the target voltage value; respectively matching the voltage value with the plurality of voltage ranges and the target voltage value to obtain a matching result; and identifying the signal source of the voltage signal based on the matching result.

[0039] It is understandable that the port mapping table is the basis for identifying the source of the voltage signal. It contains multiple voltage ranges and target voltage values. The voltage ranges correspond to the motherboard ports. Since the motherboard includes multiple motherboard ports, for each of the multiple voltage ranges, there is a corresponding motherboard port. The pull-up resistor R1 and the pull-down resistor R2 in the voltage division circuit are both adjustable. In the adjustable case, the pull-up resistor R1 and the pull-down resistor R2 can use variable resistors, digital potentiometers or other programmable resistor elements, and these elements can be adjusted through external control signals or software configuration. Furthermore, for any motherboard port, after the voltage value conversion, there is a unique voltage value. For example, the voltage range from 3.18V to 3.24V can correspond to motherboard port A, and the voltage range from 4.18V to 5.24V can correspond to motherboard port B.

[0040] The target voltage value is set for the switch. The voltage values included in the multiple voltage ranges do not include the target voltage value, that is, the target voltage can be any value other than the voltage values included in the voltage ranges. Exemplarily, the target voltage value is 0.

[0041] In some embodiments, the backplane can compare the voltage value with the multiple voltage ranges and the target voltage value in the pre-constructed port mapping table. If the voltage value falls within a certain voltage range, the backplane can identify that the signal source belongs to the device type represented by this voltage range. If the voltage value is the target voltage value, the backplane can identify that the signal source belongs to the device type represented by the target voltage value.

[0042] In the above embodiments, by comparing the voltage value with the voltage range and the target voltage value, the signal source can be accurately identified, avoiding the ambiguity and errors that may be brought by the traditional logic level identification method, and the use of the voltage value method allows the use of fewer hardware resources to distinguish more ports or devices, greatly improving the flexibility and scalability of the target device.

[0043] In an exemplary embodiment, identifying the signal source of the voltage signal based on the matching result includes: in the case where the matching result is that the voltage value is within any one of the multiple voltage ranges, identifying the signal source of the voltage signal as the motherboard port of the motherboard; in the case where the matching result is that the voltage value is the target voltage value, identifying the signal source of the voltage signal as the switch.

[0044] In some embodiments, when it is detected that the voltage value falls within any one of a plurality of voltage ranges, the backplane can determine that this voltage signal is from a certain motherboard port of the motherboard. For example, if the voltage value is 3.21V and there is a voltage range of 3.18V to 3.24V, the CPLD can identify that the signal comes from the motherboard port. Further, the model of the motherboard port can also be determined as the PE0A / PE0B port.

[0045] In some other embodiments, if the backplane detects that the voltage value is the target voltage value, such as 0V, the backplane can identify that the signal comes from the switch rather than the motherboard port. Since the second connector is connected to the grounding resistor R4, and the grounding resistor R4 can be set to 0Ω, when the switch signal sent by the switch passes through the grounding resistor R4, the voltage is converted to 0V.

[0046] In the above embodiments, the backplane can accurately and quickly distinguish whether the signal source is the motherboard port or the switch based on the detection result of the voltage value. In this way, not only can the signal source be identified, but also the appropriate control logic can be selected according to the type of the signal source in the subsequent process.

[0047] Through the above S202 - S204, for the backplane applied to the target device, the backplane is connected to the motherboard through the first connector; the backplane is connected to the switch through the second connector; the first connector is connected to the voltage dividing circuit; the second connector is connected to the grounding resistor. Further, it can receive the signal output through the pin of the first connector after the voltage value of the motherboard signal sent by the motherboard port of the motherboard is converted by the voltage dividing circuit, or receive the second voltage signal output through the pin of the second connector after the voltage value of the switch signal sent by the switch is converted by the grounding resistor. Since the voltage value of the received voltage signal, that is, the first voltage signal or the second voltage signal, can be determined, the source of the voltage signal can be identified according to the voltage value. Since the voltage value has a wider recognizable range relative to the address bits and has higher flexibility, more motherboard ports and switches can be distinguished, and the technical problem that the scalability of the current target device is limited can be solved, achieving the technical effects of increasing the flexibility and scalability of the target device and improving the performance of the target device.

[0048] In an exemplary embodiment, before identifying the signal source of the voltage signal according to the voltage value, the method further includes: for any motherboard port of the motherboard, determining a port voltage value matching the any motherboard port, and determining a switch voltage value matching the switch; performing error processing on the port voltage value of the any motherboard port according to a preset error value, and based on the port voltage value after the error processing, determining a first voltage range of the any motherboard port; constructing a first mapping relationship based on the first voltage range of the any motherboard port and the port identifier of the any motherboard port, and constructing a second mapping relationship based on the switch voltage value of the switch and the switch identifier of the switch, wherein the port mapping table corresponding to the backplane includes the first mapping relationship and the second mapping relationship.

[0049] It should be noted that for each motherboard port on the motherboard, a port voltage value matching it can be determined. The port voltage value is determined by the pull-up resistor R1 and the pull-down resistor R2, and the specific value depends on the resistance ratio of R1 and R2. For example, for the PE0A / PE0B port, R1 is set to 30 kΩ and R2 is set to 1000 kΩ, and the theoretical voltage value can be obtained as 3.21 V through voltage division calculation.

[0050] For the switch voltage value, since the switch signal will pass through the grounding resistor during the process of sending the switch signal to the backplane, its voltage value will be converted to 0 V. Therefore, the switch voltage value matching the switch is constantly 0 V.

[0051] Considering the precision error of the resistor (such as 1%), error processing can be performed on the determined port voltage value. This means that the actually detected voltage value can fluctuate within a small range of the theoretical value. For example, for the theoretical voltage value of 3.21 V, the actual detection range can be from 3.18 V to 3.24 V.

[0052] Based on the voltage value after error processing, a first voltage range is defined for each motherboard port. For example, the voltage range of PE0A / PE0B is from 3.18 V to 3.24 V, which represents the voltage change range that the CPLD can identify, so as to ensure that the signal source can be accurately identified even under small-range voltage fluctuations.

[0053] In some embodiments, a mapping relationship can be established between the first voltage range of each motherboard port and its port identifier (such as PE0A / PE0B). In this way, when the backplane detects that the voltage value is within a certain range, it can identify the signal source as the corresponding motherboard port according to the first mapping relationship. For a switch, a second mapping relationship is established, where the switch voltage value (0V) corresponds to the switch identifier (such as Broadcom, Microchip, etc.). In this way, when the backplane detects that the voltage value is 0V, it can quickly identify that the signal source is the switch and prepare to call the corresponding lighting control logic.

[0054] In a specific application, the first mapping relationship and the second mapping relationship can be summarized into the port mapping table of the backplane to form a comprehensive identification database. After detecting the voltage value, the backplane will perform a quick match according to the port mapping table. If the voltage value belongs to the first voltage range of a certain motherboard port, the backplane will identify it as the motherboard port signal source; if the voltage value is 0V, it will be identified as the switch signal source.

[0055] In the above embodiments, by pre-establishing the port mapping table, when identifying the signal source subsequently, the backplane can directly obtain the port mapping table, and can identify the signal source intelligently and accurately, and then execute the correct control logic subsequently.

[0056] In an exemplary embodiment, determining the port voltage value matching any motherboard port includes: determining the pull-up resistor value and the pull-down resistor value corresponding to any motherboard port from a preset resistance value range, where the pull-up resistor values of each motherboard port are different, the pull-down resistor values of each motherboard port are different, or the pull-up resistor values and the pull-down resistor values of each motherboard port are all different; determining the sum of the resistance values of the pull-up resistor value and the pull-down resistor value, and determining the resistance quotient based on the sum of the resistance values and the pull-down resistor value; multiplying the power supply voltage of the motherboard by the resistance quotient to determine the port voltage value matching any motherboard port.

[0057] It should be noted that a pull-up resistor value and a pull-down resistor value are set for each motherboard port from a preset resistance value range. The selection of these resistance values is crucial because they determine the final port voltage value. It should be noted that these resistance values must ensure sufficient accuracy, such as using resistors with 1% accuracy, to ensure that the voltage divider circuit can stably output the expected voltage value.

[0058] Among them, the pull-up resistor values, the pull-down resistor values, or a combination of both of each motherboard port may be different. This difference in resistance values ensures that even under the same power supply voltage, the voltage value generated by each motherboard port through the voltage divider circuit is unique, so that the backplane can distinguish different ports based on the voltage value.

[0059] For each selected motherboard port, calculate the sum of the pull-up resistor value and the pull-down resistor value thereon, which is called the resistance sum. Further, based on the resistance sum and the pull-down resistor value, calculate the resistance quotient, and determine the product of the power supply voltage of the motherboard and the resistance quotient as the port voltage value matching any motherboard port. To cope with the possible precision error of the resistor (usually ±1%), error processing can be performed on the calculated port voltage value. For example, if the calculated voltage value is 3.2V, considering the ±1% error, the final voltage range will be approximately between 3.168V and 3.232V.

[0060] In the above embodiment, by setting the pull-up resistor and the pull-down resistor values of each motherboard port, a unique port voltage value can be generated for each motherboard port, and this is used as the basis for identifying the signal source.

[0061] In an exemplary embodiment, after identifying the signal source of the voltage signal according to the voltage value, the method further includes: when the signal source of the voltage signal is the motherboard port of the motherboard, based on the port identifier corresponding to the motherboard port in the port mapping table, determine the first control instruction sent by the motherboard port of the motherboard, and parse the first control instruction according to the instruction parsing format matching the port identifier to obtain a first parsing result; control the display state of the display device according to the first parsing result, where different display states of the display device are used to indicate the state of the first hardware device connected to the motherboard, the port mapping table includes a first mapping relationship, and the first mapping relationship is constructed by the first voltage range of any motherboard port and the port identifier of the any motherboard port.

[0062] It should be noted that after the backplane identifies that the signal source is the motherboard port, it can refer to the first mapping relationship stored in the port mapping table to find the port identifier that matches the detected voltage value. The port identifier is the unique identifier of the motherboard port and is used to distinguish different motherboard ports. Once the motherboard port identifier of the signal source is determined, the backplane can start monitoring the first control instruction sent by the motherboard port through the bus. The first control instruction can include the operation requirements for the hard disk status indicators (such as SSDO_LOC and SSDO_ERR).

[0063] In some embodiments, based on the port identifier corresponding to the motherboard port in the port mapping table, the backplane can determine the format of the first control instruction to be parsed. For example, if the identified port identifier is PE0A / PE0B, the backplane can call the parsing algorithm corresponding to this port identifier, and the backplane can parse the first control instruction received from the motherboard port according to the parsing algorithm matching this port identifier. Different motherboard ports can use different control instruction formats. Therefore, the backplane needs to flexibly parse instructions of various formats.

[0064] In some embodiments, after the parsing process ends, the backplane generates a first parsing result, which contains a complete understanding of the first control instruction, that is, how to change the state of the display device to conform to the current state or management requirements of the first hardware device (such as an NVMe hard disk). The backplane calls the preset state control logic to change the state of the display device according to the instruction parameters in the first parsing result. For example, if the first control instruction requires the LED (Light Emitting Diode) at a certain hard disk position to display an error state, the backplane will send a corresponding signal to trigger the display of this state.

[0065] In a specific application, the state of the display device (such as a status indicator light) can be dynamically adjusted according to the signal sent by the backplane. Different display states (such as always on, flashing, off) can intuitively reflect the in-position, normal operation, fault and other status information of the first hardware device (such as an NVMe hard disk), providing an intuitive hardware status indication for the user. By changing the display state, the backplane can transmit the status information of the first hardware device to the user in real time and accurately. For example, when the LED is always on, it can indicate that the hard disk is in position and working properly; flashing may mean that the hard disk is reading and writing data; and off may indicate that the hard disk is not inserted or there is a fault. These state changes play an important indicating role in server operation and maintenance, helping to quickly locate the problem disk position and conduct targeted fault troubleshooting and maintenance work.

[0066] In the above embodiments, after identifying that the signal source is the motherboard port, by parsing the first control instruction received from this motherboard port according to the instruction parsing format matching the port identifier, the display state of the display device can be accurately controlled to indicate the real-time state of the first hardware device connected to the motherboard. This process relies on accurate voltage detection, port identifier matching in the mapping table, and efficient parsing of control instructions, which together constitute the core logic of display state control in the server backplane design. Through this mechanism, not only the visual management of the hardware state is enhanced, but also the operation and maintenance efficiency and user experience are improved.

[0067] In an exemplary embodiment, after identifying the signal source of the voltage signal according to the voltage value, the method further includes: when the signal source of the voltage signal is the switch, determining a second control instruction sent by the switch based on the switch identifier corresponding to the switch in the port mapping table, and parsing the second control instruction according to an instruction parsing format matching the switch identifier to obtain a second parsing result; controlling the display state of the display device according to the second parsing result, where different display states of the display device are used to indicate the state of a second hardware device connected to the switch, and the port mapping table includes a second mapping relationship, which is constructed by the switch voltage value of the switch and the switch identifier of the switch.

[0068] It should be noted that after the backplane identifies that the signal source is a switch, it can refer to the second mapping relationship stored in the port mapping table to find the switch identifier that matches the detected voltage value. The switch identifier is the unique identifier of the switch. Once the switch identifier of the signal source is determined, the backplane can start monitoring the second control instruction sent by the switch through the bus. The second control instruction may include operation requirements for hard disk status indicators (such as SSD1_LOC and SSD1_ERR).

[0069] In some embodiments, based on the switch identifier corresponding to the switch in the port mapping table, the backplane can determine the format of the second control instruction to be parsed. For example, if the identified switch identifier is SW, the backplane can call the parsing algorithm corresponding to this switch identifier, and the backplane can parse the second control instruction received from the switch according to the parsing algorithm matching the switch identifier.

[0070] In some embodiments, after the parsing process ends, the backplane generates a second parsing result, which contains a complete understanding of the second control instruction, that is, how to change the state of the display device to conform to the current state or management requirements of the second hardware device (such as an NVMe hard disk). The backplane calls the preset state control logic to change the state of the display device according to the instruction parameters in the second parsing result. For example, if the second control instruction requires the LED (Light Emitting Diode) at a certain hard disk position to display the online state, the backplane will send a corresponding signal to trigger the display of this state.

[0071] In the above embodiments, after identifying that the signal source is a switch, by parsing the second control instruction received from the motherboard port according to the instruction parsing format matched by the switch identifier, the display state of the display device can be accurately controlled to indicate the real-time state of the first hardware device connected to the motherboard. This process depends on accurate voltage detection, port identifier matching in the mapping table, and efficient parsing of control instructions, which together constitute the core logic of display state control in the server backplane design. Through this mechanism, not only the visual management of the hardware state is enhanced, but also the operation and maintenance efficiency and user experience are improved.

[0072] Through the description of the above embodiments, those skilled in the art can clearly understand that the method according to the above embodiments can be implemented by means of software plus a necessary general hardware platform. Of course, it can also be implemented by hardware, but in many cases the former is a better implementation method.

[0073] Obviously, the above-described embodiments are only a part of the embodiments of the present invention, rather than all of the embodiments. In order to better understand the above method, the following will describe the above process in conjunction with embodiments, but it is not used to limit the technical solutions of the embodiments of the present invention. Specifically:

[0074] This application is committed to overcoming the key problems existing in the prior art, aiming to optimize and upgrade the target device by innovatively introducing voltage signals. In the traditional design, 4-bit data bits are required to achieve address differentiation, and 4-bit data bits correspond to 4 pins, which exposes serious limitations when facing the continuous growth of the number of ports.

[0075] This application proposes that only by setting 1 address pin, it can replace the original combination of 4-bit data pins. Specifically, in this application, the CPLD on the backplane will have the ability to detect the voltage value of this specific pin. By accurately detecting the voltage change of this pin, the CPLD can not only efficiently identify the upstream source, clarify whether the signal actually originates from the motherboard (specifically, it can refer to the CPU (Central Processing Unit) on the motherboard) or the switch, but also accurately establish the mapping relationship with the PCIe port of the CPU. Based on this, an intelligent adaptive function will be realized, which can automatically adjust the working mode and parameter configuration according to different hardware connection situations and actual application requirements, greatly improving the flexibility, versatility and scalability of the system, and effectively breaking through the bottleneck of the prior art in address differentiation and hardware resource utilization.

[0076] First of all, from an architectural perspective, this application has adjusted the motherboard side, the backplane side and the switch. Refer to Figure 3 As shown, it is a schematic diagram of the topological structure when the motherboard is connected to the backplane. Figure 3It is divided into a main board (MB) and a backplane - 101 (BP). The MB includes: BMC, CPU, and MCIO (Mini Cool Edge Input / Output Connector), that is, components such as connectors. The pins of the MCIO, such as the X pin, are connected to a voltage - dividing circuit, and the voltage - dividing circuit is composed of R1 and R2.

[0077] Among them, the CPU can be connected to the MCIO through VPP_SCL (clock signal line) and VPP_SDA (clock data line). The MCIO can include the MCIO on the main board side, that is, Figure 3 the connector (on the main board side) in Figure 3 and the MCIO on the backplane side, that is,

[0078] Specifically, in Figure 3 R1 can be pulled up to the 3v3 power supply, and at the same time, R2 is grounded. By default, R2 is set to 1000kΩ, that is, 1MΩ. By precisely setting the resistance values of R1 and R2, different voltage outputs are achieved using the voltage - dividing principle. It is worth emphasizing that both R1 and R2 are selected as resistors with a high precision of 1%, so as to ensure the accuracy and stability of the voltage - dividing result, provide a reliable basis for subsequent information identification by detecting the pin voltage, and greatly improve the performance and reliability of the server device.

[0079] On the backplane side, by connecting to the CPLD through the connector (on the backplane side), the stability and compatibility of data transmission are ensured. At the same time, for the key first voltage signal, it is connected to the ADC (analog - to - digital conversion) pin of the CPLD to achieve precise detection and analysis of the first voltage signal. In the backplane circuit design, the first voltage signal is pulled up to the 3v3 power supply through a 500kΩ resistor R3 with a precision of 1%. The selection of this high - precision resistor effectively ensures the stability and accuracy of the voltage value of the first voltage signal, laying a solid foundation for subsequent information identification by the CPLD based on voltage detection.

[0080] Based on Figure 3The constructed topology exhibits a differentiated and efficient operating logic as follows: 1) In the case of the upstream connection to the motherboard, the settings of R1 and R2 on the motherboard follow specific design rules. According to the principle of parallel resistance voltage division, when the value of R1 is 30 kΩ, the theoretical value of the actual signal level is calculated to be 3.21 V. Considering a 1% accuracy error in the resistance, the level range of the actual voltage signal is between 3.18 V and 3.16 V. In this case, once the CPLD detects a voltage value within this range, it can accurately determine that the upstream port (i.e., the motherboard port) is PE0A / PE0B. Similarly, when R1 is set to 60 kΩ, the theoretical value of the signal level of the actual voltage signal is 3.24 V, and after considering the accuracy error, its signal level range is 3.10 V to 3.16 V. At this time, when the CPLD detects a voltage value within this range, it can be determined that the upstream port is PE0C / PE0D. When R1 is set to 400 kΩ, the theoretical value of the signal level of the actual voltage signal is 2.7 V, and after considering the accuracy error, its signal level range is 2.67 V to 2.73 V. At this time, when the CPLD detects a voltage value within this range, it can be determined that the upstream port is PE4A / PE4B. And so on, the CPLD can accurately distinguish the corresponding upstream port based on the detected different voltage values.

[0081] When the CPLD recognizes that the upstream connection is to the motherboard, the operating system (OS) level can issue a lighting instruction (i.e., Figure 3 Instruction 1, Instruction 2... Instruction 4, etc. in 2 ), common instructions such as ledctrl (a command-line tool for managing and controlling LED lights, often used to control various indicators of server devices) or setpci (a command-line tool for querying and configuring). At this time, the basic input / output system (BIOS) and the in-band mechanism will quickly recognize the instruction and send the lighting instruction to the 9555 address of the corresponding CPU port (the backplane CPLD simulates the 9555 function) through the I

[0082] Reference Figure 4 As shown, it is a schematic diagram of the connection structure between the motherboard end and the backplane end under the existing design architecture. Figure 4 The difference from Figure 3 is that Figure 4In the interface design between the backplane and the main board, that is, MCIO (MB Side), 4 address bits are set. On the main board side, by setting different pull-up or pull-down resistors for these 4 address bits (usually the pull-down is set to 100 ohms and the pull-up is set to 1k ohms), different high and low level combinations can be generated. In this way, different addresses can be used to establish a binding mapping relationship with the CPU port. When it is necessary to perform a lighting operation on a certain hard disk, a lighting instruction will be sent by the operating system (OS). This instruction will be sent to the backplane along the physical link, that is, the VPP link. After receiving the lighting instruction, the backplane will identify the upstream lighting requirement based on the I 2 C address in the VPP bus and finally light up the indicator light of the corresponding disk position.

[0083] For the case where the upstream connection is a switch (i.e., PCIe SW), Figure 5 The figure shows a topological schematic diagram of the upstream connection to PCIe SW. Refer to Figure 5 As shown, the lighting control function is implemented through a bus (i.e., the I 2 C bus). Its physical link is connected from the switch (PCIESW) to the connector (main board side), and the connected pins are the same as those used by the main board, so as to ensure that when different boards are connected, the lighting control signal can be accurately transmitted, maintaining the signal transmission consistency and compatibility of the overall system. In the switch board design, a second voltage signal is innovatively added. The second voltage signal is connected to GND through a resistor R4 on the switch board. In the backplane circuit design, the second voltage signal is pulled up to the 3v3 power supply through a 500kΩ resistor R5 with an accuracy of 1%. The selection of this high-precision resistor effectively ensures the stability and accuracy of the voltage value of the second voltage signal, laying a solid foundation for the subsequent CPLD to identify information based on voltage detection. Significantly different from the main board, the resistor R4 on the switch board is fixedly set to 0Ω, and then this pin is connected to the MCIO connector (main board side), and the connected pins are the same as those taken over by the main board. Through this unique design, the switch board can work in coordination with the main board in voltage signal processing while meeting its own specific functional requirements, greatly improving flexibility and adaptability. The main board will design an I 2 C circuit for switch board management. The I 2 C is connected from the BMC to the switch chip on the switch board. Among them, the BMC can obtain the switch model through the I 2 C.

[0084] When the uplink connection is a switch board, since the voltage signal of the switch board is directly connected to the ground through R4=0Ω, the signal level is pulled down to 0V. Therefore, when the CPLD of the backplane-101 detects that the signal level is 0V, it can quickly and accurately identify that the uplink connection is a switch board. In this connection situation, the OS issues a light-on command. After the switch recognizes the light-on command, it will further send the light-on data to the backplane CPLD through the bus. It should be noted that there are certain differences in the light-on data formats used by different PCIE SWs. For this reason, the baseboard management controller (BMC) will send a light-on command to the backplane CPLD through I 2 C obtains and identifies the PCIE SW model information, and then passes the information to the CPLD. Based on this, the CPLD can effectively parse different PCIE SW lighting data frames and finally realize the lighting control of the hard disk.

[0085] Furthermore, during operation, the present application has also constructed a complete and sensitive detection and feedback mechanism for abnormal conditions that may occur, such as uplink disconnection or poor contact. When the uplink is not connected, or the contact is poor due to line aging, connection process defects, etc., the uplink voltage signal will be disconnected. At this time, the backplane complex programmable logic device (CPLD) detects a signal level of 3.3V based on its precise signal detection capability. Once the backplane CPLD detects this abnormal signal level, it will quickly start the fault feedback process. With the help of I 2 C communication link, using efficient and stable communication protocol to send fault alarm information to the baseboard management controller (BMC). After receiving the alarm information, BMC can immediately accurately locate and record the fault, and take corresponding measures according to the pre-set fault handling strategy, such as triggering system alarms and generating detailed fault logs, so that operation and maintenance personnel can timely and accurately troubleshoot and repair the fault, minimize the impact of abnormal uplink connection on system operation, and effectively ensure the stability and reliability of the entire server system.

[0086] refer to Figure 6 As shown, Figure 6 It is a topological diagram of the upstream connection to PCIe SW in the related art. Figure 6As can be seen, the backplane adopted is BP-102. Usually, it is difficult for a single backplane to support both the upstream connection to the CPU and the upstream connection to the PCIe SW simultaneously. Therefore, for different upstream connection scenarios (such as connecting to the CPU or PCIe SW), it is necessary to develop and maintain multiple different versions of CPLD firmware corresponding to different board part numbers. This process not only consumes a large amount of human, material, and time costs, but also causes a great waste of management resources. More critically, this way of controlling firmware relying on multiple board part numbers makes it difficult to flexibly switch configurations in actual system use. When it is necessary to switch between different upstream connection modes due to changes in business requirements, it cannot be completed conveniently and efficiently, seriously restricting the flexibility and adaptability of the system and making it difficult to meet the needs of diverse and dynamically changing application scenarios. This limitation greatly restricts the versatility and flexibility of the backplane in actual application scenarios, unable to meet the diverse system configuration requirements, and urgently needs to be solved through innovative technical means.

[0087] It can be seen from this that in this application, by reducing the original 4-bit address pins to 1 ADC detection pin, 75% of the hardware interface resources are saved. By using a high-precision voltage division circuit (1% precision resistor) in combination with the ADC detection function of the CPLD, accurate identification of the upstream source (CPU or PCIe SW) is achieved. In this application, the same backplane firmware can be adapted to different hardware topologies, eliminating the current need to develop multiple versions of firmware, and the production material control efficiency is increased by more than 80%.

[0088] In this embodiment, a signal recognition device is also provided to implement the above embodiments and preferred implementation manners, and those that have been described will not be repeated. As used hereinafter, the term "module" can be a combination of software and / or hardware that can achieve a predetermined function. Although the modules described in the following embodiments are preferably implemented in software, implementation in hardware, or a combination of software and hardware is also possible and contemplated.

[0089] Figure 7 is a structural block diagram of a signal recognition device according to an embodiment of the present application. The device includes:

[0090] A receiving module 702, configured to receive a voltage signal, where the voltage signal includes: a first voltage signal or a second voltage signal; the first voltage signal is a signal output through a pin of a first connector after the voltage value of the main board signal sent by the main board port of the main board is converted by a voltage division circuit; the second voltage signal is a signal output through a pin of a second connector after the voltage value of the switch signal sent by the switch is converted by a grounding resistor;

[0091] An identification module 704, configured to determine the voltage value of the voltage signal and identify the signal source of the voltage signal according to the voltage value.

[0092] Through the above device, it is applied to the backplane in the target device. The backplane is connected to the main board through the first connector; the backplane is connected to the switch through the second connector; the first connector is connected to the voltage dividing circuit; the second connector is connected to the grounding resistor. Furthermore, it can receive the signal output through the pin of the first connector after the voltage value conversion of the main board signal sent by the main board port of the main board by the voltage dividing circuit, or receive the second voltage signal output through the pin of the second connector after the voltage value conversion of the switch signal sent by the switch by the grounding resistor. Since the voltage value of the voltage signal, that is, the first voltage signal or the second voltage signal, can be determined based on the received voltage signal, the source of the voltage signal can be identified according to the voltage value. Since the voltage value has a wider recognizable range relative to the address bit and has higher flexibility, more main board ports and switches can be distinguished, and the technical problem of the limited scalability of the current target device can be solved, achieving the technical effects of increasing the flexibility and scalability of the target device and improving the performance of the target device.

[0093] In an exemplary embodiment, the identification module 704 is further configured to obtain a pre-constructed port mapping table, where the port mapping table at least includes: a plurality of voltage ranges and a target voltage value; the voltage values included in the plurality of voltage ranges do not include the target voltage value; match the voltage value with the plurality of voltage ranges and the target voltage value respectively to obtain a matching result; and identify the signal source of the voltage signal based on the matching result.

[0094] In an exemplary embodiment, the identification module 704 is further configured to, when the matching result is that the voltage value is in any one of the plurality of voltage ranges, identify the signal source of the voltage signal as the main board port of the main board; and when the matching result is that the voltage value is the target voltage value, identify the signal source of the voltage signal as the switch.

[0095] In an exemplary embodiment, the device further includes a construction module; the construction module is configured to, for any main board port of the main board, determine the port voltage value matching the any main board port and the switch voltage value matching the switch; perform error processing on the port voltage value of the any main board port according to a preset error value, and determine the first voltage range of the any main board port based on the port voltage value after the error processing; construct a first mapping relationship based on the first voltage range of the any main board port and the port identifier of the any main board port, and construct a second mapping relationship based on the switch voltage value of the switch and the switch identifier of the switch, where the port mapping table corresponding to the backplane includes the first mapping relationship and the second mapping relationship.

[0096] In an exemplary embodiment, the building block is further configured to determine a pull-up resistor value and a pull-down resistor value corresponding to any main board port from a preset resistance value range, where the pull-up resistor values of each main board port are different, the pull-down resistor values of each main board port are different, or both the pull-up resistor values and the pull-down resistor values of each main board port are different; determine the sum of the resistance values of the pull-up resistor value and the pull-down resistor value, and determine a resistance quotient based on the sum of the resistance values and the pull-down resistor value; and determine the product of the power supply voltage of the main board and the resistance quotient as the port voltage value matching any main board port.

[0097] In an exemplary embodiment, the apparatus further includes a control module, configured to, when the signal source of the voltage signal is a main board port of the main board, determine a first control instruction sent by the main board port of the main board based on a port identifier corresponding to the main board port in a port mapping table, and parse the first control instruction according to an instruction parsing format matching the port identifier to obtain a first parsing result; and control the display state of a display device according to the first parsing result, where different display states of the display device are used to indicate the state of a first hardware device connected to the main board, the port mapping table includes a first mapping relationship, and the first mapping relationship is constructed by a first voltage range of any main board port and the port identifier of any main board port.

[0098] In an exemplary embodiment, the control module is further configured to, when the signal source of the voltage signal is the switch, determine a second control instruction sent by the switch based on a switch identifier corresponding to the switch in the port mapping table, and parse the second control instruction according to an instruction parsing format matching the switch identifier to obtain a second parsing result; and control the display state of the display device according to the second parsing result, where different display states of the display device are used to indicate the state of a second hardware device connected to the switch, the port mapping table includes a second mapping relationship, and the second mapping relationship is constructed by the switch voltage value of the switch and the switch identifier of the switch.

[0099] An embodiment of the present application further provides an electronic device, including a memory and a processor, where a computer program is stored in the memory, and the processor is configured to run the computer program to execute the steps in any of the above signal recognition method embodiments.

[0100] An embodiment of the present application further provides a computer-readable storage medium, where a computer program is stored in the computer-readable storage medium, and the computer program is configured to execute the steps in any of the above signal recognition method embodiments when running.

[0101] In an exemplary embodiment, the above computer-readable storage medium may include, but is not limited to: various media such as USB flash drives, read-only memory (ROM for short), random access memory (RAM for short), external hard drives, magnetic disks, or optical discs that can store computer programs.

[0102] The embodiments of the present application also provide a computer program product. The above computer program product includes a computer program, and when the computer program is executed by a processor, the steps in any of the above signal recognition method embodiments are implemented.

[0103] The embodiments of the present application also provide another computer program product, including a non-volatile computer-readable storage medium. The non-volatile computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the steps in any of the above signal recognition method embodiments are implemented.

[0104] Those skilled in the art can further realize that the units and algorithm steps of each example described in combination with the embodiments disclosed herein can be implemented by electronic hardware, computer software, or a combination of the two. To clearly illustrate the interchangeability of hardware and software, the composition and steps of each example have been generally described according to functions in the above description. Whether these functions are executed in a hardware or software manner depends on the specific application and design constraints of the technical solution. Skilled professionals can use different methods to implement the described functions for each specific application, but such implementation should not be considered to exceed the scope of the present application.

[0105] The above has introduced in detail a signal recognition method provided by the present application. Specific examples are used herein to elaborate on the principle and implementation manner of the present application. The description of the above embodiments is only used to help understand the method and its core idea of the present application. It should be noted that for those of ordinary skill in the art, without departing from the principle of the present application, several improvements and modifications can be made to the present application, and these improvements and modifications also fall within the protection scope of the claims of the present application.

Claims

1. A signal recognition method, characterized in that, Applied to the backplane in the target device, the backplane is connected to the main board through the first connector; The backplane is connected to the switch through the second connector; The first connector is connected to the voltage dividing circuit; The second connector is connected to the grounding resistor, and the method includes: Receiving a voltage signal, where the voltage signal includes: a first voltage signal or a second voltage signal; the first voltage signal is a signal output through the pin of the first connector after the voltage dividing circuit converts the voltage value of the main board signal sent by the main board port of the main board; the second voltage signal is a signal output through the pin of the second connector after the grounding resistor converts the voltage value of the switch signal sent by the switch; Determining the voltage value of the voltage signal and identifying the signal source of the voltage signal according to the voltage value.

2. The signal recognition method according to claim 1, characterized in that The identifying the signal source of the voltage signal according to the voltage value includes: Obtaining a pre-constructed port mapping table, where the port mapping table at least includes: a plurality of voltage ranges and a target voltage value; the voltage values included in the plurality of voltage ranges do not include the target voltage value; Matching the voltage value with the plurality of voltage ranges and the target voltage value respectively to obtain a matching result; Identifying the signal source of the voltage signal based on the matching result.

3. The signal recognition method according to claim 2, characterized in that The identifying the signal source of the voltage signal based on the matching result includes: In the case where the matching result is that the voltage value is in any one of the plurality of voltage ranges, identifying the signal source of the voltage signal as the main board port of the main board; In the case where the matching result is that the voltage value is the target voltage value, identifying the signal source of the voltage signal as the switch.

4. The signal recognition method according to claim 1, wherein Before identifying the signal source of the voltage signal according to the voltage value, the method further includes: For any main board port of the main board, determining the port voltage value matching the any main board port and determining the switch voltage value matching the switch; Performing error processing on the port voltage value of the any main board port according to a preset error value, and determining the first voltage range of the any main board port based on the port voltage value after the error processing; Constructing a first mapping relationship based on the first voltage range of the any main board port and the port identifier of the any main board port, and constructing a second mapping relationship based on the switch voltage value of the switch and the switch identifier of the switch, where the port mapping table corresponding to the backplane includes the first mapping relationship and the second mapping relationship.

5. The signal recognition method according to claim 4, characterized in that, The determining the port voltage value matching the any main board port includes: Determining the pull-up resistor value and the pull-down resistor value corresponding to the any main board port from a preset resistance value range, where the pull-up resistor values of each main board port are different, the pull-down resistor values of each main board port are different, or the pull-up resistor values and the pull-down resistor values of each main board port are all different; Determining the sum of the resistance values of the pull-up resistor value and the pull-down resistor value, and determining the resistance quotient based on the sum of the resistance values and the pull-down resistor value; Determine the product of the power supply voltage of the main board and the quotient of the resistance values as the port voltage value matching any main board port.

6. The signal recognition method according to claim 1, characterized in that, After identifying the signal source of the voltage signal according to the voltage value, the method further includes: When the signal source of the voltage signal is the main board port of the main board, based on the port identifier corresponding to the main board port in the port mapping table, determine the first control instruction sent by the main board port of the main board, and parse the first control instruction according to the instruction parsing format matching the port identifier to obtain a first parsing result; Control the display state of the display device according to the first parsing result, wherein different display states of the display device are used to indicate the state of the first hardware device connected to the main board, the port mapping table includes a first mapping relationship, and the first mapping relationship is constructed by the first voltage range of any main board port and the port identifier of any main board port.

7. The signal recognition method according to claim 1, wherein After identifying the signal source of the voltage signal according to the voltage value, the method further includes: When the signal source of the voltage signal is the switch, based on the switch identifier corresponding to the switch in the port mapping table, determine the second control instruction sent by the switch, and parse the second control instruction according to the instruction parsing format matching the switch identifier to obtain a second parsing result; Control the display state of the display device according to the second parsing result, wherein different display states of the display device are used to indicate the state of the second hardware device connected to the switch, the port mapping table includes a second mapping relationship, and the second mapping relationship is constructed by the switch voltage value of the switch and the switch identifier of the switch.

8. A signal recognition device, characterized in that, Includes: A receiving module, configured to receive a voltage signal, wherein the voltage signal includes: a first voltage signal, or a second voltage signal; the first voltage signal is a signal output through the pin of the first connector after the voltage value of the main board signal sent by the main board port of the main board is converted by a voltage dividing circuit; the second voltage signal is a signal output through the pin of the second connector after the voltage value of the switch signal sent by the switch is converted by a grounding resistor; An identifying module, configured to determine the voltage value of the voltage signal and identify the signal source of the voltage signal according to the voltage value.

9. An electronic device, characterized in that, Includes: A memory, configured to store a computer program; A processor, configured to implement the steps of the signal identification method according to any one of claims 1 to 7 when executing the computer program.

10. A computer-readable storage medium, characterized in that, A computer program is stored in the computer-readable storage medium, wherein the computer program implements the steps of the signal identification method according to any one of claims 1 to 7 when executed by a processor.

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