Circuit, method, device and system for measuring chip pin voltage

Abstract

The invention relates to the technical field of chip testing, and discloses a circuit, method, device and system for measuring the voltage of a chip pin, and the circuit comprises a relay circuit which can be in a first state or a second state through a control signal; when the relay circuit is in the first state, the chip pin is directly connected with the ATE test channel through the relay circuit; the voltage division circuit is provided with a test end, a sampling end and a reference end; and when the relay circuit is in the second state, the test end is connected with the chip pin through the relay circuit, the sampling end is connected with the ATE test channel through the relay circuit, and the reference end is connected with the reference voltage. And when the relay circuit is in the second state, the voltage of the sampling end can be adjusted to a measurable range of the ATE test channel through the voltage division circuit and the reference voltage, so that the high voltage and the negative voltage exceeding the measuring range at the chip pin can be obtained through calculation.

Description

Technical Field

[0001] This application relates to the field of chip testing technology, and for example to a circuit, method, apparatus and system for measuring chip pin voltage. Background Technology

[0002] Currently, for some chips with special functions, the output voltage of the chip pins may be negative or high, which may exceed the normal test range of ATE (Automated Test Equipment). Therefore, the test scheme of ATE needs to be improved to increase the measurement range of ATE voltage.

[0003] In related technologies, the measurement range of ATE voltage is increased by adding a high-voltage board.

[0004] In the process of implementing the embodiments of this disclosure, at least the following problems were found in the related art:

[0005] Using a high-voltage board only increases the measurement range to a limited extent; it still cannot achieve the measurement of negative voltages or higher voltages.

[0006] It should be noted that the information disclosed in the background section above is only used to enhance the understanding of the background of this application, and therefore may include information that does not constitute prior art known to those skilled in the art. Summary of the Invention

[0007] To provide a basic understanding of some aspects of the disclosed embodiments, a brief summary is given below. This summary is not intended as a general commentary, nor is it intended to identify key / important components or describe the scope of protection of these embodiments, but rather as a prelude to the detailed description that follows.

[0008] This disclosure provides a circuit, method, apparatus, and system for measuring chip pin voltages, to measure negative or higher voltages at chip pins.

[0009] In some embodiments, the circuit for measuring the voltage of a chip pin includes: a relay circuit, which can be controlled by a control signal to be in a first state or a second state; when the relay circuit is in the first state, the chip pin is directly connected to the ATE test channel through the relay circuit; a voltage divider circuit, which is provided with a test terminal, a sampling terminal and a reference terminal; when the relay circuit is in the second state, the test terminal is connected to the chip pin through the relay circuit, the sampling terminal is connected to the ATE test channel through the relay circuit, and the reference terminal is connected to a reference voltage.

[0010] Optionally, the ATE test channel is equipped with a clamping voltage; when the voltage at the chip pin is positive and less than or equal to the clamping voltage, the ATE sends a first control signal to put the relay circuit in a first state; when the voltage at the chip pin is negative or greater than the clamping voltage, the ATE sends a second control signal to put the relay circuit in a second state.

[0011] Optionally, the relay circuit includes a first relay and a second relay. When the relay circuit is in a first state, the first contact pair of the first relay is closed, and the second contact pair of the second relay is also closed. Specifically, one contact in the first contact pair is connected to a chip pin, the other contact in the first contact pair is connected to one contact in the second contact pair, and the other contact in the second contact pair is connected to the ATE test channel. When the relay circuit is in a second state, the third contact pair of the first relay is closed, and the fourth contact pair of the second relay is also closed. Specifically, one contact in the third contact pair is connected to a chip pin, the other contact in the third contact pair is connected to the test terminal of the voltage divider circuit, one contact in the fourth contact pair is connected to the sampling terminal of the voltage divider circuit, and the other contact in the fourth contact pair is connected to the ATE test channel.

[0012] Optionally, the voltage divider circuit includes a first resistor and a second resistor; one end of the first resistor serves as the test terminal of the voltage divider circuit; the other end of the first resistor is connected to one end of the second resistor as the sampling terminal of the voltage divider circuit; and the other end of the second resistor serves as the reference terminal of the voltage divider circuit.

[0013] Optionally, the resistance of the first resistor is greater than the resistance of the second resistor.

[0014] In some embodiments, the method for measuring chip pin voltage is applied to a circuit for measuring chip pin voltage as described above, the method comprising: when the relay circuit is in a first state, controlling the relay circuit to continue in the first state or change to a second state based on the voltage at the chip pin and the clamping voltage of the ATE test channel; when the relay circuit is in the first state, using the voltage measured by the ATE test channel as the voltage at the chip pin; and when the relay circuit is in the second state, calculating the voltage at the chip pin based on the voltage measured by the ATE test channel.

[0015] Optionally, the relay circuit is controlled to remain in the first state or change to the second state based on the voltage at the chip pin and the clamping voltage of the ATE test channel, including: when the voltage at the chip pin is positive and less than or equal to the clamping voltage, the relay circuit is controlled to remain in the first state; when the voltage at the chip pin is negative or greater than the clamping voltage, the relay circuit is controlled to change to the second state.

[0016] Alternatively, when the relay circuit is in the second state, the voltage at the chip pin is calculated according to the following formula:

[0017]

[0018] Where Vs is the voltage at the chip pin, Vg is the voltage measured by the ATE test channel, Vref is the reference voltage, r1 is the resistance value of the first resistor, and r2 is the resistance value of the second resistor.

[0019] In some embodiments, the apparatus for measuring chip pin voltage includes a processor and a memory storing program instructions, the processor being configured to perform the method for measuring chip pin voltage as described above when the program instructions are executed.

[0020] In some embodiments, a system for measuring chip pin voltages includes: an ATE device equipped with the means for measuring chip pin voltages as described above; and a chip under test (DUT), the chip pins of which are connected to the ATE test channel of the ATE device via the circuit for measuring chip pin voltages as described above.

[0021] The circuits, methods, apparatus, and systems for measuring chip pin voltages provided in this disclosure can achieve the following technical effects:

[0022] In this embodiment, the ATE test channel and chip pins can flexibly switch between direct measurement and voltage divider measurement through the state switching of the relay circuit. When the voltage at the chip pin is within the range of the ATE test channel, the relay circuit is in the first state, and the chip pin is directly connected to the ATE test channel, achieving high-precision direct measurement. When the voltage at the chip pin exceeds the range of the ATE test channel, the relay circuit switches to the second state, and measurement is performed through the voltage divider circuit, thereby expanding the measurement range. By reasonably designing the voltage divider circuit and the reference voltage, the voltage at the sampling end can be adjusted to the measurable range of the ATE test channel, thereby enabling the calculation of high voltages and negative voltages at the chip pins that exceed the range of the ATE test channel.

[0023] The above general description and the description below are exemplary and illustrative only and are not intended to limit this application. Attached Figure Description

[0024] One or more embodiments are illustrated by way of example with reference to the accompanying drawings. These illustrations and drawings do not constitute a limitation on the embodiments. Elements having the same reference numerals in the drawings are shown as similar elements. The drawings are not to be scaled. And wherein:

[0025] Figure 1This is a schematic diagram of a circuit for measuring chip pin voltage provided in an embodiment of this disclosure;

[0026] Figure 2 This is a circuit diagram of a circuit for measuring the voltage of a chip pin provided in an embodiment of this disclosure;

[0027] Figure 3 This is a schematic diagram of a method for measuring chip pin voltage provided in an embodiment of this disclosure;

[0028] Figure 4 This is a schematic diagram of another method for measuring chip pin voltage provided in an embodiment of this disclosure;

[0029] Figure 5 This is a schematic diagram of a device for measuring chip pin voltage provided in an embodiment of this disclosure;

[0030] Figure 6 This is a schematic diagram of a system for measuring chip pin voltages provided in an embodiment of this disclosure. Detailed Implementation

[0031] To provide a more detailed understanding of the features and technical content of the embodiments of this disclosure, the implementation of the embodiments of this disclosure will be described in detail below with reference to the accompanying drawings. The accompanying drawings are for illustrative purposes only and are not intended to limit the embodiments of this disclosure. In the following technical description, for ease of explanation, several details are used to provide a full understanding of the disclosed embodiments. However, one or more embodiments may still be implemented without these details. In other cases, well-known structures and devices may be simplified in their depiction to simplify the drawings.

[0032] The terms "first," "second," etc., used in the technical solutions described in this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate for the embodiments of this disclosure described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion.

[0033] Unless otherwise stated, the term "multiple" means two or more.

[0034] In this embodiment of the disclosure, the character " / " indicates that the objects before and after it are in an "or" relationship. For example, A / B means: A or B.

[0035] The term "and / or" describes an association between objects, indicating that three relationships can exist. For example, A and / or B means: A or B, or A and B.

[0036] The term "correspondence" can refer to an association or binding relationship. The correspondence between A and B means that there is an association or binding relationship between A and B.

[0037] Combination Figure 1 As shown, this embodiment of the present disclosure provides a circuit 100 for measuring the voltage of a chip pin, including a relay circuit 101 and a voltage divider circuit 102. The relay circuit 101 can be in a first state or a second state via a control signal. When the relay circuit 101 is in the first state, the chip pin 103 is directly connected to the ATE test channel 104 through the relay circuit 101. The voltage divider circuit 102 is provided with a test terminal B, a sampling terminal C, and a reference terminal D. When the relay circuit 101 is in the second state, the test terminal B is connected to the chip pin 103 through the relay circuit 101, the sampling terminal C is connected to the ATE test channel 104 through the relay circuit 101, and the reference terminal D is connected to a reference voltage.

[0038] In this embodiment, the ATE test channel 104 and chip pin 103 can flexibly switch between direct measurement and voltage divider measurement through the state switching of the relay circuit 101. When the voltage of chip pin 103 is within the range of the ATE test channel 104, the relay circuit 101 is in the first state, and chip pin 103 is directly connected to the ATE test channel 104, achieving high-precision direct measurement. When the voltage of chip pin 103 exceeds the range of the ATE test channel 104, the relay circuit 101 switches to the second state, and measurement is performed through the voltage divider circuit 102, thereby expanding the measurement range. By reasonably designing the voltage divider circuit 102 and the reference voltage, the voltage of the sampling terminal C can be adjusted to the measurable range of the ATE test channel 104, thereby enabling the calculation of high voltages and negative voltages at chip pin 103 that exceed the range of the ATE test channel 104.

[0039] Optionally, ATE test channel 104 is equipped with a clamping voltage.

[0040] Optionally, when the voltage at chip pin 103 is a positive voltage and less than or equal to the clamping voltage, ATE sends a first control signal to put the relay circuit 101 into a first state; when the voltage at chip pin 103 is a negative voltage or greater than the clamping voltage, ATE sends a second control signal to put the relay circuit 101 into a second state.

[0041] In this embodiment, the clamping voltage set by the ATE test channel 104 can automatically send a control signal based on the voltage level at the chip pin 103, causing the relay circuit 101 to switch to the corresponding state. This improves the automation level of the measurement process and reduces human intervention and time costs. Furthermore, setting the clamping voltage effectively protects the ATE test channel 104, preventing damage to the equipment due to excessive voltage. The presence of the clamping voltage also makes the measurement process more stable and reliable.

[0042] Optionally, the relay circuit 101 includes a first relay S1 and a second relay S2. When the relay circuit 101 is in the first state, the first contact pair of the first relay S1 is closed, and the second contact pair of the second relay S2 is also closed. One contact in the first contact pair is connected to a chip pin 103, the other contact in the first contact pair is connected to one contact in the second contact pair, and the other contact in the second contact pair is connected to the ATE test channel 104. When the relay circuit 101 is in the second state, the third contact pair of the first relay S1 is closed, and the fourth contact pair of the second relay S2 is also closed. One contact in the third contact pair is connected to a chip pin 103, the other contact in the third contact pair is connected to the test terminal B of the voltage divider circuit 102, one contact in the fourth contact pair is connected to the sampling terminal C of the voltage divider circuit 102, and the other contact in the fourth contact pair is connected to the ATE test channel 104.

[0043] In this embodiment, by setting two relays and their contact pairs, the connection between chip pin 103 and ATE test channel 104 can be precisely controlled. In the first state, by closing the first contact pair of the first relay S1 and the second contact pair of the second relay S2, it is ensured that chip pin 103 can be directly connected to ATE test channel 104, thereby enabling high-precision measurement of the voltage of chip pin 103, suitable for voltage values ​​within the range of ATE test channel 104. In the second state, by closing the third contact pair of the first relay S1 and the fourth contact pair of the second relay S2, chip pin 103 is connected to the test terminal B of voltage divider circuit 102, and the sampling terminal C of voltage divider circuit 102 is connected to ATE test channel 104, thereby enabling the handling of voltages exceeding the range of ATE test channel 104. Whether it is high voltage or negative voltage, it can be safely and accurately measured through voltage divider circuit 102.

[0044] Optionally, the voltage divider circuit 102 includes a first resistor R1 and a second resistor R2; one end of the first resistor R1 serves as the test terminal B of the voltage divider circuit 102; the other end of the first resistor R1 is connected to one end of the second resistor R2 and serves as the sampling terminal C of the voltage divider circuit 102; the other end of the second resistor R2 serves as the reference terminal D of the voltage divider circuit 102.

[0045] In this embodiment, the voltage divider circuit 102 utilizes the voltage divider principle of resistors to divide high or negative voltages into the measurable range of the ATE test channel 104, thereby expanding the measurement range. By reasonably selecting the resistance ratio of the first resistor R1 and the second resistor R2, different measurement requirements can be flexibly adapted to, and the actual voltage of the chip pin 103 can be accurately calculated, ensuring the accuracy of the measurement results.

[0046] Optionally, the resistance of the first resistor R1 is greater than the resistance of the second resistor R2.

[0047] In this embodiment, the resistance of the first resistor R1 is greater than that of the second resistor R2, which allows the first resistor R1 to share more voltage, thereby further expanding the measurement range of the ATE test channel 104.

[0048] Optionally, the reference voltage can be provided by the ATE or by a separately designed external circuit.

[0049] Based on the aforementioned circuit for measuring chip pin voltages, combined with Figure 3 As shown, this disclosure provides a method for measuring the voltage of a chip pin. The execution entity of this method can be a processor in an ATE (Automatic Test Equipment). The method includes:

[0050] S301, when the relay circuit is in the first state, the processor controls the relay circuit to continue in the first state or change to the second state based on the voltage at the chip pin and the clamping voltage of the ATE test channel.

[0051] S302, when the relay circuit is in the first state, the processor uses the voltage measured by the ATE test channel as the voltage at the chip pin.

[0052] S303: When the relay circuit is in the second state, the processor calculates the voltage at the chip pin based on the voltage measured by the ATE test channel.

[0053] In this embodiment, the state of the relay circuit is dynamically adjusted based on the voltage at the chip pin and the clamping voltage of the ATE test channel, ensuring that the measurement process is always in the optimal measurement mode and improving measurement efficiency. When the relay circuit is in the first state, the ATE test channel directly measures the voltage at the chip pin, providing high-precision measurement results. When the relay circuit is in the second state, measurement is performed through a voltage divider circuit. Based on the voltage measured by the ATE test channel and the parameter settings of the voltage divider circuit, the actual voltage at the chip pin can be accurately calculated. The voltage divider circuit can measure high and negative voltages beyond the range of the ATE test channel, thus adapting to various chip testing scenarios and enhancing its versatility and flexibility in practical applications.

[0054] Optionally, the relay circuit is controlled to remain in the first state or change to the second state based on the voltage at the chip pin and the clamping voltage of the ATE test channel, including: when the voltage at the chip pin is positive and less than or equal to the clamping voltage, the relay circuit is controlled to remain in the first state; when the voltage at the chip pin is negative or greater than the clamping voltage, the relay circuit is controlled to change to the second state.

[0055] Combination Figure 4 As shown, this disclosure provides another method for measuring chip pin voltages, including:

[0056] S401, with the relay circuit in the first state, the processor compares the voltage at the chip pin with the clamping voltage of the ATE test channel.

[0057] S402, when the voltage at the chip pin is positive and less than or equal to the clamping voltage, the control relay circuit continues to be in the first state.

[0058] S403: When the relay circuit is in the first state, the processor uses the voltage measured by the ATE test channel as the voltage at the chip pin.

[0059] S404: When the voltage at the chip pin is negative or greater than the clamping voltage, the processor controls the relay circuit to change to the second state.

[0060] S405: When the relay circuit is in the second state, the processor calculates the voltage at the chip pin based on the voltage measured by the ATE test channel.

[0061] In this embodiment, by setting the clamping voltage and switching the state of the relay circuit, not only is accurate voltage measurement achieved, but the ATE test channel is also effectively protected from damage by excessive voltage. In the second state, the high or negative voltage is reduced to a safe range by the voltage divider circuit before measurement, thereby effectively protecting the ATE test channel and ensuring the safety of the measurement process. Furthermore, the voltage divider circuit design eliminates the need for high-voltage boards, thus reducing testing and maintenance costs.

[0062] Alternatively, when the relay circuit is in the second state, the voltage at the chip pin is calculated according to the following formula:

[0063]

[0064] Where Vs is the voltage at the chip pin, Vg is the voltage measured by the ATE test channel, Vref is the reference voltage, r1 is the resistance value of the first resistor, and r2 is the resistance value of the second resistor.

[0065] In this embodiment, the actual voltage of the chip pins can be accurately calculated using the above formula, ensuring the accuracy of the measurement results, especially when measuring high and negative voltages. By selecting appropriate resistors, measurement errors can be further reduced, improving the reliability of the measurement.

[0066] In one specific embodiment, taking high voltage measurement as an example, assuming r1 = 10kΩ, r2 = 1kΩ, Vref = 0V, and the voltage Vg measured by the ATE test channel is 5V, Vs = 55V can be calculated using the formula. In another specific embodiment, taking negative voltage measurement as an example, assuming r1 = 10kΩ, r2 = 1kΩ, Vref = 5V, and the voltage Vg measured by the ATE test channel is 2V, Vs = -28V can be calculated using the formula. It can be seen that by using a voltage divider circuit and formula calculation, voltages up to 55V and negative voltages as low as -28V can be accurately measured.

[0067] Combination Figure 5 As shown, this disclosure provides an apparatus 500 for measuring chip pin voltages, including a processor 501 and a memory 502. Optionally, the apparatus may further include a communication interface 503 and a bus 504. The processor 501, communication interface 503, and memory 502 can communicate with each other via the bus 504. The communication interface 503 can be used for information transmission. The processor 501 can call logical instructions in the memory 502 to execute the method for measuring chip pin voltages described in the above embodiment.

[0068] Furthermore, the logic instructions in the aforementioned memory 502 can be implemented as software functional units and, when sold or used as independent products, can be stored in a computer-readable storage medium.

[0069] The memory 502, as a computer-readable storage medium, can be used to store software programs and computer-executable programs, such as program instructions / modules corresponding to the methods in the embodiments of this disclosure. The processor 501 executes functional applications and data processing by running the program instructions / modules stored in the memory 502, that is, it implements the method for measuring chip pin voltages in the above embodiments.

[0070] The memory 502 may include a program storage area and a data storage area. The program storage area may store the operating system and applications required for at least one function; the data storage area may store data created based on the use of the terminal device. Furthermore, the memory 502 may include high-speed random access memory and may also include non-volatile memory.

[0071] Combination Figure 6 As shown, this disclosure provides a system 600 for measuring chip pin voltages, including an ATE device 601 and a chip under test (DUT) 602. The ATE device 601 is equipped with the device 500 for measuring chip pin voltages as described above. The chip pins of the DUT 602 are connected to the ATE test channel of the ATE device 601 via the circuit 100 for measuring chip pin voltages as described above.

[0072] The installation relationships described herein are not limited to placement within the ATE equipment, but also include installation connections with other components of the ATE equipment, including but not limited to physical connections, electrical connections, or signal transmission connections. Those skilled in the art will understand that the device for measuring chip pin voltages can be adapted to a feasible ATE equipment body, thereby enabling other feasible embodiments.

[0073] This disclosure provides a computer-readable storage medium storing computer-executable instructions configured to perform the method described above for measuring chip pin voltages.

[0074] The technical solutions of this disclosure can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes one or more instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the method described in this disclosure. The aforementioned storage medium can be a non-transitory storage medium, including: a USB flash drive, a portable hard drive, a read-only memory (ROM), a random access memory (RAM), a magnetic disk, or an optical disk, and other media capable of storing program code.

[0075] The foregoing description and accompanying drawings fully illustrate embodiments of this disclosure to enable those skilled in the art to practice them. Other embodiments may include structural, logical, electrical, procedural, and other changes. The embodiments represent only possible variations. Individual components and functions are optional unless explicitly required, and the order of operation may vary. Parts and features of some embodiments may be included in or replace parts and features of other embodiments. Moreover, the terminology used in this application is for describing embodiments only and is not intended to limit the technical solutions described herein. As used in the technical solutions described herein, the singular forms “a,” “an,” and “the” are intended to equally include the plural forms unless the context clearly indicates otherwise. Similarly, the term “and / or” as used herein means including one or more of the associated listed items and all possible combinations thereof. Additionally, when used in this application, the term "comprise" and its variations "comprises" and / or "comprising" refer to the presence of stated features, integrals, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components, and / or groups thereof. Without further limitations, an element defined by the phrase "comprises a..." does not exclude the presence of other identical elements in the process, method, or apparatus that includes said element. In this document, each embodiment may focus on the differences from other embodiments, and similar or identical parts between embodiments can be referred to mutually. For methods, products, etc., disclosed in the embodiments, if they correspond to the method section disclosed in the embodiments, the relevant parts can be referred to the description of the method section.

[0076] Those skilled in the art will recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of the embodiments of this disclosure. Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the specific working processes of the systems, devices, and units described above can be referred to the corresponding processes in the foregoing method embodiments, and will not be repeated here.

[0077] The methods and products (including but not limited to devices and equipment) disclosed in the embodiments herein can be implemented in other ways. For example, the device embodiments described above are merely illustrative. For instance, the division of units may be merely a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. In addition, the coupling or direct coupling or communication connection between the shown or discussed units may be through some interfaces, and the indirect coupling or communication connection between devices or units may be electrical, mechanical, or other forms. The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units, that is, they may be located in one place or distributed across multiple network units. Some or all of the units may be selected to implement this embodiment according to actual needs. Furthermore, the functional units in the embodiments of this disclosure may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit.

[0078] The flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to embodiments of this disclosure. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of code containing one or more executable instructions for implementing a specified logical function. In some alternative implementations, the functions marked in the blocks may occur in a different order than that shown in the drawings. For example, two consecutive blocks may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. In the descriptions corresponding to the flowcharts and block diagrams in the accompanying drawings, the operations or steps corresponding to different blocks may also occur in a different order than disclosed in the description, and sometimes there is no specific order between different operations or steps. For example, two consecutive operations or steps may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. Each block in a block diagram and / or flowchart, and combinations of blocks in a block diagram and / or flowchart, can be implemented using a dedicated hardware-based system that performs the specified function or action, or using a combination of dedicated hardware and computer instructions.

Claims

1. A circuit for measuring the voltage of a chip pin, characterized in that, include: The relay circuit can be put into a first state or a second state through a control signal; when the relay circuit is in the first state, the chip pins are directly connected to the ATE test channel through the relay circuit. The voltage divider circuit is equipped with a test terminal, a sampling terminal, and a reference terminal. When the relay circuit is in the second state, the test terminal is connected to the chip pin through the relay circuit, the sampling terminal is connected to the ATE test channel through the relay circuit, and the reference terminal is connected to the reference voltage.

2. The circuit according to claim 1, characterized in that, The ATE test channel is equipped with a clamping voltage; When the voltage at the chip pin is positive and less than or equal to the clamping voltage, ATE sends a first control signal to put the relay circuit in the first state. When the voltage at the chip pin is negative or greater than the clamping voltage, ATE sends a second control signal to put the relay circuit into the second state.

3. The circuit according to claim 1, characterized in that, The relay circuit includes a first relay and a second relay; When the relay circuit is in the first state, the first contact pair of the first relay is closed, and the second contact pair of the second relay is also closed; wherein, one contact of the first contact pair is connected to the chip pin, the other contact of the first contact pair is connected to one contact of the second contact pair, and the other contact of the second contact pair is connected to the ATE test channel. When the relay circuit is in the second state, the third contact pair of the first relay is closed, and the fourth contact pair of the second relay is also closed; wherein, one contact of the third contact pair is connected to the chip pin, the other contact of the third contact pair is connected to the test terminal of the voltage divider circuit, one contact of the fourth contact pair is connected to the sampling terminal of the voltage divider circuit, and the other contact of the fourth contact pair is connected to the ATE test channel.

4. The circuit according to any one of claims 1 to 3, characterized in that, The voltage divider circuit includes a first resistor and a second resistor; One end of the first resistor serves as the test terminal of the voltage divider circuit; the other end of the first resistor is connected to one end of the second resistor, serving as the sampling terminal of the voltage divider circuit. The other end of the second resistor serves as the reference terminal for the voltage divider circuit.

5. The circuit according to claim 4, characterized in that, The resistance of the first resistor is greater than the resistance of the second resistor.

6. A method for measuring chip pin voltage, applied to the circuit for measuring chip pin voltage as described in any one of claims 1 to 5, characterized in that the method... include: When the relay circuit is in the first state, the relay circuit is controlled to continue in the first state or change to the second state according to the voltage at the chip pin and the clamping voltage of the ATE test channel. With the relay circuit in its first state, the voltage measured by the ATE test channel is taken as the voltage at the chip pin. When the relay circuit is in the second state, the voltage at the chip pin is calculated based on the voltage measured by the ATE test channel.

7. The method according to claim 6, characterized in that, Based on the voltage at the chip pin and the clamping voltage of the ATE test channel, the relay circuit is controlled to remain in the first state or change to the second state, including: When the voltage at the chip pin is positive and less than or equal to the clamping voltage, the control relay circuit continues to be in the first state. When the voltage at the chip pin is negative or greater than the clamping voltage, the control relay circuit changes to the second state.

8. The method according to claim 6 or 7, characterized in that, The voltage divider circuit includes a first resistor and a second resistor; one end of the first resistor serves as the test terminal of the voltage divider circuit; the other end of the first resistor is connected to one end of the second resistor, serving as the sampling terminal of the voltage divider circuit; the other end of the second resistor serves as the reference terminal of the voltage divider circuit; when the relay circuit is in the second state, the voltage at the chip pin is calculated according to the following formula: Where Vs is the voltage at the chip pin, Vg is the voltage measured by the ATE test channel, Vref is the reference voltage, r1 is the resistance value of the first resistor, and r2 is the resistance value of the second resistor.

9. An apparatus for measuring the voltage of a chip pin, comprising a processor and a memory storing program instructions, characterized in that, The processor is configured to, when running the program instructions, perform the method for measuring chip pin voltage as described in any one of claims 6 to 8.

10. A system for measuring the voltage of a chip pin, characterized in that, include: ATE equipment, equipped with the means for measuring chip pin voltage as described in claim 9; The chip under test (DUT) has its chip pins connected to the ATE test channel of the ATE equipment via a circuit for measuring chip pin voltage as described in any one of claims 1 to 5.

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